W191 Skew Controlled SDRAM Buffer Features Key Specifications • Six skew controlled CMOS outputs Supply Voltages: ...................................... VDDQ3 = 3.3V ±5% • Output skew between any two outputs is less than 150 ps Operating Temperature: (Commercial) ............. 0°C to +70°C • SMBus Serial configuration interface Operating Temperature: (Industrial) .............. –40°C to +85°C • 2.5 ns to 5 ns propagation delay Input Threshold:...................................................1.5V typical • DC to 133 MHz operation (Commercial) Maximum Input Voltage: .................................. VDDQ3 + 0.5V • DC to 100 MHz operation (Industrial) Input Frequency: (Commercial) ........................0 to 133 MHz • Single 3.3V supply voltage Input Frequency: (Industrial).............................0 to 100 MHz • Low power CMOS design packaged in a 16-pin SSOP (Small Shrink Outline Package) BUF_IN to SDRAM0:5 Propagation Delay:.......2.5 ns to 5 ns Min. Output Edge Rate: ............................................. 1.0V/ns Max. Output Skew: ..................................................... 150 ps Output Duty Cycle:...................................45/55% worst case Output Impedance: ...................................................15: typ. Block Diagram SDATA SCLOCK SMBus Pin Configuration[1] SDRAM0 1 16 VDDQ3 GND 2 15 SDRAM5 SDRAM0 SDRAM1 3 14 GND SDRAM1 BUF_IN 4 13 SDRAM4 SDRAM2 GND 5 12 VDDQ3 SDRAM3 SDRAM2 6 11 SDRAM3 SDRAM4 VDDQ3 7 10 GND SDRAM5 SDATA 8 9 SCLK Device Control BUF_IN Note: 1. Internal pull-up resistor of 250K on SDATA and SCLK. Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Page 1 of 9 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com W191 Pin Definitions Pin Name Pin No. SDRAM0:5 1, 3, 6, 11, 13, 15 Pin Type Pin Description O SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 2.5 to 5 ns. All outputs are skew controlled to within ±150 ps of each other. Clock Input: This clock input has an input threshold voltage of 1.5V (typ). BUF_IN 4 I SDATA 8 I/O SCLOCK 9 I SMBus clock input: The SMBus Data clock should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k: pull-up resistor. VDDQ3 7, 12, 16 P Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. GND 2, 5, 10, 14 G Ground Connection: Connect all ground pins to the common system ground plane. SMBus Data input: Data should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k: pull-up resistor. Overview Serial Control The W191 is a skew controlled fanout buffer optimized for interface with registered DIMMs. Serial control data is written to the W191 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1 Writing Data Bytes Functional Description Output Drivers The W191 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15:. Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. Table 1 gives the bit formats for registers located in Data Bytes 0-2. Table 1. Byte Writing Sequence Byte Sequence Byte Name Bit Sequence Byte Description 1 Slave Address 11010010 Commands the W191 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W191 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W191, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W191, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 5 Data Byte 1 Refer to Table 2 6 Data Byte 2 The data bits in these bytes set internal W191 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2. 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 Rev 1.0, November 20, 2006 Don’t Care Page 2 of 9 W191 Table 2. Data Bytes 0–2 Serial Configuration Map[2] Affected Pin Bit(s) Pin No. Pin Name Bit Control Control Function 0 1 Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 6 SDRAM2 Clock Output Disable Low Active 6 -- -- (Reserved) -- -- 5 -- -- (Reserved) -- -- 4 -- -- (Reserved) -- -- 3 -- -- (Reserved) -- -- 2 3 SDRAM1 Clock Output Disable Low Active 1 -- -- (Reserved) -- -- 0 1 SDRAM0 Clock Output Disable -- -- Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 -- -- Clock Output Disable -- -- 6 15 SDRAM5 Clock Output Disable Low Active 5 -- -- Clock Output Disable -- -- 4 -- -- (Reserved) -- -- 3 13 SDRAM4 Clock Output Disable Low Active 2 -- -- (Reserved) -- -- 1 -- -- (Reserved) -- -- 0 -- -- (Reserved) -- -- Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) 7 11 SDRAM3 Clock Output Disable Low Active 6 -- -- (Reserved) -- -- 5 -- -- (Reserved) -- -- 4 -- -- (Reserved) -- -- 3 -- -- (Reserved) -- -- 2 -- -- (Reserved) -- -- 1 -- -- (Reserved) -- -- 0 -- -- (Reserved) -- -- Note: 2. At power up all SDRAM outputs are enabled and active. Program Reserved bits to 0. Rev 1.0, November 20, 2006 Page 3 of 9 W191 Absolute Maximum Ratings[3] rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress Parameter Description Rating Unit VDDQ3, VIN Voltage on any pin with respect to GND –0.5 to + 7.0 V TSTG Storage Temperature –65 to + 150 °C TB Ambient Temperature under Bias –55 to + 125 °C TA Operating Temperature (Commercial) 0 to + 70 °C TA Operating Temperature (Industrial) –40 to + 85 °C DC Electrical Characteristics: TA = 0°C to +70°C (Commercial), VDDQ3 = 3.3V ± 5%,TA = –40°C to +85°C (Industrial), VDDQ3 = 3.3V ± 5% [4] Parameter Description Test Condition Min. Typ. Max. Unit IDD 3.3V Supply Current BUF_IN = 100 MHz 173 mA IDD 3.3V Supply Current in three-state BUF_IN = 100 MHz 5 mA Logic Inputs (BUF_IN, OE, SCLOCK, SDATA) VIL Input Low Voltage GND–0.3 0.8 V VIH Input High Voltage 2.0 VDDQ3+0.5 V IILEAK Input Leakage Current, BUF_IN –5 +5 µA IILEAK Input Leakage Current[5] –20 +5 µA 50 mV Logic Outputs (SDRAM0:5) VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA 3.1 IOL Output Low Current VOL = 1.5V 65 100 160 mA IOH Output High Current VOH = 1.5V 70 110 185 mA V Pin Capacitance/Inductance CIN Input Pin Capacitance (Except BUF_IN) 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Notes: 3. Multiple supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. transmission lines with 20 pF capacitors. 4. Outputs loaded by 6” 60 5. OE, SCLOCK, and SDATA logic pins have a 250-k: internal pull-up resistor (not CMOS level). : Rev 1.0, November 20, 2006 Page 4 of 9 W191 AC Electrical Characteristics: TA = 0°C to +70°C (Commercial), VDDQ3 = 3.3V ± 5%,TA = -40°C to +85°C (Industrial), VDDQ3 = 3.3V ± 5% (Lump Capacitance Test Load = 30pF) Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency (Commercial) 0 133 MHz fIN Input Frequency (Industrial) 0 100 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.0 4.0 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.0 4.0 V/ns tSR Output Skew, Rising Edges 150 ps tSF Output Skew, Falling Edges 150 ps tEN Output Enable Time 1.0 8.0 ns tDIS Output Disable Time 1.0 8.0 ns tPR Rising Edge Propagation Delay 2.5 5.0 ns tPF Falling Edge Propagation Delay 2.5 5.0 ns tD Duty Cycle 45 55 % Zo AC Output Impedance Rev 1.0, November 20, 2006 Measured at 1.5V 15 : Page 5 of 9 W191 How To Use the Serial Data Interface pulse. A transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). Electrical Requirements Figure 1 illustrates electrical characteristics for the serial interface bus used with the W191. Devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. The pull-up resistor on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. A write sequence is initiated by a “Start Bit” as shown in Figure 3. A “Stop Bit” signifies that a transmission has ended. As stated previously, the W191 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 4. Although the W191 is a receive-only device (no data write-back capability), it does transmit an “acknowledge” data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. Sending Data to the W191 The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition). The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. Signaling Requirements As shown in Figure 2, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) VDD VDD ~ 2k: ~ 2k: SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE SDCLK CLOCK IN CLOCK OUT SCLOCK SDATA DATA IN N DATA OUT CLOCK IN N DATA IN DATA OUT CHIP SET (SERIAL BUS MASTER TRANSMITTER) SDATA N CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER) Figure 1. Serial Interface Bus Electrical Characteristics . Rev 1.0, November 20, 2006 Page 6 of 9 W191 TA CK Valid Data Bit Change of Data Allowed Figure 2. Serial Data Bus Valid Data Bit A K Start Bit Stop Bit Figure 3. Serial Data Bus Start and Stop Bit Rev 1.0, November 20, 2006 Page 7 of 9 W191 Signaling from System Core Logic Start Condition Stop Condition Slave Address (First Byte) SDATA SCLOCK Command Code (Second Byte) MSB 1 1 0 1 0 0 1 LSB 0 1 2 3 4 5 6 7 8 Byte Count (Third Byte) MSB A 1 LSB 2 3 4 5 6 7 8 Last Data Byte (Last Byte) MSB A 1 MSB 2 3 4 1 LSB 2 3 4 5 6 7 8 A SDATA Acknowledgment Bit from Clock Device Signaling by Clock Device Figure 4. Serial Data Bus Write Sequence SDATA tSPF tLOW SCLOCK tSTHD tDSU tDHD tSP tHIGH tR tSPSU tSTHD tSPSU tF Figure 5. Serial Data Bus Timing Diagrams Ordering Information Ordering Code Package Type Temperature Range W191HI 16 pin = SSOP (150 mil) I = Industrial W191H 16 pin = SSOP (150 mil) Commercial Rev 1.0, November 20, 2006 Page 8 of 9 W191 Package Diagrams Shrink Small Outline Package (SSOP 150 inch) While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Page 9 of 9