USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B 128-Macrocell MAX® EPLD Features 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. • 128 macrocells in eight logic array blocks (LABs) The 128 macrocells in the CY7C342B are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. • Eight dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Advanced 0.65-micron CMOS technology to increase performance Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. • Available in 68-pin HLCC, PLCC, and PGA packages Functional Description The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is The speed and density of the CY7C342B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342B allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C342B reduces board space, part count, and increases system reliability. Logic Block Diagram 1 (B6) INPUT/CLK INPUT (A7) 2 (A6) INPUT INPUT (A8) 66 32 (L4) INPUT INPUT (L6) 36 34 (L5) INPUT INPUT (K6) 35 68 SYSTEM CLOCK 4 (A5) 5 (B4) 6 (A4) 7 (B3) 8 (A3) 9 (A2) 10 (B2) 11 (B1) 12 (C2) 13 (C1) 14 (D2) 15 (D1) 17 (E1) LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 9–16 LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 MACROCELL 121–128 LAB B MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 LAB G MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 MACROCELL 22–32 18 (F2) 19 (F1) 21 (G1) 22 (H2) 23 (H1) 24 (J2) 25 (J1) 26 (K1) 27 (K2) 28 (L2) 29 (K3) 30 (L3) 31 (K4) LAB F MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 38–48 MACROCELL 86–96 LAB D MACROCELL 49 MACROCELL 50 MACROCELL 51 MACROCELL 52 MACROCELL 53 MACROCELL 54 MACROCELL 55 MACROCELL 56 LAB E MACROCELL 72 MACROCELL 71 MACROCELL 70 MACROCELL 69 MACROCELL 68 MACROCELL 67 MACROCELL 66 MACROCELL 65 (G11) 51 (H11) 49 (H10) 48 (J11) 47 (J10) 46 (K11) 45 (K10) 44 (L10) 43 (L9) 42 (K9) 41 (L8) 40 (K8) 39 (L7) 38 MACROCELL 73–80 MACROCELL 57–64 3, 20, 37, 54 (B5, G2, K7, E10) VCC 16, 33, 50, 67 (E2, K5, G10, B7) GND • (D11) 57 (D10) 56 (E11) 55 (F11) 53 (F10) 52 MACROCELL 102–112 P I A LAB C MACROCELL 33 MACROCELL 34 MACROCELL 35 MACROCELL 36 MACROCELL 37 Cypress Semiconductor Corporation Document #: 38-03014 Rev. *B (B8) 65 (A9) 64 (B9) 63 (A10) 62 (B10) 61 (B11) 60 (C11) 59 (C10) 58 3901 North First Street () – PERTAIN TO 68-PIN PGA PACKAGE • San Jose, CA 95134 • 408-943-2600 Revised April 22, 2004 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Selection Guide 7C342B-15 7C342B-20 7C342B-25 7C342B-30 7C342B-35 Unit 15 20 25 30 35 ns Maximum Access Time Pin Configurations HLCC, PLCC Top View I/O I/O I/O V CC INPUT INPUT/CLK INPUT 17 18 19 VCC 20 21 I/O K I/O I/O I/O GND INPUT VCC I/O I/O I/O I/O I/O I/O I/O 58 57 56 55 H I/O I/O I/O I/O I/O VCC G I/O VCC GND I/O I/O I/O I/O F I/O I/O I/O I/O E I/O GND VCC I/O D I/O I/O I/O I/O C I/O I/O I/O I/O B I/O I/O I/O I/O VCC INPUT/ GND CLK I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT I/O I/O 2 3 4 5 9 10 I/O I/O I/O I/O I/O I/O INPUT V CC INPUT INPUT GND INPUT I/O I/O I/O I/O 24 45 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4344 I/O GND I/O I/O I/O 7C342B I/O I/O I/O A 1 Document #: 38-03014 Rev. *B I/O J 49 48 47 46 23 I/O I/O I/O I/O 51 50 22 I/O INPUT INPUT INPUT I/O 52 7C342B I/O 60 59 54 53 16 I/O I/O I/O I/O I/O I/O INPUT I/O 1 68 67 66 65 64 63 62 61 2 GND I/O I/O 3 13 14 I/O I/O I/O I/O I/O 4 12 15 I/O 5 L 10 11 I/O GND I/O I/O I/O 6 I/O I/O I/O I/O 7 8 I/O I/O 9 I/O I/O PGA Bottom View 6 7 I/O 8 11 Page 2 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS Logic Array Blocks placement and routing iterations required for a programmable gate array to achieve design timing objectives. There are eight logic array blocks in the CY7C342B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Timing Delays Timing delays within the CY7C342B may be easily determined using Warp®, Warp Professional™, or Warp Enterprise™ software by the model shown in Figure 1. The CY7C342B has fixed internal delays, allowing the user to determine the worst-case timing delays for any design. Design Recommendations Operation of the devices described herein with conditions above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C342B contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. Externally, the CY7C342B provides eight dedicated inputs, one of which may be used as a system clock. There are 52 I/O pins that may be individually configured for input, output, or bidirectional data flow. Programmable Interconnect Array The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals that may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a signal pass, without the multiple internal logic EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC INPUT INPUT DELAY tIN CY7C342B LOGIC ARRAY DELAY tLAD REGISTER OUTPUT DELAY tCLR tPRE tRSU tRH OUTPUT tRD tCOMB tLATCH tOD tXZ tZX SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC FEEDBACK DELAY tFD I/O DELAY tIO Figure 1. CY7C342B Internal Timing Model Document #: 38-03014 Rev. *B Page 3 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS Design Security The CY7C342B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages. Typical ICC vs. fMAX ICC ACTIVE (mA) Typ. VCC = 5.0V Room Temp. 200 VCC = 5.0V Room Temp. 150 100 IOH 50 0 1 2 3 4 5 VO OUTPUT VOLTAGE (V) When calculating synchronous frequencies, use tSU if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. 200 100 100 kHz IOL Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from straight input pin. 300 10 kHz 250 Timing Considerations 400 1 kHz IO OUTPUT CURRENT (mA) TYPICAL Output Drive Current The CY7C342B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. 0 100 Hz CY7C342B 1 MHz 10 MHz MAXIMUM FREQUENCY 50 MHz When calculating external asynchronous frequencies, use tAS1 if all inputs are on the dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. Document #: 38-03014 Rev. *B Page 4 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B DC Output Current per Pin[1] ................... –25 mA to +25 mA Maximum Ratings DC Input Voltage[1] .........................................–2.0V to +7.0V (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature ................................ –65°C to +135°C Range Ambient Temperature with Power Applied............................................ –65°C to +135°C Ambient Temperature 0°C to +70°C 5V ± 5% –40°C to +85°C 5V ± 10% Commercial Industrial Maximum Junction Temperature (under bias).................................................................. 150°C VCC Supply Voltage to Ground Potential ............–2.0V to +7.0V[1] Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VCC Supply Voltage Maximum VCC rise time is 10 ms VOH Output HIGH Voltage IOH = –4 mA DC[2] IOL = 8 mA Min. Max. Unit 4.75(4.5) 5.25(5.5) V 2.4 DC[2] VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Current VI = VCC or ground IOZ Output Leakage Current VO = VCC or ground tR Recommended Input Rise Time tF Recommended Input Fall Time V 0.45 V 2.0 VCC + 0.3 V –0.3 0.8 V –10 +10 µA –40 +40 µA 100 ns 100 ns Capacitance Parameter Description Test Conditions Max. Unit CIN Input Capacitance VIN = 0V, f = 1.0 MHz 10 pF COUT Output Capacitance VOUT = 0V, f = 1.0 MHz 20 pF AC Test Loads and Waveforms R1 464Ω R1 464Ω 5V 5V OUTPUT ALL INPUT PULSES OUTPUT R2 250Ω 50 pF INCLUDING JIG AND SCOPE Equivalent to: 3.0V INCLUDING JIG AND SCOPE (a) R2 250Ω 5 pF 10% GND ≤ 6 ns 90% 90% 10% ≤ 6 ns (b) THÉVENIN EQUIVALENT (commercial/military) 163Ω OUTPUT 1.75V Notes: 1. Minimum DC input is –0.3V. During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. Document #: 38-03014 Rev. *B Page 5 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range 7C342B-15 Parameter tPD1 Description Min. [3] Dedicated Input to Combinatorial Output Delay tPD2 I/O Input to Combinatorial Output Delay tSU Global Clock Set-Up Time 7C342B-20 Max. Min. 15 [3] 25 10 Max. Unit 20 ns 33 ns 13 [3] ns tCO1 Synchronous Clock Input to Output Delay tH Input Hold Time from Synchronous Clock Input 0 0 ns tWH Synchronous Clock Input HIGH Time 5 7 ns tWL Synchronous Clock Input LOW Time 5 7 ns fMAX Maximum Register Toggle Frequency tCNT Minimum Global Clock Period fCNT 8 [4] 9 100 71.4 12 Maximum Internal Global Clock Frequency[5] MHz 15 83.3 ns 66.7 ns MHZ Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range Parameter tPD1 Description Dedicated Input to Combinatorial Output tPD2 I/O Input to Combinatorial Output tSU Global Clock Set-Up Time 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Delay[3] Max. 25 Delay[3] 30 40 45 15 Delay[3] Max. 20 Unit 35 ns 55 ns 25 Synchronous Clock Input to Output tH Input Hold Time from Synchronous Clock Input 0 0 0 ns tWH Synchronous Clock Input HIGH Time 8 10 12.5 ns tWL Synchronous Clock Input LOW Time 8 10 12.5 ns fMAX Maximum Register Toggle tCNT Minimum Global Clock Period tODH Output Data Hold Time After Clock fCNT Maximum Internal Global Clock 16 ns tCO1 Frequency[4] 14 Max. 62.5 50 20 Frequency[5] 20 40 25 ns MHz 30 ns 2 2 2 ns 50 40 33.3 MHz Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range Parameter Description 7C342B-15 7C342B–20 Min. Min. Max. Max. Unit 20 ns tACO1 Asynchronous Clock Input to Output Delay[3] tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[6] 5 6 ns tAH Input Hold Time from Asynchronous Clock Input 5 6 ns tAWH Asynchronous Clock Input HIGH Time[6] 5 7 ns tAWL Asynchronous Clock Input LOW Time[6] 5 7 ns tACNT Minimum Internal Array Clock Frequency fACNT Maximum Internal Array Clock Frequency[5] tACO1 Asynchronous Clock Input to Output Delay[3] tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[5] 5 6 10 tAH Input Hold Time from Asynchronous Clock Input 6 8 10 15 12 83.3 15 66.7 25 ns MHz 30 Notes: 3. C1 = 35 pF. 4. The fMAX values represent the highest frequency for pipeline data. 5. This parameter is measured with a 16-bit counter programmed into each LAB 6. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. Document #: 38-03014 Rev. *B Page 6 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range (continued) Parameter Description 7C342B-15 7C342B–20 Min. Min. Max. Max. Unit tAWH Asynchronous Clock Input HIGH Time [5] 11 14 16 tAWL Asynchronous Clock Input LOW Time[5] 9 11 14 tACNT Minimum Internal Array Clock Frequency fACNT Maximum Internal Array Clock Frequency[5] 20 50 25 40 33.3 Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range 7C342B-15 Parameter Description Min. Max. 7C342B-20 Min. Max. Unit 4 ns tIN Dedicated Input Pad and Buffer Delay 3 tIO I/O Input Pad and Buffer Delay 3 4 ns tEXP Expander Array Delay 8 10 ns tLAD Logic Array Data Delay 8 12 ns tLAC Logic Array Control Delay 5 5 ns tOD Output Buffer and Pad Delay[3] 3 3 ns 5 5 ns 5 ns tZX[8] Output Buffer Enable Delay[3] tXZ Output Buffer Disable Delay[7] tRSU Register Set-Up Time Relative to Clock Signal at Register 2 1 ns tRH Register Hold Time Relative to Clock Signal at Register 7 10 ns tLATCH Flow Through Latch Delay 1 1 ns tRD Register Delay 1 1 ns tCOMB[9] Transparent Mode Delay 1 1 ns tIC Asynchronous Clock Logic Delay 6 8 ns tICS Synchronous Clock Delay 0 0 ns tFD Feedback Delay 1 1 ns tPRE Asynchronous Register Preset Time 3 3 ns tCLR Asynchronous Register Clear Time 3 3 ns tPIA Programmable Interconnect Array Delay Time 10 13 ns tIN Dedicated Input Pad and Buffer Delay 5 7 tIO I/O Input Pad and Buffer Delay 6 6 tEXP Expander Array Delay 12 14 tLAD Logic Array Data Delay 12 14 tLAC Logic Array Control Delay 10 12 tOD Output Buffer and Pad Delay[3] 5 5 10 11 tZX[8] 5 Output Buffer Enable Delay[3] tXZ Output Buffer Disable Delay[7] tRSU Register Set-Up Time Relative to Clock Signal at Register 6 8 10 tRH Register Hold Time Relative to Clock Signal at Register 4 6 8 tLATCH Flow Through Latch Delay 3 4 tRD Register Delay 1 2 10 11 Notes: 7. C1 = 5 pF. 8. Sample tested only for an output change of 500 mV. 9. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. Document #: 38-03014 Rev. *B Page 7 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range (continued) Parameter Description 7C342B-25 7C342B-30 7C342B-35 Min. Min. Min. Max. Max. Unit 4 4 ns 14 16 16 ns 3 2 1 ns Feedback Delay 1 1 2 ns tPRE Asynchronous Register Preset Time 5 6 7 ns tCLR Asynchronous Register Clear Time 5 6 7 ns tPIA Programmable Interconnect Array Delay Time 14 16 20 ns tCOMB[9] Transparent Mode Delay 3 tIC Asynchronous Clock Logic Delay tICS Synchronous Clock Delay tFD Max. Switching Waveforms External Combinatorial DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT tWH External Synchronous tWL SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER tSU tH DATA FROM LOGIC ARRAY tCO1 REGISTERED OUTPUTS External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 tAH tAWH tAWL ASYNCHRONOUS CLOCK INPUT Document #: 38-03014 Rev. *B Page 8 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Switching Waveforms (continued) Internal Combinatorial tIN INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT tCOMB tOD OUTPUT PIN Internal Synchronous CLOCK FROM LOGIC ARRAY tOD tRD DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE Internal Asynchronous tAWH tIOtR tAWL tF CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY tIC tRSU tRH DATA FROM LOGIC ARRAY tRD,tLATCH tFD tCLR,tPRE tFD REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB Document #: 38-03014 Rev. *B Page 9 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Switching Waveforms (continued) Internal Synchronous SYSTEM CLOCK PIN SYSTEM CLOCK AT REGISTER tIN tICS tRSU tRH DATA FROM LOGIC ARRAY Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C342B-15JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/ Industrial 20 CY7C342B-20JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/ Industrial 25 CY7C342B-25HC/HI H81 68-pin Windowed Leaded Chip Carrier CY7C342B-25JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/ Industrial CY7C342B-25RC/RI R68 68-pin Windowed Ceramic Pin Grid Array 30 CY7C342B-30JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/ Industrial 35 CY7C342B-35JC/JI J81 68-lead Plastic Leaded Chip Carrier CY7C342B-35RJ/RI R68 68-pin Windowed Ceramic Pin Grid Array Commercial/ Industrial Document #: 38-03014 Rev. *B Page 10 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Package Diagrams 68-pin Windowed Leaded Chip Carrier H81 51-80080-** Document #: 38-03014 Rev. *B Page 11 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Package Diagrams (continued) 68-lead Plastic Leaded Chip Carrier J81 51-85005-*A Document #: 38-03014 Rev. *B Page 12 of 14 USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Package Diagrams (continued) 68-Pin Windowed PGA Ceramic R68 51-80099-*A MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. All product and company ames mentioned in this document are the trademarks of their respective holders. Document #: 38-03014 Rev. *B Page 13 of 14 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B Document History Page Document Title: CY7C342B 128-Macrocell MAX® EPLD Document Number: 38-03014 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106314 04/25/01 SZV Change from Spec number: 38-00119 to 38-03014 *A 113612 04/11/02 OOR PGA package diagram dimensions were updated *B 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs” Document #: 38-03014 Rev. *B Page 14 of 14