USER’S MANUAL TCC720 32-bit RISC Microprocessor For Digital Media Player Preliminary Rev 0.51 TCC720 TABLE OF CONTENTS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 TABLE OF CONTENTS 1. INTRODUCTION 1.1 Features 1.2 Pin Description 1.3 Package Diagram 2. ADDRESS & REGISTER MAP 3. DAI (Digital Audio Interface) & CDIF (CD-DSP Interface) 4. INTERRUPT CONTROLLER 5. TIMER / COUNTER 6. GPIO 7. CLOCK GENERATOR 8. USB (Universal Serial Bus) CONTROLLER 9. UART / IrDA 10. GSIO (General Purpose Serial Input/Output) 11. MISCELLANEOUS PERIPHERALS 11.1 ADC 11.2 CODEC 12. DMA CONTROLLER 13. MEMORY CONTROLLER 13.1 Overview 13.2 SDRAM Controller 13.3 Miscellaneous Configuration 13.4 External Memory Controller 13.5 Internal Memories 14. BOOT ROM 14.1 External ROM Boot 14.2 UART Boot 14.3 NAND Boot 14.4 NOR Boot with Security 14.5 HPI Boot 14.6 Development Mode 15. JTAG DEBUG INTERFACE 16. PACKAGE DIMENSION 2 CHAPTER 1 INTRODUCTION TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 1 INTRODUCTION Preliminary Spec 0.51 INTRODUCTION TCC720 is system LSI for digital media player which based on ARM940T, ARM’s proprietary 32bit RISC CPU core. It can decode and encode MP3 or other types of audio/voice compression / decompression standards by software based architecture. The on-chip USB controller enables the data transmission between a personal computer and storage of device such as NAND flash, HDD, CD etc, which can be controlled by TCC720. TCC720 also includes on-chip stereo audio CODEC eliminates the need of expensive external audio CODEC. Using I2S port, TCC720 can also use the external audio CODEC by performance or other reason. 1-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 INTRODUCTION Preliminary Spec 0.51 1.1 FEATURES 32bit ARM940TDMI RISC CPU core 8KB instruction/data cache Internal boot ROM of 4Kbytes for various boot procedure(NAND, UART) and security Internal SRAM of 64K bytes for general usage On-chip peripherals - Memory controller for various memories such as PROM, FLASH, SRAM, SDRAM - IDE Interface for HDD or USB device - 4 external interrupts, 9 internal interrupts - 4 timer/counters, 2 timers - USB1.1 device (Full speed) - UART(IrDA) for serial Host I/F - GPIO, GSIO - I2S interface for internal and external audio CODEC - I2S interface for CD-DSP - On chip audio CODEC with MIC input - General purpose ADC (3 input) - 1 Channel DMA for transferring a bulk of data - JTAG interface for code debugging 0.25um low power CMOS process 2.5V for core, 3.3V for I/O port 128-pin TQFP Operating up to 120MHz 1.2 APPLICATIONS Portable Digital Audio Encoder/Decoder MP3 Juke Box Digital Audio Encoder/Decoder Digital Internet Radio Server Multimedia Storage Device 1-2 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 XIN, XOUT, XTIN, XTOUT, XFILT XA21 / DQM0 XA20 / DQM1 XA[19:18] XA17 / ND_CLE XA16 / ND_ALE / SD_nRAS XA15 / SD_nCAS XA14 / SD_BA1 XA13 / SD_BA0 XA[12:0] XD[15:0] nOE nWE nCS[3:0] / GPIO_B[5:2] SD_nCS / GPIO_B1 SD_CKE / GPIO_B0 SD_CLK ND_nWE / GPIO_B7 IDE_nCS1 / GPIO_B9 Preliminary Spec 0.51 USB_DP / GPIO_B26, USB_DN / GPIO_B27 CLK Generator Power Manager USB1.1 Ext. Memory & IDE Interface ETC logic Boot ROM (512 x 32) Timer /// Timer Timer Timer Timer Timer/// Counter Counter Counter Counter Counter Counter TCO2 / GPIO_A11 TCO5 / GPIO_A8 TCO1 / GPIO_A7 TCO4 / GPIO_A4 TCO0 / GPIO_A3 TCO3 / GPIO_A0 Interrupt Controller EXINT3 / GPIO_A15 EXINT2 / GPIO_A14 EXINT1 / GPIO_A13 EXINT0 / GPIO_A12 SRAM (64K x 8) GSIO GSIO GSIO APB AHB AHB Wrapper GPIO APB Bridge ARM940T 1 Channel DMA AHB Test Controller TDI TMS TCK nTRST TDO JTAG GSIO2[3:0] / GPIO_A[11:8] GSIO1[3:0] / GPIO_A[7:4] GSIO0[3:0] / GPIO_A[3:0] GPIO_A[15:0] GPIO_B[29:21] GPIO_B[9:7] GPIO_B[5:0] UART/IrDA UT_TX / GPIO_B8 UT_RX / GPIO_B9 DAI (I2S) for CODEC BCLK / GPIO_B21 LRCK / GPIO_B22 MCLK / GPIO_B23 DAO / GPIO_B24 DAI / GPIO_B25 DAI (I2S) for CD-DSP CDAI / GPIO_A3 CLRCK / GPIO_A2 CBCLK / GPIO_A1 16bit Audio CODEC LCH_OUT RCH_OUT RCH_IN MIC_IN LCH_IN 8 Input ADC (8bit) AHB Arbiter ADIN[7:0] Figure 1.1 Functional Block Diagram 1-3 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 1.2 Pin Description JTAG Interface Signal Name NUM Type Description TDI 99 I JTAG serial data input for ARM940T TMS 100 I JTAG Test mode select for ARM940T TCK 101 I JTAG test clock for ARM940T TDO 102 O JTAG serial data output for ARM940T nTRST 103 I Reset signal for boundary scan logic. Active low. NUM Type External Memory Interface Signal Shared Signal Description SD_CKE GPIO_B0 56 O Clock enable signal for SDRAM, Active high. / GPIO_B1 SD_CLK GPO 44 O SDRAM clock SD_nCS GPIO_B1 46 O Chip select signal for SDRAM, Active low. / GPIO_B0 XA[6:0] - 23:17 O XA[12:7] - 31:26 O XA[13] SD_BA0 34 O Bank Address 0 for SDRAM / XA[13] XA[14] SD_BA1 35 O Bank Address 1 for SDRAM / XA[14] Address bus for external memories. XA[15] SD_nCAS 36 O CAS for SDRAM / XA[15] XA[16] ND_ALE, SD_nRAS 37 O ALE for NAND flash / RAS for SDRAM / XA[16] XA[17] ND_CLE 38 O CLE for NAND flash / XA[17] XA[19:18] - 40:39 O XA[19:18] for static memory / Bus Width configuration XA[21:20] DQM[0:1] 43:42 O XA[21:20] / Data I/O mask XD[15:9], XD[15:9], 15:9, XD[8:4], XD[8:4], 6:2, I/O Data bus for external memory XD[3:0] XD[3:0] 128:125 nCS0 / ND_nOE0 GPIO_B2 47 O External chip select 0 / NAND flash 0 OE / GPIO_B2 nCS1 / ND_nOE1 GPIO_B3 48 O External chip select 1 / NAND flash 1 OE / GPIO_B3 nCS2 / ND_nOE2 GPIO_B4 49 O External chip select 2 / NAND flash 2 OE / GPIO_B4 nCS3 / ND_nOE3 GPIO_B5 50 O External chip select 3 / NAND flash 3 OE / GPIO_B5 IDE_nCS1 GPIO_B9 / UT_RX 61 O IDE chip select 1. Active low. / GPIO_B9 / UART RX ND_nWE GPIO_B7 57 O NAND flash WE. Active low. / GPIO_B7 nWE nWE 58 O Static memory write enable signal. Active low. nOE nOE 59 O Static memory output enable signal. Active low. READY - 73 I Ready information from external device. *) XA[21:0] is used as system address bus for external memories such as SRAM, ROM. XA[12:0] can be also used as RAS and CAS signals for SDRAM. XD[15:0] is used as system data bus for all types of external memories contained. SD_CLK is also used as general purpose output port by setting clock control flag. Refer to the chapter of memory controller for detail. 1-4 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 General Purpose I/O Signal Shared Signal NUM Type Description GPIO_A[15:12] EXINT[3:0] 124:121 I/O GPIO_A[15:12] / External Interrupt Source 3 ~ 0 GPIO_A[11:8] (SDI_2, FRM_2, 118:115 I/O GPIO_A[11:8] / General Purpose Serial I/O 2 I/O GPIO_A[7:4] / General Purpose Serial I/O 1 GSIO2[3:0] SCK_2, SDO_2) GSIO1[3:0] GPIO_A[7:4] 114:113 (SDI_1, FRM_1, 111 SCK_1, SDO_1) 108 GSIO0[3:1] (SDI_0, GPIO_A[3:1] FRM_0, SCK_0) / CDIF[2:0] (CDAI, 107:105 I/O 104 I/O GPIO_A[3:1] / General purpose serial I/O 0 / CD interface signals CLRCK, CBCLK) GPIO_A[0] GSIO0[0] (SDO_0) GPIO_A[0] / General purpose serial out 0 GPIO_B[29:28] - 54:53 I/O GPIO_B[29:28] GPIO_B[27:26] USB_DP, USB_DN 52:51 I/O GPIO_B[27:26] / USB_DP, USB_DN I/O GPIO_B[25:21] / I2S Interface Signals GPIO_B[25:21] GPIO_B[9:8] DAI 68 DAO 67 MCLK 66 LRCK 63 BCLK 62 UT_RX / IDE_nCS1 61 UT_TX 60 I/O GPIO_B[9:8] / UART Interface Signals IDE chip select 1 GPIO_B7 ND_nWE 57 I/O GPIO_B[5:2] nCS[3:0] 50:47 I/O GPIO_B7 / Write enable for NAND flash GPIO_B[5:2] / External Chip Select 3 ~ 0 GPIO_B1 SD_nCS 46 I/O GPIO_B1 / Chip select for SDRAM GPIO_B0 SD_CKE 56 I/O GPIO_B0 / SDRAM clock control 1-5 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 USB / UART / IrDA Interface Signal Shared Signal NUM Type USB D+ GPIO_B26 51 I/O USB D- GPIO_B27 52 I/O USB Function D- pin / GPIO_B27 UART_TXD GPIO_B8 60 I/O UART or IrDA TX data pin / GPIO_B8 61 I/O Shared Signal NUM Type GPIO_B21 BCLK 62 I/O I2S Bit clock (64fs) / GPIO_B21 GPIO_B22 LRCK 63 I/O I2S Word clock / GPIO_B22 GPIO_B23 MCLK 66 I/O I2S system clock (256fs or 384fs) / GPIO_B23 GPIO_B24 DAO 67 I/O I2S digital audio data output / GPIO_B24 UART_RXD GPIO_B9 / IDE_nCS1 Description USB Function D+ pin / GPIO_B26 UART or IrDA RX data pin / GPIO_B9 IDE chip select 1 Audio Interface Signal Description GPIO_B25 DAI 68 I/O LCH_IN LCH_IN 90 I ADC left channel input of internal audio CODEC I2S digital audio data input / GPIO_B25 RCH_IN RCH_IN 91 I ADC right channel input of internal audio CODEC MIC_IN MIC_IN 92 I Mic input of internal audio CODEC DAC left channel output of internal audio CODEC LCH_OUT LCH_OUT 93 O RCH_OUT RCH_OUT 94 O DAC right channel output of internal audio CODEC VREF VREF 95 O Reference voltage of internal audio CODEC Signal Shared Signal NUM Type CD DSP Interface Description CBCLK GPIO_A1 105 I/O CD Data Bit Clock Input / GPIO_A1 CLRCK GPIO_A2 106 I/O CD Data Word Clock Input / GPIO_A2 CDAI GPIO_A3 107 I/O CD Data input / GPIO_A3 Signal Shared Signal NUM Type Clock Interface Description XIN - 74 I XOUT - 75 O Main clock input for PLL Main clock output for PLL XFILT - 78 O PLL filter output XTIN - 69 I Sub clock input XTOUT - 70 O Sub clock output Shared Signal NUM Type GPIO_A15 124 GPIO_A14 123 GPIO_A13 122 GPIO_A12 121 External Interrupt Interface Signal EXINT[3:0] I/O Description External interrupt request [3:0] / GPIO_A[15:12] 1-6 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 General Purpose ADC Interface Signal Shared Signal NUM Type ADIN[2:0] - 84:82 I Shared Signal NUM Type Description General purpose multi-channel ADC input Mode Control Signal Description MODE1 - 98 I Mode Setting Input 1 nRESET - 72 I System Reset Signal NUM Type VDD3 112 76 64 33 16 PWR Digital Power for I/O (3.3V) VDD2D 119 109 87 71 41 24 7 PWR Digital Power for Internal (2.5V) VDD2A 89 81 77 PWR Analog Power (2.5V) VSS3D 97 65 45 32 1 PWR Digital Ground for I/O VSS2D 120 110 88 55 25 8 PWR Digital Ground for Internal VSSA 96 86 85 80 79 PWR Analog Ground Power Description 1-7 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 VSSA_CDC VREF LCH_IN MIC_IN RCH_IN RCH_OUT LCH_OUT VDDA_CDC VSSI_AIP VDDI_AIP VBBA_ADC VSSA_ADC ADIN4 ADIN2 ADIN0 VDDA_ADC VBBA_PLL VSSA_PLL XFILT VDDA_PLL VDDIO XOUT XIN READY nRESET VDDI XTOUT XTIN DAI/GPIO_B25 DAO/GPIO_B24 MCLK/GPIO_B23 VSSIO 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1.3 Package Diagram VSSIO 97 64 VDDIO MODE1 98 63 LRCK/GPIO_B22 TDI 99 62 BCLK/GPIO_B21 TMS 100 61 UT_RX/IDE_nCS1/GPIO_B9 TCK 101 60 UT_TX/GPIO_B8 TDO 102 59 nOE nTRST 103 58 nWE SDO0/GPIO_A0 104 57 ND_nWE/GPIO_B7 SCK0/GPIO_A1 105 56 SD_CKE/GPIO_B0 SFRM0/GPIO_A2 106 55 VSSI SDI0/GPIO_A3 107 54 GPIO_B29 SDO1/GPIO_A4 108 53 GPIO_B28 VDDI 109 52 USB_DN/GPIO_B27 VSSI 110 51 USB_DP/GPIO_B26 SCK1/GPIO_A5 111 50 nCS3/nOE3/GPIO_B5 VDDIO 112 49 nCS2/nOE2/GPIO_B4 SFRM1/GPIO_A6 113 48 nCS1/nOE1/GPIO_B3 SDI1/GPIO_A7 114 47 nCS0/nOE0/GPIO_B2 SDO2/GPIO_A8 115 46 SD_nCS/GPIO_B1 SCK2/GPIO_A9 116 45 VSSIO SFRM2/GPIO_A10 117 44 SD_CLK/GPO SDI2/GPIO_A11 118 43 XA21/DQM0 VDDI 119 42 XA20/DQM1 VSSI 120 41 VDDI EXINT0/GPIO_A12 121 40 XA19 EXINT1/GPIO_A13 122 39 XA18 EXINT2/GPIO_A14 123 38 XA17/CLE EXINT3/GPIO_A15 124 37 XA16/nRAS/ALE XD0 125 36 XA15/nCAS XD1 126 35 XA14/BA1 XD2 127 34 XA13/BA0 XD3 128 33 VDDIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSSIO XD4 XD5 XD6 XD7 XD8 VDDI VSSI XD9 XD10 XD11 XD12 XD13 XD14 XD15 VDDIO XA0 XA1 XA2 XA3 XA4 XA5 XA6 VDDI VSSI XA7 XA8 XA9 XA10 XA11 XA12 VSSIO TCC720 Figure 1.2 Package Diagram (128-TQFP-1414) 1-8 CHAPTER 2 ADDRESS & REGISTER MAP TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 2 Preliminary Spec 0.51 ADDRESS & REGISTER MAP 2.1 Address Map The TCC720 has fixed address maps for digital audio en-decoder system. The address space is separated MSB 4bits of address bus, the following table represents overall address space of TCC720 system. Table 2.1 Address Allocation Map of TCC720 Address Space Device Name internal or external ROM of chip select 3 (Remap == 0) 0x00000000 ~ 0x0FFFFFFF Other type memory according to base value (Remap = 1) Internal SRAM when any other memory is not assigned. 0x10000000 ~ 0x1FFFFFFF Not Used 0x20000000 ~ 0x2FFFFFFF Initial area for SDRAM 0x30000000 ~ 0x3FFFFFFF Area of internal SRAM 0x40000000 ~ 0x4FFFFFFF 0x50000000 ~ 0x5FFFFFFF 0x60000000 ~ 0x6FFFFFFF 0x70000000 ~ 0x7FFFFFFF 0x80000000 ~ 0x8FFFFFFF Initial area for chip select 0 Initial configuration is for SRAM Initial area for chip select 1 Initial configuration is for IDE type device Initial area for chip select 2 Initial configuration is for NAND flash Initial area for chip select 3 Initial configuration is for ROM Various internal peripheral devices 0x90000000 ~ 0x9FFFFFFF 0xA0000000 ~ 0xAFFFFFFF 0xB0000000 ~ 0xBFFFFFFF Not Used 0xC0000000 ~ 0xCFFFFFFF 0xD0000000 ~ 0xDFFFFFFF 0xE0000000 ~ 0xEFFFFFFF Area for internal boot ROM 0xF0000000 ~ 0xFFFFFFFF Area for memory controller configuration register space The address space (0x00000000 ~ 0x0FFFFFFF) is initially allocated to internal or external PROM for booting procedure, and a special flag is exist in memory controller unit for remapping lower half space to other type memories. Refer to the description of memory controller for 2-1 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 detailed operation. TCC720 has only one chip select for SDRAM, so its address space is dependent on SDRAM size attached to TCC720. TCC720 has various peripherals for controlling a digital audio en-decoder system. These peripherals can be configured appropriately by it’s own registers that can be accessed through specially allocated address. These address maps are represented in the following table. In case of memory controller, its space is separated for preventing illegal accessing. Refer to corresponding sections for detail information of each peripheral. Table 2.2 Address Allocation for Internal Peripherals (Base Address = 0x80000000) Offset Address Space Peripheral 0x000 ~ 0x0FF DAI & CDIF 0x100 ~ 0x1FF Interrupt Controller 0x200 ~ 0x2FF Timer Counter 0x300 ~ 0x3FF GPIO 0x400 ~ 0x4FF Clock Generator & Power Management 0x500 ~ 0x5FF USB Function 0x600 ~ 0x6FF UART/IrDA 0x700 ~ 0x7FF GSIO (General Purpose Serial Input/Output) 0x800 ~ 0x8FF - 0x900 ~ 0x9FF - 0xA00 ~ 0xAFF Analog Control & Etc. 0xB00 ~ 0xBFF - 0xC00 ~ 0xCFF - 0xD00 ~ 0xDFF - 0xE00 ~ 0xEFF DMA Controller 0xF00 ~ 0xFFF - *) Address decoding logic only monitors base address (i.e. 0x8xxxxxxx), and bit11~bit8 of accessing address bus. So care must be taken not to modify these registers unintentionally. 2-2 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 2.2 Register Map DAI & CDIF Register Map (Base Address = 0x80000000) Name Address Type Reset Description DADI_L0 0x00 R - Digital Audio Left Input Register 0 DADI_R0 0x04 R - Digital Audio Right Input Register 0 DADI_L1 0x08 R - Digital Audio Left Input Register 1 DADI_R1 0x0C R - Digital Audio Right Input Register 1 DADO_L0 0x10 R/W - Digital Audio Left Output Register 0 DADO_R0 0x14 R/W - Digital Audio Right Output Register 0 DADO_L1 0x18 R/W - Digital Audio Left Output Register 1 DADO_R1 0x1C R/W - Digital Audio Right Output Register 1 DAMR 0x20 R/W 0x0000 Digital Audio Mode Register DAVC 0x24 R/W 0x0000 Digital Audio Volume Control Register CDDI_0 0x80 R - CD Digital Audio Input Register 0 CDDI_1 0x84 R - CD Digital Audio Input Register 1 CICR 0x88 R/W 0x0000 CD Interface Control Register Interrupt Controller Register Map (Base Address = 0x80000100) Name Address Type Reset Description IEN 0x00 R/W 0x0000 CREQ 0x04 W - Clear Interrupt Request Register IREQ 0x08 R 0x0000 Interrupt Request Flag Register IRQSEL 0x0C R/W 0x0000 IRQ/FIQ Select Register ICFG 0x10 R/W 0x0000 External Interrupt Configuration Register MREQ 0x14 R 0x0000 Masked Interrupt Request Flag Register IRQREQ 0x18 R 0x0000 IRQ Interrupt Request Flag Register FIQREQ 0x1C R 0x0000 FIQ Interrupt Request Flag Register Interrupt Enable Register 2-3 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter Register Map (Base Address = 0x80000200) Name Address Type Reset Description TCFG0 0x0000 R/W 0x00 TCNT0 0x0004 R/W 0x0000 Timer/Counter 0 Counter Register TREF0 0x0008 R/W 0xFFFF Timer/Counter 0 Reference Register TMREF0 0x000C R/W 0x0000 Timer/Counter 0 Middle Reference Register TCFG1 0x0010 R/W 0x00 TCNT1 0x0014 R/W 0x0000 Timer/Counter 1 Counter Register TREF1 0x0018 R/W 0xFFFF Timer/Counter 1 Reference Register TMREF1 0x001C R/W 0x0000 Timer/Counter 1 Middle Reference Register TCFG2 0x0020 R/W 0x00 TCNT2 0x0024 R/W 0x0000 Timer/Counter 2 Counter Register TREF2 0x0028 R/W 0xFFFF Timer/Counter 2 Reference Register TMREF2 0x002C R/W 0x0000 Timer/Counter 2 Middle Reference Register TCFG3 0x0030 R/W 0x00 TCNT3 0x0034 R/W 0x0000 Timer/Counter 3 Counter Register TREF3 0x0038 R/W 0xFFFF Timer/Counter 3 Reference Register TMREF3 0x003C R/W 0x0000 Timer/Counter 3 Middle Reference Register TCFG4 0x0040 R/W 0x00 TCNT4 0x0044 R/W 0x00000 Timer/Counter 4 Counter Register TREF4 0x0048 R/W 0xFFFFF Timer/Counter 4 Reference Register TCFG5 0x0050 R/W 0x00 TCNT5 0x0054 R/W 0x00000 Timer/Counter 5 Counter Register TREF5 0x0058 R/W 0xFFFFF Timer/Counter 5 Reference Register TIREQ 0x0060 R/W 0x0000 Timer/Counter n Interrupt Request Register TWDCFG 0x0070 R/W 0x0000 Watchdog Timer Configuration Register TWDCLR 0x0074 W - Timer/Counter 0 Configuration Register Timer/Counter 1 Configuration Register Timer/Counter 2 Configuration Register Timer/Counter 3 Configuration Register Timer/Counter 4 Configuration Register Timer/Counter 5 Configuration Register Watchdog Timer Clear Register 2-4 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO Register Map (Base Address = 0x80000300) Name Addr Type Reset Description GDATA_A 0x00 R/W 0xFFFFFFFF GPIO_A Data Register GIOCON_A 0x04 R/W 0xFFFF0000 GPIO_A Direction Control Register GSEL_A 0x08 R/W 0x00000000 GPIO_A Function Select Register GTSEL_A 0x0C R/W 0x00000000 GPIO_A Function Select Register 2 GDATA_B 0x10 R/W 0x3FFFFFFF GPIO_B Data Register GIOCON_B 0x14 R/W 0x001FFCFF GPIO_B Direction Control Register GSEL_B 0x18 R/W 0x3C0000BF GPIO_B Function Select Register GTSEL_B 0x1C R/W 0x00000000 GPIO_B Function Select Register 2 Clock Generator Register Map (Base Address = 0x80000400) Name Address Type Reset Description CKCTRL 0x00 R/W 0x0003FFE PLLMODE 0x04 R/W 0x03806 PLL Control Register SCLKmode 0x08 R/W 0x082000 System Clock Control Register DCLKmode 0x0C R/W 0x0800 DCLK (DAI/CODEC) Control Register EXTCLKmode 0x14 R/W 0x0000 EXTCLK (CD/Other) Control Register UTCLKmode 0x18 R/W 0x01BE UTCLK (UART) Control Register UBCLKmode 0x1C R/W 0x000 UBCLK (USB) Control Register TCLKmode 0x24 R/W 0x000 TCLK (Timer) Control Register GCLKmode 0x28 R/W 0x000 GCLK (GSIO) Control Register SW_nRST 0x3C R/W 0x000 Software Reset Control Register Clock Control Register 2-5 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 USB Register Map (Base Address = 0x80000500) Name Address Type Reset Description UBFADR 0x00 Function Address Register UBPWR 0x04 Power Management Register UBIIR 0x08 In-Interrupt Register UBOIR 0x10 Out-Interrupt Register UBIR 0x18 Interrupt Register UBIIEN 0x1C In-Interrupt Enable Register UBOIEN 0x24 Out-Interrupt Enable Register UBIEN 0x2C Interrupt Enable Register UBFRM1 0x30 Frame Number 1 Register UBFRM2 0x34 Frame Number 2 Register UBIDX 0x38 Index Register INMXPn 0x40 IN Max Packet Register INCSR1n 0x44 IN CSR1 Register INCSR2n 0x48 IN CSR2 Register OMXPn 0x4C OUT Max Packet Register OCSR1n 0x50 OUT CSR1 Register OCSR2n 0x54 OUT CSR2 Register OFIFO1n 0x58 OUT FIFO Write Count 1 Register OFIFO2n 0x5C OUT FIFO Write Count 2 Register EP0FIFO 0x80 EP0 FIFO Register EP1FIFO 0x84 EP1 FIFO Register EP2FIFO 0x88 EP2 FIFO Register 2-6 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UART/IrDA Register Map (Base Address = 0x80000600) Name Address Type Reset Description RB 0x00 R - Receiver Buffer Register THR 0x00 W - Transmitter Holding Register DL 0x04 W 0x0000 Divisor Latch Register IR 0x08 R/W 0x000 Interrupt Register CR 0x0C R/W 0x000 UART Control Register LSR 0x10 R 0x0101 Status Register IrDACFG1 0x14 R/W 0x0003 IrDA Configuration Register 1 IrDACFG2 0x18 R/W 0x4da1 IrDA Configuration Register 2 GSIO Register Map (Base Address = 0x80000700) Name Address Type Reset Description GSDO0 0x00 R/W GSIO0 Output Data Register GSDI0 0x04 R/W GSIO0 Input Data Register GSCR0 0x08 R/W GSIO0 Control Register GSICR 0x0C R/W GSIO Interrupt Control Register GSDO1 0x10 R/W GSIO1 Output Data Register GSDI1 0x14 R/W GSIO1 Input Data Register GSCR1 0x18 R/W GSIO1 Control Register GSDO2 0x20 R/W GSIO2 Output Data Register GSDI2 0x24 R/W GSIO2 Input Data Register GSCR2 0x28 R/W GSIO2 Control Register GSDO3 0x30 R/W GSIO3 Output Data Register GSDI3 0x34 R/W GSIO3 Input Data Register GSCR3 0x38 R/W GSIO3 Control Register 2-7 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Analog Interface & ETC Register Map (Base Address = 0x80000A00) Name Address Type Reset Description ADCTR 0x00 R/W 0 ADC Control Register ADDATA 0x04 R - ADC Data Register CDCTR 0x08 R/W 0 Codec Control Register CDCGAIN 0x0C R/W 0 Codec Gain Register LZC 0x10 R/W - Leading Zero Counter Register USBCTR 0x14 R/W 0 USB Port Control Register TSTSEL 0x18 R/W 0 Test Mode Register (must be remained zero) DMA Controller Register Map (Base Address = 0x80000E00) Name Address Type Reset Description ST_SADR 0x00 R/W - Start Address of Source Block SPARAM 0x04/0x08 R/W - Parameter of Source Block C_SADR 0x0C R - Current Address of Source Block ST_DADR 0x10 R/W - Start Address of Destination Block DPARAM 0x14/0x18 R/W - Parameter of Destination Block C_DADR 0x1C R - Current Address of Destination Block HCOUNT 0x20 R/W 0x00000000 Initial and Current Hop count CHCTRL 0x24 R/W 0x00000000 Channel Configuration Memory Controller Register Map (Base Address = 0xF0000000) Name Address Type Reset SDCFG 0x00 R/W 0x4268A020 SDFSM 0x04 R - MCFG 0x08 R/W 0xZZZZ_02 TST 0x0C W 0x0000 CSCFG0 0x10 R/W CSCFG1 CSCFG2 CSCFG3 0x14 0x18 0x1C R/W R/W R/W 0x0B405601 0x0150569A 0x0060569A 0x0A70569A Description SDRAM Configuration Register SDRAM FSM Status Register Miscellaneous Configuration Register Test mode register (must be remained zero) External Chip Select 0 Configuration Register (Initially set to SRAM) External Chip Select 1 Configuration Register (Initially set to IDE) External Chip Select 2 Configuration Register (Initially set to NAND) External Chip Select 3 Configuration Register (Initially set to NOR) 2-8 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 NAND flash Register Map (Base Address = N * 0x10000000) Name Address Type Reset Description CMD 0x00 R/W - Command Cycle Register LADDR 0x04 W - Linear Address Cycle Register BADDR 0x08 W - Block Address Cycle Register IADDR 0x0C W - Single Address Cycle Register DATA 0x10 R/W - Data Access Cycle Register *) N represents BASE field of CSCFGn registers. 2-9 CHAPTER 3 DAI & CDIF TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 3 Preliminary Spec 0.51 DAI (Digital Audio Interface) & CDIF (CD-DSP Interface) 3.1 DAI The TCC720 provides digital audio interface that complies with IIS (Inter-IC Sound). The DAI has five input/output pins for IIS interface; MCLK, BCLK, LRCK, DAI, DAO. All DAI input/output pins are multiplexed with GPIO pins; GPIO_B<21:25>. The MCLK is the system clock pin that is used for CODEC system clock. The DAI provides 256fs, 384fs and 512fs as a system clock. 256fs means that 256 times of sampling frequency fs. The BCLK is the serial bit clock for IIS data exchange. The DAI can generate 64fs, 48fs and 32fs by dividing a system clock. The polarity of BCLK can be programmed. The LRCK is the frame clock for the audio channel Left and Right. The frequency of LRCK is the “fs” – sampling frequency. Generally, for audio application – such as MP3 Player , CD player, 11.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz. the fs can be set to 8kHz, 16kHz, For supporting the wide range of sampling frequency in audio application, the DCO function is very useful to generate a system clock. Refer Chap. 7 for detail information. All three clocks are selectable as master or slave. The DAI, DAO are the serial data input output pins respectively. The DAI has two 8-word input/output buffers. The buffers can be read/written through the DADI/DADO. The hidden buffer pointers automatically increment when user read/write from/to the DADI/DADO. The maximum data word size is 24 bit. Data is justified to MSB of 32bits and zeros are padded to LSB. There are 2 types of interrupt from IIS; transmit done interrupt, receive done interrupt. The transmit-done interrupt is generated when the 4 words are transferred successfully in the output buffer. At this interrupt, user should fill another 4 more words into the other part of the output buffer in the interrupt service routine (ISR). In this ISR routine, 4 consecutive stores of word data to the DADO is needed – sequence is that the left channel is the first and right channel. The receive-done interrupt is generated when the 4 words are received successfully in the input buffer. At this interrupt, user should read 4 received words from the input buffer using 4 consecutive load instructions from the DADI – sequence is that the left channel is the first. 3-1 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 DAI Register Map (Base Address = 0x80000000) Name Address Type Reset Description DADI_L0 0x00 R - Digital Audio Left Input Register 0 DADI_R0 0x04 R - Digital Audio Right Input Register 0 DADI_L1 0x08 R - Digital Audio Left Input Register 1 DADI_R1 0x0C R - Digital Audio Right Input Register 1 DADO_L0 0x10 R/W - Digital Audio Left Output Register 0 DADO_R0 0x14 R/W - Digital Audio Right Output Register 0 DADO_L1 0x18 R/W - Digital Audio Left Output Register 1 DADO_R1 0x1C R/W - Digital Audio Right Output Register 1 DAMR 0x20 R 0x0000 Digital Audio Mode Register DAVC 0x24 R/W 0x0000 Digital Audio Volume Control Register 3-2 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Digital Audio Mode Register (DAMR) 31 30 29 28 27 26 0x80000020 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 EN TE RE MD SM BM FM CC BD<1:0> FD<1:0> BP CM MM EN [15] DAI Master Enable 0 DAI disabled 1 DAI enabled TE [14] DAI Transmitter Enable 0 DAI transmitter disabled 1 DAI transmitter enabled RE [13] DAI Receiver Enable 0 DAI receiver disabled 1 DAI receiver enabled MD [12] DAI Bus Mode 0 DAI has IIS bus mode 1 DAI has MSB justified mode SM [11] DAI System Clock Master Select 0 DAI system clock is come from external pin 1 DAI system clock is generated by the clock generator block BM [10] DAI Bit Clock Master Select 0 DAI bit clock is come from external pin 1 DAI bit clock is generated by dividing DAI system clock FM [9] DAI Frame Clock Master Select 0 DAI frame clock is come from external pin 1 DAI frame clock is generated by dividing DAI bit clock LB 3-3 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 CC [8] CDIF Clock Select 0 CDIF Clock master mode disabled 1 CDIF Clock master mode enabled. BD [7:6] DAI Bit Clock Divider select 00 Div 4 ( 256fs->64fs ) 01 Div 6 ( 384fs->64fs ) 10 Div 8 ( 512fs->64fs, 384fs->48fs , 256fs->32fs) 11 Div16 ( 512fs->32fs ) FD [5:4] DAI Frame Clock Divider select 00 Div 32 ( 32fs->fs ) 01 Div 48 ( 48fs->fs ) 10 Div 64 ( 64fs->fs ) BP [3] DAI Bit Clock Polarity 0 Data is captured at positive edge of bit clock 1 Data is captured at negative edge of bit clock CM [2] CDIF Monitor Mode 0 CDIF monitor mode is disabled 1 CDIF monitor mode is enabled. Data bypass from CDIF MM [1] DAI Monitor Mode 0 DAI monitor mode is disabled 1 DAI monitor mode is enabled. TE should be enabled LB [0] DAI Loop-back Mode 0 DAI Loop back mode is disabled 1 DAI Loop back mode is enabled 3-4 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Digital Audio Volume Control Register (DAVC) 31 30 29 28 27 26 25 24 0x80000024 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Reserved VC<3:0> VC [3:0] DAI Volume control 0000 0dB 0001 -6dB 0010 -12dB 0011 -18dB 0100 -24dB 0101 -30dB 0110 -36dB 0111 -42dB 1000 -48dB 1001 -54dB 1010 -60dB 1011 -66dB 1100 -72dB 1101 -78dB 1110 -84dB 1111 -90dB 3-5 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Input Buffer DADI LEFT0 S2P RIGHT0 Input Buffer Pointer IIS_SDI LEFT1 DAVC RIGHT1 LEFT2 RIGHT2 LB LEFT3 MM RIGHT3 CDIF Data CC Output Buffer DADO LEFT0 IIS_SDO RIGHT0 Output Buffer Pointer LEFT1 RIGHT1 LEFT2 RIGHT2 P2S LEFT3 RIGHT3 DCO IIS_MCLK SM DIVIDER CDIF BCLK CC BM IIS_BCLK CDIF LRCK DIVIDER IIS_LRCK CC FM Figure 3.1 DAI Block Diagram 3-6 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 LRCK Preliminary Spec 0.51 Left 16 15 14 13 12 Right 11 10 9 8 7 6 5 4 3 2 1 16 L S B M S B BCLK DAI/O L S B M S B MD=0 (IIS mode), BP=0, BCLK = 32fs LRCK Left 32 31 30 29 28 27 10 Right 9 8 7 6 5 4 3 2 1 32 BCLK DAI/O M S B L S B M S B MD=1(MSB justified mode), BP=0, BCLK=64fs LRCK Left 24 23 22 21 20 21 Right 9 8 7 6 5 4 3 2 1 BCLK DAI/O M S B L S B M S B MD=1(MSB justified mode), BP=1, BCLK=48fs Figure 3.2 DAI Bus Timing Diagram 3-7 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 3.2 CDIF The TCC720 provides CD-ROM interface for feasible implementation of CD-ROM application such as CD-MP3 player. The CDIF supports the industry standard IIS format and the LSB justified format that is used as the most popular format for CD-ROM interface by Sony and Samsung. The CDIF has three pins for interface; CBCLK, CLRCK, CDAI that are multiplexed with GPIO_B14, GPIO_B15 and GPIO_B16, respectively. The CBCLK is the bit clock input pins of which frequency can be programmed by CICR for selection of 48fs and 32fs. The CLRCK is the frame clock input pin that indicates the channel of CD digital audio data. The CDAI is the input data pin. The CDIF has three registers; CDDI_0, CDDI_1 and CICR. The CDDI_0 and the CDDI_1 are the banked read only registers for access of data input buffer. The data input buffer is composed of four 32 bit wide registers of which upper 16 bit is left channel data and lower is right channel data. The CDIF receive the serial data from CDAI pin and store the data into the buffer through the serial to parallel register. Whenever the half of buffer is filled, the receive interrupt is generated. Only the half of input buffer can be accessible through the CDDI_0 and the CDDI_1. CDIF Register Map (Base Address = 0x80000000) Name Address Type Reset Description CDDI_0 0x80 R CD Digital Audio Input Register 0 CDDI_1 0x84 R CD Digital Audio Input Register 1 CICR 0x88 R/W 0x0000 CD Interface Control Register CD Data Input (CDDI0) 31 30 29 28 0x80000080 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 Left Channel Data 15 14 13 12 11 10 9 8 7 6 Right Channel Data CD Data Input (CDDI1) 31 30 29 28 0x80000084 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 Left Channel Data 15 14 13 12 11 10 9 8 7 6 Right Channel Data 3-8 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 CD Interface Control Register (CICR) 31 30 29 28 27 26 25 0x80000088 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 MD BP Reserved 15 14 13 12 11 Reserved 10 9 8 7 EN Reserved BS EN [7] CDIF Enable 0 CDIF disabled 1 CDIF enabled BS [3:2] CDIF Bit Clock select 00 64fs 01 32fs 10 48fs MD [1] Interface Mode select 0 IIS format 1 LSB justified format BP [3] CDIF Bit Clock Polarity 0 Data is captured at positive edge of bit clock 1 Data is captured at negative edge of bit clock 3-9 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Input Buffer CDDI0 LEFT0 RIGHT0 LEFT1 CDDI1 RIGHT1 LEFT2 Input Buffer Pointer S2P CDAI RIGHT2 LEFT3 RIGHT3 CBCLK CLRCK Figure 3.3. CDIF Block Diagram CLRCK Left 24 23 22 21 20 Right 19 10 9 8 7 6 5 4 3 2 1 16 CBCLK CDAI M S B L S B M S B MD=0 (IIS mode), BP=0, CBCLK=48fs CLRCK Left 24 23 22 21 20 19 18 Right 17 16 15 6 5 4 3 2 1 CBCLK CDAI M S B L S B MD=1(LSB justified mode), BP=0, CBCLK=48fs Figure 3.3 CDIF Bus Timing Diagram 3 - 10 CHAPTER 4 INTERRUPT CONTROLLER TCC720 INTERRUPT CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 4 Preliminary Spec 0.51 INTERRUPT CONTROLLER 4.1 Overview Interrupt controller can manage up to 16 interrupt sources. In TCC720, there are 4 external interrupt sources that can be detected various kind of method, that is a rising edge/ falling edge / level high / level low detection can be set for external interrupt sources. External interrupt sources can be reliably managed with noise filtering up to 100 ~ 400 us. There are two types of interrupt in ARM940T, IRQ type, FIQ type. Interrupt controller can manage these two types for each interrupt sources separately. The following figure represents the block diagram of interrupt controller. pi_INTIN pi_EXTIN Clock Generator Noise Filter Edge/Level Selector ICFG APB IREQ IRQ Flag CREQ MREQ nIRQ IEN nIRQ/nFIQ Generator IRQSEL nFIQ Figure 4.1 Interrupt Controller Block Diagram 4-1 TCC720 INTERRUPT CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 4.2 Register Description Interrupt Controller Register Map (Base Address = 0x80000100) Name Address Type Reset Description IEN 0x00 R/W 0x0000 CREQ 0x04 W - Clear Interrupt Request Register IREQ 0x08 R 0x0000 Interrupt Request Flag Register IRQSEL 0x0C R/W 0x0000 IRQ/FIQ Select Register ICFG 0x10 R/W 0x0000 External Interrupt Configuration Register MREQ 0x14 R 0x0000 Masked Interrupt Request Flag Register TSTREQ 0x18 R/W 0x0000 Test Mode Register (must be remained zero) Interrupt Enable Register Interrupt Enable Register (IEN) 15 14 MEN - 13 12 11 DMA LCD CDIF 0x80000100 10 9 8 7 6 5 4 3 2 1 0 - GS UB UT TC I2T I2R E3 E2 E1 E0 MEN [15] Master Enable 0 All interrupts are disabled 1 All interrupt enabled by corresponding bit[14:0] can be passed to CPU Bit Field Each Interrupt Request Control 1 = Interrupt enabled, 0 = Interrupt disabled DMA [13] DMA interrupt control LCD [12] LCD interrupt control CDIF [11] CDIF interrupt control [10] Not used GS [9] GSIO interrupt control UB [8] USB interrupt control UT [7] UART/IrDA interrupt control TC [6] Timer/Counter interrupt control I2T [5] I2S TX interrupt control I2R [4] I2S RX interrupt control E3 [3] External interrupt request 3 control E2 [2] External interrupt request 2 control 4-2 TCC720 INTERRUPT CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 E1 [1] External interrupt request 1 control E0 [0] External interrupt request 0 control Preliminary Spec 0.51 Clear Interrupt Request Register (CREQ) 15 14 - - 13 12 11 DMA LCD CDIF 0x80000104 10 9 8 7 6 5 4 3 2 1 0 - GS UB UT TC I2T I2R E3 E2 E1 E0 *) When writing “1” to each field, the interrupt request flag of corresponding interrupt is cleared. Interrupt Request Register (IREQ) 15 14 - - 13 12 11 DMA LCD CDIF 0x80000108 10 9 8 7 6 5 4 3 2 1 0 - GS UB UT TC I2T I2R E3 E2 E1 E0 *) When each field is “1”, the corresponding interrupt has been requested and not cleared. IRQ Interrupt Select Register (IRQSEL) 15 14 - - 13 12 11 DMA LCD CDIF 0x8000010C 10 9 8 7 6 5 4 3 2 1 0 - GS UB UT TC I2T I2R E3 E2 E1 E0 *) When each field is “1”, the corresponding interrupt is considered as IRQ interrupt, otherwise as FIQ interrupt. External Interrupt Configuration Register (ICFG) 15 FE3 14 13 DTYPE3 FE3~FE0 12 11 FT3 FE2 10 9 DTYPE2 8 7 FT2 FE1 0x80000110 6 5 DTYPE1 4 3 FT1 FE0 2 1 DTYPE0 0 FT0 Filter Enable 0 Noise filter is enabled (in case of DTYPEn != 3) 1 Noise filter is disabled (in case of DTYPEn != 3) *) If DTYPEn == 3, noise filter is always enabled, and this field sets which level generates the interrupt. If it is set to 1, level high triggers interrupt, and if it is set to 0, level low triggers interrupt. DTYPE3~0 Detection Type 0 Falling edge triggered external interrupt 1 Rising edge triggered external interrupt 2 Both edge triggered external interrupt 3 Level high / low triggered external interrupt FEn field determines which level triggers the interrupt. If FEn == 1, level high triggers the interrupt and FEn == 0, level low triggers the interrupt. 4-3 TCC720 INTERRUPT CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 FT3~FT0 Preliminary Spec 0.51 Filter Type 0 Clock based filter is used. The filter delay is proportional to PCLK period as the following equations. Filter Delay = TPCLK * 64 If PCLK has 25MHz, then the filter delay has about 16us. 1 Delay cell based filter is used. The filter delay varies on the operating conditions, like voltage, temperature, etc. The nominal delay is about 120ns. This type of filter must be selected when the PCLK has to be stopped, as like as stop mode etc. Masked Interrupt Request Register (MREQ) 15 14 - - 13 12 11 DMA LCD CDIF 0x80000114 10 9 8 7 6 5 4 3 2 1 0 - GS UB UT TC I2T I2R E3 E2 E1 E0 *) Same meaning as IREQ except that it represents only the enabled interrupt’s request. 4-4 CHAPTER 5 TIMER / COUNTER TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 5 Preliminary Spec 0.51 TIMER / COUNTER 5.1 Overview The TCC720 has four 16bit and two 20bit timer counter. Each timer counter has 3 registers for various operation modes. Refer to register description table for details. When operating in counter modes, External interrupt pin is used as counting clock for that counter. The main clock frequency of timer counter can be configured by setting TCLK frequency. (Refer to Clock generator block) With the 12bit internal basic counter, the timer counter can generate various intervals from micro-seconds to seconds unit. The following figure represents the block diagram of timer counter. pi_EXTIN Basic Counter Clock Selector Counter APB TCFG TCNT TREF Compare (=) TREQ Tgl TCO Figure 5.1 Timer Counter Block Diagram The following table explains the three registers of each timer counter. The address of each timer counter is 16bytes aligned. The base address of timer counter is 0x80000200. The number n represents for each timer/counter. In case of timer/counter 4, 5 (that is n = 4 or 5) 5-1 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 the TREF, TCNT register has 20bit resolution. It can be used for generation of a long time period. 5.2 Register Description Timer/Counter Register Map (Base Address = 0x80000200) Name Address Type Reset Description TCFG0 0x0000 R/W 0x00 TCNT0 0x0004 R/W 0x0000 Timer/Counter 0 Counter Register TREF0 0x0008 R/W 0xFFFF Timer/Counter 0 Reference Register TMREF0 0x000C R/W 0x0000 Timer/Counter 0 Middle Reference Register TCFG1 0x0010 R/W 0x00 TCNT1 0x0014 R/W 0x0000 Timer/Counter 1 Counter Register TREF1 0x0018 R/W 0xFFFF Timer/Counter 1 Reference Register TMREF1 0x001C R/W 0x0000 Timer/Counter 1 Middle Reference Register TCFG2 0x0020 R/W 0x00 TCNT2 0x0024 R/W 0x0000 Timer/Counter 2 Counter Register TREF2 0x0028 R/W 0xFFFF Timer/Counter 2 Reference Register TMREF2 0x002C R/W 0x0000 Timer/Counter 2 Middle Reference Register TCFG3 0x0030 R/W 0x00 TCNT3 0x0034 R/W 0x0000 Timer/Counter 3 Counter Register TREF3 0x0038 R/W 0xFFFF Timer/Counter 3 Reference Register TMREF3 0x003C R/W 0x0000 Timer/Counter 3 Middle Reference Register TCFG4 0x0040 R/W 0x00 TCNT4 0x0044 R/W 0x00000 Timer/Counter 4 Counter Register TREF4 0x0048 R/W 0xFFFFF Timer/Counter 4 Reference Register TCFG5 0x0050 R/W 0x00 TCNT5 0x0054 R/W 0x00000 Timer/Counter 5 Counter Register TREF5 0x0058 R/W 0xFFFFF Timer/Counter 5 Reference Register TIREQ 0x0060 R/W 0x0000 Timer/Counter n Interrupt Request Register TWDCFG 0x0070 R/W 0x0000 Watchdog Timer Configuration Register TWDCLR 0x0074 W - Timer/Counter 0 Configuration Register Timer/Counter 1 Configuration Register Timer/Counter 2 Configuration Register Timer/Counter 3 Configuration Register Timer/Counter 4 Configuration Register Timer/Counter 5 Configuration Register Watchdog Timer Clear Register 5-2 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter n Configuration Register (TCFGn) 15 14 13 12 11 10 9 0 CC [8] 7 CC POL 6 5 TCKSEL 4 3 2 1 IEN PWM CON 0 EN Clear Count 0 TCNTn hold its value. 1 TCNTn is cleared to zero. POL [7] 8 0x800002n0 TCK Polarity 0 TCNTn is incremented at rising edge of the selected counting clock 1 TCNTn is incremented at falling edge of the selected counting clock TCKSEL [6:4] TCK Select k=0~4 TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 2(k+1). k = 5, 6 TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 22k k=7 TCK is the external pin shared by external interrupt signal. In TCC721, there are 4 external pins for this purpose, so this configuration is valid only for timer/counter 3 ~ 0. (not for timer/counter 5, 4) IEN [3] 1 Interrupt Enable Timer/Counter interrupt is enabled PWM [2] PWM Mode Enable 1 Timer/Counter Output is changed at every time the TCNTn is equal to TREFn and TMREFn value. It can be used to generate PWM waveform, by changing TMREFn while fixing TREFn. (where, TREFn > TMREFn) CON [1] Continue Counting 0 TCNTn is stop counting at the time TCNTn is equal to TREFn 1 When the TCNTn is reached to TREFn, TCNTn continues counting from 0 at the next pulse of selected clock source EN [0] 1 Timer/Counter Enable Timer counter is enabled. TCNTn value is cleared at the same time. 5-3 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter n Counting Register (TCNTn) 31 30 29 28 27 26 25 24 0x800002n4 23 22 21 20 19 0 15 14 13 12 11 10 18 17 16 TCNTn[19:16] 9 8 7 6 5 4 3 2 1 0 TCNTn[15:0] *) TCNTn is increased by 1 at every pulse of selected clock source. TCNTn can be set to any value by writing the value to this register. In case of timer 4 and timer 5, it has 20bit. Timer/Counter n Counting Reference Register (TREFn) 31 30 29 28 27 26 25 24 23 22 0x800002n8 21 20 19 0 15 14 13 12 11 10 18 17 16 TREFn[19:16] 9 8 7 6 5 4 3 2 1 0 TREFn[15:0] *) When TCNTn is reached at TREFn, the TCNTn is cleared to 0. According to the TCFGn settings, various kinds of operations may be done. In case of timer 4 and timer 5, it has 20bit. 5-4 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter Interrupt Request Register (TIREQ) 15 0 14 13 TWF TF5 TWF 1 TFn 1 TWI 1 TIn 1 0x80000260 12 11 10 9 8 7 6 5 4 3 2 1 0 TF4 TF3 TF2 TF1 TF0 0 TW TI5 TI4 TI3 TI2 TI1 TI0 Watchdog Timer Flag Watchdog timer has reached to its reference value. Timer/Counter n Flag Timer/counter n has been overflowed. Watchdog Timer Interrupt Request Flag Watchdog timer has generated its interrupt. Timer/Counter n Interrupt Request Flag Timer/counter n has generated its interrupt. *) if a timer n has reached its reference value, the TFn is set. (bit n represents for Timer n). If its interrupt request is enabled by set bit 3 of TCFGn register, the TIn is set. And if the TC bit of IEN register is set, the timer interrupt is really generated, and this TIREQ register is used to determine which timer has requested the interrupt. After checking these flags, user can clear these TFn, TIn field by writing “1” to corresponding TIn bit field. 5-5 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Watchdog Timer Configuration Register (TWDCFG) 0x80000270 15 14 13 12 11 10 9 8 7 0 6 0 5 4 TCKSEL 3 2 1 0 IEN 0 RST EN Watchdog timer is used for the system not to be stuck by generating a reset pulse automatically when the watchdog timer counter overflows to zero. The programmer must clear the watchdog counter before it overflows by writing any value to TWDCLR register. TCKSEL [6:4] TCK Select k=0~4 TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 2(k+1). k = 5, 6 TCK is internally generated from divider circuit. It is driven by PCLK, and this value determines the division factor of this circuit. Division factor is 22k k=7 Undefined. Should not be used. IEN [3] Interrupt Enable 1 Watchdog Timer Interrupt is initiated. This field is valid only if RST field is set to 0. RST [1] Reset Enable 0 Watchdog timer does not generate reset signal although it reaches to the reference value, and it continue counting from 0. 1 Watchdog timer generates the reset signal when it reaches to the reference value, the reset signal is applied to every component in the chip. EN [0] Watchdog Timer Enable 1 Watchdog timer is enabled. If the watchdog timer is disabled, its counter goes to 0xffe0, so when it is first enabled, user must clear the counter by writing to TWDCLR register. Watchdog Timer Clear Register (TWDCLR) 15 14 13 12 11 10 9 8 0x80000274 7 6 5 4 3 2 1 0 any value *) The watchdog timer counter can be cleared to 0 by writing any value to this register. If it is not cleared before it overflows, the watchdog timer generate reset signal to the entire component of chip. 5-6 CHAPTER 6 GPIO PORT TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 6 Preliminary Spec 0.51 GPIO (General Purpose I/O) PORT 6.1 Functional Description The TCC720 has a lot of general purpose I/Os that can be programmed by setting internal registers. All I/Os are set to input mode at reset. The block diagram of GPIO is in the following figure. GIOCON Output of other block Output of test or other block 1 MUX GPIO pin 0 GDATA APB Write 2 Read GDATA MUX 1 GSEL, TSEL 0 Figure 6.1 GPIO Block Diagram The I/O mode can be set by the state of GIOCONn register. If a bit of GIOCONn register is 1, the corresponding GPIO pin has come to output mode, and if 0, which is the default state of GIOCON register, the corresponding GPIO pin is set to input mode. If GPIO pin is set to input mode, GPIO pin’s state can be fed to CPU by reading GDATAn register and when output mode, GPIO pin’s state can be controlled by the state of the corresponding bit of GDATAn register. If GDATAn register is read when the mode is output mode, the value that CPU gets is the one 6-1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 GPIO PORT Preliminary Spec 0.51 that CPU has written before. In TCC720, there are various kinds of peripherals that generate its own control signals. These peripherals can occupy the dedicated GPIO pins. This option is controlled by the state of the GSELx register. If a bit of these GSELx is 1, the corresponding GPIO pin is entered to other function mode, so used by other peripherals not by GPIO block. The direction control method of GPIO pins in the other function mode is determined case by case. One of them follows the normal direction control method using GDDR register, the other method uses a dedicated direction control signals. 6-2 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 6.2 Register Description GPIO Register Map (Base Address = 0x80000300) Name Addr Type Reset Description GDATA_A 0x00 R/W 0xFFFFFFFF GPIO_A Data Register GIOCON_A 0x04 R/W 0x00000000 GPIO_A Direction Control Register GSEL_A 0x08 R/W 0x00000000 GPIO_A Function Select Register 1 GTSEL_A 0x0C R/W 0x00000000 GPIO_A Function Select Register 2 GDATA_B 0x10 R/W 0x3FFFFFFF GPIO_B Data Register GIOCON_B 0x14 R/W 0x001FFCFF GPIO_B Direction Control Register GSEL_B 0x18 R/W 0x3C0000BF GPIO_B Function Select Register 1 GTSEL_B 0x1C R/W 0x00000000 GPIO_B Function Select Register 2 6-3 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO_A Data Register (GDATA_A) 31 30 29 28 27 26 0x80000300 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 0xFFFF 15 14 13 12 11 10 9 8 7 Data for GPIO_A[15:0] pin GPIO_A Direction Control Register (GIOCON_A) 31 30 29 28 27 26 25 24 23 0x80000304 22 21 20 19 18 17 16 6 5 4 3 2 1 0 0xFFFF 15 14 13 12 11 10 9 8 7 Direction control for GPIO_A[15:0] pin *) if a bit is set to 1, the corresponding GPIO pin is set to output mode. GPIO_A Function Select Register (GSEL_A) 31 30 29 28 27 26 25 0x80000308 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 0 10 9 GS2[2:0] 8 - GS1[2:0] - GS0[2:0] *) if a bit is set to 1, the corresponding GPIO pin is used by the other dedicated function blocks. GSn[2:0] 0 GPIO_A[10:8], GPIO_A[6:4], GPIO_A[2:0] Function GPIO_A[10:8], GPIO_A[6:4], GPIO_A[2:0] pin is working as Normal GPIO Function GS2[2] = 1 GPIO_A[10] : FRM signal of GSIO2 block GS2[1] = 1 GPIO_A[ 9] : SCK signal of GSIO2 block GS2[0] = 1 GPIO_A[ 8] : SDO signal of GSIO2 block GS1[2] = 1 GPIO_A[ 6] : FRM signal of GSIO1 block GS1[1] = 1 GPIO_A[ 5] : SCK signal of GSIO1 block GS1[0] = 1 GPIO_A[ 4] : SDO signal of GSIO1 block GS0[2] = 1 GPIO_A[ 2] : FRM signal of GSIO0 block GS0[1] = 1 GPIO_A[ 1] : SCK signal of GSIO0 block GS0[0] = 1 GPIO_A[ 0] : SDO signal of GSIO0 block *) SDI signal for GSIO2, GSIO1, GSIO0 block is always fed through GSIO_A[11], GSIO_A[7], GSIO_A[3] pin regardless of these GS[2:0] bit. But these pins must be set to input mode. 6-4 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO_A Test Select Register (GTSEL_A) 31 30 29 28 27 26 25 0x8000030C 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 0 11 10 TC2 9 0 8 TC5 TC1 0 TC4 TC0 0 TC3 *) if a bit is set to 1, and the corresponding bit of GSEL_A is 0, GPIO pin is used by the other dedicated function blocks. TC5 ~ TC0 GPIO_A[11,8,7,4,3,0] Function Select 0 GPIO_A[11,8,7,4,3,0] pin is working as Normal GPIO Function 1 GPIO_A[11,8,7,4,3,0] is the output of 6 timer/counter *) this bit field is only valid only if the corresponding bit of GSEL_A is set to 0 GPIO_B Data Register (GDATA_B) 31 30 29 28 27 0 15 26 0x80000310 25 24 23 22 21 20 19 GPIO_B[29:21] 14 13 12 11 10 0 9 8 18 30 29 28 27 0 15 26 7 6 GPIO_B[9:7] 0 25 24 5 4 3 2 13 12 11 10 0 9 8 1 0 GPIO_B[5:0] 23 0x80000314 22 21 20 19 GIO_B[29:21] 14 16 0 GPIO_B Direction Control Register (GIOCON_B) 31 17 18 17 16 1 0 0 7 GIO_B[9:7] 6 5 4 0 3 2 GIO_B[5:0] *) if a bit is set to 1, the corresponding GPIO pin is set to output mode. The GPIO_B[29:28] and GPIO_B[27:26] pin is unable to be set to different I/O mode. That is, GPIO_B[29] have always same direction with GPIO_B[28], and it is same as GPIO_B[27] and GPIO_B[26], so to make GPIO_B[27:26] output port, you must set both GIOCON_B[27] and GIOCON_B[26] to 1. GPIO_B Function Select Register (GSEL_B) 31 30 29 28 0 15 14 13 12 0 27 26 25 USB[1:0] 0 11 9 10 24 0x80000318 23 22 21 20 19 DAI[3:0] 8 7 UTX NWE 6 0 18 17 16 1 0 0 5 4 3 CS[3:0] 2 SCS CKE *) if a bit is set to 1, and the corresponding GPIO pin is set to output mode, the output of internal peripherals occupy the corresponding GPIO pin. 6-5 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB[1:0] [27:26] 0 3 DAI[3:0] [24:21] 0 Preliminary Spec 0.51 GPIO_B[27:26] Function Select GPIO_B[27:26] pin is working as Normal GPIO Function GPIO_B[27] pin is working as USB D- Port GPIO_B[26] pin is working as USB D+ Port GPIO_B[24:21] Function Select GPIO_B[24:21] pin is working as Normal GPIO Function DAI[3] = 1 GPIO_B[24] pin is working as DAO signal of DAI block DAI[2] = 1 GPIO_B[23] pin is working as MCLK signal of DAI block DAI[1] = 1 GPIO_B[22] pin is working as LRCK signal of DAI block DAI[0] = 1 GPIO_B[21] pin is working as BCLK signal of DAI block UTX [8] GPIO_B[8] Function Select 0 GPIO_B[8] pin is working as Normal GPIO Function 1 GPIO_B[8] : UART TX signal of UART block NWE [7] GPIO_B[7] Function Select 0 GPIO_B[7] pin is working as Normal GPIO Function 1 GPIO_B[7] : ND_nWE (write enable for NAND flash) of memory controller CS[3:0] [5:2] GPIO_B[5:2] Function Select 0 GPIO_B[5:2] pin is working as Normal GPIO Function CS[3] = 1 GPIO_B[5] : nCS3 or ND_nOE3 of memory controller CS[2] = 1 GPIO_B[4] : nCS2 or ND_nOE2 of memory controller CS[1] = 1 GPIO_B[3] : nCS1 or ND_nOE1 of memory controller CS[0] = 1 GPIO_B[2] : nCS0 or ND_nOE0 of memory controller SCS [1] GPIO_B[1] Function Select 0 GPIO_B[1] pin is working as Normal GPIO Function 1 GPIO_B[1] : SD_nCS (chip select for SDRAM) of memory controller CKE [0] GPIO_B[0] Function Select 0 GPIO_B[0] pin is working as Normal GPIO Function 1 GPIO_B[0] : SD_CKE (clock enable for SDRAM) of memory controller 6-6 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO_B Test Select Register (GTSEL_B) 31 30 29 28 27 26 25 24 0 15 14 13 12 0x8000031C 23 EXT 11 10 9 8 22 21 20 19 GST[2:0] 7 6 18 17 16 1 0 0 5 4 3 2 IDE *) if a bit is set to 1, and the corresponding bit of GSEL_B is 0, GPIO pin is used by the other dedicated function blocks. EXT [24] GPIO_B[24] Function Select 0 GPIO_B[24] pin is working as Normal GPIO Function or I2S Data Output 1 GPIO_B[24] pin is working as EXTCLK from Clock Controller IDE [9] GPIO_B[9] Function Select 0 GPIO_B[9] pin is working as Normal GPIO Function or UART Data Input 1 GPIO_B[9] pin is working as chip select 1 for IDE GST[2:0] [23:21] GPIO_B[23:21] Function Select 0 GPIO_B[23:21] pin is working as Normal GPIO Function GST[2] = 1 GPIO_B[23] pin is working as FRM of 1 of 4 GSIO blocks GST[1] = 1 GPIO_B[22] pin is working as SCK of 1 of 4 GSIO blocks GST[0] = 1 GPIO_B[21] pin is working as SDO of 1 of 4 GSIO blocks *) this bit field is only valid only if the corresponding bit of GSEL_B is set to 0 6-7 CHAPTER 7 CLOCK GENERATOR TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 7 Preliminary Spec 0.51 CLOCK GENERATOR 7.1 Functional Description In TCC720, there are a lot of peripherals for which has different operating frequency. To support an appropriate stable clock to each other peripherals, TCC720 has clock generator unit and for considering power consumption there is also power management unit that can manage several operating modes, such as initialization mode, normal operation mode, idle mode, stop mode. The simple block diagram of clock generator is as followings. PWRDN WAITGEN XIN PLL PLLmode i_XIN WAIT PLLOUT [18] DIVCLK1 MUX 0 1 i_XIN PLLOUT i_XIN PLLOUT FCLK 0 XTIN 1 PCLK source MUX [22] 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 SCK GEN PCLK SCLKmode MUX HCLK DCLK GEN DCLK [15:14] DCLKmode [15:14] EXCLKmode EXTCLK GEN [15:14] UTCLKmode UTCLK GEN UTCLK UBCLKmode UBCLK GEN UBCLK [7:6] [7:6] TCLKmode [7:6] GCLKmode MUX MUX MUX MUX MUX EXTCLK TCLK GEN TCLK GCLK GEN GCLK Figure 7.1 Clock Generator Block Diagram 7-1 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 WAITGEN cell is for waiting until oscillation is stabilized. It blocks internal clocks until about 2^18 number of XIN transition occurs after reset is released. If frequency of XIN is 16MHz, the wait time is about 16.4 ms The DIVCLK1 are used as main clock of TCC720 and it can be either an oscillator output or PLL output clock. It is the source of system clocks (FCLK, HCLK, PCLK). The PCLK can be also driven by XTIN. The other clocks each can be driven by one of 3 clock sources XIN, PLLOUT, XTIN independently by its mode register. DCO Control DCLK is used as the master clock of DAI (Digital Audio Interface) block when it’s mode is set to master mode. EXTCLK is used for external usage especially for CD application. UTCLK is used as the main clock of UART controller. These clocks are generated by 14bit DCO (Digital Controlled Oscillator) that can generate a stable and variable frequency as long as its frequency is below about one tenth of the divisor clock. For reliable operation of DAI, divisor clock frequency must be higher than about 200 MHz. But maximum frequency of ARM940T is lower than 120MHz, the division factor for FCLK must be greater than 2. The target frequency can be acquired by writing the phase value calculated by the following equation to the each PHASE register. D_PHASE = 214 * fDCLK / fDIV CV_PHASE = 214 * fCVCLK / fDIV EXT_PHASE = 214 * fEXTCLK / fDIV UT_PHASE = 214 * fUTCLK / fDIV For example, when you use 44.1KHz sampling rate and want to set DCLK as 256fs, the target frequency of DCLK is 256 * 44.1k = 11.2896 MHz, and if you set PLL to 266MHz, the D_PHASE value must be set to 696 ( ~= 214 * 11.2896 / 266). 7-2 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 7.2 Register Description Clock Generator Register Map (Base Address = 0x80000400) Name Address Type Reset Description CKCTRL 0x00 R/W 0x0003FFE PLLMODE 0x04 R/W 0x03806 PLL Control Register SCLKmode 0x08 R/W 0x082000 System Clock Control Register DCLKmode 0x0C R/W 0x0800 DCLK (DAI/CODEC) Control Register EXTCLKmode 0x14 R/W 0x0000 EXTCLK (CD/Other) Control Register UTCLKmode 0x18 R/W 0x01BE UTCLK (UART) Control Register UBCLKmode 0x1C R/W 0x00 UBCLK (USB) Control Register TCLKmode 0x24 R/W 0x00 TCLK (Timer) Control Register GCLKmode 0x28 R/W 0x00 GCLK (GSIO) Control Register SW_nRST 0x3C R/W 0x3FFF Clock Control Register Software Reset for each peripherals Clock Control Register (CKCTRL) 31 30 29 28 27 26 Reserved 15 14 13 0 0 0 12 0x80000400 25 24 23 22 21 20 XTIN PLL 10 - 9 8 7 GCK TCK 18 17 16 3 2 1 0 0 PDN IDLE 11 19 - 6 5 4 USB UART EXT - CDC DAI PCK This controls various sources of clocks fed to each peripherals. If each control bit is set to 1, the corresponding clock is disabled and the peripherals use that clock are also disabled. To enable the clock, clear the control bit to 0. Power down and Idle mode bit are write-only register, and it is always 0 when read CKCTRL register. PDN [25] 1 IDLE [24] 1 Power Down Mode TCC720 goes to power down mode. All blocks disabled. Idle Mode TCC720 goes to idle mode. Only ARM is disabled. 7-3 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 XTIN [12] 1 Sub Clock Control Disable XTIN Clock PLL [11] 1 PLL Control Disable PLL block GCK [9] 1 GSIO Control Disable GSIO block TCK [8] 1 Timer Control Disable Timer block USB [6] 1 USB Control Disable USB block UART [5] 1 UART Control Disable UART block EXT [4] 1 EXT Clock Control Disable External Clock Output (EXCLK pin) CDC [2] 1 Preliminary Spec 0.51 CODEC Control Disable internal CODEC block. If DAI is disabled, internal CODEC is also disabled. DAI [1] 1 DAI Control Disable DAI block If DAI is disabled, internal CODEC is also disabled. PCK [0] PCLK Control 1 Disable PCLK clock (Interrupt Control block, EFM, CIRC block, GSIO block, and ADC block are disabled) 7-4 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 PLL Control Register (PLLmode) 31 30 29 28 27 0x80000404 26 25 24 23 22 21 20 0 15 14 13 12 11 10 18 17 XTE DIV1 9 8 M XTE [19] 7 6 0 0 5 4 3 2 16 S 1 0 P XTIN mode select 0 XTIN is disabled when power down is requested. 1 XTIN is only controlled by XTIN bit of CKCTRL register DIV1 [18] Divisor Clock1 Select 0 Use Oscillator as DIVCLK1 1 Use PLL output as DIVCLK1 S/M/P S/M/P 19 PLL Frequency Setting fPLL = (M + 8) * fXin / ((P + 2) * 2S ) The TCC720 has one PLL for generating of internal main clock. This internal PLL can generate the required frequency by setting internal register. The desired frequency can be acquired by the following equation. fPLL = (M + 8) * fXin / ((P + 2) * 2S ) Where, M, P, S can be set by PLLmode register. M has 8bit resolution, P has 6bit resolution, and S has 2bit resolution. PLL has standby mode for minimizing power consumption that can be controlled by PLL bit of CKCTRL register. 7-5 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 System Clock Control Register (SCLKmode) 31 30 29 28 27 26 25 24 0 15 14 HS 0 13 12 11 10 9 H_PHASE 8 0x80000408 23 22 PS XTI 7 6 0 0 21 20 19 18 17 16 1 0 P_PHASE 5 4 3 2 F_PHASE It generates FCLK, HCLK, PCLK for system operation. FCLK is dedicated for ARM940T processor, HCLK is used as internal AHB bus clock, and PCLK is for APB bus clock. Each clock is generated by 6bit DCO (Digital Controlled Oscillator) that can generate a stable and variable frequency as long as its frequency is below about 0.1 times of that of divisor clock. For reliable operation, keep the n power of 2 relationships with divisor clock. The target frequency can be acquired by writing the phase value calculated by the following equation to the PHASE register. PHASE = 26 * fSCLK / fDIV PS,XTI [23:22] PCLK Clock Select 00 use DIVCLK1 as a divisor clock of PCLK generator 01 use XTIN pin as a divisor clock of PCLK generator 1x use FCLK as a divisor clock of PCLK generator P_PHASE [21:16] n (!= 0) 0 PCLK Frequency Select fPCLK = fDIV * n / 2 6 fPCLK = fDIV or fXTIN (depends on PS, XTI bit) *) The DIVCLK1 is selected by DIV1 bit of PLLmode register. HS [15] HCLK Clock Select 0 use DIVCLK1 as a divisor clock of HCLK generator 1 use FCLK as a divisor clock of HCLK generator H_PHASE [13:8] n (!= 0) 0 HCLK Frequency Select fHCLK = fDIV * n / 2 6 fPCLK = fDIV or fFCLK (depends on HS bit) F_PHASE [5:0] n (!= 0) 0 FCLK Frequency Select fFCLK = fDIV * n / 26 fPCLK = fDIV 7-6 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 DCLK (DAI/CODEC) Control Register (DCLKmode) 31 30 29 28 27 26 25 24 0x8000040C 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 10 9 8 D_PHASE[13:0] DIVD DIVD [15:14] DCLK Divisor Clock Select 0 use XIN as a divisor clock of DCLK generator 1 use PLL output as a divisor clock of DCLK generator 2, 3 use XTIN pin as a divisor clock of DCLK generator D_PHASE [13:0] d (!= 0) 0 DCLK Clock Frequency Select fDCLK = fDIV * d / 214 fDCLK = fDIV *) The divisor clock is selected by DIVD field of PLLmode register. DCLK is also controlled by DAI bit of CKCTRL register that can enable or disable DCLK. If this bit is set to high, DCLK is disabled and if it is low, DCLK is enabled. DCLK is for DAI and internal CODEC requires 512*fs frequency. To make DCLK of this frequency, first set the frequency of PLL (fDIV) more higher than 512*fs and set D_PHASE according to the above formulae. It is recommended to set the frequency of PLL by the n power of 2, than the duty ratio of DCLK is only dependant of that of PLL clock. 7-7 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 EXTCLK Control Register (EXTCLKmode) 15 14 13 12 11 10 9 DIVXT 0x80000414 8 7 6 5 4 use XIN pin as a divisor clock of EXTCLK generator 1 use PLL output as a divisor clock of EXTCLK generator 0 use XTIN pin as a divisor clock of EXTCLK generator EX_PHASE [13:0] 0 1 EXTCLK Divisor Clock Select 0 e (!= 0) 2 EX_PHASE[13:0] DIVXT [15:14] 2, 3 3 EXTCLK Clock Frequency Select fEXTCLK = fDIV * e / 2 14 fEXTCLK = fDIV *) The divisor clock is selected by DIVXT bit of EXTCLKmode. EXTCLK is also controlled by EXT bit of CKCTRL register that can enable or disable EXTCLK. If this bit is set to high, EXTCLK is disabled and if it is low, EXTCLK is enabled. External clock is user-programmable clock that can be used various purposes, it is not used by internal peripherals, and by setting GPIO registers, GPIO_B24 pin can output this clock to user application board. Care must be taken not to use too high frequency that the GPIO_B24 pin cannot cope with this signals, or the GPIO_B24 pin show no clock signal out. 7-8 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UTCLK (UART) Control Register (UTCLKmode) 15 14 13 12 11 10 9 DIVUT 8 7 0x80000418 6 5 4 use XIN pin as a divisor clock of UTCLK generator 1 use PLL output as a divisor clock of UTCLK generator 0 use XTIN pin as a divisor clock of UTCLK generator UT_PHASE [13:0] 0 1 UTCLK Divisor Clock Select 0 u (!= 0) 2 UT_PHASE[13:0] DIVUT [15:14] 2, 3 3 UTCLK Clock Frequency Select fUTCLK = fDIV * u / 2 14 fUTCLK = fDIV *) The divisor clock is selected by DIVUT bit of UTCLKmode. UTCLK is also controlled by UART bit of CKCTRL register that can enable or disable UTCLK. If this bit is set to high, UTCLK is disabled and if it is low, UTCLK is enabled This clock is used by UART. For reliable communication with host side, this clock has the frequency of 3.6864MHz or so. The UART clock is then divided by DL register in UART block, it is not so important to maintain the duty ratio of 50%. 7-9 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UBCLK (USB) Control Register (UBCLKmode) 31 30 29 28 27 26 25 24 0x8000041C 23 22 21 20 19 18 17 16 8 7 6 5 4 3 2 1 0 DIVUB 0 0 0 15 14 13 12 11 10 9 0 UB_PHASE[5:0] UBCLK is used as the main clock of USB block. It is generated by a DCO that has 6bit resolution, and its frequency is set by writing the phase value calculated by the following equation to the UB_PHASE register. UB_PHASE = 26 * fUBCLK / fDIV UBCLK is also controlled by USB bit of CKCTRL register that can enable or disable UBCLK. If this bit is set to low, UBCLK is enabled and if it is high, UBCLK is disabled. DIVUB [9:8] UBCLK Divisor Clock Select 0 use XIN pin as a divisor clock of UBCLK generator 1 use PLL output as a divisor clock of UBCLK generator 2, 3 use XTIN pin as a divisor clock of UBCLK generator UB_PHASE [5:0] ub (!= 0) 0 UBCLK Clock Frequency Select fUBCLK = fDIV * ub / 2 6 fUBCLK = fDIV *) The divisor clock is selected by DIVUB bit of UBCLKmode. UBCLK is also controlled by USB bit of CKCTRL register that can enable or disable UBCLK. If this bit is set to high, UBCLK is disabled and if it is low, UBCLK is enabled 7 - 10 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 TCLK (Timer) Control Register (TCLKmode) 31 30 29 28 27 26 25 0x80000424 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 0 0 15 14 13 12 11 10 0 DIVT [9:8] 9 8 DIVT TC_PHASE[5:0] TCLK Divisor Clock Select 0 use XIN pin as a divisor clock of TCLK generator 1 use PLL output as a divisor clock of TCLK generator 2, 3 use XTIN pin as a divisor clock of TCLK generator TC_PHASE [5:0] tc (!= 0) 0 TCLK Clock Frequency Select fTC = fDIV * tc / 26 fTC = fDIV *) The divisor clock is selected by DIVT field of TCLKmode. 7 - 11 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GCLK (GSIO) Control Register (GCLKmode) 31 30 29 28 27 26 25 24 0x80000428 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 0 0 15 14 13 12 11 10 0 DIVG [9:8] 9 8 DIVG GC_PHASE[5:0] GCLK Divisor Clock Select 0 use XIN pin as a divisor clock of GCLK generator 1 use PLL output as a divisor clock of GCLK generator 2, 3 use XTIN pin as a divisor clock of GCLK generator GC_PHASE [5:0] gc (!= 0) 0 GCLK Clock Frequency Select fGC = fDIV * gc / 26 fGC = fDIV *) The divisor clock is selected by DIVG field of GCLKmode. 7 - 12 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Software Reset Register (SW_nRST) 31 30 29 28 27 26 0x8000043C 25 24 23 22 21 20 19 18 17 16 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 DMA 1 ETC 1 1 1 GS UT UB GP TC IC DAI DMA [12] DMA Block Reset Control 1 Reset for DMA is released 0 Reset for DMA is generated ETC [10] Miscellaneous Block Reset Control 1 Reset for Miscellaneous Block is released 0 Reset for Miscellaneous Block is generated *) Miscellaneous block contains ADC and CODEC control register and leading zero counter register, etc. GS [6] GSIO Block Reset Control 1 Reset for GSIO is released 0 Reset for GSIO is generated UT [5] UART/IrDA Block Reset Control 1 Reset for UART/IrDA is released 0 Reset for UART/IrDA is generated UB [4] USB Block Reset Control 1 Reset for USB is released 0 Reset for USB is generated GP [3] GPIO Block Reset Control 1 Reset for GPIO is released 0 Reset for GPIO is generated TC [2] Timer/Counter Block Reset Control 1 Reset for Timer/Counter is released 0 Reset for Timer/Counter is generated 7 - 13 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 IC [1] Interrupt Controller Block Reset Control 1 Reset for Interrupt Controller is released 0 Reset for Interrupt Controller is generated DAI [0] Preliminary Spec 0.51 DAI/CDIF Block Reset Control 1 Reset for DAI/CDIF is released 0 Reset for DAI/CDIF is generated 7 - 14 CHAPTER 8 USB CONTROLLER TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 8 Preliminary Spec 0.51 USB (Universal Serial Bus) CONTROLLER 8.1 Overview The TCC720 supports a fully compliant to USB 1.1 specification, full-speed (12 Mbps) functions and suspend/resume signaling. The USB controller is compatible with both OpenHCI and Intel UHCI standards. The USB function controller has an endpoint EP0 for control and two in/output endpoints EP1/EP2 for bulk data transaction. The endpoint EP0 has a single 16 byte FIFO; Max packet size is 16 bytes. And the endpoint EP1 and EP2 have a dual 128 byte FIFO, respectively; Max packet size of EP1 and EP2 is 64 bytes. There are 4 types of internal registers; IN_CSR (IN Control Status Register), OUT_CSR (OUT Control Status Register), IN_MAXP (IN Maximum Packet size Register), and OUT WRITE COUNT. Interrupt (Status) and Interrupt Enable registers are broken down into 2 banks: Endpoint Interrupts, USB Interrupts. The MAXP, ENDPOINT INTERRUPT and ENDPOINT INTERRUPT ENABLE registers are used regardless of the direction of the endpoint. The associated CSR registers correspond to the direction of endpoint. 8-1 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 8.2 Register Description USB Register Map (Base Address = 0x80000500) Name Address Type Reset Description NON INDEXED REGISTERS UBFADR 0x00 R/W Function Address Register UBPWR 0x04 R/W Power Management Register UBEIR 0x08 Endpoint Interrupt Register UBIR 0x18 USB Interrupt Register UBEIEN 0x1C Endpoint Interrupt Enable Register UBIEN 0x2C Interrupt Enable Register UBFRM1 0x30 Frame Number 1 Register UBFRM2 0x34 Frame Number 2 Register UBIDX 0x38 Index Register COMMON INDEXED REGISTER MAXP 0x40 IN Max Packet Register IN INDEXED REGISTERS INCSR1 0x44 IN CSR1 Register (EP0 CSR Register) INCSR2 0x48 IN CSR2 Register OUT INDEXED REGISTERS OCSR1 0x50 OUT CSR1 Register OCSR2 0x54 OUT CSR2 Register OFIFO1 0x58 OUT FIFO Write Count 1 Register OFIFO2 0x5C OUT FIFO Write Count 2 Register FIFO REGISTERS EP0FIFO 0x80 - EP0 FIFO Register EP1FIFO 0x84 - EP1 FIFO Register EP2FIFO 0x88 - EP2 FIFO Register 8-2 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Function Address Register (UBFADR) 15 14 13 12 11 Reserved 10 9 0X80000500 8 7 6 5 4 UP 3 2 1 0 FADR UP [7] Function Address Update UP = 0 Function address doesn’t be updated UP = 1 Function address can be updated with FADR * The MCU sets this bit whenever it updates the FADR field. This bit is write only register. FADR [6:0] Function Address n Function address This register maintains the USB Device Address assigned by the host. The control program should write the value received through a SET_ADDRESS descriptor from host to this register. The address is used for the next token. The UP bit field should be set whenever the FADR field is written. The FADR field is used after the Status phase of a Control transfer, which is signaled by the clearing of the DATA_END bit in the endpoint EP0 CSR. 8-3 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Power Management Register (UBPWR) 15 14 13 12 11 10 9 Reserved 0x80000504 8 7 6 5 4 - - - - 3 2 1 0 RST RSM SP ENSP RST [3] Type Reset Signal 1 R Indicates that 1 reset signaling is received from the host RSM [2] Type Resume Signal 1 R/W Initiates a resume signaling (10 ~ 15 ms duration) SP [1] Type Suspend Mode 1 R Indicates that the USB enters suspend mode ENSP [0] Type Enable Suspend Mode 0 R/W Disable Suspend Mode 1 R/W Enable Suspend Mode This register is used for suspend, resume and reset signaling. If ENSP filed is zero, the device will not enter suspend mode. The SP bit field is set by the USB when it enters suspend mode. It is cleared when you clear the RSM bit field by writing zero or when the resume signal from host is received. The USB generates resume signaling while RSM bit is set in suspend mode. The RST bit field is set by USB when reset signal is received from the host. 8-4 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Endpoint Interrupt Register (UBEIIR) 15 14 13 12 11 10 9 0x80000508 8 Reserved 7 6 5 4 3 - - - - - 2 1 EP2 EP1 EP0 EP[2:0] [2:0] Type EP Interrupt Flag if bit n is 1 R Indicates that the USB EP interrupt has been generated USB Interrupt Register (UBIR) 15 14 13 12 11 10 0 0x80000518 9 8 Reserved 7 6 5 4 3 - - - - - 2 1 0 RST RSM SP RST [2] Type Reset Interrupt Flag 1 R Indicates that the USB has received reset signaling RSM [1] Type Resume Interrupt Flag 1 R Indicates that the USB has received resume signaling in suspend mode SP [0] Type 1 R Suspend Interrupt Flag Indicates that the USB has received suspend signalizing Suspend signal is implicit signal that is generated if there is no activity for 3ms. The USB controller has two interrupt registers: Endpoint interrupt register and USB interrupt register. These registers act as status registers when interrupt is generated. Once interrupt generated, it is needed to read all the interrupt registers and write back to all the registers to clear the interrupt. The endpoint interrupt register UBEIR has three bit fields that correspond to the respective endpoints. 8-5 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 USB CONTROLLER Preliminary Spec 0.51 The EP0 interrupt is generated under the following conditions: 1. OUT Packet is ready. ORDY field is set in the CSR register 2. IN Packet is ready. IRDY field is set in the CSR register 3. SENT STALL is set 4. SETUP END is set 5. DATA END is cleared (End of control transfer) The EP1/E2 interrupt is generated under the following conditions: For IN endpoints 1. IRDY field is cleared in the CSR register 2. FIFO is flushed 3. SENT STALL is set For OUT endpoints 1. ORDY field is set in the CSR register. 2. SENT STALL is set The suspend interrupt is generated when the USB receives suspend signaling. The SP bit field of the UBIR is set whenever there is no activity for 3ms on the bus. This interrupt is disabled in default. The resume interrupt is generated by a USB reset in suspend mode. The USB reset interrupt is generated when USB controller receives the reset signaling from the host. 8-6 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Endpoint Interrupt Enable Register (UBEIEN) 15 14 13 12 11 10 9 8 Reserved 0x8000051C 7 6 5 4 3 - - - - - 2 14 13 12 11 10 9 0 EP2 EP1 EP0 USB Interrupt Enable Register (UBIEN) 15 1 0x8000052C 8 Reserved 7 6 5 4 3 - - - - - 2 1 0 RST RSM SP Corresponding to each interrupt register, there is an INTERRUPT ENABLE register (except resume interrupt enable). By default, the USB reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled. Frame Number 1 Register (UBFRM1) 15 14 13 12 11 10 9 0x80000530 8 7 6 5 Reserved 4 3 2 14 13 12 11 0 FRM1 Frame Number 2 Register (UBFRM2) 15 1 10 9 0x80000534 8 Reserved 7 6 5 4 3 2 1 0 FRM2 There are two registers, UBFRM1 and UBFRM2, which inform the frame number received from the host. The UBFRM1 denotes the lower byte of frame number. The UBFRM2 denotes the higher byte of frame number. Frame number = [UBFRM2[7:0] : UBFRM1[7:0]] 8-7 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 USB Index Register (UBIDX) 15 14 13 12 11 0x80000538 10 9 8 7 6 5 4 Reserved 3 2 1 0 IDX This Index register is used to indicate the endpoint number while accessing the indexed registers: MAXP, INCSR1/2, OCSR1/2, OFIFO1/2. *) The following registers denoted by suffix letter of ‘n’ are index register. Index register means that its address is shared by each end point blocks. So if you want to access the indexed registers of EP0, write 0 to the index register ahead, and for EP1 write 1 to the index register, and so on. Max Packet Register (MAXPn) 15 14 13 12 11 Reserved 10 0x80000540 9 8 7 6 5 4 3 - - - - - MAXP[2:0] [2:0] Type Max Packet Number n R/W Max packet is 8*n 2 1 0 MAXP 8-8 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IN CSR1 Register (INCSR1n) 15 14 13 12 11 Reserved 0x80000544 10 9 8 7 6 - 5 4 3 CTGL STST ISST FLFF 2 - 1 0 FNE IRDY CTGL [6] Type Clear Data Toggle Bit 1 W The data toggle bit is cleared STST [5] Type STALL Handshake Issued 1 R Indicates that the STALL handshake is issued 0 W Clear by writing 0 ISST [4] Type Issue STALL Handshake 1 R/W Start issuing a STALL Handshake 0 R/W Clear to end STALL condition FLFF [3] Type Issue FIFO Flush 1 R/W IN FIFO is flushed 0 R This bit is cleared by the USB when the FIFO is flushed. The interrupt is generated when this happens. If a token is in progress, the USB waits until the transmission is complete before the FIFO is flushed. If two packets are loaded into the FIFO, only the top-most packet (one that was intended to be sent to the host) is flushed, and the corresponding IRDY bit for that packet is cleared. FNE [1] Type IN FIFO Not Empty 0 R/W Indicates that no packet of data is in IN-FIFO 1 R/W Indicates that at least one packet of data is in IN-FIFO IRDY [0] Type IN Packet Ready 0 R Indicates that the packet has been successfully sent to host 1 W After writing a packet of data into the IN-FIFO, set this bit to 1. 8-9 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 EP0 CSR Register (EP0CSR) 15 14 13 12 11 0x80000544 10 9 Reserved 8 7 6 5 4 3 2 1 0 CLSE CLOR ISST CEND DEND STAL IRDY ORDY *) EP0 CSR register can access by writing “0” to UBIDX register, and use same address as INCSR1. CLSE [7] Type Clear Setup End Bit 1 W The SEND bit is cleared CLOR [6] Type Clear Output Packet Ready Bit 1 W The ORDY bit is cleared ISST [5] Type Issue STALL Handshake 1 R/W Start issuing a STALL Handshake. At the same time, it clears ORDY bit if it decodes an invalid token 0 W End the STALL condition CEND [4] Type Control Setup End 1 R Indicates that the control transfer ends before DEND bit is set 0 R Indicates that the CLSE is written by “1”. At the same time, the USB flushes the FIFO, and invalidates access to the FIFO. That is, when the access to the FIFO is invalidated, this bit is cleared. DEND [3] Type 1 R Data End Indicates that the one of the following conditions matched. - after loading the last packet of data into the FIFO. (at the same time IRDY is set) - while it clears ORDY after unloading the last packet of data. - for a zero length data phase (at the same time, it clears ORDY and sets IRDY) STAL [2] Type IN Packet Ready 1 R Indicates that a control transaction is ended due to a protocol violation 8 - 10 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IRDY [1] Type IN Packet Ready 0 R Indicates that the packet has been successfully sent to host 1 W After writing a packet of data into EP0 FIFO, set this bit to 1. ORDY [0] Type 0 R Indicates that the CLOR has been set to “1” 1 R Indicates that a valid token is written to the FIFO OUT Packet Ready IN CSR2 Register (INCSR2n) 15 14 13 12 11 0x80000548 10 9 Reserved 8 7 6 - ASET [6] 3 2 1 0 - - - - Auto Set User set IRDY flag when interrupt. 1 IRDY is set automatically. ISO Select 0 Configures endpoint to Bulk mode 1 Configures endpoint to ISO mode ( Not support ) MDIN [4] 4 ASET ISO MDIN 0 ISO [5] 5 IN/OUT Select 0 Corresponding EPn is configured as OUT Mode 1 Corresponding EPn is configured as IN Mode 8 - 11 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 OUT CSR1 Register (OCSR1n) 15 14 13 12 11 10 0x80000550 9 8 Reserved 7 6 5 4 CTGL STST ISST FLFF 3 2 - - 1 0 FFL ORDY CTGL [7] Type Data Toggle Bit 1 R The data toggle sequence bit is reset to DATA0 STST [6] Type STALL Handshake Issued 1 R Indicates that the OUT token is ended with a STALL handshake ISST [5] Type Issue STALL Handshake 1 R/W Start issuing a STALL Handshake 0 R/W End the STALL Condition FLFF [4] Type Issue FIFO Flush 1 R/W OUT FIFO is flushed 0 R/W Stop flushing FIFO FFL [1] Type OUT FIFO Full 1 R ORDY [0] Type OUT Packet Ready 0 R Indicates that once the MCU reads the FIFO for all the packet 1 R Once it has loaded a packet of data into the FIFO. Indicates that no more packets can be accepted OUT CSR2 Register (OCSR2n) 15 14 13 12 11 Reserved 10 0x80000554 9 8 7 6 5 4 3 2 1 0 ACLR - - - - - - - ACLR [7] Type Auto Clear 1 R/W Whenever the MCU reads data from the OUT FIFO, ORDY of OCSR1n will automatically be cleared by the core, without any intervention from MCU. 8 - 12 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 OUT FIFO Write Count 1 Register (OFIFO1n) 15 14 13 12 11 10 9 8 0x80000558 7 6 5 Reserved 4 3 2 14 13 12 11 0 OFIFO1n OUT FIFO Write Count 2 Register (OFIFO2n) 15 1 10 9 8 0x8000055C 7 6 5 Reserved 4 3 2 1 0 OFIFO2n There are two register, OFIFO1n and OFIFO2n, which maintain the write count. OFIFO1n maintains the lower bytes, while OFIFO2n maintains the higher byte. When ORDY bit of OCSR1n is set for OUT endpoints, these registers maintain the number of bytes in the packet due to be unloaded by the MCU. EP0 FIFO Register (EP0FIFO) 15 14 13 12 11 0x80000580 10 9 8 7 6 5 4 Reserved 3 2 14 13 12 11 0x80000584 10 9 8 7 6 5 4 Reserved 3 2 14 13 12 11 Reserved 1 0 FIFO EP2 FIFO Register (EP2FIFO) 15 0 FIFO EP1 FIFO Register (EP1FIFO) 15 1 0x80000588 10 9 8 7 6 5 4 3 2 1 0 FIFO 8 - 13 CHAPTER 9 UART/IrDA CONTROLLER TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 9 Preliminary Spec 0.51 UART / IrDA 9.1 Functional Description The TCC720 has 1 simple UART module that can be used in programming the system software or IrDA interfacing. The block diagram of UART is in the following figure. LSR APB CR Receiver FIFO Receiver Shift RZ code Demod RXD Transmit FIFO Transmit Shift RZ code Modulator TXD DL IR Interrupt Generator IREQ IrDACFG2 IrDACFG1 Figure 9.1 UART Block Diagram This UART is simplified version of UART16550, it provides only a simple interface (TXD, RXD) between host system and TCC720 system. In the UART, there are two FIFO blocks for transmission and receiving link. Transmission FIFO has 4 bytes depth, receiving FIFO has 8 bytes depth. UART can also be used as IrDA interfacing. There is a signal transformer between IrDA signal and UART signal. 9-1 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 9.2 Register Desciption UART/IrDA Register Map (Base Address = 0x80000600) Name Address Type Reset Description RXD 0x00 R - Receiver Buffer Register TXD 0x00 W - Transmitter Holding Register DL 0x04 R/W 0x0000 Divisor Latch Register IR 0x08 R/W 0x000 Interrupt Register CR 0x0C R/W 0x000 UART Control Register LSR 0x10 R 0x0101 Status Register IrDACFG1 0x14 R/W 0x0003 IrDA Configuration Register 1 IrDACFG2 0x18 R/W 0x4da1 IrDA Configuration Register 2 9-2 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Receiver Buffer Register (RXD) 31 30 29 28 27 26 0x80000600 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 10 9 8 0 Received Data (when reading) Whenever FRX flag of IR register is set, or RA flag of LSR register is set, reading of this register gets the 1 byte of received data. Transmitter Holding Register (TXD) 31 30 29 28 27 26 0x80000600 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 10 9 8 0 Transmitting Data (when writing) When the transmission FIFO is not full, writing of this register fills that data to transmission FIFO. Checking TF flag of LSR register can monitor the status of a transmission FIFO. Divisor Latch Register (DL) 31 30 29 28 27 0x80000604 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Divisor Latch Value This is for generation of the desired baud rate clock. This register is set to 0 at reset, UART is disabled until this register is set by non-zero value. The value should be equal to (UART clock speed) / (16 * desired baud rate). The UART clock is generated by clock generator block. It is recommended that the frequency of UART clock is set to 3.6864MHz, so the desired baud rate can be acquired by writing (230400/baud rate) to DL register. 9-3 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Interrupt Register (IR) 31 30 29 28 0x80000608 27 26 25 24 23 22 21 20 19 18 17 16 0 15 14 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 ERS ETX ERX 0 FRS FTX FRX 0 QRS QTX QRX ERS [10] Receiver Line Status Interrupt 0 disabled 1 enabled ETX [9] Transmitter Holding Register Empty Interrupt 0 disabled 1 enabled ERX [8] Receiver Data Available Interrupt 0 disabled 1 enabled FRS [2] Flag for Receiver Line Status Interrupt 0 Interrupt has not generated 1 Interrupt has generated, but not cleared FTX [1] Flag for Transmitter Holding Register Empty Interrupt 0 Interrupt has not generated 1 Interrupt has generated, but not cleared FRX [0] Flag for Receiver Data Available Interrupt 0 Interrupt has not generated 1 Interrupt has generated, but not cleared *) FLS, FTX, FRX is set or cleared regardless of each enable settings. QRS [2] Request for Receiver Line Status Interrupt 0 Interrupt has not generated 1 Interrupt has generated, but not cleared 9-4 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 QTX [1] Request for Transmitter Holding Register Empty Interrupt 0 Interrupt has not generated 1 Interrupt has generated, but not cleared QRX [0] Request for Receiver Data Available Interrupt 0 Interrupt has not generated 1 Interrupt has generated, but not cleared *) QRLS, QTHE, QRDA is only set when each enable bit is set to 1. 9-5 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UART/IrDA Control Register (CR) 31 30 29 28 27 26 0x8000060C 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 ST B7 0 15 14 13 12 0 11 10 9 8 7 6 NO BK TF RF FIFO PR NO [9] Start Bit Width Check 0 Check if the pulse width of start bit is more than 0.5 bit duration of baud rate 1 Don’t check the pulse width of start bit (used only for test or boot mode) BK [8] Break Control Bit 0 Normal operation 1 Bit ‘0’ is transmitted regardless of THR TF [7] Reset Transmitter FIFO 1 The transmitter FIFO is cleared RF [6] Reset Receiver FIFO 1 The receiver FIFO is cleared FIFO [5:4] RX FIFO Level Select n 0 = 1byte FIFO, 1 = 2 byte FIFO 2 = 4 byte FIFO, 3 = 7 byte FIFO *) This field controls the RDA(Receive Data Available) flag or interrupt only, that is the actual FIFO depth can’t be modified and fixed to 8. If this field is set to 1, it means that the RDA flag or interrupt is influenced when the number of received data in the RX FIFO is 2. It is recommended that this field is set to 0, so right after reception of some data, the RDA flag or interrupt can be generated. PR [3:2] Parity Bit Select 0 Even parity 1 Odd parity 2, 3 Parity is disabled 9-6 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 ST [1] Stop Bit 0 1 Stop bit 1 2 Stop bit B7 [0] Number of Bits per Character 0 8 bit 1 7 bit Preliminary Spec 0.51 9-7 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Line Status Register (LSR) 31 30 29 28 27 0x80000610 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 TE TF FE PE RA 0 15 14 13 12 11 10 9 8 0 TE [4] Transmitter FIFO 0 Not empty 1 Empty *) Transmitter FIFO depth is fixed to 4. TF [3] Transmitter FIFO 0 Not full 1 Full *) Transmitter FIFO depth is fixed to 4. FE [2] Framing Status 0 Correct stop bit is received 1 The received data in the FIFO don’t have valid stop bit PE [1] Parity Status 0 Correct parity bit is received 1 The received data in the FIFO don’t have valid parity bit RA [0] Received FIFO Status 0 No data has received 1 At least 1 received data is in the FIFO 9-8 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IrDA Configuration Register 1 (IrDACFG1) 31 30 29 28 27 26 25 0x80000614 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 EN P1 POL LB 11 10 9 8 0 PW EN [15] IrDA TX Enable 0 IrDA TX is disabled, UART mode is used 1 IrDA TX is enabled P1 [14] Transmit Pulse Type 0 Pulse width is proportional to selected baud speed 1 Pulse width is proportional to UART base clock speed POL [13] Transmit Pulse Polarity 0 TX ‘0’ data is converted to level high pulse 1 TX ‘0’ data is converted to level low pulse LB [12] Loopback 0 Normal operation 1 Transmitted data is fed back to RX port. PW [3:0] IrDA RZ Pulse Width n Represents pulse width of TX ‘0’ data. If n = 3, during 3/16 of its 1 bit period or 3 * 3686400-1 sec, the high pulse is generated 9-9 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IrDA Configuration Register 2 (IrDACFG2) 31 30 29 28 27 26 25 0x80000618 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 EN P1 POL 0 11 10 9 8 DEC MAX1 MIN1 EN [15] IrDA RX Enable 0 IrDA RX is disabled, UART mode is used 1 IrDA RX is enabled P1 [14] Receiver Pulse Type 0 Received pulse width is proportional to selected baud speed 1 Received pulse width is proportional to UART base clock speed POL [13] Receive Pulse Polarity 0 The polarity of received data is not inverted 1 The polarity of received data is inverted DEC [11:8] RX Data Decision Time n The decision point for receiving data, its unit has 1/16 of baud rate. MAX1 [7:4] Maximum number of “1”s n The maximum number of “1”s to decide the received IrDA (RZ) signal as 0. If P1 is set to 1, MAX1 has the unit of 1/1843200 sec, or if P1 is set to 0, the unit of MAX1 has 1/16 of baud rate. MIN1 [3:0] n Minimum number of “1”s The minimum number of “1”s to decide the received IrDA (RZ) signal as 0. If P1 is set to 1, MIN1 has the unit of 1/1843200 sec, or if P1 is set to 0, the unit of MIN1 has 1/16 of baud rate. 9 - 10 CHAPTER 10 GSIO PORT TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 10 Preliminary Spec 0.51 GSIO (General Purpose Serial Input/Output) PORT The TCC720 has three GSIOs for communication between the TCC720 and other devices that have serial interface. All the pins in the GSIOs are multiplexed with GPIOs. User can program what these multiplexed pins are used for. The GSIO block has 4 pins; SDI, SDO, SCK, FRM. The SDO is the serial data output pin, the SDI is the serial data input pin, the SCK is the serial clock pin and the FRM is frame pin. The base clock is generated by dividing the PCLK programming the GSIO control register GSCR. The SCK is generated from the basic clock in every data transfers. Various types of serial interface can be programmed using GSIO control field in the GSCR. There are 5 control registers for GSIOs; GSCR0, GSCR1, GSCR2, GSCR3, and GSICR. The start time of transfer can be controlled with programming the delay counter field in the GSCRn. The base counter increments at every base clock right after writing the data into the GSDRn. The serial data starts to come out when delay counter value are same to base counter value. The word size of transfer can be programmed from 1 bit to 16 bits. The frame1 and the frame2 fields specify the start and end point of transition based on base counter. The frame polarity defines whether the frame signal is low active or high active signal. The Last Clock mask filed is for special serial interface, which makes the last clock pulse masked. PCLK /2 n Divider base_clk SDI GSDI divider factor n SDO GSDO word_size SCK Counter Serial CLK Generator GSCR frame1, frame2 Frame Coparator GSFC FRM Figure 10.1 GSIO Block Diagram 10 - 1 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GSIO Register Map (Base Address = 0x80000700) Name Address Type Reset Description GSDO0 0x00 R/W GSIO0 Output Data Register GSDI0 0x04 R/W GSIO0 Input Data Register GSCR0 0x08 R/W GSIO0 Control Register GSGCR 0x0C R/W GSIO Global Control Register GSDO1 0x10 R/W GSIO1 Output Data Register GSDI1 0x14 R/W GSIO1 Input Data Register GSCR1 0x18 R/W GSIO1 Control Register GSDO2 0x20 R/W GSIO2 Output Data Register GSDI2 0x24 R/W GSIO2 Input Data Register GSCR2 0x28 R/W GSIO2 Control Register GSDO3 0x30 R/W GSIO3 Output Data Register GSDI3 0x34 R/W GSIO3 Input Data Register GSCR3 0x38 R/W GSIO3 Control Register GSIOn Output Data Register (GSDO0, GSDO1, GSDO2, GSDO3) 31 30 29 28 27 26 25 24 23 22 21 0x800007x0 20 19 Reserved 15 14 13 12 11 10 9 18 17 16 WORD[3:0] 8 7 6 5 4 3 2 1 0 Data to GSIO Output Pin WORD[3:0] [19:16] GSIO word size n GSIO data has (n+1) bit unit, n = 0 ~ 15 *) This field is valid only if WS of GSCRn register is set to 1. GSIOn Input Data Register (GSDI0, GSDI1, GSDI2, GSDI3) 31 30 29 28 27 26 25 24 23 0x800007x4 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Data from GSIO Input Pin *) These registers is updated every writing to GSDO registers. 10 - 2 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GSIOn Control Register (GSCR0, GSCR1, GSCR2, GSCR3) 31 30 EN MS 15 14 0 29 28 27 26 WORD 13 12 DELAY FP 11 25 24 23 22 WS 10 9 21 0x800007x8 20 19 18 DIV 8 7 6 5 4 FRM1 3 17 16 CP CM 1 0 2 FRM2 EN [31] GSIO Enable 0 GSIO Disabled 1 GSIO Enabled MS [30] First Bit Select 0 LSB first 1 MSB first WORD [29:26] GSIO word size n GSIO data has (n+1) bit unit, n = 0 ~ 15 WS [25] Word Size Select 0 GSIO word size is determined by WORD of GSCRn register 1 GSIO word size is determined by BW of GSDO register DIV [24:18] GSIO base clock speed control n GSIO base clock has 1/(2n+2) of PCLK frequency, n = 0 ~ 127 CP [17] GSIO clock polarity 0 SDO changes at SCK falling 1 SDO changes at SCK rising CM [16] Last clock mask 0 No mask. GSIO clock is generated for every SDO. 1 GSIO clock is masked at the last SDO period. DELAY [14:13] Initial delay for serial transmission n GSIO transmission starts after n base clock has generated. 10 - 3 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 FP [12] Frame pulse polarity 0 FRM has low active pulse 1 FRM has high active pulse FRM1 [11:6] Frame pulse start position n Frame pulse starts after n base clock has generated FRM2 [5:0] Frame pulse end position n Frame pulse ends after n base clock has generated GSIO Global Control Register (GSGCR) 31 30 29 28 27 26 25 0x8000070C 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 G3 G2 G1 G0 IEN3 IEN2 IEN1 IEN0 FLG3 FLG2 FLG1 FLG0 Busy3 Busy2 Busy1 Busy0 G[3:0] [15:12] GPIO_B[23:21] Other Function Signal Select if bit n is 1 FRM, SCK, SDO output of GSIOn is come out from GPIO_B[23:21] *) If multiple bit of G[3:0] is set to 1, the output of each GSIO is orred and come out from GPIO_B[23:21] IEN[3:0] [11:8] GSIO Interrupt Enable if bit n is 1 GSIOn Interrupt is enabled 0 GSIOn Interrupt is disabled FLG[3:0] [7:4] R/W GSIO Interrupt Flag if bit n is 1 R GSIOn operation (read/write) has been completed. if bit n is 1 W Clear FLG[n] field *) If an interrupt of a GSIO is enabled, GSIO interrupt is generated when the GSIO operation is completed. These FLGn can be used to distinguish which GSIO has generated the interrupt. These flags are cleared by writing “1” at the corresponding flag. Busy[3:0] [3:0] GSIO Cycle Busy Flag if bit n is 0 GSIOn transmission has finished, and can transmit another serial data. if bit n is 1 GSIOn transmission is in operation, so it cannot accept another serial data. 10 - 4 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 The following figures represent some kinds of various GSIO operations. div_factor = 1 ; div4 = 2*(1+1) word_size = 7 ; 8bits = 7+1 init_delay = 2, clk_pol = 0 frame_pol = 1 frame1 = 18, frame2 = 20 last_clk_mask = 0 PCLK 0 1 2 3 4 5 6 7 8 9 10 .... 14 15 16 17 18 19 20 18 19 20 18 19 20 base clk SDO D1 D0 D2 .... D3 D6 D7 SCK FRM clk_pol = 1 0 1 2 3 4 5 6 7 8 9 10 .... 14 15 16 17 base clk SDO D1 D0 D2 .... D3 D6 D7 SCK FRM frame1 = 17, frame2 = 19 last_clk_mask = 1, clk_pol = 1 0 1 2 3 4 5 6 7 8 9 10 .... 14 15 16 17 base clk SDO D0 D1 D2 D3 .... D6 D7 SCK FRM Figure 10.2 GSIO operation 10 - 5 CHAPTER 11 MISCELLANEOUS PERIPHERALS TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 11 Preliminary Spec 0.51 MISCELLANEOUS PERIPHERALS 11.1 ADC The TCC720 has 3-input general purpose low-power ADC for battery level detection, remote control interface, touch screen interface, etc. It is a CMOS type 8bit/10bit changeable A/D converter which combines suitable blocks for various purpose such as an analog input multiplexer, auto offset calibration comparator, 8bit/10bit changeable successive approximation register (SAR), etc. Various operating option can be set by using ADCCON register, it can convert up to 8 analog input and be operated as 10bit ADC at about 200ksps rates, as well as 8bit ADC at about 250ksps rates. It has standby mode for power consumption also. The output of ADC can be read from the ADCDATA register. ADC Control Register (ADCCON) 31 30 29 28 27 26 0x80000A00 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 10 9 8 0 ADEN [8:5] adc ADEN Sample Rate = fPCLK / ((adc+1) * 16) ADC Standby Select 1 ADC goes to standby mode 0 ADC starts operating M8 [3] ADC Bit Select 1 Select 8bit conversion mode 0 Select 10bit conversion mode n ASEL ADC Sample Rate Select STB [4] ASEL [2:0] STB M8 ADC Input Select ADINn pin is selected as ADC input signal (n = one of 0, 2, 4) 11 - 1 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 ADC Data Register (ADCDATA) 31 30 29 28 27 26 0x80000A04 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 10 9 8 0 ADATA [10:1] adc ADATA FLG ADC Data When 8bit mode, lsb 2bit must be ignored. When 10bit mode, ADC data = adc FLG [0] ADC Status Flag 1 A/D conversion is finished, data is stable 0 A/D conversion is on processing, data is unstable 11 - 2 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 11.2 CODEC The TCC720 has on-chip sigma delta type 16bit audio stereo CODEC for high grade digital audio en-decoder systems. It contains various blocks such as compensation filter, digital volume attenuator, de-emphasis filter, FIR filter, sinc filter, digital sigma-delta modulator, analog postfilter, anti-image filter, etc. CODEC Control Register (CDC_CTRL) 31 30 29 28 27 26 0x80000A08 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 0 12 11 10 ZID ZC 9 8 AIS EMP IIS ZID [11] FSEL RST DA AD Zero Input Detection Control 0 DAC Zero Input Detection is enabled 1 DAC Zero Input Detection is disabled *) If the input data has the condition where the lower 4bits of the input data are DC and the remaining upper bits are all “0” or all “1” has continued 8192 cycles of LRCK (=32fs), then zero input is detected, and the analog postfilter output will be immediately forced to VREF. ZC [10] Zero Cross Enable Control 0 DAC Zero Cross Enable Control is disabled 1 DAC Zero Cross Enable Control is enabled *) If DAC postfilter output data has the condition where it is cross VREF reference level, DAC programmable gain amplifier control register is up-dated. It is used to improve click and popnoise. If ZC is 0, DAC Programmable Gain Control Register is modified by CDC_GAIN register. AIS [9] Analog Input Selection 0 LCH_IN and RCH_IN input is processed 1 MIC_IN input is processed EMP [8] De-emphasis Control 0 De-emphasis is disabled 1 De-emphasis is enabled *) This bit is only useful when 44.1KHz mode. 11 - 3 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 IIS [7] Data Format Select 0 16bit Right Justified Mode is selected 1 16bit IIS Mode is selected FSEL [6:5] 0, 3 Preliminary Spec 0.51 Sample Frequency Select 32KHz, 44.1KHz, 48KHz mode (System clock must be 256*fs) 1 16KHz, 22.05KHz mode (System clock must be 512*fs) 2 8KHz, 11KHz mode (System clock must be 512*fs) RST [4] Reset Signal 0 ADC, DAC reset is released 1 ADC, DAC reset is generated DA [3:2] DAC Mode Selection 00 DAC normal operation mode 01 DAC mute OFF, DAC power down ON 10 DAC mute ON , DAC power down OFF 11 DAC mute ON , DAC power down ON AD [1:0] ADC Mode Selection 00 ADC normal operation mode 01 ADC mute OFF, DAC power down ON 10 ADC mute ON , DAC power down OFF 11 ADC mute ON , DAC power down ON 11 - 4 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 CODEC Gain Control Register (CDC_GAIN) 31 30 29 28 27 26 25 0x80000A0C 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 10 9 8 0 ADR [5:4] ADR Gain Register Select 00 ADC Left Channel is selected 01 ADC Right Channel is selected 10 DAC Left Channel is selected 11 DAC Right Channel is selected DATA [3:0] n DATA Gain Data When ADR field selects ADC Gain, ADC gain = 1.5 * n dB When ADR field selects DAC Gain, DAC gain = - 2.0 * n dB 11 - 5 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 11.3 ETCETERA Count Leading Zero Register (CLZ) 31 30 29 28 27 26 0x80000A10 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLZ[31:16] 15 14 13 12 11 10 9 8 7 CLZ[15:0] When X is written to CLZ register, the number of zero counting from MSB of X can be calculated by reading CLZ register. If the value returned by reading CLZ register is Y, the number of zero counting from MSB of X is 32 – Y. USB Port Control Register (USB_CTRL) 31 30 29 28 27 26 25 0x80000A14 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 12 11 10 9 8 0 PSL CNT OVR SW *) Must be remained to 0 TEST Mode Register (TSTSEL) 31 30 29 28 27 26 0x80000A18 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 B2 B1 AC 0 15 14 13 12 11 10 0 9 8 US1 US0 *) Must be remained 0 11 - 6 CHAPTER 12 DMA CONTROLLER TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 12 Preliminary Spec 0.51 DMA CONTROLLER 12.1 Functional Description TCC720 has a simple 1-channel DMA controller for data transfer. It can be used to transfer data from some kind of memory block to other kind of memory block. The block diagram of DMA controller is in the following figure. ST_SADR ST_DADR SINC DINC C_SADR C_DADR CH_CTRL DMSK AHB SMSK Address Calculator State Control Machine Figure 12.1 DMA Controller Block Diagram There are various kinds of transfer modes for DMA operation. The following table represents each type of transfer according to CHCTRL register. Table 12.1 Type of DMA transfer LOCK (CHCTRL[11]) TYPE (CHCTRL[10:8]) Description 0 000 SINGLE type transfer without LOCK 1 000 SINGLE type transfer with LOCK 0 001 HW_ARBIT type transfer without LOCK 1 001 HW_ARBIT type transfer with LOCK 0 or 1 101 HW_BURST type transfer 0 010 SW_ARBIT type transfer without LOCK 1 010 SW_ARBIT type transfer with LOCK 0 or 1 110 SW_BURST type transfer 12 - 1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 DMA CONTROLLER Preliminary Spec 0.51 In SINGLE type transfer, 1 Hop of transfer occurs only once at every DMA requests. The 1 Hop of transfer means 1 burst read followed by 1 burst write. 1 burst means 1, 2 or 4 consecutive read or write cycles defined by CHCTRL[7:6] field. Hardware type transfer (HW_ARBIT, HW_BURST) means that the DMA transfer triggered by external or internal hardware blocks selected by CHCTRL[28:16] field. This field has same mapping with interrupt enable flag of interrupt controller, so the DMA transfer can be occurred as like as interrupt is generated. Software type transfer (SW_ARBIT, SW_BURST) means that the DMA transfer triggered by CHCTRL[0] flag (enable flag). When this flag is set to 1, the DMA transfer begins at the same time. Arbitration type transfer (HW_ARBIT, SW_ARBIT) means that at the end of every HOP transfer, the AHB bus is released from DMA channel so other master can occupy the bus when the master has requested the bus. Burst type transfer (HW_BURST, SW_BURST) means that once the DMA transfer occurs, all of transfers are executed without further DMA requests. Lock field controls the LOCK signal (refer to AHB specification), so that when the LOCK is set to 1, the corresponding transfer doesn’t be bothered by other AHB masters like LCD controller, ARM etc. This field is only meaningful for non-burst type of transfers. 12 - 2 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 12.2 Register Description DMA Controller Register Map (Base Address = 0x80000E00) Name Address Type Reset ST_SADR 0x00 R/W - Start Address of Source Block SPARAM 0x04/0x08 R/W - Parameter of Source Block C_SADR 0x0C R - Current Address of Source Block ST_DADR 0x10 R/W - Start Address of Destination Block DPARAM 0x14/0x18 R/W - Parameter of Destination Block C_DADR 0x1C R - Current Address of Destination Block HCOUNT 0x20 R/W 0x00000000 Initial and Current Hop count CHCTRL 0x24 R/W 0x00000000 Channel Configuration CLRDRQ 0x28 W - Description Clear End of DMA flag Start Source Address Register (ST_SADR) 31 30 29 28 27 26 25 24 0x80000E00 23 22 21 20 19 18 17 16 5 4 3 2 1 0 ST_SADR[31:16] 15 14 13 12 11 10 9 8 7 6 ST_SADR[15:0] *) This register contains the start address of source block for DMA transfer. The transfer begins reading data from this address. Start Destination Address Register (ST_DADR) 31 30 29 28 27 26 25 24 23 0x80000E10 22 21 20 19 18 17 16 5 4 3 2 1 0 ST_DADR[31:16] 15 14 13 12 11 10 9 8 7 6 ST_DADR[15:0] *) This register contains the start address of destination block for DMA transfer. 12 - 3 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Source Block Parameter Register (SPARAM) 31 30 29 28 27 26 25 24 0x80000E04 / 0x80000E08 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SMASK[23:8] 15 14 13 12 11 10 9 8 7 SMASK[7:0] SINC[7:0] SMASK [23:8] Source Address Mask Register 0 non-masked 1 masked *) Each bit field controls the corresponding bit of source address field. That is, if SMASK[23] is set to 1, the 28th bit of source address is masked, and if SMASK[22] is set to 1, the 27th bit of source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is unchanged during DMA transfer. This function can be used to generate circular buffer address. SINC [7:0] Source Address Increment Register sinc Source address is added by amount of sinc at every write cycles. sinc is represented as 2’s complement, so if SINC[7] is 1, the source address is decremented. The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected during DMA transfer. If the source or destination address reaches its maximum address space like 0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not from 0x80000000 or 0x30000000. 12 - 4 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Destination Block Parameter Register (DPARAM) 31 30 29 28 27 26 25 24 0x80000E14 / 0x80000E18 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DMASK[23:8] 15 14 13 12 11 10 9 8 7 DMASK[7:0] DINC[7:0] DMASK [23:8] Destination Address Mask Register 0 non-masked 1 masked *) Each bit field controls the corresponding bit of source address field. That is, if DMASK[23] is set to 1, the 28th bit of source address is masked, and if DMASK[22] is set to 1, the 27th bit of source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is unchanged during DMA transfer. This function can be used to generate circular buffer address. DINC [7:0] Destination Address Increment Register dinc Destination address is added by amount of dinc at every write cycles. dinc is represented as 2’s complement, so if DINC[7] is 1, the destination address is decremented. The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected during DMA transfer. If the source or destination address reaches its maximum address space like 0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not from 0x80000000 or 0x30000000. 12 - 5 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Current Source Address Register (C_SADR) 31 30 29 28 27 26 25 24 0x80000E0C 23 22 21 20 19 18 17 16 5 4 3 2 1 0 C_SADR[31:16] 15 14 13 12 11 10 9 8 7 6 C_SADR[15:0] *) This register contains current source address of DMA transfer. Current Destination Address Register (C_DADR) 31 30 29 28 27 26 25 24 23 0x80000E1C 22 21 20 19 18 17 16 5 4 3 2 1 0 C_DADR[31:16] 15 14 13 12 11 10 9 8 7 6 C_DADR[15:0] *) This register contains current destination address of DMA transfer. HOP Count Register (HCOUNT) 31 30 29 28 27 26 0x80000E20 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 C_HCOUNT[15:0] 15 14 13 12 11 10 9 8 7 6 ST_HCOUNT[15:0] C_HCOUNT [31:16] cn ST_HCOUNT [15:0] sn Current Hop Count Represent cn number of Hop transfer remains Start Hop Count Represent sn number of Hop transfer is transferred. *) At the beginning of transfer, the C_HCOUNT is stored by ST_HCOUNT register. And at the end of every hop transfer, this is decremented by 1 until reached to 0. 12 - 6 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Channel Control Register (CHCTRL) 31 30 29 28 27 26 0x80000E24 25 24 0 15 22 21 20 19 18 17 16 4 3 2 1 0 REP EN DMASEL[12:0] 14 CONT 23 13 PRI 12 11 LOCK 10 9 8 TYPE 7 6 BSIZE 5 WSIZE FLAG IEN DMASEL [28:16] Select Source of DMA Request non-zero Each bit field selects corresponding signal as a source for DMA request. The bit-map of this register is identical with the IEN of interrupt controller. So if you want to use EXINT0 pin as a source of DMA request, set DMASEL[0] as 1 and select HW_ARBIT or HW_BURST type transfer. If multiple bits of this register is set, all the corresponding signal can generate DMA request for this channel. CONT [15] 0 1 Issue Locked Transfer DMA transfer begins from ST_SADR / ST_DADR address DMA transfer begins from C_SADR / C_DADR address It must be used after the former transfer has been executed, so that C_SADR and C_DADR contains meaningful values. PRI [14:12] Priority 0 non-zero Priority 0 is equal to disable DMA transfer DMA channel is enabled only when have non-zero priority. LOCK [11] Issue Locked Transfer 0 DMA transfer executed without lock property 1 DMA transfer executed with lock property *) Lock field controls the LOCK signal (refer to AHB specification), so that when the LOCK is set to 1, the corresponding transfer doesn’t be bothered by other AHB masters like LCD controller, ARM etc. This field is only meaningful for non-burst type of transfers. TYPE [10:8] Transfer Type 000 SINGLE transfer 001 HW_ARBIT transfer 101 HW_BURST transfer 010 SW_ARBIT transfer 110 SW_BURST transfer *) Please refer to table 12.1 for detailed information of each transfer types. 12 - 7 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BSIZE [7:6] Preliminary Spec 0.51 Burst Size 0 1 Hop transfer consists of 1 pair of read and write cycle. 1 1 Hop transfer consists of 2 pair of read and write cycle 2, 3 1 Hop transfer consists of 4 pair of read and write cycle WSIZE [5:4] Word Size 0 byte transfer 1 half word transfer 2, 3 word transfer FLAG [3] DMA Flag 1 Represents that all hop of transfers are fulfilled IEN [2] 1 Interrupt Enable At the same time FLAG goes to 1, DMA interrupt request is generated. *) To generate IRQ or FIQ interrupt, the corresponding enable bit in the interrupt controller must be set to 1 ahead. CONT [1] 0 Continuous Transfer After all of hop transfer has executed, the DMA channel is disabled The DMA channel remains enabled, so when another DMA request has 1 occurred, the DMA channel start transfer data again with the same manner (type, address, increment, mask) as the latest transfer of that channel. *) This bit is only valid if the transfer type is hardware and non-burst type transfer. EN [0] DMA Channel Enable DMA channel is disabled or terminated. 0 Once terminated, user must make HCOUNT to 0 not to continue transfer after channel is re-enabled. DMA channel is enabled. If software type transfer is selected, this bit 1 generates DMA request directly, or if hardware type transfer is used, the interrupt request generates DMA request. 12 - 8 CHAPTER 13 MEMORY CONTROLLER TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 13 Preliminary Spec 0.51 MEMORY CONTROLLER 13.1 Overview TCC720 has a memory controller for various kind of memory for digital media en-decoding system. It can manipulate SDRAM, Flash (NAND, NOR type), ROM, SRAM type memories, and also support the IDE interface for HDD or USB2.0 device. It has configurable data bus width through the GPIO pin or each configuration register. The data bus width can be configured for each chip select separately The memory controller provide the power saving function for SDRAM (self refresh). The following figure represents the block diagram of memory control unit. SDCFG SDRAM State Machine Refresh Controller AHB SDRAM Signal Generator Remap Flag Signal Mixer Memory Control Signals ExtMEM Signal Generator CSCFGn ExtMEM State Machine Figure 13.1 Memory Controller Block Diagram The registers for memory controller block have the base address of 0xF0000000. 13 - 1 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Memory Controller Register Map (Base Address = 0xF0000000) Name Address Type Reset SDCFG 0x00 R/W SDFSM 0x04 R - MCFG 0x08 R/W 0xZZZZ_02 TST 0x0C W 0x0000 CSCFG0 0x10 R/W 0x0B405601 CSCFG1 0x14 R/W 0x0150569A CSCFG2 0x18 R/W 0x0060569A Description 0x4268A020 SDRAM Configuration Register SDRAM FSM Status Register Miscellaneous Configuration Register Test mode register (must be remained zero) External Chip Select 0 Configuration Register (Initially set to SRAM) External Chip Select 1 Configuration Register (Initially set to IDE) External Chip Select 2 Configuration Register (Initially set to NAND) NAND flash Register Map (Base Address = N * 0x10000000) Name Address Type Reset Description CMD 0x00 R/W - Command Cycle Register LADDR 0x04 W - Linear Address Cycle Register BADDR 0x08 W - Block Address Cycle Register IADDR 0x0C W - Single Address Cycle Register DATA 0x10 R/W - Data Access Cycle Register *) N represents BASE field of CSCFGn registers. 13 - 2 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 13.2 SDRAM Controller SDRAM controller can control from 64Mbit up to 256Mbit SDRAM. In TCC720 system, the SDRAM contains almost parts for system operation. (program, data, ESP buffer, etc is located in SDRAM). The SDRAM parameter such as size, refresh period, RAS to CAS delay, refresh to idle delay can be programmed by internal register. The registers for SDRAM controller is as the followings. Refer to SDRAM cycle diagram in figure 13.2 SDRAM Configuration Register (SDCFG) 31 30 CL BW 15 14 RD0 29 28 27 CW 13 RP 26 25 0xF0000000 24 23 SDBASE 12 11 10 9 22 21 20 RC 8 7 RW 19 18 RCD 6 5 4 3 17 16 RD[2:1] 2 1 0 Refresh *) The reset value means the following configuration. CL=2cycle, CW=8bit, BW=16bit, SDBASE=2, RC =3, RCD=2, RD=1, RP=2, RW=12bit, Refresh=0x20 CL [31] CAS Latency (tCL) 0 CAS latency is 2 cycle 1 CAS latency is 3 cycle BW [30] Bus Width Select 0 Bus width for SDRAM is 32 bit 1 Bus width for SDRAM is 16 bit CW [29:28] CAS Width 0, 1 8 bit is used for CAS address 2 9 bit is used for CAS address 3 10 bit is used for CAS address 13 - 3 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 SDBASE [27:24] SDRAM Base Address N Indicates the MSB 4bit of SDRAM area. That is SDRAM base = 0xN0000000 RC [23:21] Delay of Refresh to Idle (tRC) n n number of HCLK cycle is used to meet the refresh to idle delay time RCD [20:18] n Delay of RAS to CAS (tRCD) (n+1) number of HCLK cycle is used to meet the RAS to CAS delay time RD [17:15] Delay of Read to Precharge (tRD) n n number of HCLK cycle is used to meet the read to precharge time RP [14:12] Delay of Precharge to Refresh (tRP) n (n+1) number of HCLK cycle is used to meet the precharge to refresh time RW [11] RAS Width 0 12bit is used for RAS address bus 1 13bit is used for RAS address bus Refresh [10:0] n Refresh Cycle Every (n * 16 + 15) number of HCLK cycle has passed, the SDRAM refresh request is generated. If on going cycle has finished, the refresh cycle starts. Real refresh period depends on the period of HCLK. SDRAM FSM Status Register (SDFSM) 31 30 29 28 27 26 25 0xF0000004 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 15 14 13 0 12 11 10 9 8 SDFSM *) Represents current status of finite state machine in the SDRAM controller. 13 - 4 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 SDRAM Write Cycle (Non-sequential) SDCLK SDnCS nRAS tDO nCAS XA tRCD RAS CAS0 CAS1 DQ0 DQ1 DQM0 DQM1 WR Cmd WR Cmd nWE DQ DQM RAS Cmd Stop Cmd SDRAM Read Cycle (Row Actived) SDCLK SDnCS nRAS nCAS nWE tCL DQ DQ0 DQ2 DQ3 tCL DQM RD Cmd Stop Cmd SDRAM Precharge / Refresh Cycle SDCLK SDnCS nRAS nCAS tRP nWE DQ tRC tRD Valid PreC Cmd RFR Cmd Memory controller goes to IDLE state Figure 13.2 SDRAM Cycle Diagram 13 - 5 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 13.3 Miscellaneous Configuration In this register, there is various special flag for TCC720 system. One of them is for supporting boot PROM. In initialization, the lower address space (0x00000000 ~ 0x0FFFFFFF) is mapped to internal or external boot ROM but after initialization, a kind of RAM must be mapped to these space as the system program including interrupt vector table is located in this area. To satisfy this requirement, TCC720 provide RM flag. BM flag is used to select the boot procedure between the 7 kinds of them. Refer to chapter of boot mode for details. BM flag is determined at the rising edge of the nRESET pin, and contains the state of GPIO_A[10:8] pin. BW flag is used to know the initial system bus width configuration. This flag is read-only, and contains the state of GPIO_A[5:4] pin at the rising edge of nRESET pin. So user can control the bus width by pulling up or down the GPIO_A[5:4] pin. 13 - 6 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Miscellaneous Configuration Register (MCFG) 31 30 29 28 27 26 25 24 0xF0000008 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 IM GPO RM 0 15 14 13 RDY 0 0 RDY [15] 12 11 BW 10 9 8 BM Type 0 R 1 0 JTEN SDEN SDS Bus Width Flag The state of READY pin is low. The state of READY pin is high. *) READY pin is used to extend the access cycle for the external memories, it controls directly the cycle of external memory access by setting the URDY bit of each configuration register or can be used as a flags by polling the state of this bit, especially it can be used as a ready signal of NAND flash. bw* [12:11] Type 00, 01 10 Bus Width Flag The corresponding memory is configured by 32bit data bus. R 11 The corresponding memory is configured by 16bit data bus. The corresponding memory is configured by 8bit data bus. *) bw is calculated by xoring the BW field of MCFG register and BW field of CSCFGn register, that is bw = BW(of MCFG) ^ BW(of CSCFGn). BW(of MCFG) is determined by status of GPIO_A[5:4] at the rising edge of nRESET signal. BM [10:8] Type Boot Mode 000 Booting procedure begins at the external memory attached at nCS3 001 Booting for downloading firmware by UART port using XIN as main clock 010 Booting for downloading firmware by UART port using XTIN as main clock 011 Booting from NAND flash without decryption process. 100 101 R Booting from NAND flash with decryption process. Booting from NOR flash with decryption process. 110 Booting from HPI bus interface. 111 Development mode: JTAG and SDRAM is enabled, and the base address of SDRAM is set to 0. The TCC721 is waiting for JTAG connection while toggling the GPIO_A[0] output. *) Except the case of BM == 0, the booting sequence always starts from the internal boot ROM. Refer to chapter of boot mode for more detailed information about booting procedure. 13 - 7 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 JTEN [5] 0 1 SDEN [4] 0 1 SDS [3] 0 1 Type R/W Master of Internal Memory Select JTAG port is disabled JTAG port is enabled Type R/W Master of Internal Memory Select SDRAM controller is disabled SDRAM controller is enabled Type R/W GPO [1] Type 0/1 R/W IM [2] Type 0 Preliminary Spec 0.51 SD_CLK output select SDRAM Clock is out from SD_CLK pin SD bit is out from SD_CLK pin SD_CLK output When SDS bit is high, this bit is out through SD_CLK pin SD_CLK output select Memory controller automatically into idle state, when there is no memory request during 4 cycle of HCLK. If memory request occur, R/W 1 memory controller can serve that request immediately. Memory controller is always active regardless of request state, unless power down or idle state begins. RM [0] Type 0 The area 0 (0x00000000 ~ 0x0FFFFFFF) space is mapped to internal / R/W 1 Remap Flag external boot ROM The area 0 space is released from boot ROM *) If external boot ROM is used, it is considered as default that it is attached to nCS3 chip select pin. In initialization, RM flag direct that the lower address space is mapped to internal or external boot PROM, as program running, the program contained in the internal or external boot ROM must set the RM flag to 1. After this flag is set to 1, the lower address space is released from boot PROM. This lower address space can be mapped to other memories including SDRAM or Flash by changing the base address of that memories. The RM flag can be restored to 0 by clearing bit [0] of 0xF0000008. The lower address space is remapped to boot ROM. Care must be taken not to illegally change the RM flag. 13 - 8 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 13.4 External Memory Controller External memory controller can control external memories such as NAND or NOR type flash memory and ROM, SRAM type memory. These memories are selected by nCS3 ~ nCS0 pins. The cycle parameter for accessing external memory can be configured by internal registers. In case of NAND flash, additional parameters for address, command, data cycles are provided. External Chip Select n Configuration Register (CSCFGn) 31 30 29 0 28 27 EPW 15 14 0 AMSK 13 12 26 25 BW 11 PSIZE 24 23 MTYPE 10 9 CLADR 8 22 0xF0000010 + n*4 21 20 CSBASE 7 6 5 STP 19 18 17 URDY RDY 4 3 0 2 PW 16 1 0 HLD *) The reset value means the following configuration for each chip select. Chip Select 0 : 16bit, SRAM, Base = 0x40000000, tSTP=0, tPW=1, tHLD=1 Chip Select 1 : 32bit, IDE, Base = 0x50000000, not use Ready, tSTP=2, tPW=4, tHLD=2 Chip Select 2 : 32bit, NAND, Base = 0x60000000, AMSK=1, PSIZE=1, cLADR=3, tSTP=2, tPW=4, tHLD=2 Chip Select 3 : 16bit, NOR, Base = 0x70000000, tSTP=2, tPW=4, tHLD=2 *bw [27:26] Bus Width Select 0, 1 Bus width = 32 bit 2 Bus width = 16 bit 3 Bus width = 8 bit *) The bw is determined by xoring the BW field of CSCFGn register with the BW field of MCFG register. MTYPE [25:24] Type of External Memory 0 NAND type 1 IDE type 2 SMEM_0 type (Byte write is not permitted. Ex : ROM, NOR flash) 3 SMEM_1 type (Byte write is permitted. Ex : SRAM) CSBASE [23:20] M Chip Select n Base Address Indicates the MSB 4bit of nCS[n] area. That is nCS[n] base = M * 0x10000000 13 - 9 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 URDY [19] 1 Preliminary Spec 0.51 Use Ready Ready / Busy signal monitoring is enabled The memory controller waits until the state of READY pin indicate that its access request has accomplished. RDY [18] 0 Ready / Busy Select The selected GPIO pin indicating the READY signal. The memory controller waits until this pin goes to high state. 1 The selected GPIO pin indicating the BUSY signal. The memory controller waits until this pin goes to low state. AMSK [14] 0 Address Mask Bit Upper half of data bus is masked to zero. *) In case of 16bit width NAND flash, the upper half byte must be held low, during address cycles. This bit must be set to zero. But if the system uses multiple NAND flashes by sharing a chip select but separating each data to 16 or 32bit data bus of TCC720, the AMSK must be set to 1, so the address can be fed to each NAND flashes. PSIZE [13:12] psize Page size of NAND Flash The size of one page for NAND type flash. It represents byte per page calculated by the following equation. 1 Page = 256 * 2psize CLADR [11:9] N Number of Cycle for Linear Address The number of linear address command cycle for NAND type flash. (N+1) cycle is used for generating linear address command. STP [8:6] N EPW,PW [5:3] N ( = 0~15 ) HLD [2:0] N Number of Cycle for Setup Time (tSH) N cycle is issued between the falling edge of nCS[n] and nOE / nWE. Number of Cycle for Pulse Width (tPW) (N+1) cycle is issued between the falling and rising edge of nOE / nWE. Number of Cycle for Hold Time (tHLD) N cycle is issued between the rising edge of nOE / nWE and nCS[n]. 13 - 10 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 The following figure displays the element cycle diagram for external memories. SMEM_0 Type Cycle (Bus width >= Data width) nCS XA nOE ADDR0 ADDR1 tPW tSH tHLD nWE tSH tHLD tPW tH DQR DQ DQW SMEM_0 Type Cycle (Bus width < Data width) nCS XA nOE ADDR0 ADDR1 tPW tPW tHLD tSH tH DQRL DQ DQRH SMEM_1 Type Cycle (Bus width >= Data width) nCS ADDR0 XA nOE ADDR1 tPW tSH tHLD nWE tSH tHLD tPW tH DQM1 DQM0 DQ1 DQ[15:8] DQ[7:0] DQ0 Figure 13.3 Basic Timing Diagram for External Memories In case of IDE type memories, there are two chip enable signals for it. In TCC720, each enable can be controlled by offset address space. ‘nCS0’ reflects that the offset address range of 0 ~ 0x1F is accessed, ‘nCS1’ reflects that 0x20 ~ 0x3F is accessed. For larger address than 0x3F, if bit5 of address value means which enable signal is activated. (0 to ‘nCS0’, 1 to ‘nCS1’) 13 - 11 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 In case of NAND flash type memories, there are several sub-registers for accessing. The followings are these sub-registers. (M is base field of CSCFGn register) Command Cycle Register (CMD) 31 30 29 28 27 26 0xM0000000 25 24 23 22 21 CMD3 15 14 13 12 11 20 19 18 17 16 2 1 0 CMD2 10 9 8 7 6 5 CMD1 4 3 CMD0 *) If bus width of NAND flash is more than 8bit, the CMD1 ~ 3 may be used as command register, otherwise only CMD0 is used as command register. The following values are an example commands for NAND flash of SAMSUNG. 0x00/0x01 : Page Read Command 0x50 : Spare Read Command 0x80 : Page Program Command 0x60 : Block Erase Command 0x70 : Status Read Command (status read command is generated by reading 0xM0000700 address, not 0xM0000000) *) Refer to corresponding datasheet of NAND flash chip for detailed command list. Linear Address Cycle Register (LADDR) 31 30 29 28 27 26 25 0xM0000004 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 LADDR[31:16] 15 14 13 12 11 10 9 8 7 LADDR[15:0] *) LADDR is used as the linear address for accessing NAND flash data. The number of cycle is determined by CLADR of CSCFGn register. Memory controller assumes that the byte per page is 512, so from the second cycle of address, LADDR[31:9] value is fed to NAND flash. Block Address Cycle Register (BADDR) 31 30 29 28 27 26 25 0xM0000008 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 BADDR[31:16] 15 14 13 12 11 10 9 8 7 BADDR[15:0] *) BADDR is used as the block address for accessing NAND flash data with a block unit. The number of cycle is determined by CLADR and PSIZE of CSCFGn register. 13 - 12 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Single Address Cycle Register (IADDR) 31 30 29 28 27 26 25 0xM000000C 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Reserved IADDR *) When CPU writes to this register, one cycle of address cycle is generated. Data Register (DATA) 31 30 29 28 0xM0000010 27 26 25 24 23 22 21 DATA3 15 14 13 12 11 DATA1 20 19 18 17 16 2 1 0 DATA2 10 9 8 7 6 5 4 3 DATA0 *) DATA3~1 may be used as the value of data register, otherwise only DATA0 is used as data register. The number of data cycle is dependent on the bus width of NAND flash and the data size of access cycle. 13 - 13 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 14.5 Internal Memories In TCC720, there is 64Kbytes of SRAM for general purposes and 4Kbytes of ROM for system initialization. SRAM area is dedicated to area 3 (0x30000000 ~ 0x3FFFFFFF), and also accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when there are no devices assigned to area 0. ROM area is dedicated to area E (0xE0000000 ~ 0xEFFFFFFF), and also accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when RM flag of MCFG register is cleared to 0. In case of internal ROM, the access speed is not enough to cope with that of system bus (AHB). So when the system bus clock is higher than about 40MHz, the ROM access cycle must be extended by inserting 1 wait cycle. This wait cycle is determined by writing any value to ROM area. When writing to address the bit 2 of which is 1 (such as 0xE0000004, 0xE000000C, 0xE0000014, …) , the wait cycle is to be inserted from the next ROM access cycle. On the other hand writing to address the bit 2 of which is 0 (such as 0xE0000000, 0xE0000008, 0xE0000010, …), the wait cycle is to be removed from the next ROM access cycle. The access time of internal SRAM is faster than that of internal ROM, so there is no need to extend access cycle for SRAM. 13 - 14 CHAPTER 14 BOOTING PROCEDURE TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 14 Preliminary Spec 0.51 BOOTING PROCEDURE In the TCC720, there is a internal boot ROM for system initialization process. It contains the fundamental routines for system initialization or firmware upgrading through various interface such as UART, HPI(Host Port Interface) BUS. There are 8 modes for booting procedure. It is selected by the state of GPIO_A[10:8] at nRESET going to high. The following table represents the boot mode of TCC720. Table 14.1 Booting Mode of TCC720 BM Description 1 F/W download from UART interface with XIN clock source 2 F/W download from UART interface with XTIN clock source 3 NAND boot with non-security NAND must be attached to chip select 2, and use only XD[7:0] 4 NAND boot with security NAND must be attached to chip select 2, and use only XD[7:0] 5 NOR boot with security NOR must be attached to chip select 3, and bus width can be configured by BW 6 HPI boot Processing for HPI bus cycle from HOST processor 7 Development mode JTAG and SDRAM is enabled, and the base address of SDRAM is set to 0. The TCC720 is waiting for JTAG connection while toggling the GPIO_A[0] output. 0 External boot External ROM must be attached to chip select 3 14 - 1 TCC720 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 BOOTING PROCEDURE Preliminary Spec 0.51 14.1 External Boot It support an external boot ROM. When external boot mode, the sequence begins from external ROM that is attached to nCS3. The bus width of external boot ROM can be determined by state of GPIO_A[5:4] at the rising edge of nRESET pin. If GPIO_A[5:4] == 0, the bus width is 16bit, if GPIO_A[5:4] == 1, it is 8bit, otherwise, it is 32bit. (Refer to the chapter of memory controller for more details) 14 - 2 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 14.2 UART Boot For the flexibility and safety of code transfer, there are 2 modes in TCC720 for selecting UART clock. One is using XIN clock divided by 8, the other is using XTIN clock. This can be selected by setting GPIO_A[10:8] appropriately as described in table 14.1. Normally, the frequency of UART need to be about 3.6864MHz. But that of XIN may be variable according to the applications. To compromise the difference of clock between TCC720 and host (most case it is a desktop PC), the code is transferred by 1 bit per 1 byte transmission. That is, although the UART transmission is accomplished by 1 byte unit, TCC720 take it as 1 bit transfer, so if the received character is not 0xFF it is regarded as 0, and if 0xFF is received, it is regarded as 1. So, to receive 32bit value, a host must transmit 32 bytes with MSB first order. Figure 14.1 illustrates the transmission of one 32bit value. Host Transmit Data = 0xABCD1234 TX (Host) FF 00 FF 00 FF 00 FF FF RX Regarded as 1 0 1 0 1 0 1 1 0xA Host Transmit Data = 0xABCD1234 0xB .... .... .... 00 00 FF FF 00 FF 00 00 0 0 1 1 0 1 0 0 0x3 0x4 Received Data is packed to 0xABCD1234 Figure 14.1 The waveform of UART transmission Because of TCC720 always regard none 0xFF data as ‘0’, it is more robust to set the baud rate of a host UART faster than that of TCC720. The baud rate of a host UART must be as fast as that the duration of the start bit is shorter than that of TCC720 and longer than the period of UART clock (XIN/8 or XTIN). But between each transfer cycles, it is recommended to make sufficient delay times for TCC720 to receive each data correctly. The procedure of boot code transmission is like as follows. Remember each bit is transferred by 14 - 3 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 1 byte unit. (0xFF or others) i) TCC720 enables UART as 9600 baud, none parity bit, 1 stop bit, and 7 data bits. ii) It receives initial code size of 16bit. iii) Receive a code of 32bit with order of MSB first and then 1 bit even parity information. iv) If parity check is succeeded, TCC720 transfer an acknowledgement of 0xFF, or it transfers 0x00, so a host must check if the transfer is succeeded or not. v) After all of codes are transferred TCC720 branches to address 0x00000000. This procedure is illustrated in figure 14.2. Mode Setting (9600 baud, None Parity, 1 Stop bit, 7 Data bits) Receive the size of Initial Codes ( = SIZE) consist of 16 consequtive bytes transfer with MSB first order Receive 1 word consist of 32 consequtive bytes transfer with MSB first order Receive 1 bit of parity Parity is even, that is, if the number of ones in the received word is even, the parity bit is 0. Parity OK ? No Yes Send ACK (= '0xff') Send NACK (= '0x00') Write the received code to SRAM SIZE = SIZE - 4 No SIZE == 0 ? Yes Jump to SRAM (0x00000000) Figure 14.2 UART booting procedure 14 - 4 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 14.3 NAND Boot There are 2 modes in TCC720 for booting from NAND flash. One is booting from NAND flash containing a pure F/W code, the other is booting from one containing an encrypted F/W code. This can be selected by setting GPIO_A[10:8] appropriately as described in table 14.1. The NAND flash is considered to be connected with nCS2, and the bus width is 8 bit regardless of bus width configuration through GPIO_A[5:4]. The supported NAND flash types are as follows. Table 14.2 Supported NAND flash types Size (bytes) Size of Page (bytes) Number of Page CADR* Device ID 1M 128 4K 3 6E 2M 256 4K 3 EA / 64 4M 256 8K 3 E3 / E5 8M 512 8K 3 E6 16M 512 16K 3 73 32M 512 32K 3 75 64M 512 64K 4 76 128M 512 128K 4 79 256M 2048 64K 5 AA / DA At first, TCC720 checks if the second byte of each spare area is ‘0xC4’ or not starting from the last page to first page. It considers the page of containing ‘0xC4’ at the second byte in that spare area as the start page of containing the initialization codes, so it copies those codes from NAND to internal SRAM. The amount of codes to be transferred is the size of page – 4. The last 4 bytes mean the start number of page which containing the main F/W codes. (TCC720 considers all memories as little endian. So the byte located first means least significant byte in 32bit number, and so on.) Regardless of encryption option, this initialization codes are not encrypted, so there is no need of decryption and TCC720 directly jump to the code just copied to internal SRAM(0x00000000). At this point, the register R0 contains the number of start page that contains the main F/W codes, and R5 contains page size. If you want change these value, modify these registers 14 - 5 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 before returning from the initialization code. The initialization code must be encapsulated by the entrance command of ‘STR LR, [SP - #4]!’, and the exit command of ‘LDR PC, [SP], #4’. This code may contain various routines such as memory configuration or user customized booting code itself. After the initialization code finishes, and the code returns by the above exit code, the main F/W copy code begins copy from the start page contained in R0 register. TCC720 copies the size of page – 8 bytes of codes per every page to the area starting from the address of ‘0x00000000’. You must configure this area appropriately before returning from the initialization code. In case of encrypted F/W code, it is decrypted and then copied to as like as in non-encrypted case. The next page number is consisted of 4 bytes and located at (the size of page – 7) ~ (the size of page – 4) in current page of data to be copied. The last 4 bytes in page of data are reserved for future use. If the next page number is equal to ‘0xFFFFFFFF’, that page is the last page containing F/W code. TCC720 copy F/W code until this number is acquired. Figure 14.3 illustrates the organization of NAND flash. 1 Page Spare area Last Page of NAND Start flag S0 C4 Start page number (= S0) S0 1st Code of F/W (Page size - 8 bytes) S1 next page number (= S1) S1 2nd Code of F/W (Page size - 8 bytes) S2 next page number (= S2) Sn Last Code of F/W (Page size - 8 bytes) Sequence of searching for 'C4' Initialization Code (Page size - 4 bytes) -1 Last page flag (= 0xFFFFFFFF) 1st Page of NAND Figure 14.3 The boot code structure in NAND flash 14 - 6 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 The procedure of booting from NAND flash is displayed in figure 14.4 Device code reading & Mode Setting (Bus width = 8bit, CADR register setting) N = last page number Read 2nd byte in spare data of page N Data == 0xC4 ? N=N-1 No Yes Copy (SIZE - 4) bytes from NAND to SRAM JUMP to SRAM (0x00000000) Initialization & Customization code is executed. It may or may not return to boot ROM N = Register R0 Read (SIZE - 8) bytes from NAND Encrypted ? Yes No Decrypt data Copy (SIZE - 8) bytes to Memory (starts from 0x00000000, can be SDRAM, SRAM by setting the base register of memory controller) Read the next page number N No N == 0xFFFFFFFF ? Yes Jump to 0x00000000 Figure 14.4 NAND boot procedure 14 - 7 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 14.4 NOR Boot with Security There are two modes for booting from NOR flash. One is booting from external ROM that is commonly used for various applications, and the other is booting from encrypted external ROM that can be used to hide one’s code from the non-authorized user. It can be selected by setting GPIO_A[10:8] appropriately as described in table 14.1. In both cases, the NOR flash must be connected via nCS3 signal. In case of non-encrypted mode, the F/W code in external flash is directly fetched to TCC720 without any other intermediate processing, but in case of encrypted mode, the F/W code in external flash is stored in encrypted value, so boot ROM must decrypt it ahead and then copy these codes to the other random accessible memories. Figures 14.5 illustrate the allocation map of encrypted F/W code in NOR flash. 1 byte 0x00000000 Size of Initialization Code (= SA = SA3*224 + SA2*216 + SA1*28 + SA0) SA0 0x00000004 SA2 24 SA3 16 8 Size of F/W Code (= SB = SB3*2 + SB2*2 + SB1*2 + SB0) SB0 0x00000008 SA1 SB1 SB2 SB3 Initialization Code Area (SA bytes) . . . Returning from these area, the register R0 contains the start address of F/W code SA + 8 R0 Main F/W Code Area (SB bytes) Figure 14.5 Allocation of encrypted F/W code 14 - 8 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 14.5 Development mode To ease the effort for starting development withTCC720, TCC720 provides development mode in booting. In this mode, JTAG interface is enabled and set cache & protection unit of TCC720 appropriately. The table 14.4 describes the region setting in this mode. Table 14.4 Region Settings in Development Mode Region # Start End I Cache D Cache Buffer Protection 0 0x00000000 0xFFFFFFFF Enabled Enabled Enabled Full Access 1 0x20000000 0x3FFFFFFF Enabled Disabled Enabled Full Access 2 0x40000000 0x4FFFFFFF Enabled Disabled Enabled Full Access 3 0x50000000 0x5FFFFFFF Enabled Disabled Enabled Full Access 4 0x60000000 0x6FFFFFFF Enabled Disabled Enabled Full Access 5 0x70000000 0x7FFFFFFF Enabled Disabled Enabled Full Access 6 0x80000000 0xFFFFFFFF Enabled Disabled Enabled Full Access 7 0x3000F000 0x3000FFFF Enabled Disabled Enabled Full Access *) The region of higher number has higher priority than that of the lower regions. That is, region 7 has highest priority and region 0 has lowest priority. After region setting finishes, it goes into a infinite loop toggling GPIO_A[0]. 14 - 9 CHAPTER 15 JTAG DEBUG INTERFACE TCC720 JTAG DEBUG INTERFACE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 15 Preliminary Spec 0.51 JTAG DEBUG INTERFACE The TCC720 has the ARM940T core as main controller, and JTAG interface for developing the application programs. It can be connected with Multi-ICE of ARM or other third party’s in-circuit emulator supporting for ARM940T core. With the use of in-circuit emulator, the user can easily develop the program for his or her own system. It provides hardware breakpoints, internal register monitoring, memory dump, etc. Refer to user’s manual of in-circuit emulator for more detail functions of it. 15 - 1 CHAPTER 16 PACKAGE DEMENSION TCC720 PACKAGE DIMENSION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 16 Preliminary Spec 0.51 PACKAGE DEMENSION 16.1 128-Pin TQFP 1 ~ 7o 64 98 63 99 62 100 61 101 60 102 59 103 58 104 57 105 56 106 55 107 54 108 53 109 52 110 51 111 50 112 49 113 48 114 47 TCC720 117 46 45 44 0.40BSC 0.18 0.05 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 33 11 34 128 10 35 127 9 36 126 8 37 125 7 38 124 6 39 123 5 40 122 4 41 121 3 42 120 2 43 119 1 118 0.15 116 0.60 115 +0.10 -0.01 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 0.10 97 12 16.00BSC 14.00BSC 96 16.00BSC 14.00BSC (0.80) 0.10 1.00 0.05 0.05 1.20MAX Figure 16.1 Package Dimension of 128-TQFP-1414 16 - 1