19-2936; Rev 0; 7/03 10.7Gbps Adaptive Receive Equalizer Features ♦ 3mm x 3mm Package ♦ Spans 30in (0.75m) of 6-mil FR-4 ♦ Spans 24ft (8m) of Coax ♦ Automatic Receive Equalization to Reduce ISI Caused by Path Losses ♦ Up to 10.7Gbps NRZ Data Operating Range ♦ Signal-Detect Output ♦ Output-Enable Control ♦ 135mW Power Consumption ♦ DC-Coupled Input and Output to Terminations as Low as 1.65V ♦ Differential or Single-Ended Operation ♦ +3.3V Core Power Supply Ordering Information Applications PART OC-192, 10GbE Switches and Routers OC-192, 10GbE Serial Modules TEMP RANGE MAX3805ETE High-Speed Signal Distribution PINPACKAGE -40°C to +85°C 16 Thin QFN PACKAGE CODE T1633F-3 Pin Configuration appears at end of data sheet. Typical Operating Circuit LINE CARD SWITCH CARD 1.8V 2.5V +3.3V 10Gbps CDR/SERDES 2 +3.3V VCC 2 2 SDO VCC2 2.5V SDI FR-4 STRIPLINE 2 MAX3805 MAX3805 SD EN 10Gbps SWITCH VCC2 Rx SDO 2 2 PC BOARD BACKPLANE Tx Rx VCC VCC1 2 2 SDI FR-4 STRIPLINE Tx SD EN VCC1 1.8V ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3805 General Description The MAX3805 is designed to provide up to 30in (0.75m) reach on 6-mil differential FR-4 transmission line, or up to 24ft (8m) on RG-188A/U type coaxial cable, for PRBS data from 9.95Gbps to 10.7Gbps. The MAX3805 adaptive equalizer reduces intersymbol interference, resulting in 20ps residual jitter after equalization. An internal feedback network controls the equalizer to automatically match frequency-dependent skin effect and dielectric losses. The MAX3805 provides LVCMOS-compatible output-enable and signaldetect functions. The MAX3805 has separate supply connections for the internal logic and I/O circuits. This allows the currentmode logic (CML) input and CML output to be connected to isolated supplies for independent DC-coupled interfaces to 1.8V, 2.5V, or 3.3V ICs. The MAX3805 comes in a very small 3mm x 3mm package and consumes only 135mW. MAX3805 10.7Gbps Adaptive Receive Equalizer ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) ............................................-0.5V to +4.0V CML Supply Voltage (VCC1, VCC2) ..........................................-0.5V to (VCC + 0.5V) Current at SDO±...............................................................±25mA SDI±, EN, SD, HFPD, LFPD........................-0.5V to (VCC + 0.5V) Current at HFPD, LFPD ......................................................400µA Continuous Power Dissipation (TA = +85°C) 16-Lead QFN-EP (derate 17.5mW/°C above +85°C) ............................................................1398mW Operating Ambient Temperature Range .............-40°C to +85°C Storage Ambient Temperature Range...............-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING CONDITIONS PARAMETER SYMBOL CONDITIONS MIN TYP 3.3 Supply Voltage VCC 3.0 Input Termination Voltage VCC1 1.65 Output Termination Voltage VCC2 1.65 Operating Ambient Temperature -40 +25 MAX UNITS 3.6 V VCC V VCC V +85 °C ELECTRICAL CHARACTERISTICS (Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at VCC = +3.3V, VCC1 = VCC2 = 1.8V, TA = +25°C, unless otherwise noted.) (Values at -40°C are guaranteed by design and characterization.) PARAMETER SYMBOL CONDITIONS Supply Current ICC VCC = VCC1 = VCC2 CML Input Differential Voltage VIN AC-coupled or DC-coupled at transmission line input (Notes 1, 6) CML Input Common-Mode Voltage CML Input Resistance Differential CML Input Return Loss 100MHz to 10GHz CML Output Differential Voltage VOUT CML Output Resistance CML Output Transition Time tr/tf CML Output Return Loss MIN TYP MAX UNITS 41 60 mA 400 1200 mVP-P 1.3 VCC1 V 85 100 115 10 Ω dB VCC2 = 1.65V to 3.6V 400 500 600 mVP-P Differential 85 100 115 Ω 20% to 80% (Notes 2, 6) 35 100MHz to 5GHz 10 Equalizer Time Constant ps dB 10 µs Output Residual Jitter (Notes 3–6) 21 Signal-Detect Assert PRBS231 - 1 at 10.7Gbps (Note 1) 200 mVP-P Signal-Detect Deassert PRBS231 - 1 at 10.7Gbps (Note 1) 220 mVP-P LVCMOS Input-High Leakage Current 2 IH +10 _______________________________________________________________________________________ 30 +60 psP-P µA 10.7Gbps Adaptive Receive Equalizer (Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at VCC = +3.3V, VCC1 = VCC2 = 1.8V, TA = +25°C, unless otherwise noted.) (Values at -40°C are guaranteed by design and characterization.) PARAMETER LVCMOS Input-Low Leakage Current SYMBOL CONDITIONS MIN IL -30 LVCMOS Input High VIH 1.5 LVCMOS Input Low VIL LVCMOS Output High VOH IOH = 12.5µA LVCMOS Output Low VOL IOL = 0.5mA TYP MAX UNITS +30 µA 0.5 V V 2.1 V 0.2 V Note 1: Differential input sensitivity is defined at the input to a transmission line with path length up to 30in. Note 2: Measured using 10 ones and 10 zeros at 10.7Gbps. Note 3: Residual jitter is the difference in total jitter between the signal at the input to the transmission line and the equalizer output. Total residual jitter is DJP-P + 14.1 × RJRMS. Note 4: Measured at 10.7Gbps using a pattern of 100 ones, PRBS 210 - 1, 100 zeros, PRBS 210 - 1. Note 5: VIN = 400mVP-P to 1200mVP-P, input path is 0 to 30in, 6-mil microstrip in FR-4, εr = 4.5, and tan δ = 0.02. Note 6: Guaranteed by design and characterization. Typical Operating Characteristics (VCC = 3.3V, VCC1 = 1.8V, VCC2 = 1.8V, and TA = +25°C, unless otherwise noted.) EQUALIZER INPUT EYE AFTER 30in OF FR-4 (210 - 1PRBS WITH 100 CIDs AT 9.953Gbps) EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (210 - 1PRBS WITH 100 CIDs AT 9.953Gbps) MAX3805 toc02 MAX3805 toc01 65mV/div 65mV/div 20ps/div EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (231 - 1PRBS AT 10.7Gbps) MAX3805 toc03 65mV/div 20ps/div 20ps/div _______________________________________________________________________________________ 3 MAX3805 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VCC = 3.3V, VCC1 = 1.8V, VCC2 = 1.8V, and TA = +25°C, unless otherwise noted.) EQUALIZER OUTPUT EYE AFTER 24ft OF RG-188/U COAXIAL CABLE, SINGLE ENDED (223 - 1PRBS AT 10.7Gbps) MAX3805 toc04 SUPPLY CURRENT vs. TEMPERATURE MAX3805 toc05 65 MAX3805 toc06 EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (CJTPAT 10.0Gbps LFPD/(HFPD + LFPD) = 0.6) VCC = VCC1 = VCC2 = +3.3V 65mV/div SUPPLY CURRENT (mA) 60 65mV/div 55 50 45 40 35 20ps/div -40 20ps/div -20 0 20 40 TEMPERATURE (°C) DATA RATE = 9.953Gbps PATTERN = PRBS 210 -1 40 35 RESIDUAL JITTER = DJ + 14.1 x RJ 30 FR4 = 30in 25 40 35 30 25 20 20 RESIDUAL JITTER = DJ + 14.1 x RJ FR4 = 18in 15 400 500 600 700 800 12 15 18 21 24 RESIDUAL JITTER vs. RLFPD/(RHFPD + RLFPD) 35 30 25 50 30in FR4 20 27 VIN = 400mVP-P PATTERN = CJTPAT DATA RATE = 10.0Gbps (RLFPD + RHFPD) = 100kΩ 45 RESIDUAL JITTER (ps) 40 9 RESIDUAL JITTER vs. DATA RATE VIN = 400mVP-P PATTERN = 100 1's PRBS 210-1 100 0's PRBS 210-1 RESIDUAL JITTER = DJ + 14.1 x RJ 45 6 FR-4 PATH LENGTH (in) MAX3805 toc09 50 3 900 1000 1100 1200 AMPLITUDE (mVP-P) 40 30 MAX3805 toc10 15 35 18in FR4 30 25 20 15 18in FR4 15 10 6 7 8 9 DATA RATE (Gbps) 4 DATA RATE = 10.7Gbps PATTERN = PRBS 210 -1 VIN = 400mVP-P 45 RESIDUAL JITTER RESIDUAL JITTER (ps) 45 50 MAX3805 toc07 50 MAX3805 toc08 RESIDUAL JITTER vs. FR-4 PATH LENGTH RESIDUAL JITTER vs. AMPLITUDE RESIDUAL JITTER (ps) MAX3805 10.7Gbps Adaptive Receive Equalizer 10 11 30in FR4 RESIDUAL JITTER = DJ + 14.1 x RJ 0.5 0.6 0.7 0.8 RLFPD/(RHFPD + RLFPD) _______________________________________________________________________________________ 0.9 60 80 10.7Gbps Adaptive Receive Equalizer PIN NAME 1 VCC1 FUNCTION 2 SDI+ Positive Differential Serial Data Input, CML 3 SDI- Negative Differential Serial Data Input, CML 4 VCC1 Supply Voltage, CML Input (1.8V to VCC) 5 GND 6 SD Signal-Detect Output, LVCMOS. Low indicates <200mVP-P, high indicates >220mVP-P. 7 EN Enable Input, LVCMOS. Low disables output, high enables output, typically connected to SD. 8 GND Supply Ground 9, 12 VCC2 Supply Voltage, CML Output (1.8V to VCC) 10 SDO- Negative Differential Serial Data Output, CML 11 SDO+ Positive Differential Serial Data Output, CML 13 HFPD High-Frequency Power Detector. Leave open for 9.953Gbps to 10.7Gbps PRBS NRZ data. 14 LFPD Low-Frequency Power Detector. Leave open for 9.953Gbps to 10.7Gbps PRBS NRZ data. 15 VCC Supply Voltage, CML Input (1.8V to VCC) Supply Ground Supply Voltage, Equalizer Core, 3.3V 16 GND EP Exposed Pad Supply Ground Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. Detailed Description and Applications Information The MAX3805 adaptive equalizer is designed to operate with 9.95Gbps to 10.7Gbps PRBS nonreturn-to-zero (NRZ) data at the receive end of a transmission line, typically differential 6-mil FR-4 PC board. It adaptively corrects intersymbol interference caused by frequencydependent path loss. It can also be used with coaxial cable links and with transmission lines that include wellengineered connectors, as long as the total path loss is relatively smooth and does not exceed 20dB at 5GHz. The signal path for the MAX3805 consists of a CML input stage, two amplifiers feeding a pair of variable attenuators controlled by feedback, and a limiting amplifier with a CML output stage. An enable input, EN, is used to control the output stage. A signal-detect output, SD, indicates when input signal to the transmission line is above 220mVP-P or below 200mVP-P, typically. See the Functional Diagram. CML Input and Output Buffers The MAX3805 CML input and output buffers are internally terminated with 50Ω to VCC1 and VCC2, respectively. The input and output circuitry have separate voltage connections to control noise coupling and provide DC-coupling to +1.8V, +2.5V, or +3.3V CML. If desired, the CML inputs and outputs can be AC-coupled. See Figure 1 for the output structure. The low-frequency cutoff of the input-stage offset-cancellation circuit is nominally 21kHz. For single-ended operation (typically coaxial cable links), the input must be AC-coupled; connect the unused input to VCC1 using a series combination of an AC-coupling capacitor and a 50Ω resistor, as shown in Figure 2. Note that the MAX3805 is specified for differential operation, and the performance may be reduced in single-ended operation. _______________________________________________________________________________________ 5 MAX3805 Pin Description 10.7Gbps Adaptive Receive Equalizer MAX3805 Functional Diagram VCC1 VCC2 VCC FLAT AMP VARIABLE ATTENUATOR SDO+ SDI+ ∑ CML IN LIMITING AMP CML OUT SDI- SDOVARIABLE ATTENUATOR POWER DETECTOR EN LF POWER DETECTOR BOOST AMP MAX3805 SIGNAL DETECT LOOP FILTER LFPD SD HFPD Input Stage with Equalization The low-noise input stage of the MAX3805 includes two amplifiers, one with flat frequency response and the other with a highpass frequency response compensating for the loss characteristic of 6-mil FR-4 PC board transmission line. A current-steering network, implemented with a pair of variable attenuators feeding into a common summing node, provides the means to continuously vary the amount of equalization. The amount of equalization is controlled by feedback from two powerdetector blocks that set the variable attenuators to match the loss of a particular transmission path. VCC VCC2 50Ω 50Ω OUT+ OUT- ESD STRUCTURES Dual Power-Detector Feedback Loop The MAX3805 adapts the equalizer to a specific path loss by sampling the output of the summing node with a pair of frequency-dependent power detectors. The first power detector has a lowpass bandwidth of 500MHz; the second power detector has full bandwidth. NRZ PRBS data has a sin2(f)/f2 spectral characteristic. When this data is passed through a lossy FR-4 path, high-frequency components are attenuated, while low- 6 Figure 1. CML Output Structure _______________________________________________________________________________________ 10.7Gbps Adaptive Receive Equalizer MAX3805 VCC 50Ω TRANSMISSION LINE 0.01µF 500kΩ IN+ VCC1 50Ω 0.01µF MAX3805 LFPD IN- HFPD MAX3805 Figure 2. Single-Ended Operation Figure 3. Connecting a Potentionmeter Across HFPD and LFPD frequency components remain essentially intact. These changes in the spectral characteristic of the signal at the output of the path are measured with the two power detectors to provide a means to determine the path loss. The dual power-detector feedback loop measures the ratio between the outputs of the two power detectors and adjusts the attenuation to restore the sin 2 (f)/f 2 characteristic. The time constant for this feedback loop is nominally 10µs. Operating with Different Data Rates and Codes The MAX3805 equalizer feedback loop is optimized for 9.95Gbps to 10.7Gbps NRZ PRBS data; however, it can also be used at a lower data rate or with a different coding type by adjusting the feedback loop. The relative gain of the two power detectors can be adjusted by connecting a 500kΩ trimmer potentiometer between HFPD and LFPD pins, with the wiper connected to VCC, as shown in Figure 3. Set the trimmer potentiometer for the best eye opening. Adding the potentiometer between HFPD and LFPD can change the assert and deassert levels of the signal detector, which could render the signal-detect output invalid. For normal operation with 9.953Gbps to 10.7Gbps PRBS NRZ data, these signals should be left open with no connections to pin 13 (HFPD) or pin 14 (LFPD). Note that excessive capacitance on pin 13 or pin 14 can affect the operation of the feedback loop. Make certain that the PC board traces from these pins to the trimmer potentiometer are kept short. Signal Detect The output of the high-frequency power detector is used to generate an LVCMOS-compatible signal-detect (SD) output. The SD output asserts when the input signal at the transmission line falls below 200mVP-P, and deasserts when the input signal at the transmission line rises above 220mVP-P. The SD output can be directly connected to the EN input to disable the MAX3805 output when no data signal is available. The SD output has an LVCMOS fanout of one. Package and Layout Considerations The MAX3805 is packaged in a 3mm x 3mm plasticencapsulated 16-lead thin QFN package with exposed pad for signal integrity. The exposed pad provides thermal and electrical connectivity to the IC, and must be soldered to a high-frequency ground plane. Use good layout techniques for the10Gbps SDI and SDO PC board transmission lines, and configure the trace geometry near the IC package to minimize impedance discontinuities. Power-supply decoupling capacitors should be provided for each supply connection and located as close as practical to the IC package. VCC 60kΩ SD Enable Function The EN output is an LVCMOS-compatible pin that enables the output stage of the MAX3805. Connect EN to VCC or LVCMOS high to enable the output stage of the device or to GND or LVCMOS low to disable the output stage of the device. ESD STRUCTURES Figure 4. Signal-Detect Output Circuit _______________________________________________________________________________________ 7 Pin Configuration GND VCC LFPD HFPD Chip Information TRANSISTOR COUNT: 1647 PROCESS: SiGe Bipolar 16 15 14 13 VCC1 1 12 VCC2 SDI+ 2 11 SDO+ SDI- 3 10 SDO- VCC1 4 9 VCC2 5 6 7 8 SD EN GND MAX3805 GND MAX3805 10.7Gbps Adaptive Receive Equalizer *EXPOSED PAD IS CONNECTED TO GND 8 _______________________________________________________________________________________ 10.7Gbps Adaptive Receive Equalizer 12x16L QFN THIN.EPS D2 0.10 M C A B b D D2/2 D/2 E/2 E2/2 CL -A- (NE - 1) X e E E2 L -B- k e CL (ND - 1) X e CL CL 0.10 C 0.08 C A A2 A1 L L e e PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0136 REV. C 1 2 _______________________________________________________________________________________ 9 MAX3805 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3805 10.7Gbps Adaptive Receive Equalizer Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0136 REV. C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.