MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers General Description Features The MAX3280E/MAX3281E/MAX3283E/MAX3284E are single receivers designed for RS-485 and RS-422 communication. These devices guarantee data rates up to 52Mbps, even with a 3V power supply. Excellent propagation delay (15ns max) and package-to-package skew time (8ns max) make these devices ideal for multidrop clock distribution applications. o ESD Protection: ±15kV Human Body Model ±6kV IEC 1000-4-2, Contact Discharge ±12kV IEC 1000-4-2, Air-Gap Discharge The MAX3280E/MAX3281E/MAX3283E/MAX3284E have true fail-safe circuitry, which guarantees a logichigh receiver output when the receiver inputs are opened or shorted. The receiver output will be a logic high if all transmitters on a terminated bus are disabled (high impedance). These devices feature 1/4-unit-load receiver input impedance, allowing up to 128 receivers on the same bus. o Guaranteed 2ns Receiver Skew o Guaranteed 52Mbps Data Rate o Guaranteed 15ns Receiver Propagation Delay o Guaranteed 8ns Package-to-Package Skew Time o VL Pin for Connection to FPGAs/ASICs o Allow Up to 128 Transceivers on the Bus (1/4-unit-load) o Tiny SOT23 Package The MAX3280E is a single receiver available in a 5-pin SOT23 package. The MAX3281E/MAX3283E single receivers have a receiver enable (EN or EN) function and are offered in a 6-pin SOT23 package. The MAX3284E features a voltage logic pin that allows compatibility with low-voltage logic levels, as in digital FPGAs/ASICs. On the MAX3284E, the voltage threshold for a logic high is user-defined by setting VL in the range from 1.65V to V CC . The MAX3284E is also offered in a 6-pin SOT23 package. o True Fail-Safe Receiver o -7V to +12V Common-Mode Range o 3V to 5.5V Power-Supply Range o Enable (High and Low) Pins for Redundant Operation o Three-State Output Stage (MAX3281E/MAX3283E) o Thermal Protection Against Output Short Circuit Applications Ordering Information Clock Distribution PART Telecom Racks TEMP RANGE PINPACKAGE TOP MARK Base Stations MAX3280EAUK+T -40°C to +125°C 5 SOT23 +ADVM Industrial Control MAX3280EAUK/V+T -40°C to +125°C 5 SOT23 +AFME MAX3281EAUT+T -40°C to +125°C 6 SOT23 +ABAT MAX3283EAUT+T -40°C to +125°C 6 SOT23 +ABAU MAX3284EAUT+T -40°C to +125°C 6 SOT23 +ABAV Local Area Networks Pin Configurations appear at end of data sheet. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. /V denotes an automotive qualified part. Selector Guide PART VL ENABLE DATA RATE PACKAGE MAX3280E — — 52Mbps 5-Pin SOT23 MAX3281E — Active High 52Mbps 6-Pin SOT23 MAX3283E — Active Low 52Mbps 6-Pin SOT23 MAX3284E ✔ — 52Mbps (Note 1) 6-Pin SOT23 Note 1: MAX3284E data rate is dependent on VL. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-2320; Rev 2; 12/12 MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers ABSOLUTE MAXIMUM RATINGS (All Voltages Referenced to GND) Supply Voltage (VCC) ...............................................-0.3V to +6V Control Input Voltage (EN, EN).................................-0.3V to +6V VL Input Voltage .......................................................-0.3V to +6V Receiver Input Voltage (A, B)..............................-7.5V to +12.5V Receiver Output Voltage (RO)....................-0.3V to (VCC + 0.3V) Receiver Output Voltage (RO) (MAX3284E) .....................................-0.3V to (VL + 0.3V) Receiver Output Short-Circuit Current .......................Continuous Continuous Power Dissipation (TA = +70°C) 5-Pin SOT23 (derate 7.1mW/°C above +70°C)............571mW 6-Pin SOT23 (derate 8.7mW/°C above +70°C)............696mW Operating Temperature Range MAX328_EA__ ..............................................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 3V to 5.5V, VL = VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 5V and TA = +25°C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS Supply Voltage VCC Supply Current ICC VL Input Range VL MAX3284E VL Supply Current IL No load (MAX3284E) Input Current (A and B) IA, B VCC = V GND or 5.5V Receiver Differential Threshold Voltage VTH -7V VCM +12V (Note 4) MIN TYP 3.0 No load 9 1.65 MAX UNITS 5.5 V 15 mA VCC V 10 µA RECEIVER VIN = +12V 250 VIN = -7V -200 Receiver Input Hysteresis VTH VA + VB = 0V Receiver Enable Input Low VENIL MAX3281E, MAX3283E only Receiver Enable Input High VENIH MAX3281E, MAX3283E only Receiver Enable Input Leakage ILEAK MAX3281E, MAX3283E only Receiver Output High Voltage Receiver Output Low Voltage VOH VOL -200 -125 -50 25 VCC - 0.4 MAX3284E, I OH = -1mA, 1.65V VL VCC, RO high VL - 0.4 mV V ±10 µA V V MAX3280E/MAX3281E/MAX3283E, I OL = 4mA, RO low 0.4 MAX3284E, I OL = 1mA, 1.65V VL VCC, RO low 0.4 ±5 Three-State Output Current at Receiver I OZR 0 V O VCC, RO = high impedance Receiver Input Resistance RIN -7V VCM +12V (Note 5) Receiver Output Short-Circuit Current I OSR 0 VRO VCC mV 0.4 2 MAX3280E/MAX3281E/MAX3283E, I OH = -4mA, RO high µA V 48 µA k ±130 mA ESD PROTECTION ESD Protection (A, B) 2 Human Body Model ±15 IEC1000-4-2 (Air-Gap Discharge) ±12 IEC1000-4-2 (Contact Discharge) ±6 kV Maxim Integrated MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers SWITCHING CHARACTERISTICS (VCC = 3V to 5.5V, VL = VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 5V and TA = +25°C.) (Notes 2, 3) PARAMETER SYMBOL Maximum Data Rate Receiver Propagation Delay Receiver Output |t PLH - tPHL| CONDITIONS MIN TYP MAX fMAX CL = 15pF (Notes 5, 6) t PLH Figure 1, CL = 15pF, VID = 2V, VCM = 0V 7 15 t PHL Figure 1, CL = 15pF, VID = 2V, VCM = 0V 8 15 t PSKEW 52 Mbps Figure 1, CL = 15pF, TA = +25°C Same power supply, maximum temperature difference between devices = +30°C. Device-to-Device Propagation Delay Matching UNITS ns 2 ns 8 ns ENABLE/DISABLE TIME FOR MAX3281E/MAX3283E Receiver Enable to Output Low t PRZL Figure 2, CL = 15pF 500 ns Receiver Enable to Output High t PRZH Figure 2, CL = 15pF 500 ns Receiver Disable Time from Low tPRLZ Figure 2, CL = 15pF 500 ns Receiver Disable Time from High t PRHZ Figure 2, CL = 15pF 500 ns Note 2: Parameters are 100% production tested at +25°C, limits over temperature are guaranteed by design. Note 3: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to device ground, unless otherwise noted. Note 4: VCM is the common-mode input voltage. VID is the differential input voltage. Note 5: Not production tested. Guaranteed by design. Note 6: See Table 2 for MAX3284E data rates with VL < VCC. Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) 3 VCC = 3.3V VCC = 5V 2 VCC = 5V 3 VCC = 3.3V 2 1 0 0 10 20 30 40 OUTPUT CURRENT (mA) Maxim Integrated 50 60 5.0 VCC = 5V 4.5 4.0 3.5 VCC = 3.3V 3.0 VA = 1V, B = GND, IOH = -4mA 2.5 -50 -40 -30 -20 OUTPUT CURRENT (mA) -10 0 MAX3280/1/3/4E toc03 4 1 0 MAX3280/1/3/4E toc02 OUTPUT VOLTAGE (V) 4 5 OUTPUT VOLTAGE (V) MAX3280/1/3/4E toc01 5 RECEIVER OUTPUT HIGH VOLTAGE vs. TEMPERATURE RECEIVER OUTPUT HIGH VOLTAGE vs. OUTPUT CURRENT RECEIVER OUTPUT HIGH VOLTAGE (V) RECEIVER OUTPUT LOW VOLTAGE vs. OUTPUT CURRENT -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) 3 MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) 150 10 MAX3280/1/3/4E toc05 9 MAX3280/1/3/4E toc04 8 VCC = 3.3V 9 VCC = 5V VCC = 5V 100 7 tPHL (ns) tPLH (ns) RECEIVER OUTPUT LOW VOLTAGE (mV) 200 RECEIVER PROPAGATION DELAY (tPHL) vs. TEMPERATURE RECEIVER PROPAGATION DELAY (tPLH) vs. TEMPERATURE MAX3280/1/3/4E toc06 RECEIVER OUTPUT LOW VOLTAGE vs. TEMPERATURE VCC = 3.3V VCC = 5V 8 VCC = 3.3V 6 50 7 5 A = GND, VB = 1V, IOL = 4mA 6 4 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 -25 0 75 100 125 7 MAX3280/1/3/4E toc08 8 60 50 DATA RATE (Mbps) MAX3280/1/3/4E toc07 VCC = 5V 50 MAX3284E MAXIMUM DATA RATE vs. VOLTAGE LOGIC LEVEL SUPPLY CURRENT vs. TEMPERATURE 9 25 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY CURRENT (mA) -50 125 6 40 30 VCC = 3.3V 5 20 0 25 50 75 100 2.5 3.5 SUPPLY CURRENT vs. DATA RATE VL SUPPLY CURRENT vs. TEMPERATURE MAX3280/1/3/4E toc09 8 ICC, VCC = VL = 3.3V IL, VCC = VL = 5V 4 2 5.5 10 1 VCC = VL = 5V DATA RATE = 52Mbps VCC = VL = 3.3V DATA RATE = 52Mbps 0.1 VCC = VL = 5V DATA RATE = 100kbps 0.01 VCC = VL = 3.3V DATA RATE = 100kbps IL, VCC = VL = 3.3V 0 0.001 10 100 1000 DATA RATE (kbps) 4 4.5 VOLTAGE LOGIC LEVEL (V) ICC, VCC = VL = 5V 6 1.5 TEMPERATURE (°C) 10 SUPPLY CURRENT (mA) 125 MAX3280/1/3/4 toc10 -25 VL SUPPLY CURRENT (mA) -50 10,000 100,000 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) Maxim Integrated MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers Pin Description PIN MAX3283E MAX3284E NAME FUNCTION MAX3280E MAX3281E 1 1 1 1 VCC Positive Supply: 3V VCC 5.5V. Bypass with a 0.1µF capacitor to GND. 2 2 2 2 GND Ground 3 3 3 3 RO 4 4 4 4 B Receiver Output. RO will be high if (VA - VB) -50mV. RO will be low if (VA - VB) -200mV. Inverting Receiver Input — — 5 — EN Receiver Output Enable. Drive EN low to enable RO. When EN is high, RO is high impedance. — 5 — — EN Receiver Output Enable. Drive EN high to enable RO. When EN is low, RO is high impedance. — — — 5 VL Low-Voltage Logic-Level Supply Voltage. VL is a user-defined voltage, ranging from 1.65V to VCC. RO output high is pulled up to VL. Bypass with a 0.1µF capacitor to GND. 5 6 6 6 A Noninverting Receiver Input Detailed Description The MAX3280E/MAX3281E/MAX3283E/MAX3284E are single, true fail-safe receivers designed to operate at data rates up to 52Mbps. The fail-safe architecture guarantees a high output signal if both input terminals are open or shorted together. See the True Fail-Safe section. This feature assures a stable and predictable output logic state with any transmitter driving the line. These receivers function with a 3.3V or 5V supply voltage and feature excellent propagation delay times (15ns). The MAX3280E is a single receiver available in a 5-pin SOT23 package. The MAX3281E (EN, active high) and MAX3283E (EN, active low) are single receivers that also contain an enable pin. Both the MAX3281E and MAX3283E are available in a 6-pin SOT23 package. The MAX3284E is a single receiver that contains a VL pin, which allows communication with low-level logic included in digital FPGAs. The MAX3284E is available in a 6-pin SOT23 package. The MAX3284E’s low-level logic application allows users to set the logic levels. A logic high level of 1.65V will limit the maximum data rate to 20Mbps. ±15kV ESD Protection ESD-protection structures are incorporated on the receiver input pins to protect against ESD encountered during handling and assembly. The MAX3280E/ MAX3281E/MAX3283E/MAX3284E receiver inputs (A, B) have extra protection against static electricity found in normal operation. Maxim’s engineers developed state-of-the-art structures to protect these pins against Maxim Integrated ±15kV ESD without damage. After an ESD event, this family of parts continues working without latchup. ESD protection can be tested in several ways. The receiver inputs are characterized for protection to the following: • ±15kV using the Human Body Model • ±6kV using the Contact Discharge method specified in IEC 1000-4-2 (formerly IEC 801-2) • ±12kV using the Air-Gap Discharge method specified in IEC 1000-4-2 (formerly IEC 801-2) ESD Test Conditions ESD performance depends on a number of conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. Human Body Model Figure 3a shows the Human Body Model, and Figure 3b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5kΩ resistor. IEC 1000-4-2 Since January 1996, all equipment manufactured and/or sold in the European community has been required to meet the stringent IEC 1000-4-2 specification. The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX3280E/MAX3281E/MAX3283E/MAX3284E help 5 MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers users design equipment that meets Level 3 of IEC 10004-2, without additional ESD-protection components. The main difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2. Because series resistance is lower in the IEC 1000-4-2 ESD test model (Figure 4a), the ESD-withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 4b shows the current waveform for the ±8kV IEC 1000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charger probe. The Contact Discharge method connects the probe to the device before the probe is energized. Machine Model The Machine Model for ESD testing uses a 200pF storage capacitor and zero-discharge resistance. It mimics the stress caused by handling during manufacturing and assembly. All pins (not just the RS-485 inputs) require this protection during manufacturing. Therefore, the Machine Model is less relevant to the I/O ports than are the Human Body Model and IEC 1000-4-2. True Fail-Safe The MAX3280E/MAX3281E/MAX3283E/MAX3284E guarantee a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This guaranteed logic high is achieved by setting the receiver threshold between -50mV and -200mV. If the differential receiver input voltage (VA - VB) is greater than or equal to -50mV, RO is logic high. If (VA - VB) is less than or equal to -200mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver’s differential input voltage is pulled to ground by the termination. This results in a logic high with a 50mV minimum noise margin. Unlike previous fail-safe devices, the -50mV to -200mV threshold complies with the ±200mV EIA/TIA-485 standard. Receiver Enable (MAX3281E and MAX3283E only) The MAX3281E and MAX3283E feature a receiver output enable (EN, MAX3281E or EN, MAX3283E) input that controls the receiver. The MAX3281E receiver enable (EN) pin is active high, meaning the receiver outputs are active when EN is high. The MAX3283E receiver enable (EN) pin is active low. Receiver outputs are high impedance when the MAX3281E’s EN pin is low and when the MAX3283E’s EN pin is high. 6 Table 1. MAX3281E/MAX3283E Enable Table ENABLE = HIGH ENABLE = LOW MAX3281E PART Active High Z MAX3283E High Z Active Low-Voltage Logic Levels (MAX3284E only) An increasing number of applications now operate at low-voltage logic levels. To enable compatibility with these low-voltage logic level applications, such as digital FPGAs, the MAX3284E VL pin is a user-defined supply voltage that designates the voltage threshold for a logic high. At lower VL voltages, the data rate will also be lower. A logic-high level of 1.65V will receive data at 20Mbps. Table 2 gives data rates at various voltages at VL. Table 2. MAX3284E Data Rate Table VCC = 3V TO 5.5V VL MAXIMUM DATA RATE 1.65V 20Mbps 2.2V 33Mbps ≥3.3V 52Mbps Applications Information Propagation Delay Matching The MAX3280E/MAX3281E/MAX3283E/MAX3284E (VCC = VL) exhibit propagation delays that are closely matched from one device to another, even between devices from different production lots. This feature allows multiple data lines to receive data and clock signals with minimal skew with respect to each other. Figure 5 shows the typical propagation delays. Small receiver skew times, the difference between the low-tohigh and high-to-low propagation delay, help maintain a symmetrical ratio (50% duty cycle). The receiver skew time | tPLH - tPHL | is under 2ns for either a 3.3V supply or a 5V supply. Multidrop Clock Distribution Low package-to-package skew (8ns max) makes the MAX3280E/MAX3281E/MAX3283E/MAX3284E (VCC = VL) ideal for multidrop clock distribution. When distributing a clock signal to multiple circuits over long transmission lines, receivers in separate locations, and possibly at two different temperatures, would ideally Maxim Integrated MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers provide the same clock to their respective circuits. Thus, minimal package-to-package skew is critical. The skew must be kept well below the period of the clock signal to ensure that all of the circuits on the network are synchronized. 128 Receivers on the Bus The standard RS-485 input impedance is 12kΩ (oneunit load). The standard RS-485 transmitter can drive 32 unit loads. The MAX3280E/MAX3281E/MAX3283E/ MAX3284E present a 1/4-unit-load input impedance (48kΩ), which allows up to 128 receivers on the bus. Any combination of these RS-485 receivers with a total of 32 unit loads can be connected to the same bus. Thermal Protection The MAX3280E/MAX3281E/MAX3283E/MAX3284E feature thermal protection. Thermal protection sets the output stage in high-impedance mode when a short circuit occurs at the output, limiting both the power dissipation and temperature. The thermal temperature threshold is +165°C, with a hysteresis of 20°C. Test Circuits/Timing Diagrams VOH RO VCC/2 VCC/2 VOL OUTPUT tPHL 1V A -1V B tPLH INPUT fIN = 1MHz tr, tf ≤ 3ns Figure 1. Receiver Propagation Delay S3 S1 1.5V VCC 1kΩ -1.5V VID R S2 CL GENERATOR 50Ω VCC VCC S1 OPEN S2 CLOSED S3 = 1.5V VCC/2 0 EN 0 EN tPRZH tPRZL VOH OUT VCC VCC/2 VCC/2 OUT 0 VOL VCC VCC S1 OPEN S2 CLOSED S3 = 1.5V VCC/2 EN S1 CLOSED S2 OPEN S3 = -1.5V VCC/2 0 S1 CLOSED S2 OPEN S3 = -1.5V VCC/2 0 EN tPRHZ tPRLZ OUT 0.25V VOH VCC OUT 0 FOR MAX3281E THE ENABLE SIGNAL IS INVERTED. 0.25V VOL Figure 2. MAX3281E/MAX3283E Receiver Enable/Disable Timing Maxim Integrated 7 MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers Test Circuits/Timing Diagrams (continued) RC 1MΩ RD 1.5kΩ DISCHARGE RESISTANCE CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF IP 100% 90% Ir AMPERES DEVICE UNDER TEST STORAGE CAPACITOR 36.8% 10% 0 0 Figure 3a. Human Body ESD Test Model Cs 150pF 90% DEVICE UNDER TEST STORAGE CAPACITOR I PEAK HIGHVOLTAGE DC SOURCE tDL CURRENT WAVEFORM I 100% DISCHARGE RESISTANCE CHARGE-CURRENT LIMIT RESISTOR TIME tRL Figure 3b. Human Body Model Current Waveform RD 330Ω RC 50Ω to 100Ω PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) 10% Figure 4a. IEC 1000-4-2 ESD Test Model t r = 0.7ns to 1ns t 30ns 60ns Figure 4b. IEC 1000-4-2 ESD Generator Current Waveform A, 1V/div RO, 2.5V/div B = GND 10ns Figure 5. Receiver Propagation Delay Driven by External RS485 Device 8 Maxim Integrated MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers Pin Configurations TOP VIEW + + VCC 1 GND 2 5 A MAX3280E RO 3 GND 2 4 + VCC 1 B MAX3281E MAX3283E RO 3 SOT23-5 6 A VCC 1 5 EN (EN) GND 2 4 B MAX3284E RO 3 SOT23-6 6 A 5 VL 4 B SOT23-6 ( ) ARE FOR MAX3283E Typical Operating Circuit Chip Information PROCESS: BiCMOS TRANSMITTER DATA IN 120Ω MAX3283E RO1 EN MAX3281E MAX3281E/MAX3283E IN REDUNDANT RECEIVER APPLICATION Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. RO2 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 5 SOT23 U5+2 21-0057 90-0174 6 SOT23 U6+1 21-0058 90-0175 EN Maxim Integrated 9 MAX3280E/MAX3281E/ MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers Revision History REVISION NUMBER REVISION DATE 0 1/02 Initial release 1 3/11 Added lead-free parts to the Ordering Information, deleted the transistor count from the Chip Information section 2 2/12 Added automotive qualified part to Ordering Information DESCRIPTION PAGES CHANGED — 1, 9 1 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 10 ________________________________Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.