ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold General Description Features Some device/package combinations are obsolete and shown for reference only. The ADC12030, and ADC12H030 families are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexers. The ADC12034/ADC12H034 and ADC12038/ADC12H038 have 4 and 8 channel multiplexers, respectively. The differential multiplexer outputs and A/D inputs are available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins. The ADC12030/ADC12H030 has a two channel multiplexer with the multiplexer outputs and A/D inputs internally connected. The ADC12030 family is tested with a 5 MHz clock, while the ADC12H030 family is tested with an 8 MHz clock. On request, these A/Ds go through a self calibration process that adjusts linearity, zero and fullscale errors to less than ±1 LSB each. The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range (0V to +5V) can be accommodated with a single +5V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the positive because of the 12-bit plus sign output data format. The serial I/O is configured to comply with NSC MICROWIRE. For voltage references see the LM4040, LM4050 or LM4041. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Serial I/O (MICROWIRE Compatible) 2, 4, or 8 chan differential or single-ended multiplexer Analog input sample/hold function Power down mode Variable resolution and conversion rate Programmable acquisition time Variable digital output word length and format No zero or full scale adjustment required Fully tested and guaranteed with a 4.096V reference 0V to 5V analog input range with single 5V power supply No Missing Codes over temperature Key Specifications ■ Resolution ■ 12-bit plus sign conversion time – ADC12H30 family – ADC12030 family 12-bit plus sign 5.5 µs (max) 8.8 µs (max) ■ 12-bit plus sign throughput time – ADC12H30 family – ADC12030 family ■ Integral Linearity Error ■ Single Supply ■ Power consumption – Power down 8.6 µs (max) 14 µs (max) ±1 LSB (max) 5V ±10% 33 mW (max) 100 µW (typ) Applications ■ Medical instruments ■ Process control systems ■ Test equipment TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 11354 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold April 2007 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 ADC12038 Simplified Block Diagram 1135401 Connection Diagrams 16-Pin Wide Body SO Packages 20-Pin Wide Body SO Packages 1135406 Top View 1135407 Top View www.national.com 2 28-Pin Wide Body SO Packages 1135408 Top View 1135409 Top View Ordering Information Industrial Temperature Range Package −40°C ≤ TA ≤ +85°C ADC12H030CIWM, ADC12030CIWM M16B, Wide Body SO ADC12030CIWMX M16B, Wide Body SO - Tape & Reel ADC12032CIWM M20B, Wide Body SO ADC12034CIN N24C, Dual-In-Line ADC12034CIWM M24B, Wide Body SO ADC12H034CIMSA MSA24, SSOP ADC12H034CIMSAX MSA24, SSOP - Tape & Reel ADC12H038CIWM, ADC12038CIWM M28B, Wide Body SO ADC12H038CIWMX, ADC12038CIWMX M28B, Wide Body SO - Tape & Reel * Some of these product/package combinations are on lifetime buy or are obsolete and shown here for reference only. Check our web site for product/package availability. 3 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 24-Pin Wide Body SO, DIP, SSOP-EIAJ Packages ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Pin Descriptions CCLK SCLK DI DO EOC CS www.national.com The clock applied to this input controls the successive approximation conversion time interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 µs. This is the serial data clock input. The clock applied to this input controls the rate at which the serial data exchange occurs. The rising edge loads the information on the DI pin into the multiplexer address and mode select shift register. This address controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation for the A/D. With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed 1 µs. This is the serial data input pin. The data applied to this pin is shifted by the rising edge of SCLK into the multiplexer address and mode select register. Table 2 through Table 5 show the assignment of the multiplexer address and the mode select data. The data output pin. This pin is an active push/pull output when CS is low. When CS is high, this output is TRI-STATE®. The A/D conversion result (D0–D12) and converter status data are clocked out by the falling edge of SCLK on this pin. The word length and format of this result can vary (see Table 1). The word length and format are controlled by the data shifted into the multiplexer address and mode select register (see Table 5). This pin is an active push/pull output and indicates the status of the ADC12030/2/4/8. When low, it signals that the A/D is busy with a conversion, auto-calibration, auto-zero or power down cycle. The rising edge of EOC signals the end of one of these cycles. This is the chip select pin. When a logic low is applied to this pin, the rising edge of SCLK shifts the data on DI into the address register. This low also brings DO out of TRI- DOR CONV PD 4 STATE. With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The falling edge of CS resets a conversion in progress and starts the sequence for a new conversion. When CS is brought back low during a conversion, that conversion is prematurely terminated. The data in the output latches may be corrupted. Therefore, when CS is brought back low during a conversion in progress the data output at that time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied it expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC expects is the same as the digital output word length. This word length can be modified by the data shifted in on the DO pin. Table 5 details the data required. This is the data output ready pin. This pin is an active push/pull output. It is low when the conversion result is being shifted out and goes high to signal that all the data has been shifted out. A logic low is required on this pin to program any mode or change the ADC's configuration as listed in the Mode Programming Table 5 such as 12-bit conversion, 8-bit conversion, Auto-Cal, Auto Zero etc. When this pin is high the ADC is placed in the read data only mode. While in the read data only mode, bringing CS low and pulsing SCLK will only clock out on DO any data stored in the ADCs output shift register. The data on DI will be neglected. A new conversion will not be started and the ADC will remain in the mode and/or configuration previously programmed. Read data only cannot be performed while a conversion, Auto-Cal or Auto-Zero are in progress. This is the power down pin. When PD is high the A/D is powered down; when PD is low the A/D is powered up. The A/D takes a maximum of 250 µs to power up after the command is given. These are the analog inputs of the MUX. A channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register (See Tables 2, 3, 4). The voltage applied to these inputs should not exceed VA+ or go below GND. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. COM This pin is another analog input pin. It is used as a pseudo ground when the analog multiplexer is single-ended. MUXOUT1,MUXOUT2 These are the multiplexer output pins. A/DIN1, /DIN2 These are the converter input pins. MUXOUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external circuitry is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2 it may be necessary to protect these pins. The voltage at these pins should not ex- VREF+ VREF− VA+, VD+ DGND AGND 5 ceed VA+ or go below AGND (see Figure 6). This is the positive analog voltage reference input. In order to maintain accuracy, the voltage range of VREF (VREF = VREF+ − VREF−) is 1 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 5 for recommended bypassing. The negative voltage reference input. In order to maintain accuracy, the voltage at this pin must not go below GND or exceed VA+. (See Figure 5). These are the analog and digital power supply pins. VA+ and VD+ are not connected together on the chip. These pins should be tied to the same power supply and bypassed separately (see Figure 5). The operating voltage range of VA+ and VD+ is 4.5 VDC to 5.5 VDC. This is the digital ground pin (see Figure 5). This is the analog ground pin (see Figure 5). www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 CH0–CH7 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Absolute Maximum Ratings Operating Ratings (Notes 1, 2) Operating Temperature Range (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (V+ = VA+ = VD+) Voltage at Inputs and Outputs except CH0–CH7 and COM Voltage at Analog Inputs CH0–CH7 and COM |VA+ − VD+| Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25°C (Note 4) ESD Susceptibility (Note 5) Human Body Model Soldering Information N Packages (10 seconds) SO Package (Note 6): Vapor Phase (60 seconds) Infrared (15 seconds) Storage Temperature TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C Supply Voltage (V+ = VA+ = VD+) |VA+ − VD+| VREF+ VREF− VREF (VREF+ − VREF−) VREF Common Mode Voltage Range [(VREF+) − (VREF−)] / 2 A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 Voltage Range A/D IN Common Mode Voltage Range [(VIN+) − (VIN−)] / 2 6.5V −0.3V to (V+ +0.3V) GND −5V to (V+ +5V) 300 mV ±30 mA ±120 mA +4.5V to +5.5V ≤ 100 mV 0V to VA+ 0V to (VREF+ −1V) 1V to VA+ 0.1 VA+ to 0.6 VA+ 0V to VA+ 0V to VA+ Package Thermal Resistance 500 mW Thermal Resistance (θJA) Part Number 1500V 260°C 215°C 220°C −65°C to +150°C ADC12(H)030CIWM 70°C/W ADC12032CIWM 64°C/W ADC12034CIN 42°C/W ADC12034CIWM 57°C/W ADC12H034CIMSA 97°C/W ADC12(H)038CIWM 50°C/W Some product/package combinations are obsolete or on lifetime buy. These are shown for reference only. Please check our web site for availability. Converter Electrical Characteristics The following specifications apply for V+ = VA+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 12 + sign Bits (min) ±1/2 ±1 LSB (max) ±1 LSB (max) After Auto-Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max) Negative Full-Scale Error After Auto-Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max) Offset Error After Auto-Cal (Notes 5, 18) VIN(+) = VIN (−) = 2.048V ±1/2 ±2 LSB (max) DC Common Mode Error After Auto-Cal (Note 15) ±2 ±3.5 LSB (max) Total Unadjusted Error After Auto-Cal (Notes 12, 13, 14) ±1 ILE Integral Linearity Error After Auto-Cal (Notes 12, 18) DNL Differential Non-Linearity After Auto-Cal Positive Full-Scale Error TUE Resolution with No Missing Codes 8-bit + sign mode LSB 8 + sign Bits (min) INL Integral Linearity Error 8-bit + sign mode (Note 12) ±1/2 LSB (max) DNL Differential Non-Linearity 8-bit + sign mode ±3/4 LSB (max) Positive Full-Scale Error 8-bit + sign mode (Note 12) ±1/2 LSB (max) Negative Full-Scale Error 8-bit + sign mode (Note 12) ±1/2 LSB (max) Offset Error 8-bit + sign mode, after Auto-Zero VIN(+) = VIN(−) = + 2.048V (Note 13) ±1/2 LSB (max) www.national.com 6 TUE Parameter Total Unadjusted Error Conditions 8-bit + sign mode after Auto-Zero (Notes 12, 13, 14) Multiplexer Chan-to-Chan Matching Power Supply Sensitivity Typical (Note 10) Limits (Note 11) Units (Limits) ±3/4 LSB (max) ±0.05 LSB V+ = +5V ±10%, VREF = +4.096V Offset Error + Full-Scale Error − Full-Scale Error Integral Linearity Error ±0.5 ±0.5 ±0.5 ±0.5 ±1 ±1.5 ±1.5 LSB (max) LSB (max) LSB (max) LSB Output Data from “12-Bit Conversion of Offset” (see Table 5) (Note 20) +10 −10 LSB (max) LSB (min) Output Data from “12-Bit Conversion of Full-Scale” (see Table 5) (Note 20) 4095 4093 LSB (max) LSB (min) UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS S/(N+D) Signal-to-Noise Plus Distortion Ratio −3 dB Full Power Bandwidth fIN = 1 kHz, VIN = 5 VP-P, VREF+ = 5.0V 69.4 dB fIN = 20 kHz, VIN = 5 VP-P, VREF+ = 5.0V 68.3 dB fIN = 40 kHz, VIN = 5 VP-P, VREF+ = 5.0V 65.7 dB VIN = 5 VP-P, where S/(N+D) drops 3 dB 31 kHz fIN = 1 kHz, VIN = ±5V, VREF+ = 5.0V 77.0 dB fIN = 20 kHz, VIN = ±5V, VREF+ = 5.0V 73.9 dB fIN = 40 kHz, VIN = ±5V, VREF+ = 5.0V 67.0 dB VIN = ±5V, where S/(N+D) drops 3 dB 40 kHz DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS S/(N+D) Signal-to-Noise Plus Distortion Ratio −3 dB Full Power Bandwidth REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS CREF Reference Input Capacitance 85 pF CA/D A/DIN1, A/DIN2 Analog Input Capacitance 75 pF A/DIN1, A/DIN2 Analog Input Leakage Current VIN = +5.0V or VIN = 0V ±0.1 CH0–CH7 and COM Input Voltage CCH CH0–CH7 and COM Input Capacitance CMUXOUT MUX Output Capacitance RON ±1.0 µA (max) GND − 0.05 (VA+) + 0.05 V (min) V (max) 10 pF 20 pF Off Channel Leakage CH0–CH7 and COM Pins (Note 16) On Channel = 5V and Off Channel = 0V −0.01 −0.3 µA (min) On Channel = 0V and Off Channel = 5V 0.01 0.3 µA (max) On Channel Leakage CH0–CH7 and COM Pins (Note 16) On Channel = 5V and Off Channel = 0V 0.01 0.3 µA (max) On Channel = 0V and Off Channel = 5V −0.01 −0.3 µA (min) MUXOUT1 and MUXOUT2 Leakage Current VMUXOUT = 5.0V or VMUXOUT = 0V 0.01 0.3 µA (max) MUX On Resistance VIN = 2.5V and VMUXOUT = 2.4V 850 1150 Ω (max) RON Matching Chan-to-Chan VIN = 2.5V and VMUXOUT = 2.4V 5 Chan-to-Chan Crosstalk VIN = 5 VP-P, fIN = 40 kHz MUX Bandwidth 7 % −72 dB 90 kHz www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Symbol ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 DC and Logic Electrical Characteristics The following specifications apply for V+ = VA+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Notes 7, 8, 9) Symbo l Parameter Typical (Note 10) Conditions Limits (Note 11) Units (Limits) CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage V+ = 5.5V 2.0 V (min) VIN(0) Logical “0” Input Voltage V+ = 4.5V 0.8 V (max) IIN(1) Logical “1” Input Current VIN = 5.0V 0.005 1.0 µA (max) IIN(0) Logical “0” Input Current VIN = 0V −0.005 −1.0 µA (min) V+ = 4.5V, IOUT = −360 µA 2.4 V (min) V+ = 4.5V, IOUT = − 10 µA 4.25 V (min) DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage V+ VOUT(0) Logical “0” Output Voltage = 4.5V, IOUT = 1.6 mA 0.4 V (max) VOUT = 0V −0.1 −3.0 µA (max) IOUT TRI-STATE Output Current VOUT = 5V 0.1 3.0 µA (max) +ISC Output Short Circuit Source Current VOUT = 0V 14 6.5 mA (min) Output Short Circuit Sink Current VOUT = VD+ 16 8.0 mA (min) Digital Supply Current ADC12030, ADC12032, ADC12034 and ADC12038 Awake CS = HIGH, Powered Down, CCLK on CS = HIGH, Powered Down, CCLK off 1.6 600 20 2.5 mA (max) µA µA Digital Supply Current ADC12H030, ADC12H032, ADC12H034 and ADC12H038 Awake CS = HIGH, Powered Down, CCLK on CS = HIGH, Powered Down, CCLK off 2.3 0.9 20 3.2 mA mA µA Positive Analog Supply Current Awake CS = HIGH, Powered Down, CCLK on CS = HIGH, Powered Down, CCLK off 2.7 10 0.1 4.0 IA+ mA (max) µA µA IREF Reference Input Current Awake CS = HIGH, Powered Down 70 0.1 −ISC POWER SUPPLY CHARACTERISTICS ID+ µA µA AC Electrical Characteristics The following specifications apply for V+ = VA+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK = fSK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Note 17) Symb ol fCK fSK Parameter Typical (Note 10) Conditions ADC12H030/2/4/8 ADC12030/2/4/8 Limits Limits (Note 11) (Note 11) Units (Limits) Conversion Clock (CCLK) Frequency 10 1 8 5 MHz (max) MHz (min) Serial Data Clock SCLK Frequency 10 0 8 5 MHz (max) Hz (min) Conversion Clock Duty Cycle 40 60 40 60 % (min) % (max) Serial Data Clock Duty Cycle 40 60 40 60 % (min) % (max) www.national.com 8 tC Parameter Typical (Note 10) Conditions 44(tCK) 44(tCK) 5.5 44(tCK) 8.8 (max) µs (max) 8-Bit + Sign or 8-Bit 21(tCK) 21(tCK) 2.625 21(tCK) 4.2 (max) µs (max) 6(tCK) 6(tCK) (min) 7(tCK) 7(tCK) (max) 0.75 0.875 1.2 1.4 µs (min) µs (max) 10(tCK) 10(tCK) (min) 11(tCK) 11(tCK) (max) 1.25 1.375 2.0 2.2 µs (min) µs (max) 18(tCK) 18(tCK) (min) 19(tCK) 19(tCK) (max) 2.25 2.375 3.6 3.8 µs (min) µs (max) 34(tCK) 34(tCK) (min) 35(tCK) 35(tCK) (max) 4.25 4.375 6.8 7.0 µs (min) µs (max) 4944(tCK) 4944(tCK) (max) 618.0 988.8 µs (max) 76(tCK) 76(tCK) (max) 9.5 15.2 µs (max) 2(tCK) 2(tCK) (min) 3(tCK) 3(tCK) (max) 0.250 0.375 0.40 0.60 µs (min) µs (max) 9(tSK) 9(tSK) 1.125 9(tSK) 1.8 (max) µs (max) 8(tSK) 8(tSK) 8(tSK) (max) 1.0 1.6 µs (max) 6(tCK) 6 Cycles Programmed 10(tCK) 10 Cycles Programmed Acquisition Time (Note 19) 18(tCK) 18 Cycles Programmed 34(tCK) 34 Cycles Programmed 4944(tCK) tCKAL Self-Calibration Time tAZ Auto-Zero Time tSYNC Self-Calibration or Auto-Zero Synchronization Time from DOR tDOR DOR High Time when CS is Low Continuously for Read Data and Software Power Up/ Down tCONV CONV Valid Data Time Units (Limits) 12-Bit + Sign or 12-Bit Conversion Time tA ADC12H030/2/4/8 ADC12030/2/4/8 Limits Limits (Note 11) (Note 11) 76(tCK) 2(tCK) Timing Characteristics The following specifications apply for V+ = VA+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03, fCK = fSK = 5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (Note 17) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) tHPU Hardware Power-Up Time, Time from PD Falling Edge to EOC Rising Edge 140 250 µs (max) tSPU Software Power-Up Time, Time from Serial Data Clock Falling Edge to EOC Rising Edge 140 250 µs (max) tACC Access Time Delay from CS Falling Edge to DO Data Valid 20 50 ns (max) tSET-UP Set-Up Time of CS Falling Edge to Serial Data Clock Rising Edge 30 ns (min) 9 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Symb ol ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Symbol Parameter Conditions tDELAY Delay from SCLK Falling Edge to CS Falling Edge t1H, t0H Delay from CS Rising Edge to DO TRI-STATE tHDI tSDI tHDO DO Hold Time from Serial Data Clock Falling Edge tDDO Delay from Serial Data Clock Falling Edge to DO Data Valid tRDO tFDO Typical (Note 10) Limits (Note 11) Units (Limits) 0 5 ns (min) 40 100 ns (max) DI Hold Time from Serial Data Clock Rising Edge 5 15 ns (min) DI Set-Up Time from Serial Data Clock Rising Edge 5 10 ns (min) 25 50 5 ns (max) ns (min) RL = 3k, CL = 100 pF RL = 3k, CL = 100 pF 35 50 ns (max) DO Rise Time, TRI-STATE to High RL = 3k, CL = 100 pF 10 30 ns (max) DO Rise Time, Low to High RL = 3k, CL = 100 pF 10 30 ns (max) DO Fall Time, TRI-STATE to Low RL = 3k, CL = 100 pF 12 30 ns (max) DO Fall Time, High to Low RL = 3k, CL = 100 pF 12 30 ns (max) tCD Delay from CS Falling Edge to DOR Falling Edge 25 45 ns (max) tSD Delay from Serial Data Clock Falling Edge to DOR Rising Edge 25 45 ns (max) CIN Capacitance of Logic Inputs 10 pF COUT Capacitance of Logic Outputs 20 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+ or VD+), the current at that pin should be limited to 30 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55 VDC to ensure accurate conversions. 1135402 Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V + pin. Note 9: With the test condition for VREF (VREF+ − VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV. Note 10: Typical figures are at TJ = TA = 25°C and represent most likely parametric norm. Note 11: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive fullscale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figures 2, 3). Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions between 1 to 0 and 0 to +1 (see Figure 4). Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors. Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. Note 16: Channel leakage current is measured after the channel selection. www.national.com 10 Note 18: The ADC12030 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a maximum repeatability uncertainty of 0.2 LSB. Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum. Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output data from these modes are not an indication of the accuracy of a conversion result. 1135410 FIGURE 1. Transfer Characteristic 1135411 FIGURE 2. Simplified Error Curve vs. Output Code without Auto-Calibration or Auto-Zero Cycles 11 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Note 17: Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 1135412 FIGURE 3. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle 1135413 FIGURE 4. Offset or Zero Error Voltage www.national.com 12 The following curves apply for 12-bit + sign mode after autocalibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9) Linearity Error Change vs. Clock Frequency Linearity Error Change vs. Temperature 1135453 1135454 Linearity Error Change vs. Reference Voltage Linearity Error Change vs. Supply Voltage 1135455 1135456 Full-Scale Error Change vs. Clock Frequency Full-Scale Error Change vs. Temperature 1135457 1135458 13 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Typical Performance Characteristics ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Full-Scale Error Change vs. Reference Voltage Full-Scale Error Change vs. Supply Voltage 1135460 1135459 Zero Error Change vs. Clock Frequency Zero Error Change vs. Temperature 1135461 1135462 Zero Error Change vs. Reference Voltage Zero Error Change vs. Supply Voltage 1135464 1135463 www.national.com 14 Digital Supply Current vs. Clock Frequency 1135465 1135466 Digital Supply Current vs. Temperature 1135467 15 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Analog Supply Current vs. Temperature ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. Bipolar Spectral Response with 1 kHz Sine Wave Input Bipolar Spectral Response with 10 kHz Sine Wave Input 1135468 1135469 Bipolar Spectral Response with 20 kHz Sine Wave Input Bipolar Spectral Response with 30 kHz Sine Wave Input 1135470 1135471 Bipolar Spectral Response with 40 kHz Sine Wave Input Bipolar Spectral Response with 50 kHz Sine Wave Input 1135472 www.national.com 1135473 16 Unipolar Signal-to-Noise Ratio vs. Input Frequency 1135474 1135475 Unipolar Signal-to-Noise + Distortion Ratio vs. Input Frequency Unipolar Signal-to-Noise + Distortion Ratio vs. Input Signal Level 1135476 1135477 Unipolar Spectral Response with 1 kHz Sine Wave Input Unipolar Spectral Response with 10 kHz Sine Wave Input 1135478 1135479 17 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Bipolar Spurious Free Dynamic Range ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Unipolar Spectral Response with 20 kHz Sine Wave Input Unipolar Spectral Response with 30 kHz Sine Wave Input 1135480 1135481 Unipolar Spectral Response with 40 kHz Sine Wave Input Unipolar Spectral Response with 50 kHz Sine Wave Input 1135482 www.national.com 1135483 18 DO “TRI-STATE” (t1H, tOH) DO except “TRI-STATE” 1135403 1135404 Leakage Current 1135405 Timing Diagrams DO Falling and Rising Edge DO “TRI-STATE” Falling and Rising Edge 1135418 1135419 DI Data Input Timing 1135420 19 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Test Circuits ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 DO Data Output Timing Using CS 1135421 DO Data Output Timing with CS Continuously Low 1135422 ADC12038 Auto Cal or Auto Zero 1135423 Note: DO output data is not valid during this cycle. www.national.com 20 1135424 ADC12038 Read Data without Starting a Conversion with CS Continuously Low 1135425 21 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 ADC12038 Read Data without Starting a Conversion Using CS ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 ADC12038 Conversion Using CS with 8-Bit Digital Output Format 1135426 ADC12038 Conversion Using CS with 16-Bit Digital Output Format 1135451 www.national.com 22 1135428 ADC12038 Conversion with CS Continuously Low and 16-Bit Digital Output Format 1135429 23 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 ADC12038 Conversion with CS Continuously Low and 8-Bit Digital Output Format ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 ADC12038 Software Power Up/Down Using CS with 16-Bit Digital Output Format 1135452 ADC12038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format 1135431 www.national.com 24 1135432 Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register. ADC12038 Configuration Modification—Example of a Status Read 1135433 Note: In order for all 9 bits of Status Information to be accessible, the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus sign, 12 bits, 12 bits plus sign, or greater. 25 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 ADC12038 Hardware Power Up/Down ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 1135435 *Tantalum **Monolithic Ceramic or better FIGURE 5. Recommended Power Supply Bypassing and Grounding 1135434 FIGURE 6. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins www.national.com 26 TABLE 1. Data Out Formats DO Formats 17 Bits with Sign without sign DB0 X DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB1 0 X X X Sign MSB MSB 13 Sign First Bits MSB 10 9 8 9 Sign Bits MSB 6 5 DB1 1 DB1 2 DB1 3 DB1 4 3 2 1 LSB X X X X LSB 10 9 8 7 6 5 4 7 6 5 4 3 2 1 LSB 4 3 2 1 LSB 17 Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign LSB 13 First Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign 9 Bits LSB 1 2 3 4 5 6 16 Bits 0 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 MSB 12 MSB First Bits 10 9 8 7 6 5 4 3 2 1 LSB 8 MSB Bits 6 5 4 3 2 1 LSB 16 Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB 0 0 0 LSB 12 First Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB 8 Bits LSB 1 2 3 4 5 6 MSB DB1 DB16 5 MSB Sign X = High or Low state. 27 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Format and Set-Up Tables ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 TABLE 2. ADC12038 Multiplexer Addressing Analog Channel Addressed and Assignment with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to MUXOUT2 MUX Address A/D Input Polarity Assignment Multiplexer Output Channel Assignment Mode DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CO A/DIN1 A/DIN2 MUXOUT MUXOUT M 1 2 L L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H H L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H − + − + + − + − − + − + − + − + + + + + + + − CH0 CH1 + − CH2 CH3 + − CH4 CH5 + CH6 CH7 − − + CH0 CH1 − + CH2 CH3 − + CH4 CH5 − + CH6 CH7 − + − CH0 COM − + − CH2 COM − + − CH4 COM − + − CH6 COM − + − CH1 COM − + − CH3 COM − + − CH5 COM − + − CH7 COM + + + Differential Single-Ended TABLE 3. ADC12034 Multiplexer Addressing MUX Address DI0 DI1 L L Analog Channel Addressed and Assignment with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to MUXOUT2 DI2 CH0 CH1 L L + − L H L H L L H H H L L H L H H H L H H H www.national.com − CH2 CH3 + − COM + − + + + Multiplexer Output Channel Assignment A/DIN1 A/DIN2 MUXOUT1 MUXOUT2 + − CH0 CH1 + CH2 CH3 − − + CH0 CH1 − + CH2 CH3 − + − CH0 COM − + − CH2 COM − + − CH1 COM − + − CH3 COM + + A/D Input Polarity Assignment 28 Mode Differential Single-Ended Analog Channel Addressed and Assignment with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to MUXOUT2 MUX Address DI0 DI1 CH0 CH1 L L + L H − − + H L + H H A/D Input Polarity Assignment COM + Multiplexer Output Channel Assignment Mode A/DIN1 A/DIN2 MUXOUT1 MUXOUT2 + CH0 CH1 − − + CH0 CH1 − + − CH0 COM − + − CH1 COM Differential Single-Ended Note: ADC12030 and ADC12H030 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins. TABLE 5. Mode Programming ADC12038 DI0 DI1 DI2 ADC12034 DI0 DI1 DI2 ADC12030 and ADC12032 DI0 DI1 DI4 DI5 DI6 DI7 DI3 DI4 DI5 DI6 DI2 DI3 DI4 DI5 See Tables 2, 3 or Table 4 L L L See Tables 2, 3 or Table 4 L L L See Tables 2, 3 or Table 4 L L H L L DI3 L Mode Selected (Current) DO Format (next Conversion Cycle) L 12 Bit Conversion 12 or 13 Bit MSB First H 12 Bit Conversion 16 or 17 Bit MSB First L 8 Bit Conversion 8 or 9 Bit MSB First L L L H H 12 Bit Conversion of Full-Scale 12 or 13 Bit MSB First See Tables 2, 3 or Table 4 L H L L 12 Bit Conversion 12 or 13 Bit LSB First See Tables 2, 3 or Table 4 L H L H 12 Bit Conversion 16 or 17 Bit LSB First See Tables 2, 3 or Table 4 L H H L 8 Bit Conversion 8 or 9 Bit LSB First L L L L L H H H 12 Bit Conversion of Offset 12 or 13 Bit LSB First L L L L H L L L Auto Cal No Change L L L L H L L H Auto Zero No Change L L L L H L H L Power Up No Change L L L L H L H H Power Down No Change L L L L H H L L Read Status Register No Change L L L L H H L H Data Out without Sign No Change H L L L H H L H Data Out with Sign No Change L L L L H H H L Acquisition Time—6 CCLK Cycles No Change L H L L H H H L Acquisition Time—10 CCLK Cycles No Change H L L L H H H L Acquisition Time—18 CCLK Cycles No Change H H L L H H H L Acquisition Time—34 CCLK Cycles No Change L L L L H H H H User Mode No Change H Test Mode (CH1–CH7 become Active Outputs) No Change H X X X H H H Note: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first, and user mode. X = Don't Care TABLE 6. Conversion/Read Data Only Mode Programming CS CONV PD Mode L L L See Table 5 for Mode L H L Read Only (Previous DO Format). No Conversion. H X L Idle X X H Power Down X = Don't Care 29 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 TABLE 4. ADC12032 and ADC12030 Multiplexer Addressing ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 TABLE 7. Status Register Status Bit Location DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 Status Bit PU PD Cal 8 or 9 12 or 13 16 or 17 Sign Justification Test Mode “High” indicates an 8 or 9 bit format “High” indicates a 12 or 13 bit format “High” indicates a 16 or 17 bit format Device Status Function “High” indicates a Power Up Sequence is in progress www.national.com “High” indicates a Power Down Sequence is in progress “High” indicates an AutoCal Sequence is in progress DO Output Format Status 30 “High” indicates that the sign bit is included. When “Low” the sign bit is not included. When “High” the conversion result will be output MSB first. When “Low” the result will be output LSB first. When “High” the device is in test mode. When “Low” the device is in user mode. Some of the device/package combinations are obsolete and are described here for reference only. Please see our web site for availability. 1.0 DIGITAL INTERFACE 1.1 Interface Concepts The example in Figure 7 shows a typical sequence of events after the power is applied to the ADC12030/2/4/8: 1135436 FIGURE 7. Typical Power Supply Power Up Sequence 1.3 CS Low Continuously Considerations When CS is continuously low, it is important to transmit the exact number of SCLK pulses that the ADC expects. Not doing so will desynchronize the serial communications to the ADC. When the supply power is first applied to the ADC, it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the ADC expects to see is the same as the digital output word length. The digital output word length is controlled by the Data Out (DO) format. The DO format maybe changed any time a conversion is started or when the sign bit is turned on or off. The table below details out the number of clock periods required for different DO formats: The first instruction input to the A/D via DI initiates Auto-Cal. The data output on DO at that time is meaningless and is completely random. To determine whether the Auto Cal has been completed, a read status instruction is issued to the A/ D. Again the data output at that time has no significance since the Auto Cal procedure modifies the data in the output shift register. To retrieve the status information, an additional read status instruction is issued to the A/D. At this time the status data is available on DO. If the Cal signal in the status word, is low Auto Cal has been completed. Therefore, the next instruction issued can start a conversion. The data output at this time is again status information. To keep noise from corrupting the A/D conversion, status can not be read during a conversion. If CS is strobed and is brought low during a conversion, that conversion is prematurely ended. EOC can be used to determine the end of a conversion or the A/D controller can keep track in software of when it would be appropriate to communicate to the A/D again. Once it has been determined that the A/D has completed a conversion, another instruction can be transmitted to the A/D. The data from this conversion can be accessed when the next instruction is issued to the A/D. Note, when CS is low continuously it is important to transmit the exact number of SCLK cycles, as shown in the timing diagrams. Not doing so will desynchronize the serial communication to the A/D. (See Section 1.3.) Number of SCLKs Expected DO Format 8-Bit MSB or LSB First 12-Bit MSB or LSB First 16-Bit MSB or LSB first SIGN OFF 8 SIGN ON 9 SIGN OFF 12 SIGN ON 13 SIGN OFF 16 SIGN ON 17 If erroneous SCLK pulses desynchronize communications, the simplest way to recover is by cycling the power supply to the device. Not being able to easily resynchronize the device is a shortcoming of leaving CS low continuously. The number of clock pulses required for an I/O exchange may be different for the case when CS is left low continuously vs. the case when CS is cycled. Take the I/O sequence detailed in Figure 7 (Typical Power Supply Sequence) as an example. The table below lists the number of SCLK pulses required for each instruction: 1.2 Changing Configuration The configuration of the ADC12030/2/4/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit MSB First, 10 CCLK acquisition time, user mode, no Auto Cal, no Auto Zero, and power up mode. Changing the acquisition time and turning the sign bit on and off requires an 8-bit instruction to be issued to the ADC. This instruction will not start a conversion. The instructions that select a multiplexer address and format the output data do start a conversion. Figure 8 describes an example of changing the configuration of the ADC12030/2/4/8. During I/O sequence 1, the instruction on DI configures the ADC12030/2/4/8 to do a conversion with 12-bit +sign resolution. Notice that when the 6 CCLK Acquisition and Data Out without Sign instructions are issued to the ADC, I/O sequences 2 and 3, a new conversion is not started. The data output during these instructions is from conversion N which was started during I/O sequence 1. The Configuration Modification timing diagram describes in detail the sequence of Instruction CS Low Continuously CS Strobed Auto Cal 13 SCLKs 8 SCLKs Read Status 13 SCLKs 8 SCLKs Read Status 13 SCLKs 8 SCLKs 12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs 12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs 1.4 Analog Input Channel Selection The data input on DI also selects the channel configuration (see Tables 2, 3, 4, 5). In Figure 8 the only times when the 31 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 events necessary for a Data Out without Sign, Data Out with Sign, or 6/10/18/34 CCLK Acquisition time mode selection. Table 5 describes the actual data necessary to be input to the ADC to accomplish this configuration modification. The next instruction, shown in Figure 8, issued to the A/D starts conversion N+1 with 8 bits of resolution formatted MSB first. Again the data output during this I/O cycle is the data from conversion N. The number of SCLKs applied to the A/D during any conversion I/O sequence should vary in accord with the data out word format chosen during the previous conversion I/O sequence. The various formats and resolutions available are shown in Table 1. In Figure 8, since 8-bit, without sign, MSB first format was chosen during I/O sequence 4, the number of SCLKs required during I/O sequence 5 is 8. In the following I/O sequence the format changes to 12-bit without sign MSB first; therefore the number of SCLKs required during I/O sequence 6 changes accordingly to 12. Applications Information ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 channel configuration could be modified is during I/O sequences 1, 4, 5 and 6. Input channels are reselected before the start of each new conversion. Shown below is the data bit stream required on DI, during I/O sequence number 4 in Figure 8, to set CH1 as the positive input and CH0 as the negative input for the different versions of ADCs: Part Number 1.5 Power Up/Down The ADC may be powered down by taking the PD pin HIGH or by the instruction input on DI (see Table 5 and Table 6, and the Power Up/Down timing diagrams). When the ADC is powered down in this way, the A/D conversion circuitry is deactivated but the digital I/O circuitry is kept active. Hardware power up/down is controlled by the state of the PD pin. Software power-up/down is controlled by the instruction issued to the ADC. If a software power up instruction is issued to the ADC while a hardware power down is in effect (PD pin high) the device will remain in the power-down state. If a software power down instruction is issued to the ADC while a hardware power up is in effect (PD pin low), the device will power down. When the device is powered down by software, it may be powered up by either issuing a software power up instruction or by taking PD pin high and then low. If the power down command is issued during an A/D conversion, that conversion is interrupted, so the data output after power up cannot be relied upon. DI Data DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 ADC12H030 ADC12030 L H L L H L X X ADC12H032 ADC12032 L H L L H L X X ADC12H034 ADC12034 L H L L L H L X ADC12H038 ADC12038 L H L L L L H L Where X can be a logic high (H) or low (L). 1135437 FIGURE 8. Changing the ADC's Conversion Configuration 1.6 User Mode and Test Mode An instruction may be issued to the ADC to put it into test mode, which is used by the manufacturer to verify complete functionality of the device. During test mode CH0–CH7 become active outputs. If the device is inadvertently put into the test mode with CS continuously low, the serial communications may be desynchronized. Synchronization may be regained by cycling the power supply voltage to the device. Cycling the power supply voltage will also set the device into user mode. If CS is used in the serial interface, the ADC may be queried to see what mode it is in. This is done by issuing a “read STATUS register” instruction to the ADC. When bit 9 of the status register is high, the ADC is in test mode; when bit 9 is low the ADC, is in user mode. As an alternative to cycling the power supply, an instruction sequence may be used to return the device to user mode. This instruction sequence must be issued to the ADC using CS. The following table lists the instructions required to return the device to user mode. Note that this entire sequence, including both Test Mode and User Mode values, should be sent to recover from the test mode. www.national.com Instruction DI Data DI0 DI1 DI2 DI3 DI4 DI5 DI6 D17 TEST MODE H X X X H H H H Reset Test Mode Instructions L L L L H H H L L L L L H L H L L L L L H L H H USER MODE L L L L H H H H Power Up L L L L H L H L L L L H H L H L L H H H L Set DO with or H without Sign or L Set Acquisition Time H H or or L L Start a Conversion H H or H H or or L L or L L L H H or H or or L L L X = Don't Care The power up, data with or without sign, and acquisition time instructions should be resent after returning to the user mode. This is to ensure that the ADC is in the required state before a conversion is started. 32 2.0 THE ANALOG MULTIPLEXER For the ADC12038, the analog input multiplexer can be configured with 4 differential channels or 8 single ended channels 4 Differential Channels 8 Single-Ended Channels with COM as Zero Reference 1135438 1135439 FIGURE 9. Differential Configuration Single-Ended Configuration 1135440 1135441 A/DIN1 and A/DIN2 can be assigned as the + or − input A/DIN1 is + input A/DIN2 is − input FIGURE 10. CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1 pin in the differential configuration, while CH1, CH3, CH5, and CH7 can be assigned to the MUXOUT2 pin. In the differential configuration, the analog inputs are paired as follows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7. The A/DIN1 and A/DIN2 pins can be assigned positive or negative polarity. With the single-ended multiplexer configuration CH0 through CH7 can be assigned to the MUXOUT1 pin. The COM pin is always assigned to the MUXOUT2 pin. A/DIN1 is assigned as the positive input; A/DIN2 is assigned as the negative input. (See Figure 10). The Multiplexer assignment tables for the ADC12030,2,4,8 (Tables 2, 3, 4) summarize the aforementioned functions for the different versions of A/Ds. 2.1 Biasing for Various Multiplexer Configurations Figure 11 is an example of biasing the device for single-ended operation. The sign bit is always low. The digital output range is 0 0000 0000 0000 to 0 1111 1111 1111. One LSB is equal to 1 mV (4.1V/4096 LSBs). 33 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 with the COM input as the zero reference or any combination thereof (see Figure 9). The difference between the voltages on the VREF+ and VREF− pins determines the input voltage span (VREF). The analog input voltage range is 0 to VA+. Negative digital output codes result when VIN− > VIN+. The actual voltage at VIN− or VIN+ cannot go below AGND. 1.7 Reading the Data Without Starting a Conversion The data from a particular conversion may be accessed without starting a new conversion by ensuring that the CONV line is taken high during the I/O sequence. See the Read Data timing diagrams. Table 6 describes the operation of the CONV pin. ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 1135446 FIGURE 11. Single-Ended Biasing For pseudo-differential signed operation, the biasing circuit shown in Figure 12 shows a signal AC coupled to the ADC. This gives a digital output range of −4096 to +4095. With a 2.5V reference, 1 LSB is equal to 610 µV. Although, the ADC is not production tested with a 2.5V reference, when VA+ and VD+ are +5.0V linearity error typically will not change more than 0.1 LSB (see the curves in the Typical Electrical Characteristics Section). With the ADC set to an acquisition time of 10 clock periods, the input biasing resistor needs to be 600Ω or less. Notice though that the input coupling capacitor needs to be made fairly large to bring down the high pass corner. Increasing the acquisition time to 34 clock periods (with a 5 MHz CCLK frequency) would allow the 600Ω to increase to 6k, which with a 1 µF coupling capacitor would set the high pass corner at 26 Hz. Increasing R, to 6k would allow R2 to be 2k. 1135447 FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC An alternative method for biasing pseudo-differential operation is to use the +2.5V from the LM4040 to bias any amplifier circuits driving the ADC as shown in Figure 13. The value of the resistor pull-up biasing the LM4040-2.5 will depend upon the current required by the op amp biasing circuitry. In the circuit of Figure 13 some voltage range is lost since the amplifier will not be able to swing to +5V and GND with a single +5V supply. Using an adjustable version of the LM4041 www.national.com to set the full scale voltage at exactly 2.048V and a lower grade LM4040D-2.5 to bias up everything to 2.5V as shown in Figure 14 will allow the use of all the ADC's digital output range of −4096 to +4095 while leaving plenty of head room for the amplifier. Fully differential operation is shown in Figure 15. One LSB for this case is equal to (4.1V/4096) = 1 mV. 34 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 1135448 FIGURE 13. Alternative Pseudo-Differential Biasing 1135449 FIGURE 14. Pseudo-Differential Biasing without the Loss of Digital Output Range 35 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 1135450 FIGURE 15. Fully Differential Biasing an initial adjustment to null reference voltage induced fullscale errors. Below are recommended references along with some key specifications. 3.0 REFERENCE VOLTAGE The difference in the voltages applied to the VREF+ and VREF − defines the analog input span (the difference between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist. The voltage sources driving VREF+ or VREF− must have very low output impedance and noise. The circuit in Figure 16 is an example of a very stable reference appropriate for use with the device. Part Number Temperature Coefficient LM4041CI-Adj ±0.5% ±100ppm/°C LM4040AI-4.1 ±0.1% ±100ppm/°C LM4120AI-4.1 ±0.2% ±50ppm/°C LM4121AI-4.1 ±0.2% ±50ppm/°C LM4050AI-4.1 ±0.1% ±50ppm/°C LM4030AI-4.1 ±0.05% ±10ppm/°C LM4140AC-4.1 ±0.1% ±3.0ppm/°C Circuit of Figure 16 Adjustable ±2ppm/°C The reference voltage inputs are not fully differential. The ADC12030/2/4/8 will not generate correct conversions or comparisons if VREF+ is taken below VREF−. Correct conversions result when VREF+ and VREF− differ by 1V and remain, at all times, between ground and VA+. The VREF common mode range, (VREF+ + VREF−)/2 is restricted to (0.1 × VA+) to (0.6 × VA+). Therefore, with VA+ = 5V the center of the reference ladder should not go below 0.5V or above 3.0V. Figure 17 is a graphic representation of the voltage restrictions on VREF+ and VREF−. 1135442 *Tantalum FIGURE 16. Low Drift Extremely Stable Reference Circuit The ADC12030/2/4/8 can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog input voltage is proportional to the voltage used for the ADC's reference voltage. When this voltage is the system power supply, the VREF+ pin is connected to VA+ and VREF− is connected to ground. This technique relaxes the system reference stability requirements because the analog input voltage and the ADC reference voltage move together. This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference inputs. Typically, the reference voltage's magnitude will require www.national.com Output Voltage Tolerance 36 1135445 FIGURE 17. VREF Operating Range 4.0 ANALOG INPUT VOLTAGE RANGE The ADC12030/2/4/8's fully differential ADC generate a two's complement output that is found by using the equations shown below: for (12-bit) resolution the Output Code = 7.0 INPUT BYPASS CAPACITANCE External capacitors (0.01 µF–0.1 µF) can be connected between the analog input pins, CH0–CH7, and analog ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors will not degrade the conversion accuracy. for (8-bit) resolution the Output Code = 8.0 NOISE The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects of the noise sources. Round off to the nearest integer value between −4096 to 4095 for 12-bit resolution and between −256 to 255 for 8-bit resolution if the result of the above equation is not a whole number. Examples are shown in the table below: VREF+ VREF− VIN+ VIN− Digital Output Code +2.5V +1V +1.5V 0V 0,1111,1111,1111 +4.096V 0V +3V 0V 0,1011,1011,1000 +4.096V 0V +4.096V 0V 9.0 POWER SUPPLIES Noise spikes on the VA+ and VD+ supply lines can cause conversion errors; the comparator will respond to the noise. The ADC is especially sensitive to any power supply spikes that occur during the auto-zero or linearity correction. The minimum power supply bypassing capacitors recommended are low inductance tantalum capacitors of 10 µF or greater paralleled with 0.1 µF monolithic ceramic capacitors. More or different bypassing may be necessary depending on the overall system requirements. Separate bypass capacitors should be used for the VA+ and VD+ supplies and placed as close as possible to these pins. +2.499V +2.500V 1,1111,1111,1111 0V +4.096V 1,0000,0000,0000 5.0 INPUT CURRENT At the start of the acquisition window (tA) a charging current flows into or out of the analog input pins (A/DIN1 and A/DIN2) depending on the input voltage polarity. The analog input pins are CH0–CH7 and COM when A/DIN1 is tied to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value of this input current will depend on the actual input voltage applied, the source impedance and the internal multiplexer switch on resistance. With MUXOUT1 tied to A/DIN1 and MUXOUT2 tied to A/DIN2 the internal multiplexer switch on resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux on resistance is typically 750Ω. 10.0 GROUNDING The ADC12030/2/4/8's performance can be maximized through proper grounding techniques. These include the use of separate analog and digital areas of the board with analog and digital components and traces located only in their respective areas. Bypass capacitors of 0.01 µF and 0.1 µF surface mount capacitors and a 10 µF are recommended at each of the power supply pins for best performance. These 37 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 6.0 INPUT SOURCE RESISTANCE For low impedance voltage sources (<600Ω), the input charging current will decay, before the end of the S/H's acquisition time of 2 µs (10 CCLK periods with fC = 5 MHz), to a value that will not introduce any conversion errors. For high source impedances, the S/H's acquisition time can be increased to 18 or 34 CCLK periods. For less ADC resolution and/or slower CCLK frequencies the S/H's acquisition time may be decreased to 6 CCLK periods. To determine the number of clock periods (Nc) required for the acquisition time with a specific source impedance for the various resolutions the following equations can be used: 12 Bit + Sign NC = [RS + 2.3] × fC × 0.824 8 Bit + Sign NC = [RS + 2.3] × fC × 0.57 Where fC is the conversion clock (CCLK) frequency in MHz and RS is the external source resistance in kΩ. As an example, operating with a resolution of 12 Bits+sign, a 5 MHz clock frequency and maximum acquisition time of 34 conversion clock periods the ADC's analog inputs can handle a source impedance as high as 6 kΩ. The acquisition time may also be extended to compensate for the settling or response time of external circuitry connected between the MUXOUT and A/ DIN pins. An acquisition is started by a falling edge of SCLK and ended by a rising edge of CCLK (see timing diagrams). If SCLK and CCLK are asynchronous one extra CCLK clock period may be inserted into the programmed acquisition time for synchronization. Therefore with asynchronous SCLK and CCLKs the acquisition time will change from conversion to conversion. ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 capacitors should be located as close to the bypassed pin as practical, especially the smaller value capacitors. to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise (S/N), signal-to-noise + distortion ratio (S/(N + D)), effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter's capability. An A/D converter's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter's input, and the transform is then performed on the digitized waveform. S/(N + D) and S/N are calculated from the resulting FFT data, and a spectral plot may also be obtained. Typical values for S/N are shown in the table of Electrical Characteristics, and spectral plots of S/(N + D) are included in the typical performance curves. The A/D converter's noise and distortion levels will change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. This can be seen in the S/(N + D) versus frequency curves. Effective number of bits can also be useful in describing the A/D's noise and distortion performance. An ideal A/D converter will have some amount of quantization noise, determined by its resolution, and no distortion, which will yield an optimum S/(N + D) ratio given by the following equation: 11.0 CLOCK SIGNAL LINE ISOLATION The ADC12030/2/4/8's performance is optimized by routing the analog input/output and reference signal conductors as far as possible from the conductors that carry the clock signals to the CCLK and SCLK pins. Maintaining a separation of at least 7 to 10 times the height of the clock trace above its reference plane is recommended. 12.0 THE CALIBRATION CYCLE A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough time to stabilize after initial turn-on. During the calibration cycle, correction values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors. These values are stored in internal RAM and used during an analog-to-digital conversion to bring the overall full-scale, offset, and linearity errors down to the specified limits. Full-scale error typically changes ±0.4 LSB over temperature and linearity error changes even less; therefore it should be necessary to go through the calibration cycle only once after power up if the Power Supply Voltage and the ambient temperature do not change significantly (see the curves in the Typical Performance Characteristics). S/(N + D) = (6.02 × n + 1.76) dB where "n" is the A/D's resolution in bits. Since the ideal A/D converter has no distortion, the effective bits of a real A/D converter, therefore, can be found by: 13.0 THE AUTO-ZERO CYCLE To correct for any change in the zero (offset) error of the A/D, the auto-zero cycle can be used. It may be necessary to do an auto-zero cycle whenever the ambient temperature or the power supply voltage change significantly. (See the curves titled “Zero Error Change vs. Ambient Temperature” and “Zero Error Change vs. Supply Voltage” in the Typical Performance Characteristics.) n(effective) = ENOB = (S/(N + D) - 1.76 / 6.02 As an example, this device with a differential signed 5V, 1 kHz sine wave input signal will typically have a S/(N + D) of 77 dB, which is equivalent to 12.5 effective bits. 15.0 AN RS232 SERIAL INTERFACE Shown on the following page is a schematic for an RS232 interface to any IBM and compatible PCs. The DTR, RTS, and CTS RS232 signal lines are buffered via level translators and connected to the ADC12038's DI, SCLK, and DO pins, respectively. The D flip flop drives the CS control line. 14.0 DYNAMIC PERFORMANCE Many applications require the A/D converter to digitize AC signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the A/D converter's performance with AC input signals. The important specifications for AC applications reflect the converter's ability 1135444 Note: VA+, VD+, and VREF+ on the ADC12038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF caps. The assignment of the RS232 port is shown below COM1 www.national.com B7 B6 B5 B4 B3 B2 B1 B0 Input Address 3FE X X X CTS X X X X Output Address 3FC X X X 0 X X RTS DTR 38 power up, 12- or 13-bit MSB first, and user mode. Auto Cal, Auto Zero, Power Up and Power Down instructions do not change these default settings. The following power up sequence should be followed: 1. Run the program 2. Prior to responding to the prompt apply the power to the ADC12038 3. Respond to the program prompts It is recommended that the first instruction issued to the ADC12038 be Auto Cal (see Section 1.1). 39 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 A sample program, written in Microsoft QuickBasic, is shown on the next page. The program prompts for data mode select instruction to be sent to the A/D. This can be found from the Mode Programming table shown earlier. The data should be entered in “1”s and “0”s as shown in the table with DI0 first. Next the program prompts for the number of SCLKs required for the programmed mode select instruction. For instance, to send all “0”s to the A/D, selects CH0 as the +input, CH1 as the −input, 12-bit conversion, and 13-bit MSB first data output format (if the sign bit was not turned off by a previous instruction). This would require 13 SCLK periods since the output data format is 13 bits. The ADC powers up with No Auto Cal, No Auto Zero, 10 CCLK Acquisition Time, 12-bit conversion, data out with sign, ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Code Listing: 'variables DOL=Data Out word length, DI=Data string for A/D DI input, ' DO=A/D result string 'SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) 'set RTS HIGH OUT &H3FC, (&HFE AND INP(&H3FC)) 'set DTR LOW OUT &H3FC, (&HFD AND INP(&H3FC)) 'set RTS LOW OUT &H3FC, (&HEF AND INP(&H3FC)) 'set B4 low 10 LINE INPUT “DI data for ADC12038 (see Mode Table on data sheet)”; DI$ INPUT “ADC12038 output word length (8,9,12,13,16 or 17)”; DOL 20 'SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) 'set RTS HIGH OUT &H3FC, (&HFE AND INP(&H3FC)) 'set DTR LOW OUT &H3FC, (&HFD AND INP(&H3FC)) 'set RTS LOW 'SET CS# LOW OUT &H3FC, (&H2 OR INP (&H3FC)) 'set RTS HIGH OUT &H3FC, (&H1 OR INP(&H3FC)) 'set DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'set RTS LOW DO$= “ ” 'reset DO variable OUT &H3FC, (&H1 OR INP(&H3FC)) 'SET DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low FOR N=1 TO 8 Temp$=MID$(DI$,N,1) IF Temp$=“0” THEN OUT &H3FC,(&H1 OR INP(&H3FC)) ELSE OUT &H3FC, (&HFE AND INP(&H3FC)) END IF 'out DI OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high IF (INP(&H3FE) AND 16)=16 THEN DO$=DO$+“0” ELSE DO$=DO$+“1” END IF 'input DO OUT &H3FC, (&H1 OR INP(&H3FC)) 'SET DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low NEXT N IF DOL>8 THEN FOR N=9 TO DOL OUT &H3FC, (&H1 OR INP(&H3FC)) 'SET DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high IF (INP(&H3FE) AND &H10)=&H10 THEN DO$=DO$+“0” ELSE DO$=DO$+“1” END IF NEXT N END IF OUT &H3FC, (&HFA AND INP(&H3FC)) 'SCLK low and DI high FOR N=1 TO 500 NEXT N PRINT DO$ INPUT “Enter “C” to convert else “RETURN” to alter DI data”; s$ IF s$=“C” OR s$=“c” THEN GOTO 20 ELSE GOTO 10 END IF END www.national.com 40 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Physical Dimensions inches (millimeters) unless otherwise noted Order Number ADC12030CIWM or ADC12H030CIWM NS Package Number M16B Order Number ADC12032CIWM NS Package Number M20B 41 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Order Number ADC12034CIWM NS Package Number M24B Order Number ADC12H034CIMSA NS Package Number MSA24 www.national.com 42 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Order Number ADC12038CIWM or ADC12H038CIWM NS Package Number M28B Order Number ADC12034CIN NS Package Number N24C 43 www.national.com ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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