INDEX MX98741 XRC 100 BASE-TX/FX REPEATER CONTROLLER 1.0 FEATURES • Eight 100 BASE-TX/FX ports; each port individually configurable to TX or FX • Direct interface with analog clock generation/recovery chips • Three Media Independent Interface (MII) • Expandable to increase number of repeater ports • Low latency design simplified high port number Class II repeater implementation • Management features accessible through MII or serial ports • All ports can be separately isolated or partitioned in reponse to fault conditions • Conforms to IEEE 802.3u Repeater Unit Specification • LED display for TX/FX port activities and collisions • 208-pin, CMOS device in PQFP package 2.0 GENERAL DESCRIPTION Control Functions and management status are implemented through internal registers. These registers are accessed via either standard MII management interface (MDC, MDIO) or several serial ports. These serial ports are accessed easily by hardware for debugging and configuration purposes. A dedicated management chip can also utilize these serial ports to access the XRC. The MX98741 (100BASE-TX Repeater Controller, XRC) is a 208-pin PQFP device that interfaces directly with offshell clock generation/recovery chips. Eight ports can be configured as 100 BASE-TX or FX ports individually. Three additional ports have Media Independent Interfaces (MII) which allow easy connection of management and bridge devices. The expansion port allows multiple XRCs to be linked together to form a repeater of high port counts. LEDs are provided for visual monitoring of TX/FX port activities and collisions. The XRC's design inserts minimum delay between the TX/FX ports and the expansion port. A master-slave type arbitration is also implemented to shorten the communciation time among multiple XRCs. As a result, design for Class II stackable hub is greatly simplified. P/N:PM0342 REV. 1.4, NOV. 07, 1998 1 INDEX MX98741 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 GND GND MDC MDIO CRSC RXDVC TXERC TXDC3 TXDC2 TXDC1 TXDC0 TXENC VCC RXCLKJ COL RXER RXD3 RXD2 RXD1 RXD0 GND TXCLK COCLK VCC CRSE RXDVB TXERB TXDB3 TXDB2 TXDB1 TXDB0 TXENB GND CRSA RXDVA TXERA TXDA3 TXDA2 TXDA1 TXDA0 TXENA TDAT24 TDAT23 TDAT22 TDAT21 TDAT20 RDAT24 RDAT23 RDAT22 RDAT21 RDAT20 GND 3.0 PIN CONFIGURATION 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 MX98741 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 GND SIGDET2 RSCLK2 GND TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 VCC RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 VCC SIGDET1 RSCLK1 ACTP7 ACTP6 ACTP5 ACTP4/XRCADD4 VCC ACTP3/XRCADD3 ACTP2/XRCADD2 ACTP1/XRCADD1 ACTP0/XRCADD0 GND ANYACT BDATENL EXTCRS JAMI JAMO GND EFAT4 EDAT3 EDAT2 EDAT1 EDAT0 VCC VCC TDAT04 TDAT03 TDAT02 TDAT01 TDAT00 RDAT04 RDAT03 RDAT02 RDAT01 RDAT00 GND GND RSCLK6 SIGDET6 RDAT60 RDAT61 RDAT62 RDAT63 RDAT64 TDAT60 TDAT61 TDAT62 TDAT63 TDAT64 GND RSCLK7 SIGDET7 RDAT70 RDAT71 RDAT72 RDAT73 RDAT74 GND TDAT70 TDAT71 TDAT72 TDAT73 TDAT74 VDD VCC XACTLED0 XACTLED1 XACTLED2 XACTLED3 XACTLED4 XACTLED5 XACTLED6 XACTLED7 GND VCC REGCK REGLTCH GND RDXWR PIDISI PTSCEN JBFLO PARTNK ISC GND RSCLKO SIGDETO GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VCC RSCLK3 SIGDET3 RDAT30 RDAT31 RDAT32 RDAT33 RDAT34 GND GND TDAT30 TDAT31 TDAT32 TDAT33 TDAT34 GND GND RSCLK4 SIGDET4 VCC RDAT40 RDAT41 RDAT42 RDAT43 RDAT44 GND TDAT40 TDAT41 TDAT42 TDAT43 TDAT44 RSCLK5 SIGDET5 RDAT50 RDAT51 RDAT52 RDAT53 RDAT54 VCC VCC TDAT50 TDAT51 TDAT52 TDAT53 TDAT54 GND SCRCTRL RESETL XCOLED TEST TSEL GND P/N:PM0342 REV. 1.4, NOV. 07, 1996 2 INDEX MX98741 4.0 PIN DESCRIPTION Table 4-1 Pin Description for MX98741 PAD # 59-63 96-100 111-115 167-171 183-187 197-201 9-13 23-27 135 54-58 90-94 106-110 160-164 177-181 190-194 4-8 17-21 50,87 102,158 174,188 2,15 51,88 103,159 175,189 3,16 134 A. MX Data Transceiver (Am78965/Am78966 or MC68836), 98 pins Name I/O Description TDAT[0:7][0:4] O, EXP Transmit Data. These five outputs are 4B/5B encoded transmit data symbols, driven at the rising edge of TXCLK. TDAT4 is the Most Significant Bit. TXCLK I, TTL Transmit Clock. This pin supplies the frequency reference to the transmit logic. It should be driven by an external 25 MHz crystal-controlled clock source. Receive Data. These 5-bit parallel data symbols from transceiver are latched by the rising edge of RSCLK. RDAT4 is the Most Significant Bit. RDAT[0:7][0:4] I, TTL RSCLK[0:7] I, TTL Recovered Sumbol Clock. This is a 25 MHz clock, which is derived from the clock synchroniztion PLL circuit. SIGDET[0:7] I, TTL Signal Detect. This signal indicates that the received signal is above the detection threshold and will be used for the link test state machine. COCLK I, TTL Core Clock. 50M Clock input used by Repeater Core. P/N:PM0342 REV. 1.4, NOV. 07, 1996 3 INDEX MX98741 PAD # 72 Name JAMO 73 JAMI 75 EDATENL 66-70 EDAT[0:4] 84-86 ACTP[5:8] 78-81, 83 ACTP[0:4] /XRCADD[0:4] 76 ANYACT 74 EXTCRS 204 RESETL 203 SCRCTRL B. Expansion Port, 18 pins I/O Description O, TTL Forced Jam Out. Active High. The OR’d forced jam signals exclude JAMI input) controlled by Carrier Integrity Monitor of each port. If collision occurs inside the XRC, this pin is also asserted. I, Schm Forced Jam Input. Active High. Asserted by external arbiter, and XRC will generate JAM patterns to all its ports. Note : Glitch on JAMI and EDATENL may cause internal state machine malfunction. I, Schm Enable Expansion Data. Active Low. Asserted by an external arbitor. XRC will drive data into EDAT. I/O, EXP Expansion Data. Bidirectional 5-bit wide data. By default, EDAT is an input. When EDATENL is low, EDAT changed from input mode to output mode. Internally pull-up. O, TTL Activity Out. This is the activity of port 5..8 synchronous to COCLK (50M clock used by core). It also serves as data framing signal for the packet on EDAT. ACTP leads EDAT's /J/K/ pattern by more than 80 ns and deasserted 40ns after the /T/R/ or the last byte of jam patterns. I/O, TTL Activity Out/Physical Address. When RESETL goes high, value on ACTP[0;4] will be latched into internal buffer as physical address of XRC. After reset, these five pins have the same function as ACTP[5:8]. O, TTL Any Activity. Active High. The OR’d ACTP[7:0] and TXEN A to C. This is used as an indication that an XRC is ready to drive data into EDAT. I, Schm External Carrier Sense. Active high. Asserted by an external arbitor indicating activity from other XRC's at the expansion port. C. Miscellaneous Pins, 2 pins I, Schm Reset. Active Low. This signal is output by the system to reset all the logic on the chip. I, TTL Scrambler Control. If high, the scrambler/descrambler of each port is individually controlled by MII register 17. If low, the scrambler/ descrambler is bypassed in all the ports. P/N:PM0342 REV. 1.4, NOV. 07, 1996 4 INDEX MX98741 PAD # 47 Name PARTLNK I/O O, TTL 46 JBFLO O, TTL 45 PTSCEN I/O, TTL 44 PIDIS I/O, TTL 48 ISO O, TTL 43 RDXWR I, TTL 41 REGLTCH I/O, TTL 40 REGCK I, TTL D. Register Access Pins, 8 pins Description Partition/Link Status. This pin shows the status of internal register #18 in round-robin fashion starting at port 0 partition status and ending at port7 Link Status after REGLTCH is deasserted. Jabber/Buffer Status. This pin shows the status of internal register #19 in round-robin fashion starting at port 0 Jabber Status and ending at port 7 Elastic Buffer Over/Underflow Status after REGLTCH is deasserted. Port/Scrambler Enable. If RDXWR is high, each port's enable/disable status (register #17) will be displayed at the rising edge of REGCK in round-robin fashion starting at port 0 Port 0 Enable status and ending at port 7 Scrambler Enable status after REGLTCH is deasserted. If RDXWR is low, 16-bit data can be written into the XRC at the rising edge of REGCK in round-robin fashion starting at port 0 Port Enable Signal and ending at port 7 Scrambler enable after REGLTCH is asserted high. Internally pull-up. Partition/Isolation Disable. If RDXWR is high, each port's partition/ Isolation Disable status will be displayed at the rising edge of REGCK in round-robin fashion starting at port 0 partition disable status and ending at port7 Isolation Disable status after REGLTCH is deasserted. If RDXWR is low, 16-bit data can be written into the XRC at the rising edge of REGCK in round-robin fashion starting at port 0 partition disable status and ending at port 7 Isolation disable status after REGLTCH is asserted high. Internally pull-down. Isolation. Active High. Each port's isolation status will be displayed at the rising edge of REGCK in round-robin fashion starting at port0 after REGLTCH is deasserted. Read/Write. High indicates "Read" mode; register is being read out. REGLTCH is output. Low indicates "Write" mode; control registers are being written and REGLTCH is input. When RDXWR is programmed to "Write" Mode, internal "Read" status machine will be reset immediately. Register Latch. An output if RDXWR is high; an input if RDXWR is low. At the rising edge of REGCK, PARTLNK, JBFLO, PTSCEN, PIDIS, ISO display bit 0 status of corresponding registers, at the rising edge of next REGCK, bit 1 status is displayed, etc. After bit 15 is displayed, REGLTCH is asserted at the rising edge of next REGCK. Note : Both Data and REGLTCH are driven at the falling edge of REGCK inside the XRC. To make sure the data setup time, it is strongly recommended that the frequency of REGCK is below 12.5 MHz. Internally pull-down. Register Clock. A clock used as reference to display various status of each port or to latch control information inside XRC. The recommended clock's frequency is below 12.5MHz. P/N:PM0342 REV. 1.4, NOV. 07, 1996 5 INDEX MX98741 PAD # 30-37 Name XACTLED[0:7] 205 XCOLED 116 TXENA 117-120 TXDA[0:3] 121 TXERA 122 RXDVA 123 CRSA 153 MDIO E. LED Pins, 9 pins I/O Description O, TTL Activity LED. Active Low. This pin provides a minimum 80ms ON time (low) and 20ms OFF time (high) for activities on each port. External buffers are necessary to drive LEDs. O, MII Collision LED. This pin is capable of driving LED directly to display Activity status. The ON (active low) time and OFF (active high) time of LED's is 80ms and 20ms respectively. F. Media Independent Interface (MII), 33 pins I, TTL Transmit Enable MII A. Synchronous to the TXCLK's rising edge. It is asserted by the MAC with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. I, TTL Transmit Data MII A. Synchronous to the TXCLK's rising edge. For each TXCLK period in which TXENA is asserted, TXDA[3:0] are also driven by the MAC. While TXENA is de-asserted, the value of TXDA[3:0] is ignored. TXDA3 is the Most Significant Bit. I, TTL Transmit Error MII A. Synchronous to the TXCLK's rising edge. When TXERA is asserted for one or more TXCLK period while TXENA is also asserted, one or more "HALT" symbols will present at TDAT4_0. O, TTL Receive Data Valid MII A. Synchronous to RXCLK's rising edge. This signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame delimiter. High impedance after reset. O, TTL Carrier Sense MII A. In TX mode, synchronous to RXCLK. This pin is asserted when (1) the receiving medium is not idle, or (2) the transmitting medium is not idle in the half-duplex mode. High impedance after reset. I/O, TTL Management Data Input/Output. A bi-directional signal. After reset, this pin is in high-impedance state. The selection of input/ output direction is based on IEEE 802.3u management functions (Section 22.2.4). Low after reset due to internally pull-down. When RDXWR is low (i.e. Write operation, MDIO will be forced to low to disable the function of MDC and MDIO. i.e. Programming internal registers through register access pins owns higher priority. P/N:PM0342 REV. 1.4, NOV. 07, 1996 6 INDEX MX98741 F. Media Independent Interface (MII, Continued) PAD # Name I/O Description 125 TXENB I, TTL Transmit Enable MII B. Synchronous to the TXCLK's rising edge. It is asserted by the MAC with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. 126-129 TXDB[0:3] I, TTL Transmit Data MII B. Synchronous to the TXCLK's rising edge. For each TXCLK period in which TXENB is asserted, TXDB[3:0] are also driven by the MAC. While TXENB is de-asserted, the value of TXDB[3:0] is ignored. TXDB3 is the Most Significant Bit. 130 TXERB I, TTL Transmit Error MII B. Synchronousto the TXCLK's rising edge. When TXERB is asserted for one or more TXCLK period while TXENB is also asserted, one or more "HALT" symbols will present at TDAT4_0. 131 RXDVB O, TTL Receive Data Valid MII B. Synchronous to RXCLK's rising edge. This signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame deliminter. High impedance after reset. 132 CRSB O, TTL Carrier Sense MII B. In TX mode, synchronous to RXCLK. This pin is asserted when (1) the receiving medium is not idle, or (2) the transmitting medium is not idle in the half-duplex mode. High impedance after reset. 145 TXENC I, TTL Transmit Enable MII C. Synchronous to the TXCLK's rising edge. It is asserted by the MAC with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. 146-149 TXDC[0:3] I, TTL Transmit Data MII C. Synchronous to the TXCLK's rising edge. For each TXCLK period in which TXENC is asserted, TXDC[3:0] are also driven by the MAC. While TXENC is de-asserted, the value of TXDC[3:0] is ignored. TXDC3 is the Most Significant Bit. 150 TXERC I, TTL Transmit Error MII C. Synchronousto the TXCLK's rising edge. When TXERC is asserted for one or more TXCLK period while TXENC is also asserted, one or more "HALT" symbols will present at TDAT4_0 151 RXDVC O, TTL 152 EDATACT O, TTL Receive Data Valid MII C. Synchronous to RXCLK's rising edge. This signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame deliminter. High impedance after reset. Expansion DATa Activity. When XRC is outputing data onto expansion EDAT, this pin will be asserted high. User can use this pin to control external EDAT bus switch in case multiple HUBs application is necessary. P/N:PM0342 REV. 1.4, NOV. 07, 1996 7 INDEX MX98741 PAD # 141 Name RXER I/O O, EXP 143 RXCLK O, MII 137-140 RXD[0:3] O, MII 142 COL O, EXP 154 MDC I, TTL G. Power/Ground/Test/Loopback, 39 pins 206 TEST I, TTL 207 1,14,22, 38,42,49 52,53,71, 77,101 104,105, 124,136, 155,156, 165,166, 173,182, 202,208 28,29, 39,64, 65,82, 89,95, 133,144, 157,176, 195,196 TSEL I, TTL Description Receive Error. Synchronous to RXCLK's rising edge. While RXDV is asserted, i.e. a frame is being received, this signal is asserted if any coding error is detected. High-impedence after reset. Receive Clock MII. 25 MHz continuous clock that provides the timing reference for the transfer of the RXDV, RXD and RXER signals. High-impedance after reset. Receive Data MII. Synchronous to RXCLK's rising edge. For each RXCLK period in which RXDV is asserted, RXD[3:0] should be latched by the MAC. While RXDV is deasserted, RXD[3:0] are the nibbles 5B/4B decoded from RDAT[4:0]. RXD3 is the Most Significant Bit. High-impedance after reset. Collision MII. This signal is asserted if both the receiving media and TXEN are active. High-impedance after reset. Management Data Clock. The timing reference for MDIO. The minumum high and low times are 200 ns each. No limitation on the maximum high and low time. Test. Industrial test pin. Set to 0 or left unconnected for normal operation. When programmed to logic 1, XRC is in test mode. Internal Pulldown. Test Mode Select. When TEST is high and TSEL is low, XRC is in "Real Time Counter" Mode; when TEST is high and TSEL is high, XRC is in "Test Mode Counter" mode. Internally pull down. GND Ground. VCC 5V Power Supply. P/N:PM0342 REV. 1.4, NOV. 07, 1996 8 INDEX MX98741 5.0 FUNCTIONAL & OPERATION DESCRIPTION 5.1 MINIMUM AND MAXIMUM MODE APPLICATION Arb XRC XRC DT& DT& DT& DT& PMD PMD PMD PMD Port 0 Port 7 Port 8 Port 15 Figure 5-1 Minimum Mode Operation for XRC TX PMD T4 PMD Bridge Bridge MII_A Arbitor Mgmnt MII_C MII_B XRC XRC DT& PMD DT& PMD DT& PMD DT& PMD Port 0 Port 7 Port 8 Port 15 Figure 5-2 Maximum Mode Operation for XRC P/N:PM0342 REV. 1.4, NOV. 07, 1996 9 INDEX MX98741 5.2 INTERNAL REGISTERS There are two ways to access the XRC internal registers. All the registers can be accessed through MII's MDC and MDIO. Although XRC connects to multiple 100-TX PHY's, they are all identical. Each XRC has only one PHY address as defined by ACTP[4:0] pins. If multiple XRC's are on the same MDIO bus, each of them should have different PHY address. Other non-XRC PHY devices (e.g. T4) are also allowed to be managed with the same management interface as long as PHY address of each device is distinct. Another way to access registers is through register access pins. Register 17 (Scrambler Enable and Port Enable), Register 18 (Link Status, Partition Status), Register 19 (Elastic Buffer Status and Jabber Status), Register 20 (Isolation Status), Register 21 (Isolation Disable and Partition Disable) can also be read through PTSCEN, PARTLNK, JBFLO, ISO and PIDIS, respectively. The exception are register 0 (Command Register), register 1 (Status Register), and register 16 (Port Reset Register) which can only be accessed through MDC and MDIO. The register access pins facilitate a simple read/write protocol suitable for hardware-only configuration and status display design. P/N:PM0342 REV. 1.4, NOV. 07, 1996 10 INDEX MX98741 A. Command Register (register #0) (R/W) Table 5-1 Control Register Bit Definition Bit(s) 0.15 Name Reset 0.14 Loop Back 0.13 Speed Selection 0.12 0.11 Auto-Negotiation Enable Power-Down 0.10 Isolate 0.9 Restart Auto-Negotiation 0.8 Duplex Mode 0.7 Collision Test 0.6:0 Reserved Description 1 : PHY reset. A 240ns reset pulse will be generated to reset XRC internal logic. 0 : normal operation 1 : enable loopback mode. 0 : disable loopback mode. The default setting is 0. Forced to 1 and indicate 100 Mb/s. Write 0 to this bit has no effect. Forced to 0 and indicate that Auto-Negotiation process is disabled. Write 1 to this bit has no effect. 1 : power-down. COCLK and TXCLK for each port will be disabled. Clock for Management Block will keep running. During power-down, all state machines will be reset to its default state. 0 : normal operation. 1 : electrically Isolate PHY from MII 0 : normal operation Forced to 0 and indicate that Auto-Negotiation process is disable. Write 1 to this bit has no effect. Forced to 0 and indicate that only Half Duplex is available. Write 1 to this bit has no effect. 1 : enable COL signal test. The PHY will assert the COL signal within 5120 ns in response to the assertion of TXEN. While this bit is set to one, the PHY will deassert the COL signal within 40 ns in response to the deassertion of TXEN. 0 : normal operation. Set to 0 after power on reset. Value 0 will be read when one tries to read these bits. P/N:PM0342 R/W R/W SC R/W R R R/W R/W R R R/W R REV. 1.4, NOV. 07, 1996 11 INDEX MX98741 B. Status Register (register #1) (R) Table 5-2 Status Register Bit Definition Bit(s) 1.15 1.14 1.13 1.12 1.11 1.10:6 1.5 1.4 1.3 1.2 1.1 1.0 Name 100BASE-T4 Description Forced to 0 and indicates that XRC is not able to perform 100BASE-T4. 100BASE-X Forced to 0 and indicates that XRC is not able to perform Full Duplex 100BASE-X Full Duplex. 100BASE-X Forced to 1 and indicates that XRC is able to perform Half Duplex 100BASE-X Half Duplex. 10 Mb/s Full Duplex Forced to 0 and indicates that XRC is not able to perform 10 Mb/s Full Duplex. 10 Mb/s Half Duplex Forced to 0 and indicates that XRC is not able to perform 10 Mb/s Half Duplex. Reserved Value 0 will be released by XRC when read. Auto-Negotiation Complete Forced to 0. Remote Fault Forced to 0. Auto-Negotiation Ability Forced to 0. Link Status 1 : All ports are link up. 0 : Any port is link fail. Will be set to 1 after this port is read. Jabber Detect 1 : Jabber condition in any port is detected. 0 : No Jabber condition detected for all ports Extended Capability Forced to 1. P/N:PM0342 R/W R R R R R R R R R R R R REV. 1.4, NOV. 07, 1996 12 INDEX MX98741 C. Port Reset Register (register #16) (R/W) Table 5-3 Port Reset Register Bit Definition Bit(s) Name 16.15:8 Reserved 16.7 ResetP7 16.6 ResetP6 16.5 ResetP5 16.4 ResetP4 16.3 16.2 ResetP3 ResetP2 16.1 ResetP1 16.0 ResetP0 Description Ignored when read. 1 : reset Port 7's Logic. 0 : not reset Port 7's Logic. Power on low. 1 : reset Port 6's Logic. 0 : not reset Port 6's Logic. Power on low. 1 : reset Port 5's Logic. 0 : not reset Port 5's Logic. Power on low. 1 : reset Port 4's Logic. 0 : not reset Port 4's Logic. Power on low. 1 : reset Port 3's Logic. 0 : not reset Port 3's Logic. Power on low. 1 : reset Port 2's Logic. 0 : not reset Port 2's Logic. Power on low. 1 : reset Port 1's Logic. 0 : not reset Port 1's Logic. Power on low. 1 : reset Port 0’s Logic. 0 : not reset Port 0’s Logic. Power on low. P/N:PM0342 R/W R R/W R/W R/W R/W R/W R/W R/W R/W REV. 1.4, NOV. 07, 1996 13 INDEX MX98741 D. Port Control Register (register #17) (R/W) Table 5-4 Port Control Register Bit Definition Bit(s) 17.15 Name ScrenP7 17.14 ScrenP6 17.13 ScrenP5 17.12 17.11 ScrenP4 ScrenP3 17.10 ScrenP2 17.9 ScrenP1 17.8 17.7 ScrenP0 EnP7 17.6 EnP6 17.5 EnP5 Description 1 : Enable Scrambler/Descrambler at Port 7 0 : Disable Scrambler/Descrambler at Port 7 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 6 0 : Disable Scrambler/Descrambler at Port 6 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 5 0 : Disable Scrambler/Descrambler at Port 5 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 4 0 : Disable Scrambler/Descrambler at Port 4 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 3 0 : Disable Scrambler/Descrambler at Port 3 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 2 0 : Disable Scrambler/Descrambler at Port 2 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 1 0 : Disable Scrambler/Descrambler at Port 1 The default value after power on is 1. 1 : Enable Scrambler/Descrambler at Port 0 0 : Disable Scrambler/Descrambler at Port 0 The default value after power on is 1. 1 : Enable RX/TX functions at Port 7. 0 : Disable RX/TX functions at Port 7. The default value after power on is 1. 1 : Enable RX/TX functions at Port 6. 0 : Disable RX/TX functions at Port 6. The default value after power on is 1. 1 : Enable RX/TX functions at Port 5. 0 : Disable RX/TX functions at Port 5. The default value after power on is 1. P/N:PM0342 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REV. 1.4, NOV. 07, 1996 14 INDEX MX98741 Table 5-4 Port Control Register Bit Definition (Continued) Bit(s) 17.4 Name EnP4 17.3 EnP3 17.2 17.1 17.0 EnP2 EnP1 EnP0 Description 1 : Enable RX/TX functions at Port 4. 0 : Disable RX/TX functions at Port 4. The default value after power on is 1. 1 : Enable RX/TX functions at Port 3. 0 : Disable RX/TX functions at Port 3. The default value after power on is 1. 1 : Enable RX/TX functions at Port 2. 0 : Disable RX/TX functions at Port 2. The default value after power on is 1. 1 : Enable RX/TX functions at Port 1. 0 : Disable RX/TX functions at Port 1. The default value after power on is 1. 1 : Enable RX/TX functions at Port 0. 0 : Disable RX/TX functions at Port 0. The default value after power on is 1. P/N:PM0342 R/W R/W R/W R/W R/W R/W REV. 1.4, NOV. 07, 1996 15 INDEX MX98741 E. Link and Partition Status Register (register #18) (R) Table 5-5 Link and Partition Status Register Bit Definition Bit(s) 18.15 Name LinkP7 18.14 LinkP6 18.13 LinkP5 18.12 18.11 LinkP4 LinkP3 18.10 LinkP2 18.9 LinkP1 18.8 18.7 LinkP0 PartP7 18.6 PartP6 18.5 PartP5 Description 1 : Link Status is OK at port 7 0 : Link Status is Fail at Port 7 Status is updated at every TXCLK clock. 1 : Link Status is OK at port 6 0 : Link Status is Fail at Port 6 Status is updated at every TXCLK clock. 1 : Link Status is OK at port 5 0 : Link Status is Fail at Port 5 Status is updated at every TXCLK clock. 1 : Link Status is OK at port 4 0 : Link Status is Fail at Port 4 Status is updated at every TXCLK clock. 1 : Link Status is OK at port 3 0 : Link Status is Fail at Port 3 Status is updated at every TXCLK clock. 1 : Link Status is OK at port 2 0 : Link Status is Fail at Port 2 Status is updated at every TXCLK clock. 1 : Link Status is OK at port 1 0 : Link Status is Fail at Port 1 Status is updated at every TXCLK clock. 1 : Link Status is OK at port 0 0 : Link Status is Fail at Port 0 Status is updated at every TXCLK clock. 1 : Port 7 has been partitioned 0 : Port 7 has not been partitioned Status is updated every 40 ns. 1 : Port 6 has been partitioned 0 : Port 6 has not been partitioned Status is updated every 40 ns. 1 : Port 5 has been partitioned 0 : Port 5 has not been partitioned Status is updated every 40 ns. P/N:PM0342 R/W R R R R R R R R R R R REV. 1.4, NOV. 07, 1996 16 INDEX MX98741 Table 5-5 Link and Partition Status Register Bit Definition (Continued) Bit(s) 18.4 Name PartP4 18.3 PartP3 18.2 PartP2 18.1 18.0 PartP1 PartP0 Description 1 : Port 4 has been partitioned 0 : Port 4 has not been partitioned Status is updated every 40 ns. 1 : Port 3 has been partitioned 0 : Port 3 has not been partitioned Status is updated every 40 ns. 1 : Port 2 has been partitioned 0 : Port 2 has not been partitioned Status is updated every 40 ns. 1 : Port 1 has been partitioned 0 : Port 1 has not been partitioned Status is updated every 40 ns. 1 : Port 0 has been partitioned 0 : Port 0 has not been partitioned Status is updated every 40 ns. P/N:PM0342 R/W R R R R R REV. 1.4, NOV. 07, 1996 17 INDEX MX98741 F. Elastic Buffer Over/Underflow and Jabber Status Register (register #19) (R) Table 5-6 Elastic Buffer Over/Underflow and Jabber Register Bit Definition Bit(s) 19.15 19.14 Name EBOUF7 EBOUF6 19.13 EBOUF5 19.12 EBOUF4 19.11 19.10 EBOUF3 EBOUF2 19.9 EBOUF1 19.8 EBOUF0 19.7 19.6 19.5 19.4 19.3 JABP7 JABP6 JABP5 JABP4 JABP3 Description 1 : Elastic Buffer Over/Underflow at Port 7 0 : Normal Condition. Clear to 0 by RESETL (or RESETP7). 1 : Elastic Buffer Over/Underflow at Port 6 0 : Normal Condition. Clear to 0 by RESET (or RESETP6). 1 : Elastic Buffer Over/Underflow at Port 5 0 : Normal Condition. Clear to 0 by RESET (or RESETP5). 1 : Elastic Buffer Over/Underflow at Port 4 0 : Normal Condition. Clear to 0 by RESET (or RESETP4). 1 : Elastic Buffer Over/Underflow at Port 3 0 : Normal Condition. Clear to 0 by RESET (or RESETP3). 1 : Elastic Buffer Over/Underflow at Port 2 0 : Normal Condition. Clear to 0 by RESET (or RESETP2). 1 : Elastic Buffer Over/Underflow at Port 1 0 : Normal Condition. Clear to 0 by RESET (or RESETP1). 1 : Elastic Buffer Over/Underflow at Port 0 0 : Normal Condition. Clear to 0 by RESET (or RESETP0). 1 : Receive Jabber Active at Port 7 0 : No Jabber condition at Port 7 1 : Receive Jabber Active at Port 6 0 : No Jabber condition at Port 6 1 : Receive Jabber Active at Port 5 0 : No Jabber condition at Port 5 1 : Receive Jabber Active at Port 4 0 : No Jabber condition at Port 4 1 : Receive Jabber Active at Port 3 0 : No Jabber condition at Port 3 P/N:PM0342 R/W R R R R R R R R R R R R R REV. 1.4, NOV. 07, 1996 18 INDEX MX98741 Table 5-6 Elastic Buffer Over/Underflow and Jabber Register Bit Definition (Continued) Bit(s) 19.2 19.1 19.0 Name JABP2 JABP1 JABP0 Description 1 : Receive Jabber Active at Port 2 0 : No Jabber condition at Port 2 1 : Receive Jabber Active at Port 1 0 : No Jabber condition at Port 1 1 : Receive Jabber Active at Port 0 0 : No Jabber condition at Port 0 R/W R R R G. Isolation Status Register (register #20) (R) Table 5-7 Isolation Status Register Bit Definition Bit(s) 20.15 Name ISO7 20.14 ISO6 20.13 ISO5 20.12 ISO4 20.11 ISO3 20.10 ISO2 20.9 ISO1 20.8 ISO0 20.7:0 Reserved Description 1 : Port Isolation is occuring at port 7, 0 : Port Isolation is not occuring at port 7. Set to 1 by CIM state machine, cleared to 0 by asserting RESETL pin or writing to Port Reset Register or by CIM state machine. 1 : Port Isolation is occuring at port 6, 0 : Port Isolation is not occuring at port 6. 1 : Port Isolation is occuring at port 5, 0 : Port Isolation is not occuring at port 5. 1 : Port Isolation is occuring at port 4, 0 : Port Isolation is not occuring at port 4. 1 : Port Isolation is occuring at port 3, 0 : Port Isolation is not occuring at port 3. 1 : Port Isolation is occuring at port 2, 0 : Port Isolation is not occuring at port 2. 1 : Port Isolation is occuring at port 1, 0 : Port Isolation is not occuring at port 1. 1 : Port Isolation is occuring at port 0, 0 : Port Isolation is not occuring at port 0. Ignored while read. P/N:PM0342 R/W R R R R R R R R R REV. 1.4, NOV. 07, 1996 19 INDEX MX98741 H. Isolation/Partition Disable Register (register #21) (R/W) Table 5-8 Isolation/Partition Disable Register Bit Definition Bit(s) 21.15 Name ISODIS7 21.14 ISODIS6 21.13 ISODIS5 21.12 21.11 ISODIS4 ISODIS3 21.10 ISODIS2 21.9 ISODIS1 21.8 ISODIS0 21.7 PARDIS7 21.6 PARDIS6 21.5 PARDIS5 21.4 PARDIS4 Description 1 : Port 7 Isolation function is disabled 0 : Port 7 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 6 Isolation function is disabled 0 : Port 6 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 5 Isolation function is disabled 0 : Port 5 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 4 Isolation function is disabled 0 : Port 4 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 3 Isolation function is disabled 0 : Port 3 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 2 Isolation function is disabled 0 : Port 2 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 1 Isolation function is disabled 0 : Port 1 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 0 Isolation function is disabled 0 : Port 0 Isolation function is not disabled. The default value is 0 after reset. 1 : Port 7 Parition function is disbled. 0 : Port 7 Partition function is not disabled. The default value is 0 after reset. 1 : Port 6 Parition function is disbled. 0 : Port 6 Partition function is not disabled. The default value is 0 after reset. 1 : Port 5 Parition function is disbled. 0 : Port 5 Partition function is not disabled. The default value is 0 after reset. 1 : Port 4 Parition function is disbled. 0 : Port 4 Partition function is not disabled. The default value is 0 after reset. P/N:PM0342 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REV. 1.4, NOV. 07, 1996 20 INDEX MX98741 Table 5-8 Isolation/Partition Disable Register Bit Definition (Continued) Bit(s) 21.3 Name PARDIS3 21.2 PARDIS2 21.1 21.0 PARDIS1 PARDIS0 Description 1 : Port 3 Parition function is disbled. 0 : Port 3 Partition function is not disabled. The default value is 0 after reset. 1 : Port 2 Parition function is disbled. 0 : Port 2 Partition function is not disabled. The default value is 0 after reset. 1 : Port 1 Parition function is disbled. 0 : Port 1 Partition function is not disabled. The default value is 0 after reset. 1 : Port 0 Parition function is disbled. 0 : Port 0 Partition function is not disabled. The default value is 0 after reset. R/W R/W R/W R/W R/W Note : Physical address input from ACTP[4:0] during RESETL is asserted will be stored at bit 4:0 of register #31. 6.0 ABSOLUTE MAXIMUM RATINGS Table 6-1 Absolute Maximum Rating for MX98741 RATING Supply Voltage (VCC) DC Input Voltage (Vin) DC Output Voltage (Vout) Storage Temperature Range (TSTG) Power Dissipation (PD) ESD rating (Rzap = 1.5K, Czap = 100pF) VALUE 4.75V to 5.25V -0.5V to VCC+0.5V -0.5V to VCC+0.5V -55 C to 150 C 750 mW 2000V Notice : 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cauase permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Preliminary, Subject to change. P/N:PM0342 REV. 1.4, NOV. 07, 1996 21 INDEX MX98741 7.0 DC CHARACTERISTICS Table 7-1 DC Characteristics for MX98741 SYMBOL PARAMETER ICC Average Active (TXing /RXing) Supply Current Average Idle Supply Current ICCIDLE IDD Static IDD Current CONDITIONS A. Supply Current COCLK = 50MHz VIN = Switching COCLK = 50MHz VIN=VCC/GND COCLK=Undriven MIN. MAX. UNIT - 50 mA - TBD (Note) TBD (Note) mA uA Note : These two parameters will be measured while DC/AC characterization is proceeding. SYMBOL PARAMETER Vil Vih Iin Voh Vol Ioz Maximum Low Level Input Voltage Minimum High Level Input Voltage Input Current Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum TRI-STATE Output Leakage Current Voh Vol Vil Vih Ioz Voh Vol Vil Vih Ioz Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Low Level Input Voltage Minimum High Level Input Voltage Maximum TRI-STATE Output Leakage Current Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Low Level Input Voltage Minimum High Level Input Voltage Maximum TRI-STATE Output Leakage Current CONDITIONS MIN. B. TTL Inputs, Outputs, Tri-States GND = 0V 2.0 VI=VCC/GND -1.0 Ioh = -2mA 2.4 Iol = 2mA VOUT=VCC/GND -10.0 C. EXP Outputs, Tri-States Ioh = -4mA 2.4 Iol = 4mA - 2.0 MAX. UNIT 0.8 VCC+0.5 1.0 0.4 V V uA V V 10.0 uA 0.4 0.8 - V V V V VOUT=VCC/GND -10.0 D. MII Inputs, Outputs, Tri-States Ioh = -8mA 2.4 Iol = 8mA 2.0 10.0 uA 0.4 0.8 - V V V V VOUT=VCC/GND 10.0 uA P/N:PM0342 -10.0 REV. 1.4, NOV. 07, 1996 22 INDEX MX98741 Table 7-1 DC Characteristics for MX98741 (Continued) SYMBOL PARAMETER Vil Vih Maximum Low Level Input Voltage Minimum High Level Input Voltage CONDITIONS MIN. E. TTL Input With Schmitt Trigger 2.7 MAX. UNIT 0.6 - V V MAX. UNIT 200 20 20 3000 20 uA uA uA uA uA - uA uA uA uA uA 1450 - uA uA Note : 1.All parameters listed in category A/B/C/D are preliminary, subject to change. After wafer is out, the value measured on tester will be the finalized Voltage Characteristics. 2.For MII port, see item F in next page for one's reference. SYMBOL Iih Iil Iiq PARAMETER CONDITIONS MIN. F. Input Current Limits for MII Input High Current with Vi = 5.25 Volt All Except COL, MDC, MDIO(Note 1) COL (Note 2) MDC (Note 3) MDIO (Note 4) MDIO (Note 5) Input Low Current with Vi = 0.00 Volt All Except COL, MDC, MDIO(Note 1) -20 COL (Note 2) -200 MDC (Note 3) -20 MDIO (Note 4) -180 MDIO (Note 5) -3800 Input Quiescent Current with Vi = 2.4 Volt MDIO (Note 4) MDIO (Note 5) -1450 Note 5 : Measured at input of XRC which cn be attached via the mechanical interface specified in sec tion 22.6 in [1]. Note1 : Measured at input of Reconcilation sublayer for CRSs, RXD[3:0], RXCLK, RXDVs, RXER, and TXCLK. Measured at inputs of XRC for TXD[3:0], TXEN, and TXER. Note 2 : Measured at input of Reconciliation sublayer. Note 3 : Measured at input of XRC. Note 4 : Measured at input of STA. Caution : Input Current limit is only for board designer’s reference. In MX98741, we will not use this specification to verify the input signals provided by stimulus patterns. P/N:PM0342 REV. 1.4, NOV. 07, 1996 23 INDEX MX98741 8.0 AC CHARACTERISTICS AND WAVEFORMS A. Media Independent Interface T01 T02 T03 MDC T04 T05 MDIO Figure 8-1 MDIO Timing Relationship to MDC Symbol T01 T02 T03 T04 T05a T05b Description Period for MDC High Time for MDC Low Time for MDC MDIO Setup to MDC rising edge (Write Command) MDIO Hold to MDC rising edge (Write Command) MDIO Hold to MDC rising edge (Read Command) P/N:PM0342 MIN. 400 160 160 10 10 5 MAX. 10 UNIT ns ns ns ns ns ns REV. 1.4, NOV. 07, 1996 24 INDEX MX98741 T11 T12 T13 RSCLK T14 T15 RXD[3:0] RXDV RXER Figure 8-2 Receive Signal Timing Relationships at the MII Symbol T11 T12 T13 T14 T15 Description RXCLK Period (Note 1) RXCLK High Time RXCLK Low Time RXD[3:0]/RXDVs/RXER Setup Time to RXCLK rising edge (Note 2) RXD[3:0]/RXDVs/RXER Hold Time to RXCLK rising edge (Note 2) MIN. 40 19 17 MAX. 40 - UNIT ns ns ns 10 - ns 15 - ns Note 1 : The accurate RXCLK frequency shall be 25MHz +/- 100 ppm. Note 2 : The setup time of an MII signal relative to an MII clock edge is defined as the length of time between when the signal exits and remains out of the switching region and when the clock enters the switching region. The hold time of an MII signal relative to an MII clock edge is defined as the length of time between when the clock exits the switching region and when the signal enters the switching region. P/N:PM0342 REV. 1.4, NOV. 07, 1996 25 INDEX MX98741 T21 T22 T23 TXCLK T24 T25 TXD[3:0] TXEN TXER Figure 8-3 Trannsmit Signal Timing Relationships at the MII Symbol T21 T22 T23 T24 T25 Description TXCLK Period (Note 1) TXCLK High Time TXCLK Low Time TXD[3:0]/TXENs/TXERs Setup Time to TXCLK rising edge (Note 2) TXD[3:0]/TXENs/TXERs Hold Time to TXCLK rising edge (Note 2) MIN. 40 0.35*T21 0.35*T21 MAX. 40 0.65*T21 0.65*T21 UNIT ns ns ns 10 - ns 10 - ns Note 1 : The accurate TXCLK frequency shall be 25 MHz +/- 100 ppm. Note 2 : The setup time of an MII signal relative to an MII clock edge is defined as the length of time between when the signal exits and remains out of the switching region and when the clock enters the switching region. The hold time of an MII signal relative to an MII clock edge is defined as the length of time between when the clock exits the switching region and when the signal enters the switching region. P/N:PM0342 REV. 1.4, NOV. 07, 1996 26 INDEX MX98741 B. Data Transceiver Interface TXCLK T31 TDAT[4:0] Figure 8-4 Trannsmit Signal Timing Relationships at the DT Symbol T31 Description TDAT[4:0] to TXCLK Rise Delay Time MIN. 5 MAX. 15 UNIT ns MAX. 40 - UNIT ns ns ns ns ns Note : Tested under 30pF loading. T41 T42 T43 RSCLK T44 T45 RDAT[4:0] Figure 8-5 Receive Signal Timing Relationships at the DT Symbol T41 T42 T43 T44 T45 Description RSCLK Period (Note 1) RSCLK Pulse Width High RSCLK Pulse Width Time RDAT[4:0] Valid to RSCLK Rise RSCLK Rise to RDAT[4:0] Invalid MIN. 40 10 20 2 4 Note 1 : The accurate RXCLK frequency shall be 25 MHz +/- 100 ppm. P/N:PM0342 REV. 1.4, NOV. 07, 1996 27 INDEX MX98741 T51 RESETL T52 T53 T54 COCLK TXCLK Figure 8-6 Timing Relationship for COCLK, TXCLK, and RESETL Symbol T51 T52 T53 T54 Description Pulse Width for RESETL COCLK Period (Note 1) COCLK Pulse Width High COCLK Pulse Width Low MIN. 2400 20 8 8 MAX. 20 - UNIT ns ns ns ns Note 1 : The Maximum Frequency variation for COCLK shold be less than 100ppm. P/N:PM0342 REV. 1.4, NOV. 07, 1996 28 INDEX MX98741 T61 T62 T63 REGCK T66 REGLTCH T64 T65 PARTLNK JBFLO PTSCEN PIDIS ISO Figure 8-7 Timing Relationship for REGCK, REGLTCH and Round-Robin Status pins D. Status Pins Symbol T61 T62 T63 T64 T65 T66 Description REGCK Period REGCK Pulse width High REGCK Pulse Width LOW REGCK falling to Status Valid RegCK Falling to Status Invalid REGCK falls to REGLTCH asserted (Note 1) MIN. 50 12 12 5 MAX. 10 12 10 UNIT ns ns ns ns ns ns Note 1 : One can use REGCK rising edge to latch data in system application. Note 2 : Test under 30pF loading. P/N:PM0342 REV. 1.4, NOV. 07, 1996 29 INDEX MX98741 T71 Receiving Port T72 Listening Port Figure 8-8 Receive Signal Timing Relationships at the DT E. Network Interface Pins Symbol T71 T72 Description Receiving Port goes to IDLE to activate again (Note) Listening Port activate after other port IDLE (Note) MIN. 100 100 MAX. - UNIT ns ns Note : The restriction in IEEE 802.3u specifiction is 96BT. i.e 960 ns. Interframe Gap time less than the value shown above may cause packet loss and internal state machine malfunction. P/N:PM0342 REV. 1.4, NOV. 07, 1996 30 INDEX MX98741 F. Expansion Port Interface TXCLK T81 T81 ANYACT T82 T82 JAMO T83 T83 T87 EDATENL JAMI EXTCRS T84 EDATOE T85 T86 EDAT /I/ /J/ /D1/ /K/ /R/ /T/ Figure 8-9 Expansion Port Timing Relationship Symbol T81 T82 T83 T84 T85a T85b T86 T87 Description TXCLK rising to ANYACT assert/deassert TXCLK rising to JAMO assert /deassert ANYACT assert to EDATENL assert (Note) TXCLK rising to EDATOE assert EDAT to TXCLK delay time (Output by MX98741) EDAT to TXCLK hold time (Input by MX98741) EDAT to TXCLK setup time (Input by MX98741) EDATENL asserted to TXCLK rising setup time MIN. 12 4 2 5 MAX. 18 13 17 25 26 - UNIT ns ns ns ns ns ns ns ns Note : If the external arbitor cannot generate EDATENL signals within 35 ns form TXCLK rising edge (or 17 ns after ANYACT is asserted in figure 9-9) for some reason, EDAT has to be delayed by one TXCLK cycle. Consequently, the longer the delay time changes the repeater from Class II to Class I. A 7ns PAL is suggested to be used for external arbitor to minimize the delay. P/N:PM0342 REV. 1.4, NOV. 07, 1996 31 INDEX MX98741 REVISION HISTORY Revision Description Page 1.4 (1) 5.2 Internal Registers, register 0, 1, and 16 can only be accessed through MDC and MD10. (2) Delete the redundant page. (3) Figure 8-6, delete T55. (4) Figure 9-9, EDAT to TXCLK setup/hold time and EDATENL to TXCLK rising edge setup time are added. P/N:PM0342 Date NOV/07/1998 P.13 P.21 P.35 P.38 REV. 1.4, NOV. 07, 1996 32 INDEX MX98741 10.0 PACKAGE INFORMATION 208-PIN PLASTIC QUAD FLAT PACK A B ITEM MILLIMETERS INCHES A 31.20 ±.30 1.228 ±.12 B 28.00 ±.10 1.102 ± .004 C 28.00 ±.10 1.102 ±.004 D 31.20 ±.30 1.228 ±.012 E 25.35 .999 F 1.33 [REF.] .052 [REF.] G 1.33 [REF.] .052 [REF.] H .30 [Typ.] .012 [Typ.] I .65 [Typ.] .026 [Typ.] J 1.60 [REF.] .063 [REF.] K .80 ±.20 .031 ±.008 L .15 [Typ.] .006 [Typ.] M .10 max. .004 max. N 3.35 max. .132 max. O .10 min. .004 min. 3.68 max. .145 max. P NOTE: 120 121 81 80 E F Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. 160 1 C D 41 40 G H I J N P L M P/N:PM0342 K O REV. 1.4, NOV. 07, 1996 33 INDEX MX98741 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 34