TOSHIBA TC6371AF

TC6371AF Specification
Rev. 1.8
02/01/22
PCI to SD Memory Card / SmartMedia™
Interface Controller
TC6371AF
Outline
Rev. 1.8
2002-01-22
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.1
TC6371AF Specification
Rev. 1.8
02/01/22
Revision history
TITLE: TC6371AF Specification
REV
NO.
1.00
'00-09-08
Issued
1.01
'01-03-26
1.02
'01-04-02
1.03
'01-04-18
Page 34
Page 40
Page 33
Page 35-52
Page 32
1.04
'01-04-25
Mentioned ‘5.2.2PCI Interface DC Characteristics’.
Mentioned ‘5.3.1PCI clock AC characteristics’.
Symbol ‘Topr’ is raised to 70°C from 60°C
Ta is changed to ‘0-70°C’ from ‘0-60°C’
Recommended resistance of SDCD3 line is changed to
100 KΩPull-up from 510 KΩPull-down.
Added 4.11 item
Low active signals are unified as #xxxx.
(ex. SDCD#Æ#SDCD)
Modified recommended resistance of SDCD3-0 and
SDCMD case of MMC not supported.
(100KΩÆ47KΩ)
Modified a comment of [4.7 SUSPEND State ].
Modified recommended resistance of SDCD2-0 and
SDCMD case of MMC not supported.
(47KΩÆ100KΩ)
Added Current Dissipation Characteristics
Added [4.12 Processing Unused
Interface External Pins].
Modified recommended resistance of #SDCD
and SDWP. (100KΩÆ10KΩ)
Added [6 Package outline].
1.1
1.2
DATE
'01-05-17
'01-07-20
CONTENTS
REVISED
APP’D
S.Ueta
T.Takada
T.Murakami
T.Takada
S.Ueta
T.Takada
S.Ueta
T.Takada
S.Ueta
T.Takada
S.Ueta
T.Takada
S.Ueta
T.Takada
Page 56
S.Ueta
T.Takada
Added SmartMedia DC spec. for #SMLOCK, #SMEJCT
and #SMLED.
To be slimed files.
Page 38
S.Ueta
T.Takada
S.Ueta
T.Takada
Page17,19
S.Ueta
T.Takada
Page17,19
(red letters)
Page27
(red letters)
Page5
(red letters)
Page36
Page21
(red letters)
Page36
S.Ueta
T.Takada
S.Ueta
T.Takada
S.Ueta
T.Takada
S.Ueta
T.Takada
1.3
'01-08-17
1.4
'01-08-31
1.5
'01-09-03
1.6
'01-10-02
1.61
'01-11-09
Added the comment regarding Subsystem Vendor ID
and Subsystem Device ID.
Corrected the written.
1.62
'01-11-26
Corrected the written.
1.7
'02-01-09
1.8
'02-01-22
Regarding serial rom I/F, specified that only 4K bits
serial rom be supported.
Added #SMLED signal specification.
Modified the explanation of CLK32 signal.
Added GPIO interface specification.
Parts
Page 33
Page 32
Page 26
Page 32
Page 41
Page 34-35
Page 32
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.2
TC6371AF Specification
Rev. 1.8
02/01/22
Contents
1
Outline ___________________________________________________________________________________ 5
1.1
Chip Specifications ______________________________________________________________________ 5
1.2
Low power dissipation ___________________________________________________________________ 5
1.3
General Specifications ___________________________________________________________________ 5
2
Block diagram______________________________________________________________________________ 6
3
Signals ___________________________________________________________________________________ 7
4
3.1
Pin Assignments ________________________________________________________________________ 7
3.2
Pin Signals ____________________________________________________________________________ 8
3.3
Power Supply, GND, and NC Pins (26) _____________________________________________________ 14
3.4
Interface Pin Summary __________________________________________________________________ 14
Description of Functions_____________________________________________________________________ 15
4.1
PCI Device Interface____________________________________________________________________ 15
4.1.1
Resource Space ____________________________________________________________________ 15
4.2
Register Map__________________________________________________________________________
4.2.1
SD Host Controller Configuration Register ______________________________________________
4.2.2
SD Control Register ________________________________________________________________
4.2.3
SmartMedia™ Host Controller Configuration Register _____________________________________
4.2.4
SmartMedia™ Control Register _______________________________________________________
17
17
18
19
20
4.3
Clock / Reset__________________________________________________________________________ 21
4.3.1
Clocks ___________________________________________________________________________ 21
4.3.2
Reset ____________________________________________________________________________ 21
4.4
Detection of Insertion/Removal of SD Card/ SmartMediaTM _____________________________________ 22
4.4.1
Detection of Insertion/Removal of SD Card ______________________________________________ 22
4.4.2
Detection of Insertion/Removal of SmartMediaTM _________________________________________ 22
4.5
Interrupts_____________________________________________________________________________ 23
4.5.1
Interrupt Sources by SD Card _________________________________________________________ 23
4.5.2
Interrupt Sources by SmartMediaTM ____________________________________________________ 23
4.6
Card Slot Power Supply Control___________________________________________________________ 24
4.6.1
SD Card Slot Power Supply Control____________________________________________________ 24
4.6.2
SmartMedia™ Slot Power Supply Control_______________________________________________ 24
4.7
Suspend State _________________________________________________________________________ 25
4.8
Power Management ____________________________________________________________________
4.8.1
PME Register Structure _____________________________________________________________
4.8.2
PME State ________________________________________________________________________
4.8.3
PME Context Register ______________________________________________________________
4.8.4
#PME Generation __________________________________________________________________
4.8.5
#PME Pin ________________________________________________________________________
4.8.6
#PWRST _________________________________________________________________________
4.8.7
Vaux in D3cold State _______________________________________________________________
4.9
26
26
26
27
28
28
29
30
Serial ROM Interface ___________________________________________________________________ 31
4.10
Pulled-Up/Pulled-Down Resistors _______________________________________________________ 32
4.10.1 SD Card Interface __________________________________________________________________ 32
4.10.2 SmartMedia™ Interface _____________________________________________________________ 32
4.11
Connection example of SD Card/SmartMedia™ socket _________________________________________ 33
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.3
TC6371AF Specification
Rev. 1.8
02/01/22
4.12 Processing Unused InterfaceExternal Pins___________________________________________________ 34
4.12.1 Processing Pins (SmartMedia™ Interface unsupported) _____________________________________ 34
4.12.2 Processing Pins (SD Interface unsupported)_______________________________________________ 35
5
4.13
#SMLED signal _______________________________________________________________________ 36
4.14
GPIO interface specification _____________________________________________________________ 36
Electrical Characteristics ____________________________________________________________________ 37
5.1
6
Absolute Maximum Ratings ______________________________________________________________ 37
5.2
DC Characteristics _____________________________________________________________________
5.2.1
Power Supply Voltage: Recommended Conditions_________________________________________
5.2.2
PCI Interface DC Characteristics ______________________________________________________
5.2.3
SmartMedia™ Interface DC Characteristics______________________________________________
5.2.4
SmartMedia™ Power Supply Control DC Characteristics ___________________________________
5.2.5
SD Card Interface Pin DC Characteristics _______________________________________________
5.2.6
SD Card Power Supply Control DC Characteristics________________________________________
5.2.7
System Interface Pin (5 V-Tolerant) DC Characteristics ____________________________________
5.2.8
GPIO Interface Pin DC Characteristics__________________________________________________
5.2.9
TEST Pin DC Characteristics _________________________________________________________
5.2.10 Current Dissipation Characteristics ____________________________________________________
37
37
38
39
39
40
40
41
42
42
43
5.3
AC Characteristics _____________________________________________________________________
5.3.1
PCI Interface Signal AC Characteristics_________________________________________________
5.3.2
SmartMedia™ Interface Signal AC Characteristics ________________________________________
5.3.3
SD Card Interface Signal AC Characteristics _____________________________________________
5.3.4
System Interface Signal AC Characteristics ______________________________________________
44
44
48
55
56
Package outline____________________________________________________________________________ 57
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.4
TC6371AF Specification
Rev. 1.8
02/01/22
1 Outline
The TC6371AF is an SD memory card/SmartMediaTM controller LSI with a 32-bit PCI bus interface. This product
conforms to SD memory card physical layer specifications as well as to SmartMediaTM electrical and physical
format specifications.
The TC6371AF can also be used with all power supplies for memory card interfaces. When the memory card is
inserted, TC6371AF automatically detects the card type and the power supply in use. In addition to supporting a
CLKRUN function and advanced configuration power interface (ACPI), the TC6371AF supports a PCI power
management-compliant PME, giving the product fully developed power management functions that allow it to
minimize the system’s power dissipation.
With such features as subsystem ID and subsystem vendor ID supplied from external serial ROM, the TC6371AF
can be used as a PCI card or CardBus card LSI.
1.1 Chip Specifications
• 0.35-µm CMOS process
• Number of gates: 80,000 approx.
• 0.4-mm pitch, 128-pin QFP package
(LQFP128-P-1414B)
1.2 Low power dissipation
• Conforms to PCI power management
specifications (Supports #PME *)
• Supports CLOCKRUN (mobile PC/PCI)
• Internal gate clock design
1.3 General Specifications
View of TC6371AF
• Conforms to PCI power management
specification revision 1.1
• Conforms to PCI local bus specification revision 2.2 *
• Supports remote wakeup feature (#PME-compliant) **
• Supports PCI interrupts (INT)
• Supports PCI CLKRUN
• Supports suspend state
• Supports Plug & Play
• Operating frequency: PCI (33 MHz max)
• Supports LSI MIC2563 which controls power supply
• Supports subsystem ID and subsystem vendor ID from 4k bits EEPROM (3-line serial ROM interface)
(Only 4K bits EEPROM supports)
• Supports 3.3-V PCI interface
• Conforms to SD memory card physical layer specifications (ver. 1.0)
Operating frequency 16 MHz max
Offers Multimedia card read/write
Supports 3.3 V
Offers multi-block write/read
• Conforms to SmartMediaTM electrical specifications (ver. 1.20) and physical format specifications (ver. 1.20),
supporting:
Supports 3.3-V SmartMediaTM (5.0 V not supported)
Supports hardware ECC
* The minimum input voltage level of "PCICLK" “#PCIRST”shall not exceed 0.7 times ofVcc.Vih(min)= 0,7*Vcc
**As of January. 2002, the SD/MMC/SmartMediaTM driver does not perform any functions by enabling #PME.
SmartMediaTM is a registered trademark of Toshiba Corporation.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.5
TC6371AF Specification
Rev. 1.8
02/01/22
2 Block diagram
CPU
North Bridge
SYSTEM
MEMORY
PCI Bus
#PME
INTX
INTX
TC6371AF
South Bridge
VGA
Interrupt
Control
Power Management
Power Control
Power
Control
SD Control
Register
SD Memory Card
Control
PCI
TARGET Control
Serial ROM
ROM Interface
SmartMedia™
Control Register
SmartMedia™
Control
Power
Switch
SD Memory Card
MultiMedia Card
SmartMedia™
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.6
TC6371AF Specification
Rev. 1.8
02/01/22
3 Signals
3.1
Pin Assignments
SMD5
SMD3
SMD6
SMD2
VDD
SMD7
SMD1
SDCMD
SMLVD
VSS
SMD0
SDCD3
#SMWP
SDCD2
#SMRB
VDD
#SMWE
#SMRE
SMALE
#SMCE
VSS
SMCLE
#SMEJSW
#SMWPD
SMVC3EN
RSVO0
VDD
SDPWR
ROM_CS
ROM_SK
ROM_D
VSS
QFP128 Matrix Diagram
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
□□□□■□□□□□□□□□□■□□□□□□□□□□■□□□□□
VSS
SDCLK
SMD4
#SMCD
SDCD0
SDCD1
VDD
#SDCD
SDWP
#SMEJCT
#SMLED
VSS
#SMLOCK
GPIO0
GPIO1
GPIO2
VDD
GPIO3
GPIO4
GPIO5
GPIO6
VSS
GPIO7
IDSEL1
#INTA
#INTB
#PCIRST
VDD
PCICLK
NC
NC
#PME
□
□
□
□
□
□
■
□
□
□
□
□
□
□
□
□
■
□
□
□
□
□
□
□
□
□
□
■
□
□
□
□
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TC6371AF
LQFP128-PKG
(TOP VIEW)
□
□
□
□
■
□
□
□
□
□
□
□
□
□
□
■
□
□
□
□
□
□
□
□
□
■
□
□
□
□
□
□
TSTI3
TSTI2
TSTI1
TSTI0
VDD
CLK32
FCMODE
#SUSPEND
#PWRST
#CLKRUN
VSS
AD0
AD1
AD2
AD3
VDD
AD4
AD5
AD6
AD7
VSS
CBE0
AD8
AD9
AD10
VDD
AD11
AD12
AD13
AD14
AD15
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
●
VSS
AD31
AD30
AD29
AD28
VDD
AD27
AD26
AD25
AD24
CBE3
VSS
IDSEL0
AD23
AD22
AD21
VDD
AD20
AD19
AD18
AD17
AD16
VSS
#FRAME
#IRDY
#TRDY
#DEVSEL
VDD
#STOP
PAR
CBE2
CBE1
□□□□□■□□□□□□□□□□■□□□□□□□□□□■□□□□
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.7
TC6371AF Specification
3.2
Rev. 1.8
02/01/22
Pin Signals
PCI Interface (50-Pin)
NAME
Pin
AD31
2
AD30
3
AD29
4
AD28
5
AD27
7
AD26
8
AD25
9
AD24
10
AD23
14
AD22
15
AD21
16
AD20
18
AD19
19
AD18
20
AD17
21
AD16
22
AD15
34
AD14
35
AD13
36
AD12
37
AD11
38
AD10
40
AD9
41
AD8
42
AD7
45
AD6
46
AD5
47
AD4
48
AD3
50
AD2
51
AD1
52
AD0
53
#CBE3
11
#CBE2
31
#CBE1
32
#CBE0
43
PAR
30
IO
VCC (V)
FUNCTION
IO
3.3
PCI address/data bus
IO
3.3
PCI bus command/byte enable. Specifies bus commands at the PCI cycle
address phase. Specifies the byte enable that indicates which byte lane of
the 32 bits to use for sending data at the data phase.
O
3.3
PCI bus parity. Parity bit for even-number parity checks on the PCI
address/data bus and bus command line.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.8
TC6371AF Specification
Rev. 1.8
02/01/22
Pin Signals (Continued)
PCI Interface (Continued)
NAME
Pin
IO
VCC
(V)
FUNCTION
#FRAME
24
I
3.3
PCI cycle frame. Driven by the initiator, this signal indicates that the bus
cycle is in progress. When the signal is asserted, address and bus command
output starts. When de-asserted, the signal indicates that the next data
transfer phase is the final data transfer.
#IRDY
25
I
3.3
Enables PCI initiator. Indicates that the initiator is ready for data transfer. The
R/W data are transferred when signal asserted.
#TRDY
26
O
3.3
Enables PCI target. Indicates that the target is ready for data transfer. The
R/W data are transferred when signal asserted.
#STOP
29
O
3.3
Terminates the PCI cycle. The target uses this signal to ask the initiator to
terminate processing that is currently in progress. Supports three types of
termination: retry/disconnect/target abort.
3.3
Selects the PCI bus initialization device (ID). Asserted to specify the
TC6371AF as the target device during a configuration access. This signal is
used for SD card controller functions. When the FCMODE pin is set to H, this
signal is used for the SD card/SmartMedia™ controller multifunction device
feature.
IDSEL0
13
I
IDSEL1
120
I
3.3
Selects the PCI bus initialization device (ID). Asserted when the TC6371AF
is specified as the target device during configuration access. This signal is
used for SmartMedia™ controller functions. When the FCMODE pin is set to
H, the TC6371AF operates as a multifunction device using IDSEL0 and
therefore this signal does not function. (In Multifunction mode, pull up this
pin.)
#CLKRUN
55
IO
3.3
Runs the PCI clock. Can request a stop or slowdown of the PCI clock.
#DEVSEL
27
O
3.3
Selects the PCI device. Asserted by the TC6371AF in response to bus
access.
PCICLK
125
I
3.3
PCI bus clock. Inputs a 33-MHz clock. All processing on the PCI bus is on
the PCICLK rising edge.
#PCIRST
123
I
3.3
Resets PCI bus. Asserted when power is turned on and or when system has
been reset.
#INTA
121
3.3
PCI interrupt INTA.
3.3
PCI interrupt INTB.
3.3
#PME interrupt signal
O
(OD) *1
O
#INTB
122
(OD) *1
O
#PME
128
(OD) *1
*1:
Level cannot be converted.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.9
TC6371AF Specification
Rev. 1.8
02/01/22
Pin Signals (Continued)
SD Card Interface (8 pins)
NAME
Pin
IO
VCC (V)
SDCD3
85
SDCD2
83
SDCD1
102
SDCD0
101
SDCMD
FUNCTION
IO
3.3
SD card data bus
89
IO
3.3
SD command
SDCLK
98
O
3.3
SD card clock
#SDCD
104
I
3.3
SD card detection
SD card write-protect.
SDWP
105
I
3.3
When H, SD card write-protected.
SD Card Power Supply Controller (One pin)
NAME
Pin
IO
VCC (V)
SDPWR
69
O
3.3
FUNCTION
Controls SD card power supply.
3.3-V enable signal.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.10
TC6371AF Specification
Rev. 1.8
02/01/22
Pin Signals (Continued)
SmartMedia™ Interface (22 pins)
NAME
Pin
SMD7
91
SMD6
94
SMD5
96
SMD4
99
SMD3
95
SMD2
93
SMD1
90
SMD0
86
SMCLE
75
IO
VCC (V)
IO
3.3
O (3state)
FUNCTION
Data
Enables the command latch.
SMALE
78
O (3state)
Enables the address latch.
#SMCE
77
O (3state)
Enables the chip.
#SMWE
80
O (3state)
Enables a write.
#SMRE
79
O (3state)
Enables a read.
#SMWP
84
O (3state)
Protects against write.
#SMRB
82
I
Busy
#SMCD
100
I
Detects card.
SMLVD
88
I
Detects low voltage.
#SMWPD
73
I
Write-protection seal
When L, a write-protected media is inserted.
Ejects request.
When H, a media is inserted. When L, no media is inserted.
*1:
#SMEJSW
74
I
#SMLED
107
O (OD) *1
Turns on the LED.
#SMLOCK
109
O (OD) *1
Lock mode
#SMEJCT
106
O (OD) *1
Eject response
Changes detection control to one where L indicates a media is inserted
by setting bit 7 of the SmartMedia™ host controller’s configuration
register 63h.
Level cannot be converted.
SmartMedia™ Power Supply Control (2 pins)
NAME
Pin
IO
VCC (V)
FUNCTION
SMVC3EN
72
O
3.3
Parallel power supply control. VCC 3.3 V enable signal.
RSVO0
71
O
3.3
Leave pin open.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.11
TC6371AF Specification
Rev. 1.8
02/01/22
Pin Signals (Continued)
System Interface (4 pins)
NAME
Pin
IO
VCC (V)
FUNCTION
CLK32
59
I
3.3
Detects card or allow interruptions when PCICLK stops.
#PWRST
56
I
3.3
Power-on reset signal input.
#SUSPEND
57
I
3.3
When #SUSPEND is Low, prevents throughput of data input from the SD card
and SmartMediaTM. Control signals output from TC6371AF are controlled at
non-active level.
Function mode signal.
FCMODE
58
I
3.3
When the FCMODE pin is set to L, the TC6371AF operates as a
single-function PCI device. (IDSEL0 is used for the SD card controller
functions, IDSEL1 for the SmartMedia™ functions.)
When the FCMODE pin is set to H, TC6371AF operates as a multifunction
device. (Only IDSEL0 is valid. FUNCTION0 controls the SD card controller
functions; FUNCTION1 controls the SmartMedia™ controller functions.)
Serial ROM Interface (3 pins)
NAME
Pin
IO
VCC (V)
FUNCTION
Serial ROM interface: Chip selection
Connect to serial ROM chip select (CS) pin.
ROM_CS
68
O
3.3
Set TSTI[3-0] to be “0010” when the serial ROM interface applied.
Leave the pin open when the serial ROM interface not applied,.
Serial ROM interface: Clock
ROM_SK
67
O
3.3
Connect to serial ROM clock pin (SK).
Leave the pin open when the serial ROM interface not applied.
Serial ROM interface: Data
ROM_D
66
IO
3.3
Connect to the serial ROM data input/output pin.
Pull up the pin with a 100-kΩ resistor when the serial ROM interface not
applied.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.12
TC6371AF Specification
Rev. 1.8
02/01/22
GPIO Interface (8 pins)
NAME
Pin
IO
VCC (V)
GPIO0
110
IO
3.3
FUNCTION
General-purpose port 0.
Pull up this pin.
General-purpose port 1.
GPIO1
111
IO
3.3
Pull up this pin.
General-purpose port 2.
GPIO2
112
IO
3.3
Set to Low when 8-bit ROM selected or set to High when 16-bit ROM
selected in ROM interface mode.
Pull up this pin .when the serial ROM interface is not applied,
General-purpose port 3.
GPIO3
114
IO
3.3
Pull up this pin.
General-purpose port 4.
GPIO4
115
I
3.3
Set to Low.
General-purpose port 5.
GPIO5
116
I
3.3
Set to High.
General-purpose port 6.
GPIO6
117
I
3.3
Set to Low.
General-purpose port 7.
GPIO7
119
I
3.3
Set to Low.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.13
TC6371AF Specification
Rev. 1.8
02/01/22
Pin Signals (Continued)
Test Pins (4 pins)
3.3
NAME
Pin
TSTI0
61
TSTI1
62
TSTI2
63
TSTI3
64
IO
FUNCTION
Test mode signals 3, 2, 1, 0
I
3.3
Used in Test mode.
Set TSTI[3-0] to “0000” in normal operating mode. Set TSTI[3-0] to “0010”
when using the serial ROM interface.
Power Supply, GND, and NC Pins (26)
NAME
Pin
FUNCTION
VSS
1, 12, 23, 33, 44, 54, 65, 76, 87, 97, 108, 118
GND
VDD
6, 17, 28, 39, 49, 60, 70, 81, 92, 103, 113, 124
3.3V
126, 127
Not connected.
NC
3.4
VCC (V)
Interface Pin Summary
Interface
Number of pins
PCI
50
SD card
8
SD card power supply control
1
SmartMedia™
22
SmartMedia™ power supply control
2
System
19
Sub total
System interface, Serial ROM interface, GPIO interface,
TEST pins
103
Power supply
12
GND
12
Not connected (NC)
2
Total
Remarks
Leave open.
128
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.14
TC6371AF Specification
Rev. 1.8
02/01/22
4 Description of Functions
4.1
PCI Device Interface
•
•
•
•
•
Address decode timing
Delayed transaction
LOCK#
PERR#, SERR#
Resource space
4.1.1
Medium
Supported
Not supported
Not supported
Resource Space
The TC6371AF has the following resource space:
• SD host controller configuration register space
• SD control register space
• SmartMedia™ host controller configuration register space
• SmartMedia™ control register space
SD host controller /SmartMedia™ host controller configuration register space
The configuration space of the host controllers is set by external pins IDSEL0, IDSEL1, and FCMODE.
SD host controller
configuration register space
FCMODE pin
SmartMedia™ host controller
configuration register space
0
Determined by IDSEL0
Determined by IDSEL1
Single-function mode
Header-type 00h
Header-type 00h
Determined by IDSEL0
Determined by IDSEL0
1
FUNCTION No. 0
FUNCTION No. 1
Multifunction mode
Header-type 80h
Header-type 80h
IDSEL1 pulled up
IDSEL1 pulled up
Note:
When using only either the SD host controller function or the SmartMedia™ host controller function in
systems using the TC6371AF, set Single-Function mode and mask the configuration space of the host
controller you don’t need.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.15
TC6371AF Specification
Rev. 1.8
02/01/22
• SD Control Register Space
Use the base address register (config offset: 10h) of the SD host controller’s configuration register for accessing
the resources in the SD control register space. This allows you to set the SD control register space to any
memory space. However, the SD control register space cannot be set to I/O resource space.
SD host controller
Configuration Registers
Host Memory
Space
Offset
Base Address + 00 h
Offset
10 h
Base Address
SD Control
Register
:
:
Base Address + FF h
:
FFh
• SmartMedia™ Control Register Space
Use the base address register (config offset: 10h) of the SmartMedia™ host controller’s configuration register
for accessing the resources in the SmartMedia™ control register space. This allows you to set SmartMedia™
control register space to any memory or I/O space.
SmartMedia host controller
Configuration Registers
Host Memory
Space
Offset
Base Address + 00 h
Offset
10 h
Base Address
:
SmartMedia
Control
Register
:
:
Base Address + 07 h
FFh
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.16
TC6371AF Specification
4.2
Rev. 1.8
02/01/22
Register Map
The TC6371AF incorporates an SD host controller registers and a SmartMedia™ host controller registers.
• SD host controller configuration register
• SD control register
• SmartMedia™ host controller configuration register
• SmartMedia™ control register
4.2.1
SD Host Controller Configuration Register
31
23
15
07
00
Port
Device ID (0803h)
Vendor ID (1179h)
00h
Status (0210h)
Command (0000h)
04h
Class Code (088000h)
Revision ID (02h)
08h
Cache Line Size
0Ch
Header Type
SD Card Register Base Address
10h
14h-27h
Subsystem Device ID (0001h) *1
CISPT
28h
Subsystem Vendor ID (1179h) *1
2Ch
30h
Capability Pointer
34h
38h
SD Clock Mode
Interrupt Pin
Interrupt Line
3Ch
PCI Clock Control
Gated Clock Control
40h
Pin Status
Card Detect Reset
44h
*2 Power Control
48h
*2 Card Detect Mode
4Ch
50h-7Fh
Power Management Capabilities (PMC)
Data
Next Item Ptr
PMCSR PCI to PCI Bridge
Support (PMCSR_BSE)
Capability ID
Power Management Control/Status (PMCSR)
*2 PME Trigger Enable
80h
84h
88h
8Ch-9Fh
*2 CIS
A0h-EFh
F0h-F7h
Single Function
*2 PM Write Protect
TEST
F8h
Write Protect
FCh
*1:Regarding Subsystem Vendor ID and Subsystem Device ID, the default values of these register are The
TOSHIBA’s ID. In the case of using TC6371AF, please set these register to your ID. Please set your ID by BIOS as
followings.
(1) Set 01h to Write Protect Register(Config.FCh).
(2) Set your ID to Subsystem Vendor ID and Subsystem Device ID Register.
(3) Set 00h to Write Protect Register(Config.FCh).
*2: PME context register
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.17
TC6371AF Specification
4.2.2
Offset
Rev. 1.8
02/01/22
SD Control Register
15-08 bit
07-00 bit
Offset
15-08 bit
07-00 bit
02h
06h
0Ah
0Eh
12h
16h
1Ah
1Eh
22h
26h
2Ah
2Eh
32h
36h
3Ah
3Eh
SD_PORT
SD_ARG1
SD_LENGTH
SD_RSP1
SD_RSP3
SD_RSP5
SD_RSP7
SD_INFO2
SD_INFO2_MASK
SD_WIDTH
----SD_BUF1
-------
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
SD_CMD
SD_ARG0
SD_STOP
SD_RSP0
SD_RSP2
SD_RSP4
SD_RSP6
SD_INFO
SD_INFO_MASK
SD_CLK
SD_OPTION
--SD_BUF0
-------
42h
46h
4Ah
4Eh
52h
56h
5Ah
5Eh
62h
|
7Eh
-----------------
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
|
7Ch
-----------------
82h
86h
8Ah
8Eh
92h
96h
9Ah
9Eh
A2h
A6h
AAh
AEh
B2h
B6h
BAh
BEh
C2h
|
DEh
---------------------------------
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
|
DCh
---------------------------------
E2h
E6h
EAh
EEh
F2h
F6h
FAh
FEh
CORE_REV
BUF_ADR
----------Revision
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
SOFT_RST
--Resp_Header
-----------
---
---
---
---
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.18
TC6371AF Specification
4.2.3
Rev. 1.8
02/01/22
SmartMedia™ Host Controller Configuration Register
31
23
15
07
00
Port
Device ID (0804h)
Vendor ID (1179h)
00h
Status (0490h)
Command (0000h)
04h
Class Code (088000h)
Revision ID (02h)
Header Type
08h
0Ch
SmartMedia™ Controller Register Base Address
10h
14h-27h
CIS Pointer
Subsystem Device ID(0001h)
28h
Subsystem Vendor ID(1179h)
2Ch
30h
Capability Pointer
34h
38h
Interrupt Pin
Interrupt Line
3Ch
40h-47h
*2 Event Control
*2 PME Enable
*2 INT Enable
*2 CLKRUN Control
48h
4Ch
50h-57h
*2 Debug
58h
5Ch-5Fh
*2 SmartMedia™ Detect
Control
*2 SmartMedia™
Transaction Control
*2 SmartMedia™ Power
Supply Control
60h
64h-7Fh
*2 Power Management Capabilities (PMC)
*2 Data
*2 Next Item Ptr
*2 PMCSR PCI to PCI
Bridge Support
(PMCSR_BSE)
*2 Capability ID
*2 Power Management Control/Status (PMCSR)
80h
84h
88h-9Fh
*2 CIS
*2 ROM Control
*2 ROM Index Port
A0h-EFh
*2 ROM Data Port
F0h
F4h-FBh
*2 Monitor Select
*2 Configuration Control
FCh
*1:Regarding Subsystem Vendor ID and Subsystem Device ID, the default values of these register are The
TOSHIBA’s ID. In the case of using TC6371AF, please set these register to your ID. Please set your ID by BIOS as
followings.
(1) Set 01h to Configuration Control Register(Config.FCh).
(2) Set your ID to Subsystem Vendor ID and Subsystem Device ID Register.
(3) Set 00h to Configuration Control Register(Config.FCh).
*2: PME context register
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.19
TC6371AF Specification
4.2.4
Rev. 1.8
02/01/22
SmartMedia™ Control Register
Config-60h
bit4=1
Config-60h
bit4=0
Offset1
Offset2
Register name
R/W
00h
03h-00h
Data Register
RW
01h
-
Reserved
02h(Write)
04h(Read/Write)
*Mode Register
W(R/W)
02h(Read)
05h
*Status Register
R
04h
06h
*Interrupt Status Register
R
06h
07h
*Interrupt Mask Register
RW
03h, 05h, 07h
-
Reserved
-
-
* PME context register
The offset of this register set varies according to the status of the bit that controls the SmartMedia™ control
register’s High-Speed mode (config 60h bit 4). (Setting bit 4 = 0 enables 32/16-bit access to the data register.)
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.20
TC6371AF Specification
4.3
4.3.1
Rev. 1.8
02/01/22
Clock / Reset
Clocks
The TC6371AF has two pins for input clocks: PCICLK and CLK32.
(1)
(2)
4.3.2
PCICLK: PCI clock input (33 MHz max)
PCI interface and internal operation reference clock.
CLK32: 32-kHz clock input
Used as detecting insertion and removal of SD card and SmartMedia and an interrupt detection clock
and for event detection in D3 state. The interrupt signal, implied insertion or detachment, shall be
generated synchronous to this clock signal. Note that if CLK32 is stopped, the interrupt detector does
not operate while TC6371AF is suspended or in D1-3 state set according to the PCI bus power
management interface specifications.
Reset
The TC6371AF uses the following two reset signals.
(1)
(2)
#PCIRST: PCI reset signal. Asserted at power on and at a transition to D3cold. When the input
destination of this signal is set to D3 state, the contents of the context register are saved and not
cleared even when #PCIRST is asserted.
#PWRST: Power-on reset signal. Asserted at power on. Asserting #PWRST clears all the TC6371AF’s
internal registers.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.21
TC6371AF Specification
4.4
4.4.1
Rev. 1.8
02/01/22
Detection of Insertion/Removal of SD Card/ SmartMediaTM
Detection of Insertion/Removal of SD Card
The TC6371AF detects insertion and removal of the SD card using #SDCD and SDCD3. When #SDCD is Low or
SDCD3 is High, the SD card is inserted. When #SDCD is High or SDCD3 is Low, the SD card is withdrawn.
The following is an example of how to detect insertion of the SD card.
1. The TC6371AF detects that #SDCD is Low, then turns power on to the SD card socket.
2. The TC6371AF detects that the SDCD3 pin is High.
The following is an example of how to detect removal of the SD card.
1. The TC6371AF detects that #SDCD is High, or SDCD3 is Low.
2. The TC6371AF turns power off.
* Removing the SD card while the card is being accessed may damage the card.
The SD card insertion/removal status can be checked by bit 9, 8, 4, and 3 of 1Ch SD port register.
4.4.2
TM
Detection of Insertion/Removal of SmartMedia
The TC6371AF can detect insertion and removal of the SmartMediaTM using #SMCD and #SMEJSW. When
#SMCD or #SMEJSW is Low, the SmartMediaTM is inserted. When #SMCD or #SMEJSW is High, the
SmartMediaTM is withdrawn. When the bit 7 of the SmartMediaTM host controller configuration register 63h set
to “1” and when #SMEJSW is High, this indicates that the SmartMediaTM is inserted. When the bit 6 of
SmartMediaTM host controller configuration register 63h set to “1”, detection of SmartMediaTM has been masked
using #SMEJSW.
The following is an example of how to detect insertion of the SmartMediaTM.
1. The TC6371AF detects that #SMCD is Low, then #SMEJSW is Low.
2. The TC6371AF then turns power on to the SmartMediaTM socket.
The following is an example of how to detect removal of the SmartMediaTM.
1. The TC6371AF detects that #SMEJSW is High, then #SMCD is High.
2. The TC6371AF then turns power off.
* Removing the SmartMedia
TM
card when the SmartMedia
TM
TM
is being accessed may damage the SmartMedia .
The SmartMediaTM insertion status can be checked using status bits 3 and 2 and interrupt status bit 3 of the
SmartMediaTM control register.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.22
TC6371AF Specification
4.5
Rev. 1.8
02/01/22
Interrupts
When the TC6371AF detects the following interrupt sources, the TC6371AF asserts interrupt signals (#INTA,
#INTB, #PME). The power management register has to be set in order to get #PME output.
4.5.1
Interrupt Sources by SD Card
Interrupt sources by the SD card are as listed below:
Normal interrupts
• SD card insertion interrupt by #SDCD *
• SD card removal interrupt by #SDCD *
• SD card insertion interrupt by SDCD3 *
• SD card removal interrupt by SDCD3 *
• Interrupt by write enable buffer signal
• Interrupt by read enable buffer signal
• Interrupt by R/W end signal
• Interrupt by response end signal
Error interrupts
• Timeout error (command) interrupt
• Buffer underflow interrupt
• Buffer overflow interrupt
• Timeout error (data) interrupt
• End bit error interrupt
• CRC error interrupt
• CMD index error interrupt
TM
4.5.2
Interrupt Sources by SmartMedia
Interrupt sources by the SmartMediaTM are as listed below:
•
•
•
•
SmartMediaTM insertion interrupt
SmartMediaTM removal interrupt
Interrupt by #SMEJSW signal
Interrupt when #SMRB signal changes from Low to High
* Interrupt sources which can be output to #PME. Other interrupt sources can only be output to #INTA or #INTB.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.23
TC6371AF Specification
4.6
Rev. 1.8
02/01/22
Card Slot Power Supply Control
The TC6371AF is designed so that it can be connected to MIC2563 (power supply control LSI). An example of
application circuit is shown below.
System Power
Supply
3.3V
Vcc
SMVC3EN
VCC3EN
VCC5EN
EN0
EN1
VC3EN
VC5EN
EN0
EN1
MIC2563
TC6371AF
SDPWR
VCC
(3.3v)
SmartMedia
Slot
VCC
(3.3v)
SD Card/MMC
Slot
GND
4.6.1
SD Card Slot Power Supply Control
Setting the power control register (config offset: 48h) enables to control the power supply of SD card.
Parallel power supply control signal
4.6.2
Signal name
Function
Pin
SDPWR
Controls 3.3-V VCC for SD card
69
SmartMedia™ Slot Power Supply Control
There are two modes for controlling power supply to the SmartMediaTM slot: Manual Power Supply Control mode
and Automatic Power Supply Control mode. Those modes are switched using the bit 7 of the SmartMediaTM host
controller configuration register at 62h. In Manual Power Supply Control mode, bits 3 and 2 of the
SmartMediaTM control register (offset: 02h) are used. In Automatic Power Supply Control mode, when the
SmartMediaTM is inserted, power is automatically turned on. When the SmartMediaTM is removed, power is
turned off.
As of January. 2002, the SmartMediaTM driver uses a manual power supply control.
Parallel power supply control signal
Signal name
Function
Pin
SMVC3EN
Controls 3.3-V VCC for SmartMedia™
72
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.24
TC6371AF Specification
4.7
Rev. 1.8
02/01/22
Suspend State
When #SUSPEND is Low, TC6371AF prevents throughput of data input from the SD card and SmartMediaTM.
Control signals, output from TC6371AF, are set at non-active level. Among PC system is Suspend state, it is
recommended that VDD of TC6371AF is power off.
Phase I
VCC
X
PWRST#
X
PCIRST#
X
SUSPEND#
X
PCICLK
X
Phase II
Phase III
Phase IV
Suspended
• Phase I: Immediately after power on, #PCIRST and #PWRST are L and #SUSPEND is H. This state clears
all circuits.
• Phase II: Normal state with #PCIRST de-asserted (H).
• Phase III: Asserting #SUSPEND sets suspend state. In this state, TC6371AF prevents throughput of
signals input from the SD card and SmartMediaTM.(*) In this state, TC6371AF cannot accept PCI
transactions. Stopping the PCICLK in suspend state reduces power consumption.
• Phase IV: De-asserting #SUSPEND restores TC6371AF to its normal operating state.
*
When #SUSPEND is Low, TC6371AF prevents current flow from VCC to GND even if an intermediate
potential is applied and TC6371AF masks out the input buffer signals as well.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.25
TC6371AF Specification
4.8
Rev. 1.8
02/01/22
Power Management
The TC6371AF supports a power management function conforming to PCI bus power management interface
specification revision 1.1 (PCI-PM) for both the SD host controller and the SmartMedia™ host controller. As of
January. 2002, the SD/MMC/ SmartMediaTM driver does not support a function which enables #PME and then
performs output.
4.8.1
PME Register Structure
To support the #PME, the TC6371AF registers conform to PCI-PM specifications.
Config.
PME Registers
Offset
Power Management Capabilities
Next Item Ptr
Capability ID
80h
(PMC)
Data
PMCSR PCI to PCI
Bridge Support
(PMCSR_BSE)
4.8.2
Power Management Control/Status
84h
(PMCSR)
PME State
The PCI power management specifications are defined by five states (D0uninitialized D0active, D1, D2, D3hot,
and D3cold) according to the power dissipation level.
The TC6371AF can support all five states.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.26
TC6371AF Specification
4.8.3
Rev. 1.8
02/01/22
PME Context Register
In D3hot and D3cold states, TC6371AF supports PME. This allows the TC6371AF to detect wakeup events and
assert #PME even when #PCIRST is asserted and auxiliary power only (D3cold) is supplied. The required
registers must therefore be saved. The following are the registers to be saved.
1) SD Host Controller
Configuration register
• Offset 80-87h
• Offset 48h
• Offset 4Ch
• Offset 88h
• Offset A0-Efh
• Offset FDh
SD IO register
• Offset 20h
bit 9, 8, 4, 3
Power management-related register
Power Control
CardDetect Mode
PME Trigger Enable
CIS
PM Write Protect
SD INFO MASK register
2) Smart Media™ Host Controller
Configuration register
• Offset 80-87h
• Offset 48h
• Offset 49h
• Offset 4Ah
• Offset 4Ch
• Offset 5Bh
• Offset 60h
• Offset 62h
• Offset 63h
• Offset A0-EFh
• Offset F0-F1h
• Offset F2h
• Offset F3h
• Offset FCh
• Offset FFh
Power management-related register
Interrupt Enable
PME Enable
Event Control
CLKRUN Control
Debug
SmartMedia™ Transaction Control
SmartMedia™ Power Supply Control
SmartMedia™ Detect Control
CIS
ROM Data Port
ROM Index Port
ROM Control
Configuration Control
Moniter Select Protect
SmartMedia™ Control register
• Offset 00-03h(00h)
• Offset 04h(02h Write)
• Offset 05h(02h Read)
• Offset 06h(04h)
• Offset 07h(06h)
Data register
Mode register
Status register
Interrupt Status register
Interrupt Mask register
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.27
TC6371AF Specification
4.8.4
Rev. 1.8
02/01/22
#PME Generation
#PME is controlled (enabled/disabled) by the bit 8 (PME_EN) of the power management control/status register
(config offset: 84h). The status can be checked using the bit 15 of the register. When the TC6371AF detects card
insertion/removal events or other interrupt events, the TC6371AF asserts #PME. The host controller controls
registers to perform masking events and controlling flags.
Card type
Interrupt event
Pin name
Details
SD host controller
Card insertion/removal
#SDCD、SDCD3(CD)
Indicates insertion into/removal from card slot
SmartMedia™ host
controller
Card insertion/removal
#SMCD、#SMEJSW
Indicates insertion into/removal from card slot
BSY release
#SMRB
Triggered by SmartMedia™ BSY release
Note:
4.8.5
The TC6371AF uses a 32-kHz clock (CLK32) for the #PME control circuit.
In D3hot/D3cold state or in D1/D2 state where the CLKRUN protocol operates, PCICLK is stopped.
Therefore, when CLK32 is not input, the TC6371AF’s #PME control circuit does not operate and #PME
cannot be supported.
#PME Pin
The #PME pin outputs power management interrupts according to PCI bus power management interface
specifications. Because the pin is an open drain output determined by PCI bus power management interface
specifications, it must be pulled up outside the TC6371AF. To prevent leak current from the external pull-up
even when the power supply to this pin is off, the pin is open-drain output with failsafe measures.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.28
TC6371AF Specification
4.8.6
Rev. 1.8
02/01/22
#PWRST
The TC6371AF supports a #PME wakeup from D3cold state (in conformance to the PCI 2.1 power-on reset
sequence). The #PWRST signal is used to reset the PME context at power on.
Phase I
Phase II
VCC
OFF
ON
PCICLK
OFF
ACTIVE
#PCIRST
X
#PWRST
X
Internal state
Internal clear
(general)
Internal clear
(PME context)
X
D0uninit.
Phase III
Phase IV
Phase V
Vaux
ON
OFF
D0 - D2
D3hot
Phase II
ACTIVE
D3cold
D0uninit.
D0active-
X
X
T2
T1
T1 = (Period until #PCIRST raised T2 = (Period until #PCIRST raised -
#PWRST raising)
>= 0
VCC is turned on again) > 1ms
• Phase I: #PWRST and #PCIRST are L when the VCC is turned on from power off. This state clears all
circuits, including the PME context.
• Phase II: Normal operating mode. #PWRST and #PCIRST are both H.
• Phase III: Setting PMCSR (config 84h) bits 1 and 0 to 11b sets the internal circuitry to D3hot. The PCICLK
is set to L except at a configuration access of PMCSR. Setting bits 1 and 0 of PMCSR to 00b shifts to
D0uninit state. Asserting #PCIRST at L shifts to Phase IV D3cold.
• Phase IV: Asserting #PCIRST at L sets the internal circuitry to D3cold. During this period, the power
supply to VCC can be switched to Vaux. At that time, VCCP can be turned off, but because #PCIRST is L
and #PWRST is H, the PME context is saved.
• Phase V: VCCP is turned back on and PCICLK goes active. While #PCIRST is L, an internal (general) clear
resets all circuits except the PME context. Next, the TC6371AF returns to normal operating mode and
the context can be written.
#PWRST
#PCIRST
PME context
L
X
Cleared
H
L
Saved
H
H
Normal
Notes:
・If D3cold is not supported, set the #PCIRST input signal level the same as that of the #PWRST input signal.
・If D3cold is supported, it is desirable to switch Vaux after asserting #PCIRST. When restoring from D3cold state,
make sure that the PCICLK waveform is stable.
TOSHIBA CONFIDENTIAL
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PAGE NO.29
TC6371AF Specification
4.8.7
Rev. 1.8
02/01/22
Vaux in D3cold State
Because the TC6371AF supports a D3cold state, it requires an auxiliary power supply (Vaux). The four systems
that need the auxiliary power supply are:
• TC6371AF internal PME context (includes interrupt detection): VCC
• Card slot power supply (power-SW) related control: VCC
• Interface with host (system interface): VCC
• SmartMedia™ slot/SD card slot interface: VCC
Toshiba recommends asserting #PCIRST to be “Low" before moving to Vaux operation.
CNT
CNT
Vaux
Vaux
VCC
VCC
Vaux Schematic
Power
Switch
VCC
VCC
TC6371AF
Host I/F
CORE
SmartMedia
I/F
SmartMedia
SD Card
I/F
SD Card
MMC
Pins that are active when operating on auxiliary power supply.
Host I/F
SD I/F (VCC)
#PME
#SDCD
CLK32
SmartMedia™ (VCC)
#SMCD
#SMEJSW
#PWRST
#SUSPEND
SDPWR
SMVC3EN
TOSHIBA CONFIDENTIAL
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PAGE NO.30
TC6371AF Specification
4.9
Rev. 1.8
02/01/22
Serial ROM Interface
The TC6371AF supports a serial ROM interface. The ROM interface is used to load the configuration register
initial values (mainly subsystem ID and subsystem vendor ID initial values) and CIS information when using the
CardBus card.
When using the serial ROM interface, connect the interface as below and set the external pins TST1[3-0] to
D010.
Toshiba verified operation of the serial ROM interface using one ”NM93C66”(Fairchild) with a 10-kΩ resistor
connected shown as the figure below.
ROM_CS
Chip select
ROM_SK
Clock
ROM_D
Output data
TC6371AF
Input data
EEPROM
TOSHIBA CONFIDENTIAL
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PAGE NO.31
TC6371AF Specification
Rev. 1.8
02/01/22
4.10 Pulled-Up/Pulled-Down Resistors
The TC6371AF needs pulled-up/pulled-down resistors attached to each interface. The following resistance values
are provided as a guide.
4.10.1 SD Card Interface
Pull-up/
Pull-down
Pull-up power
supply
Resistance
Pull-up
SDVCC
47KΩ
Pull-up
SDVCC
100KΩ
102
Pull-up
SDVCC
100KΩ
101
Pull-up
SDVCC
100KΩ
NAME
Pin
SDCD3
85
SDCD2
83
SDCD1
SDCD0
IO
IO
SD card data bus
*1：33KΩ
SDCMD
89
IO
Pull-up
FUNCTION
SDVCC
*2：100KΩ
SD card / command
*1: MultiMedia Card
supported
*2: MultiMedia Card not
supported
SDCLK
98
O



#SDCD
104
I
Pull-up
VCC
10KΩ
SD card detection
SDWP
105
I
Pull-up
VCC
10KΩ
SD card write-protection
IO
Pull-up/
Pull-down
Pull-up power
supply
Resistance
IO
Pull-down

100KΩ
Data
SD card clock
4.10.2 SmartMedia™ Interface
NAME
Pin
FUNCTION
SMD7
91
SMD6
94
SMD5
96
SMD4
99
SMD3
95
SMD2
93
SMD1
90
SMD0
86
SMCLE
75
O (3state)
Pull-down

100KΩ
Enables the command latch.
SMALE
78
O (3state)
Pull-down

100KΩ
Enables the address latch.
#SMCE
77
O (3state)
Pull-up
SMVCC
100KΩ
Enables the chip.
#SMWE
80
O (3state)
Pull-up
SMVCC
100KΩ
Enables a write.
#SMRE
79
O (3state)
Pull-up
SMVCC
100KΩ
Enables a read.
#SMWP
84
O (3state)
Pull-down

100KΩ
Write-protection
#SMRB
82
I
Pull-up
SMVCC
10KΩ
Busy
#SMCD
100
I
Pull-up
VCC
10KΩ
Detects card.
SMLVD
88
I
Pull-down

100KΩ
Detects low voltage.
#SMWPD
73
I
Pull-up
VCC
10KΩ
Write-protection seal
#SMEJSW
74
I
Pull-up
VCC
10KΩ
Eject request
#SMLED
107
O (OD)
Pull-up
VCC
100KΩ
Turns on the LED.
#SMLOCK
109
O (OD)
Pull-up
VCC
100KΩ
Lock mode
#SMEJCT
106
O (OD)
Pull-up
VCC
100KΩ
Eject response
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.32
TC6371AF Specification
4.11
Rev. 1.8
02/01/22
Connection example of SD Card/SmartMedia™ socket
It is shown that total 32 signal connections example of TC6371AF which have 8 signals of SD card
TM
interface, 1 signal of a power supply control for SD card, 22 signals of SmartMedia interface and 1 signal
TM
of a power supply control for SmartMedia . As for our company, a movement confirmation of the SD card
TM
/SmartMedia was done by using FRS-001-2000-0 and FPS009-3000 of theYAMAICHI Company. An
outside pull-up/down resistance that is mentioned on an item of the "4.10 Pull-up/down resistance" is not
shown in a bottom figure. When you design a circuit, please refer to recommended resistance by an item
of the "4.10 Pull-up/down " and a bottom figure.
FPS009-3000 manufactured by the
YAMAICHI Company
TC6371AF
DAT3
CMD
Vss
Vdd
CLK
Vss
DAT0
DAT1
DAT2
SD-WP
Vss
SD-SW
SDCD3
SDCMD
SDCLK
SDCD0
SDCD1
SDCD2
SDWP
#SDCD
SDPWR
MIC2563 manufactured by the
MICREL Company
FRS-001-2000-0 manufactured by the
YAMAICHI Company
SMVC3EN
SM-D7
SM-D6
SM-D5
SM-D4
SM-D3
SM-D2
SM-D1
SM-D0
SM-CLE
SM-ALE
SM-WE
SM-RE
SM-CE
SM-WP
SM-R/B
SM-CD
SM-LVD
SM-WP-1
SM-WP-2
SM-SW-1
SM-SW-2
SM-Vcc
SM-Vcc
SM-Vss
SM-Vss
SM-Vss
SMD7
SMD6
SMD5
SMD4
SMD3
SMD2
SMD1
SMD0
SMCLE
SMALE
#SMWE
#SMRE
#SMCE
#SMWP
#SMRB
#SMCD
SMLVD
#SMWPD
#SMEJSW
#SMLED
#SMLOCK
#SMEJCT
GND
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.33
TC6371AF Specification
4.12
Rev. 1.8
02/01/22
Processing Unused InterfaceExternal Pins
TC6371AF accommodates one port of SD Card Interface and one port of SmartMedia™ Interface. See
descriptions for processing pins in respective sections of interface when dealing with unused External
Pins for interfaces.
4.12.1
Processing Pins (SmartMedia™ Interface unsupported)
Process Pins according to the following table when SmartMedia™ Interface is unused (when each signals
are not connected to other parts) :
NAME
Pin
I/O
Process
SMD7
91
IO
Pull-up resistance for 100KΩ
SMD6
94
IO
Pull-up resistance for 100KΩ
SMD5
96
IO
Pull-up resistance for 100KΩ
SMD4
99
IO
Pull-up resistance for 100KΩ
SMD3
95
IO
Pull-up resistance for 100KΩ
SMD2
93
IO
Pull-up resistance for 100KΩ
SMD1
90
IO
Pull-up resistance for 100KΩ
SMD0
86
IO
Pull-up resistance for 100KΩ
SMCLE
75
O (3state)
OPEN
SMALE
78
O (3state)
OPEN
OPEN
#SMCE
77
O (3state)
#SMWE
80
O (3state)
OPEN
#SMRE
79
O (3state)
OPEN
#SMWP
84
O (3state)
OPEN
#SMRB
82
I
High
SMLVD
88
I
Low
#SMCD
100
I
High
High
#SMWPD
73
I
#SMEJSW
74
I
High
#SMLED
107
O (OD)
OPEN
#SMLOCK
109
O (OD)
OPEN
#SMEJCT
106
O (OD)
OPEN
SMVC3EN
72
O
OPEN
Process
And,
NAME
Pin
I/O
FCMODE
58
I
Low
IDSEL0
13
I
Connect to any AD line
IDSEL1
120
I
Low
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.34
TC6371AF Specification
4.12.2
Rev. 1.8
02/01/22
Processing Pins (SD Interface unsupported)
Process Pins according to the following table when SD Interface is unused (when each signals are not
connected to other parts):
NAME
Pin
I/O
Process
SDCD3
85
IO
Pull-up resistance for 100KΩ
SDCD2
83
IO
Pull-up resistance for 100KΩ
SDCD1
102
IO
Pull-up resistance for 100KΩ
SDCD0
101
IO
Pull-up resistance for 100KΩ
SDCMD
89
IO
Pull-up resistance for 100KΩ
SDCLK
98
O
Low
High
#SDCD
104
I
SDWP
105
I
Low
SDPWR
69
O
OPEN
And,
NAME
Pin
I/O
Process
FCMODE
58
I
Low
IDSEL0
13
I
Low
IDSEL1
120
I
Connect to any AD line
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.35
TC6371AF Specification
4.13
Rev. 1.8
02/01/22
#SMLED signal
TC6371AF has the #SMLED signal for SmartMedia interface. It is recommended that this signal is used for
access LED, for example reading and writing. This signal is controlled by setting Mode Register(Offset:04h)
of SmartMedia control register.
TC6371AF
Vcc
Vcc
#SMLED
When Mode Register is written 04h, #SMLED becomes low and LED turns on. In reverse, in the case of
being written 00h, #SMLED becomes high and LED turns off.
4.14
GPIO interface specification
TC6380AF holds 8 pins(GPIO[7:0] signals) as general port. As GPIO[7:4] signals are input ones, please
use them as fixed values with referring to page 14. It shows a usage method of GPIO[3:0] signals.
GPIO[3:0] signals can be output by setting 1b to D5 of Monitor Select Register(Config Offset:FFh) of
SmartMedia host controller register. GPIO3 signal can be controlled by D3 of Monitor Select Register, GPIO2
signal can be controlled by D2 of Monitor Select Register, GPIO1 signal can be controlled by D3 of Monitor
Select Register and GPIO0 signal can be controlled by D0 of Monitor Select Register.
As of January. 2002, the SD/MMC/SmartMedia driver does not perform any functions by controlling GPIO
signals.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.36
TC6371AF Specification
Rev. 1.8
02/01/22
5 Electrical Characteristics
5.1
Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Condition
Note
1
Vcc
Supply Voltage Range
-0.3
5.0
V
GND=0V
Vin3
Input Voltage (3.3V)
-0.3
Vcc+0.3
V
GND=0V
Vout
Output Voltage
-0.3
Vcc+0.3
V
GND=0V
Tstg
Storage Temperature Range
-40
125
°C
Note 1: VCC power supply
(Caution)
The absolute maximum ratings indicate a level at which permanent damage to the device may occur if those
ratings are exceeded and are not intended to provide a guarantee that damage will not occur by staying
within the level of the ratings.
5.2
DC Characteristics
5.2.1
Power Supply Voltage: Recommended Conditions
Power Pin
Parameter
Vcc
Supply Voltage for Core Logic
Topr
Ambient Temperature under bias
Min
Typ
Max
Unit
3.0
3.3
3.6
V
0
25
70
°C
Note
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.37
TC6371AF Specification
5.2.2
Rev. 1.8
02/01/22
PCI Interface DC Characteristics
PCI interface DC characteristics at 3.3 V operation.
Symbol
Parameter
Min
Max
Unit
Test Condition
Note
Vih
Input High Voltage
0.5Vcc
Vcc+0.5
V
1-1
Vil
Input Low Voltage
-0.5
0.3Vcc
V
1-1
Vih
Input High Voltage
0.7Vcc
Vcc+0.5
V
1-2
Vil
Input Low Voltage
-0.5
0.2Vcc
V
1-2
0.9Vcc

V
Voh
Output High Voltage
Vol
Output Low Voltage

0.1Vcc
V
Iout=1500µΑ
1-4
Ioh
Switching Current High 1
-12Vcc

mA
Vout=0.3Vcc
1-3
Switching Current High 2

-32Vcc
mA
Vout=0.7Vcc
1-3
Switching Current Low 1
16Vcc

mA
Vout=0.6Vcc
1-4
Switching Current Low 2

38Vcc
mA
Vout=0.18Vcc
1-4
Input Leakage Current
-10
10
µA
0<Vin<Vcc
1-1
Iol
Iilk
Iout=-500µA
1-3
1-2
Slewr
Output Rise Slew Rate
1
4
V/ns
1-3
Slewf
Output Fall Slew Rate
1
4
V/ns
1-3
Note 1-1: Applied for AD[31:0], CBE#[3:0], #FRAME, #IRDY, #CLKRUN, IDSEL0, IDSEL1 pins
Note1-2: Applied for #PCIRST PCICLK pins
Note1-3: Applied for AD[31:0], CBE#[3:0], PAR, #TRDY, #STOP, #DEVSEL, #CLKRUN pins
Note1-4: Applied for AD[31:0], CBE#[3:0], PAR, #TRDY, #STOP, #DEVSEL, #CLKRUN, #INTA, #INTB, #PME pins
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.38
TC6371AF Specification
5.2.3
Rev. 1.8
02/01/22
SmartMedia™ Interface DC Characteristics
SmartMedia™ interface DC characteristics at 3.3 V operation (VCC =3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Condition
Note
Vih
Input High Voltage
2.2

V
2-1
Vil
Input Low Voltage

0.6
V
2-1
Output High Voltage
2.4

V
Voh
Iout=-1mA
2-2
3.0V<Vcc<3.6V
Vol1
Output Low Voltage

0.4
V
Iout=1mA
2-2
3.0V<Vcc<3.6V
Vol2
Output Low Voltage

0.4
V
Iout=8mA
2-3
3.0V<Vcc<3.6V
Iilk
Input Leakage Current
-10
10
µA
Vin=0-Vcc
2-1
Note2-1: Applied for SMD[7:0], #SMRB, #SMCD, SMLVD, #SMWPD, #SMEJSW pins
Note2-2: Applied for SMD[7:0], SMCLE, SMALE, #SMCE, #SMWE, #SMRE, #SMWP pins
Note2-3: Applied for #SMLOCK, #SMEJCT, #SMLED pins
5.2.4
SmartMedia™ Power Supply Control DC Characteristics
SmartMedia™ power supply control DC characteristics at 3.3 V operation (Vcc =3.0-3.6V,
Ta=0-70℃
℃)
Symbol
Voh
Parameter
Output High Voltage
Min
Max
Unit
Condition
Note
2.4

V
Iout=-100µA
2-4
3.0V<Vcc<3.6V
Vol
Output Low Voltage

0.6
V
Iout=100µA
2-4
3.0V<Vcc<3.6V
Note2-4: Applied for SMVC3EN pin
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.39
TC6371AF Specification
5.2.5
Rev. 1.8
02/01/22
SD Card Interface Pin DC Characteristics
SD card interface DC characteristics at 3.3 V operation (VCC =3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Condition
Note
Vih
Input High Voltage
0.7Vcc
Vcc+0.3
V
3-1
Vil
Input Low Voltage
Vss-0.3
0.175Vcc
V
3-1
Vih
Input High Voltage
0.8Vcc

V
3-2
Vil
Input Low Voltage

0.2Vcc
V
3-2
Voh
Output High Voltage
0.75Vcc

V
Vol
Output Low Voltage

0.125Vcc
V
Iout=-1mA
3-3
3.0V<Vcc<3.6V
Iout=1mA
3-3
3.0V<Vcc<3.6V
Iilk
Input Leakage Current
-10
10
µA
0<Vin<Vcc
3-1
3-2
Rdat3
Pull-up
(pin1)
resistance
inside
card
10
90
KΩ
Note3-1: Applied for SDCD[3:0], SDCMD, SDWP pins
Note3-2: Applied for #SDCD pins
Note3-3: Applied for SDCD[3:0], SDCMD, SDCLK pins
5.2.6
SD Card Power Supply Control DC Characteristics
SD card power supply control DC characteristics at 3.3 V operation (Vcc =3.0-3.6V, Ta=0-70℃
℃)
Symbol
Parameter
Min
Max
Unit
Condition
Note
Iout=-100µA
3-3
Voh
Output High Voltage
2.4

V
Vol
Output Low Voltage

0.6
V
3.0V<Vcc<3.6V
Iout=100µA
3-3
3.0V<Vcc<3.6V
Note3-3: Applied for SDPWR pin
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.40
TC6371AF Specification
5.2.7
Rev. 1.8
02/01/22
System Interface Pin (5 V-Tolerant) DC Characteristics
System interface pin DC characteristics (VCC =3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Test Condition
Note
Vih
Input High Voltage
Vcc-0.6

V
4-1
Vil
Input Low Voltage

0.6
V
4-1
Iilk
Input Leakage Current
-10
10
µA
Vih
Input High Voltage
0.8Vcc

V
4-2
Vil
Input Low Voltage

0.6
V
4-2
Iilk
Input Leakage Current
-10
10
µA
Vih
Input High Voltage
0.8Vcc

V
4-3
Vil
Input Low Voltage

0.2Vcc
V
4-3
0<Vin<Vcc
0<Vin<Vcc
4-1
4-2
Iilk
Input Leakage Current
-10
10
µA
Vih
Input High Voltage
0.8Vcc

V
4-4
Vil
Input Low Voltage

0.2Vcc
V
4-4
Iilk
Input Leakage Current
-10
10
µA
Vin=
0<Vin<Vcc
4-3
4-4
Note4-1: Applied for CLK32 pin
Note4-2: Applied for #PWRST pin
Note4-3: Applied for #SUSPEND pin
Note4-4: Applied for FCMODE pin
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.41
TC6371AF Specification
5.2.8
Rev. 1.8
02/01/22
GPIO Interface Pin DC Characteristics
GPIO interface pin DC characteristics (Vcc =3.0-3.6V, Ta=0-70℃
℃)
Condition
Symbol
Parameter
Min
Max
Unit
Note
Vih
Input High Voltage
0.8Vcc

V
5-1
Vil
Input Low Voltage

0.2Vcc
V
5-1
Ioh
Output High Current

-4
mA
Voh=2.4V
5-2
Iol
Output Low Current
4

mA
Vol=0.4V
5-2
Iilk
Input Leakage Current
-10
10
µA
0<Vin<Vcc
5-1
Condition
Note
Note5-1: Applied for GPIO[7:0] pins
Note5-2: Applied for GPIO[3:0] pins
5.2.9
TEST Pin DC Characteristics
TEST pin DC characteristics (Vcc =3.0-3.6V, Ta=0-70℃
℃)
Symbol
Parameter
Min
Max
Unit
Vih
Input High Voltage
0.8Vcc

V
6-1
Vil
Input Low Voltage

0.2Vcc
V
6-1
Iilk
Input Leakage Current
-10
10
µA
0<Vin<Vcc
6-1
Note6-1: Applied for TSTI[3:0] pins
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.42
TC6371AF Specification
Rev. 1.8
02/01/22
5.2.10 Current Dissipation Characteristics
Power Supply Current
Symbol
Parameter
Iccstd
Power Supply Current,
Standby
IccSM
Power Supply Current,
Operating SmartMedia™
IccSD/
MMC
Power Supply Current,
Operating SD Card or MultiMedia
Card
Min
Typ
Max
Unit
Condition
100
µA
PCICLK=0,
CLK32=32KHz
VCC=3.6V
#SUSPEND=low
56
mA
PCICLK=33MHz,
CLK32=32KHz
VCC=3.6V
75
mA
PCICLK=33MHz,
CLK32=32KHz
VCC=3.6V
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.43
TC6371AF Specification
5.3
Rev. 1.8
02/01/22
AC Characteristics
5.3.1
PCI Interface Signal AC Characteristics
PCI clock AC characteristics (VCC=3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Notes
PCICLK
Tcyc
CLK cycle time
30
∞
ns
Thigh
CLK High time
11

ns
Tlow
CLK Low time
11

ns
t1d
Slew Rate, PCICLK Rising Edge
1
4
V/ns
t1e
Slew Rate, PCICLK Falling Edge
1
4
V/ns
PCICLK Timing
Tcyc
Tlow
Thigh
0.7VCC
PCICLK
t1e
t1d
0.2VCC
0.4VCC p-to-p Min
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.44
TC6371AF Specification
Rev. 1.8
02/01/22
PCI Reset AC Characteristics (VCC=3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Notes
#PCIRST
Trst
Trst-clk
Reset active time after power stable
Reset active time after CLK stable
1
ms
100
µs
PCI Reset Timing
POWER
0.4Vcc
0.4Vcc
Trst
#PCIRST
Trst-clk
0.4Vcc
PCICLK
PCI Reset Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.45
TC6371AF Specification
Rev. 1.8
02/01/22
PCI Interface Output AC Characteristics (VCC=3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Notes
CL=10pF
AD[31:0], #CBE[3:0], PAR, #DEVSEL, #TRDY, #STOP, #CLKRUN
Tval
CLK to signal valid delay-bused signals
2
11
ns
Ton
Float to active delay
2

ns
Toff
Active to float delay

28
ns
PCI Output Signals Timing
0.4Vcc
PCICLK
Tval
OUTPUT
(Shared)
0.285VCC:Rise Edge, 0.615VCC:Fall Edge
Ton
OUTPUT
Toff
PCI Output Signal Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.46
TC6371AF Specification
Rev. 1.8
02/01/22
PCI Interface Input Signal AC Characteristics (VCC=3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Notes
AD[31:0], #CBE[3:0], #FRAME, #IRDY, #CLKRUN, IDSEL0, IDSEL1
Tsu
Input setup time to CLK-bused signals
7

ns
Th
Input hold time from CLK
0

ns
PCI Input Signals Timing
0.4Vcc
PCICLK
Tsu
Th
INPUT
0.4Vcc
PCI Input Signals Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.47
TC6371AF Specification
5.3.2
Rev. 1.8
02/01/22
SmartMedia™ Interface Signal AC Characteristics
(VCC=3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
tCLS
SMCLE Setup Time
20

ns
tCLH
SMCLE Hold Time
40

ns
tCS
#SMCE Setup Time
20

ns
tCH
#SMCE Hold Time
40

ns
tWP
#SMWE Pulse Width
2PCICLK
6PCICLK
ns
tALS
SMALE Setup Time
20

ns
tALH
SMALE Hold Time
40

ns
tDS
Data Setup Time
30

ns
tDH
Data Hold Time
20

ns
tWH
#SMWE High Hold Time
3PCICLK

ns
tWW
#SMWP High to #SMWE Low
100

ns
tRR
Ready to #SMRE Low
20

ns
tRP
Read Pulse Width
3PCICLK
6PCICLK
ns
tRC
Read Cycle Time
80

ns
tCEH
#SMCE High Hold Time(at the Last Serial Read)
250

ns
tREH
#SMRE High Hold Time
2PCICLK

ns
tIR
Output Hi-Z to #SMRE Low
0

ns
tWHC
#SMWE High to #SMCE Low
50

ns
tWHR
#SMWE High to #SMRE Low
60

ns
tAR1
SMALE Low to #SMRE Low(Address Register Read, ID Read)
200

ns
tCR
#SMCE Low to #SMRE Low(Data Register Read ,ID Read)
200

ns
AC Test Conditions
Parameter
3.3V Model
Input Pulse Level
0.4V∼2.4V
Input comparison Level
1.5V / 1.5V
Output Data comparison Level
1.5V / 1.5V
Output Load
1TTL Gate and Cl=100pF
TOSHIBA CONFIDENTIAL
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PAGE NO.48
TC6371AF Specification
Rev. 1.8
02/01/22
Command Cycle Timing
SMCLE
t CLS
t CS
#SMCE
t CLH
t CH
t WP
#SMWE
t ALS
t ALH
SMALE
t DS
t DH
SMD0-7
Command Cycle Signals Timing
Serial Read Cycle Timing
t RC
#SMCE
t RP
t REH
#SMRE
SMD0-7
t RR
#SMRB
Serial Read Cycle Signals Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.49
TC6371AF Specification
Rev. 1.8
02/01/22
Address Cycle Timing
t CLS
SMCLE
t CS
t WC
t WC
#SMCE
t WP
t WH
t WP
t WH
t WP
#SMWE
t ALS
t ALH
SMALE
t DS
t DH
t DS
t DH
t DS
t DH
SMD0-7
Address Cycle Signals Timing
Status Read Cycle Timing
SMCLE
#SMCE
tCLH
t CLS
t CS
tCLS
t WP
t CH
t WHC
#SMWE
t WHR
#SMRE
t DS
t DH
SMD0-7
#SMRB
Status Read Cycle Signals Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.50
TC6371AF Specification
Rev. 1.8
02/01/22
Data Write Cycle Timing
t CLH
SMCLE
t WC
t CH
#SMCE
t WP
t WH
t DS
t DH
t WP
t WH
#SMWE
t ALS
SMALE
t DS
t DH
t DS
t DH
SMD0-7
Data Write Cycle Signals Timing
Reset Cycle Timing
SMCLE
t CLS
t CLH
#SMCE
t CS
t CH
t WP
SMD0-7
t ALS
SMALE
t ALH
t DS
t DH
SMD0-7
#SMRB
t WW
t WW
#SMWP
Reset Cycle Signals Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.51
TC6371AF Specification
Rev. 1.8
02/01/22
Read Cycle Timing
SMCLE
t CEH
#SMCE
#SMWE
t ALH
t RC
SMALE
#SMRE
t WB
････
t DS
SMD0-7
････
t RB
t DH
#SMRB
Read Cycle Timing
Read Cycle Timing in case #SMCE is set to High
SMCLE
#SMCE
#SMWE
t ALH
t RC
SMALE
#SMRE
t WB
････
t DS
SMD0-7
#SMRB
････
t DH
Read Cycle Timing in case #SMCE is set to High
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.52
TC6371AF Specification
Rev. 1.8
02/01/22
ID Read Timing
SMCLE
#SMCE
t CLS
t CS
t CH
#SMWE
t ALH
t ALS
t CR
SMALE
tAR1
#SMRE
t DS t DH
SMD0-7
00
90h
ID Read Command
Maker Code Device Code
Output
Output
Address Input
ID Read Timing
Sequential Read Timing
SMCLE
#SMCE
#SMWE
SMALE
#SMRE
SMD0-7
00h
CA0-7 PA0-7
Column
Address
N
PA8-15
PA16-23
N
N+1
N+3
527
0
1
2
527
Page
Address
M
#SMRB
Page M
access
Page M+1 512+16Byte/Page：Dout527
access
Sequential Read Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.53
TC6371AF Specification
Rev. 1.8
02/01/22
Auto Page Program Timing
SMCLE
#SMCE
#SMWE
SMALE
t ww
#SMRE
SMD0-7
CA0-7 PA0-7
00h
PA8-15
PA16-23
Din
Din
Din
10h
70h
Status
Output
#SMRB
Serial Data Input
Command
Auto Program
Command
Status Read
Command
512+16Byte/Page：Dout527
#SMWP
Auto Page Program Timing
Auto Block Erase Timing
SMCLE
#SMCE
#SMWE
SMALE
#SMRE
SMD0-7
#SMRB
60h
PA0-7
PA8-15
PA16-23
D0h
70h
Busy
Auto Block Erase Setup
Command
Erase
Command
Status Read
Command
Status
Output
#SMWP
Auto Block Erase Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.54
TC6371AF Specification
5.3.3
Rev. 1.8
02/01/22
SD Card Interface Signal AC Characteristics
(VCC=3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Notes
SDCD[3:0], SDCMD, SDCLK
Fpp
Clock frequency Data Transfer Mode
0
16
MHz
Cl=25pF
Fod
Clock frequency Identification Mode
0
256
KHz
Cl=25pF
Twl
Clock Low time
30

ns
Cl=25pF
Twh
Clock High time
30

ns
Cl=25pF
Ttlh
Clock fall time

10
ns
Cl=25pF
Tthl
Clock rise time

10
ns
Cl=25pF
Tisu
Input set-up time
10

ns
Cl=25pF
Tih
Input hold time
10

ns
Cl=25pF
Output delay time

25
ns
Cl=25pF
Todly
SD Card Interface Signals Timing
Fpp, Fod
0.75Vcc
Twl
SDCLK (output)
Twh
Ttlh
0.125Vcc
Tthl
Tisu
Tih
INPUT
OUTPUT
Todly (max)
Vol=0.125Vcc,
Todly (min)
Voh=0.75Vcc
SD Card Interface Signals Timing
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.55
TC6371AF Specification
5.3.4
Rev. 1.8
02/01/22
System Interface Signal AC Characteristics
CLK32 AC Characteristics (VCC=3.0-3.6V, Ta=0-70°C)
Symbol
Parameter
Min
Max
Unit
Notes
CLK32
Tcyc32
CLK cycle time
31
∞
µs
Thigh32
CLK High time
11

µs
Tlow32
CLK Low time
11

µs
t1d32
Slew Rate, CLK32 Rising Edge
10

ns
t1e32
Slew Rate, CLK32 Falling Edge
10

ns
CLK32 Timing
Tcyc32
Tlow32
Thigh32
Vcc-0.6
CLK32
t1e32
t1d32
0.6
TOSHIBA CONFIDENTIAL
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PAGE NO.56
TC6371AF Specification
Rev. 1.8
02/01/22
6 Package outline
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.57
TC6371AF Specification
Rev. 1.8
02/01/22
000707EAA1
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
TOSHIBA CONFIDENTIAL
TOTAL 58
PAGE NO.58