SIPEX SP706P

SP706P/R/S/T, SP708R/S/T
®
+3.0V/+3.3V Low Power Microprocessor
Supervisory Circuits
■ Precision Low Voltage Monitor:
SP706P/R and SP708R at +2.63V
SP706S and SP708S at +2.93V
SP706T and SP708T at +3.08V
■ RESET Pulse Width - 200ms
■ Independent Watchdog Timer - 1.6 sec
Timeout (SP706P/S/R/T)
■ 40µA Maximum Supply Current
■ Debounced TTL/CMOS Manual-Reset Input
■ RESET Asserted Down to VCC = 1V
■ RESET Output:
SP706P Active-High
SP706R/S/T Active-Low
SP708R/S/T Both Active High + Active Low
■ WDI Can Be Left Floating, Disabling the
Watchdog Function
Now Available in Lead Free Packaging
■ Built-In Vcc Glitch Immunity
■ Available in 8-pin PDIP, NSOIC, and
µSOIC packages
■ Voltage Monitor for Power Failure or Low
Battery Warning
■ Pin Compatible Enhancement to Industry
Standards 706P/R/S/T and 708R/S/T
The SP706P/S/R/T, SP708R/S/T series is a family of microprocessor (µP) supervisory circuits
that integrate myriad components involved in discrete solutions which monitor power-supply and
battery, in µP, and digital systems. The SP706P/S/R/T, SP708R/S/T series will significantly
improve system reliability and operational efficiency when compared to results obtained with
discrete components. The features of the SP706P/S/R/T, SP708R/S/T series include a
watchdog timer, a µP reset, a Power Fail Comparator, and a manual-reset input. The SP706P/
S/R/T, SP708R/S/T series is ideal for +3.0V or +3.3V applications in automotive systems,
computers, controllers, and intelligent instruments. The SP706P/S/R/T, SP708R/S/T series is
an ideal solution for systems in which critical monitoring of the power supply to the µP and related
digital components is demanded.
Part Number
RESET Active
RESET Threshold
Manual Reset
PFI Accuracy
Watchdog Input
SP706P
HIGH
2.63V
YES
4%
YES
SP706R
LOW
2.63V
YES
4%
YES
SP706S
LOW
2.93V
YES
4%
YES
SP706T
LOW
3.08V
YES
4%
YES
SP708R
LOW/HIGH
2.63V
YES
4%
NO
SP708S
LOW/HIGH
2.93V
YES
4%
NO
SP708T
LOW/HIGH
3.08V
YES
4%
NO
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
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© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
Continuous Power Dissipation
Plastic DIP
(derate 9.09mW/OC above +70OC)..................727mW
SO
(derate 5.88mW/OC above +70OC)..................471mW
Mini SO
(derate 4.10mW/OC above +70OC)..................330mW
Storage Temperature Range.............-65˚C to +160˚C
Lead Temperature (solding 10 sec)................+300˚C
Terminal Voltage (with respect to GND):
VCC........................................................-0.3V to +6.0V
All Other Inputs ...........................-0.3V to (VCC +3.0V)
Input Current:
VCC.....................................................................20mA
GND...................................................................20mA
Output Current (all outputs)...............................20mA
ESD Rating...........................................................2kV
SPECIFICATIONS
Vcc = 2.7V to 5.5V for SP70_P/R, VCC = 3.0 to 5.5V for SP70_S, VCC = 3.15V to 5.5V for SP70_T, TA= TMIN to TMAX to TMAX, unless otherwise noted,
typical at 25°C.
PARAMETER
Operating Voltage Range, VCC
Supply Current, ISUPPLY
Reset Threshold
Reset Threshold Hysteresis
Reset Pulse Width, tRS
RESET Output Voltage
VOH
VOL
VOH
VOL
RESET Output Voltage
VOH
VOL
VOH
VOL
Watchdog Timeout Period, tWD
WDI Pulse Width, tWP (Note1)
WDI Input Threshold,
VIL
VIH
VIL
VIH
WDI Input Current
MIN.
1.0
2.55
2.85
3.00
140
TYP.
MAX.
5.5
UNITS
V
25
2.63
2.93
3.08
20
200
40
2.70
3.00
3.15
µA
V
280
mV
ms
0.3
V
0.8xVCC
VCC-1.5
0.4
VCC-0.6
0.3
V
VCC-1.5
1.00
50
1.60
0.4
2.25
s
ns
0.6
0.7xVCC
3.5
-1
V
0.8
0.02
1
µA
CONDITIONS
MR=VCC or Floating, WDI Floating
SP70_P/R
SP70_S
SP70_T
Note 2
Note 2
VRST(MAX)<VCC<3.6V, ISOURCE = 500µA
VRST(MAX)<VCC<3.6V, ISINK =1.2mA
4.5V<VCC<5.5V, ISOURCE = 800µA
4.5V<VCC<5.5V, ISINK = 3.2mA
VRST(MAX)<VCC<3.6V, ISOURCE = 215µA
VRST(MAX)<VCC<3.6V, ISOURCE =1.2mA
4.5V<VCC<5.5V, ISOURCE = 800µA
4.5V<VCC<5.5V, ISOURCE = 3.2mA
VCC<3.6V
VIL = 0.4V, VIH = 0.8xVCC
VRST (MAX) <VCC <3.6V
VRST (MAX) <VCC <3.6V
VCC = 5.0V
VCC = 5.0V
WDI = 0 or VCC
Note1: WDI Minimum Rise/Fall time is 1 microsecond.
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© Copyright 2004 Sipex Corporation
SPECIFICATIONS (continued)
Vcc = 2.7V to 5.5V for SP70_P/R, VCC = 3.0 to 5.5V for SP70_S, VCC = 3.15V to 5.5V for SP70_T, TA= TMIN to TMAX to TMAX, unless otherwise noted,
typical at 25°C.
PARAMETER
MIN.
TYP.
MAX.
UNITS
0.3
V
CONDITIONS
WDO Output Voltage
VOH
VOL
0.8xVCC
VOH
VOL
VCC-1.5
0.4
MR Pull-Up Current
25
100
MR Pulse Width, tMR
500
150
MR Input Threshold
VIL
VIH
VIL
VIH
0.7xVCC
70
250
PFI Input Current
PFO Output Voltage
VOH
VOL
VOH
VOL
Date: 6-28-04
µA
ns
0.6
V
0.8
2.0
MR to Reset Out Delay, tMD
PFI Input Threshold
250
600
VRST(MAX)<VCC<3.6V
4.5V<VCC<5.5V
VRST(MAX)<VCC<3.6V
VRST(MAX)<VCC<3.6V
4.5V<VCC<5.5V
4.5V<VCC<5.5V
ns
VRST(MAX)<VCC<3.6V,NOTE 2
4.5V<VCC<5.5V,NOTE 2
VCC = 3.0V for the SP70_P/R,VCC =
3.3V for the SP70_S/T,PFI falling
1.25
1.30
V
-25.00
0.01
25.00
nA
0.3
V
VCC-1.5
MR = 0V,VRST(MAX)<VCC<3.6V
MR = 0V,4.5V<VCC<5.5V
750
250
1.20
0.8xVCC
VRST(MAX)<VCC<3.6V, ISOURCE = 500µA
VRST(MAX)<VCC<3.6V, ISINK =1.2mA
4.5V<VCC<5.5V, ISOURCE = 800µA
4.5V<VCC<5.5V, ISINK = 3.2mA
0.4
VRST(MAX)<VCC<3.6V, ISOURCE = 500µA
VRST(MAX)<VCC<3.6V,ISINK =1.2mA
4.5V<VCC<5.5V, ISOURCE = 800µA
4.5V<VCC<5.5V, ISINK = 3.2mA
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
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© Copyright 2004 Sipex Corporation
µSOIC
DIP and SOIC
MR 1
8
VCC 2
7 RESET / RESET*
SP706P/R/S/T
RESET / RESET* 1
WDO
WDO 2
8
SP706P/R/S/T
WDI
7 PFO
GND 3
6
WDI
MR 3
6
PFI
PFI 4
5
PFO
4
5
GND
MR 1
8
RESET
RESET 1
8
N.C.
VCC 2
7 RESET
RESET 2
7 PFO
SP708S/R/T
VCC
SP708S/R/T
GND 3
6
N.C.
MR 3
6
PFI
PFI 4
5
PFO
VCC 4
5
GND
*SP706P only
*SP706P only
Figure 1. Pinouts
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© Copyright 2004 Sipex Corporation
PIN DESCRIPTION
NAME
SP706P
FUNCTION
SP706R/S/T
SP708R/S/T
DIP/
SOIC
µSOIC
DIP/
SOIC
µSOIC
DIP/
SOIC
µSOIC
MR
Manual Reset - This input triggers a reset pulse
when pulled below 0.8V. This active-LOW input
has an internal 70µA pull-up current. It can be
driven from a TTL or CMOS logic line or shorted
to ground with a switch
1
3
1
3
1
3
VCC
Voltage input.
2
4
2
4
2
4
Ground reference for all signals
3
5
3
5
3
5
PFI
Power-Fail Input - When this voltage monitor input
is less than 1.25V, PFO goes LOW. Connect PFI
to ground or VCC when not in use.
4
6
4
6
4
6
PFO
Power-Fail Output - This output is HIGH until PFI
is less than 1.25V.
5
7
5
7
5
7
WDI
Watchdog Input - If this input remains HIGH or
LOW for 1.6s, the internal watchdog timer times
out and WDO goes LOW. Floating WDI or
connecting WDI to a high-impedance tri-state
buffer disables the watchdog feature. The internal
watchdog timer clears whenever RESET is
asserted, WDI is tri-stated, or whenever WDI sees
a rising or falling edge.
6
8
6
8
-
-
N.C.
No Connect.
-
-
-
-
6
8
RESET
Active-LOW RESET Output - This output pulses
LOW for 200ms when triggered and stays LOW
whenever VCC is below the reset threshold. It
remains LOW for 200ms after Vcc rises above the
reset threshold or MR goes from LOW to HIGH.
A watchdog timeout will not trigger RESET unless
WDO is connected to MR.
-
-
7
1
7
1
WDO
Watchdog Output - This output pulls LOW when
the internal watchdog timer finishes its 1.6s count
and does not go HIGH again until the watchdog is
cleared. WDO also goes LOW during low-line
conditions. Whenever VCC is below the reset
threshold, WDO stays LOW. However, unlike
RESET, WDO does not have a minimum pulse
width. As soon as VCC is above the reset
threshold, WDO goes HIGH with no delay.
8
2
8
2
-
-
R ESET
Active-HIGH RESET Output - This output is the
complement of RESET. Whenever RESET is
HIGH, RESET is LOW, and vice versa. Note the
SP708R/S/T has a reset output only.
7
1
-
-
8
2
GND
Table 1. Device Pin Description
Date: 6-28-04
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© Copyright 2004 Sipex Corporation
WATCHDOG
TRANSITION
DETECTOR
WDI
WATCHDOG
TIMER
WDO
VCC
70µA
TIMEBASE FOR
RESET AND
WATCHDOG
MR
RESET
GENERATOR
RESET/RESET*
VCC
2.63V for the SP706P/R
2.93V for the SP706S
3.08V for the SP706T
PFI
PFO
1.25V
SP706P/R/S/T
GND
* For the SP706P only
Figure 2. Internal Block Diagram for the SP706P/R/S/T
VCC
RESET
250µA
MR
RESET
GENERATOR
RESET
VCC
2.63V for the SP708R
2.93V for the SP708S
3.08V for the SP708T
PFI
PFO
1.25V
SP708R/S/T
GND
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© Copyright 2004 Sipex Corporation
+3.3V
VCC = +3.3V
TA = +25 C
1.4V
PFI
1.2V
PFI
PFO
3V
PFO
30pF
+1.25V
0V
1KΩ
Figure 4B. Circuit for the Power-Fail Comparator
De-assertion Response Time.
Figure 4A. Power-Fail Comparator De-assertion
Response Time.
+3.3V
1.4V
VCC = +3.3V
TA = +25 C
PFI
1.2V
1KΩ
3V
PFI
PFO
PFO
0V
30pF
+1.25V
Figure 5A. Power-Fail Comparator Assertion
Response Time.
Figure 5B. Circuit for the Power-Fail Comparator
Assertion Response Time.
VCC
TA = +25oC
3.6V
VCC
VCC
2KΩ
0V
RESET
RESET
RESET
330pF
GND
Figure 6B. Circuit for the SP706 RESET Output
Voltage vs. Supply Voltage.
Figure 6A. SP706 RESET Output Voltage vs. Supply
Voltage.
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© Copyright 2004 Sipex Corporation
VCC
TA = +25oC
VCC
10KΩ
RESET
RESET
330pF
GND
Figure 7A. SP706 RESET Response Time
Figure 7B. Circuit for the SP706 RESET Response
Time
3.2V
2.8V
RESET
RESET
0V
0V
3.2V
2.8V
RESET
RESET
0V
0V
Figure 8. SP708 RESET and RESET Assertion
Figure 9. SP708 RESET and RESET De-Assertion
VCC
TA = +25oC
VCC
10KΩ
RESET
330pF
RESET
330pF
GND
10KΩ
Figure 10. Circuit for the SP708 RESET and RESET Assertion and De-Assertion
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
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© Copyright 2004 Sipex Corporation
3.6V
VCC
0V
RESET
0V
Figure 12. SP708 RESET Response Time
Figure 11. SP708 RESET Output Voltage vs. Supply
Voltage
VCC
VCC
RESET
330pF
10KΩ
GND
Figure 13. Circuit for the SP708 RESET Output Voltage vs. Supply Voltage and the RESET Response Time
Figures
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
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© Copyright 2004 Sipex Corporation
the reset threshold, an internal timer releases
RESET after 200ms. RESET pulses LOW whenever VCC dips below the reset threshold, such as
in a brownout condition. When a brownout
condition occurs in the middle of a previously
initiated reset pulse, the pulse continues for at
least another 140ms. During power-down, once
VCC falls below the reset threshold, RESET
stays LOW and is guaranteed to be 0.4V or less
until VCC drops below 1V.
FEATURES
The SP706P/R/S/T-SP708R/S/T series provides
four key functions:
1. A reset output during power-up, power-down
and brownout conditions.
2. An independent watchdog output that goes
LOW if the watchdog input has not been toggled
within 1.6 sec.
3. A 1.25V threshold detector for power-fail
warning, low battery detection, or monitoring a
power supply other than +3.3V/+3.0V.
4. An active-LOW manual-reset that allows
RESET to be triggered by a pushbutton switch.
The active-HIGH RESET output is simply
the complement of the RESET output and is
guaranteed to be valid with VCC down to 1.1V.
Some µPs, such as Intel's 80C51, require an
active-HIGH reset pulse.
The SP706R/S/T devices are the same as the
SP708R/S/T devices except for the active-HIGH
RESET substitution of the watchdog timer. The
SP706P device is the same as the SP706R device except an active-HIGH RESET is provided
rather than an active-LOW RESET.
Watchdog Timer
The SP706P/R/S/T-SP708R/S/T series watchdog
circuit monitors the µP's activity. If the µP does
not toggle the watchdog input (WDI) within 1.6
seconds and WDI is not tri-stated, WDO goes
LOW. As long as RESET is asserted or the WDI
input is tri-stated, the watchdog timer will stay
cleared and will not count. As soon as RESET
is released and WDI is driven HIGH or LOW,
the timer will start counting. Pulses as short as
50ns can be detected.
THEORY OF OPERATION
The SP706P/R/S/T-SP708R/S/T series is a microprocessor (µP) supervisory circuit that monitors the power supplied to digital circuits such
as microprocessors, microcontrollers, or
memory. The series is an ideal solution for
portable, battery-powered equipment that requires power supply monitoring. Implementing
this series will reduce the number of components and overall complexity of a system. The
watchdog functions of this product family will
continuously oversee the operational status of a
system. The operational features and benefits of
the SP706P/R/S/T-SP708R/S/T series are described, in more detail, below.
Typically, WDO will be connected to the
non-maskable interrupt input (NMI) of a µP.
When VCC drops below the reset threshold, WDO
will go LOW independent of the current status
of the watchdog timer. Normally this would
trigger an NMI but RESET goes LOW simultaneously, and thus overrides the NMI.
If WDI is left unconnected, WDO can be used as
a low-line output. Since floating WDI disables
the internal timer, WDO goes LOW only when
V CC falls below the reset threshold, thus
functioning as a low-line output.
RESET Output
A microprocessor's reset input starts the µP
in a known state. The SP706P/R/S/T-SP708R/
S/T series asserts reset during power-up and
prevents code execution errors during powerdown or brownout conditions.
Power-Fail Comparator
The power-fail comparator can be used for
various purposes because its output and
noninverting input are not internally connected.
The inverting input is internally connected to
a 1.25V reference.
During power-up, once VCC reaches 1V, RESET
is a guaranteed logic LOW of 0.4V or less. As
VCC
rises, RESET stays LOW. When VCC rises above
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
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© Copyright 2004 Sipex Corporation
tWP
tWD
tWD
+3.3V
WDI
0V
+3.3V
WDO
0V
tWD
+3.3V
RESET*
0V
tRS
+3.3V
RESET*
0V
* externally triggered LOW by MR,
RESET is for the SP813L/813M only
Figure 14. Watchdog Timing Waveforms
Manual Reset
The manual-reset input (MR) allows RESET to
be triggered by a pushbutton switch. The switch
is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/
CMOS logic compatible, so it can be driven by
an external logic line. MR can be used to force
a watchdog timeout to generate a RESET pulse
in the SP706P/R/S/T-SP708R/S/T series.
Simply connect WDO to MR.
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in Figure 16. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator drops
out. Use PFO to interrupt the µP so it can prepare
for an orderly power-down.
+3.3V
VCC
VRT
VRT
0V
+3.3V
WDO
0V
tRS
tRS
+3.3V
RESET
0V
+3.3V
MR*
0V
*externally driven LOW
tMD
tMR
Figure 15. Timing Diagrams with WDI Tri-stated. The RESET Output is the Inverse of the RESET Waveform
Shown.
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© Copyright 2004 Sipex Corporation
VCC line. Connect PFO to MR to initiate a
RESET pulse when PFI drops below 1.25V.
Figure 17 shows the SP706R/S/T-SP708R/
S/T series configured to assert RESET when the
+3.3V/+3.0V supply falls below the RESET
threshold, or when the +12V supply falls below
approximately 11V.
Ensuring a Valid RESET Output Down to
VCC = 0V
When VCC falls below 1V, the RESET output no
longer sinks current, it becomes an open circuit.
High-impedance CMOS logic inputs can drift to
undetermined voltages if left undriven. If a pulldown resistor is added to the RESET pin, any
stray charge or leakage currents will be shunted
to ground, holding RESET LOW. The resistor
value is not critical. It should be about 100KΩ,
large enough not to load RESET and small
enough to pull RESET to ground.
Monitoring a Negative Voltage Supply
The power-fail comparator can also monitor a
negative supply rail, shown in Figure 18.
When the negative rail is good (a negative
voltage of large magnitude), PFO is LOW. By
adding the resistors and transistor as shown, a
HIGH PFO triggers RESET. As long as PFO
remains HIGH, the SP706P/R/S/T-SP708R/S/
T series will keep RESET asserted (where
RESET = LOW and RESET = HIGH). Note that
this circuit's accuracy depends on the PFI
threshold tolerance, the VCC line, and the resistors.
Monitoring Voltages Other Than the
Unregulated DC Input
Monitor voltages other than the unregulated DC
by connecting a voltage divider to PFI and
adjusting the ratio appropriately. If required,
add hysteresis by connecting a resistor (with a
value approximately 10 times the sum of the
two resistors in the potential divider network)
between PFI and PFO. A capacitor between PFI
and GND will reduce the power-fail circuit's
sensitivity to high-frequency noise on the
line being monitored. RESET can be used to
monitor voltages other than the +3.3V/+3.0V
Interfacing to mPs with Bidirectional
RESET Pins
µPs with bidirectional RESET pins, such as the
Motorola 68HC11 series, can contend with the
RESET output. If, for example, the RESET
Regulated +3.3V/+3.0V
Power Supply
+3.3V/+3.0V
Unregulated DC
Power Supply
0.1µF
VCC
µP
RESET
PFO
PFI
NMI
MR
R1
RESET
INTERRUPT
PFI
PFI
PFO
130KΩ
1%
R2
WDO
to µP
MR
RESET
GND
GND
1MΩ
1%
VCC
VCC
I/O LINE
+12V
GND
PUSHBUTTON
SWITCH
Figure 16. Typical Operating Circuit
Date: 6-28-04
Figure 17. Monitoring Both +3.3V/+3.0V and +12V
Power Supplies
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
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© Copyright 2004 Sipex Corporation
the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse
width a negative-going VCC transient may
typically have without causing a reset pulse to
be issued. As the amplitude of the transient
increases (i.e. goes farther below the reset
threshold), the maximum allowable pulse width
decreases. Typically, a VCC transient that goes
100mV below the reset threshold and lasts for
40µs or less will not cause a reset pulse to be
issued. A 100nF bypass capacitor mounted close
to the VCC pin provides additional transient
immunity.
output is driven HIGH and the µP wants to pull
it LOW, indeterminate logic levels may result.
To correct this, connect a 4.7kΩ resistor
between the RESET output and the µP reset
I/O, as shown if Figure 19. Buffer the
RESET output to other system components.
Negative-Going VCC Transients
While issuing resets to the µP during power-up,
power-down, and brownout conditions, these
supervisors are relatively immune to shortduration negative-going VCC transients (glitches).
It is usually undesirable to reset the µP when VCC
experiences only small glitches.
Applications
The SP706P/R/S/T-SP708R/S/T series offers
unmatched performance and the lowest power
consumption for these industry standard devices. Refer to Figures 21 and 22 for supply
current performance characteristics rated against
temperature and supply voltages.
Figure 20 shows maximum transient duration vs. reset-comparator overdrive, for which
reset pulses are not generated. The data was generated using negative-going VCC pulses, starting
at 3.3V and ending below the reset threshold by
+3.3V/+3.0V
VCC
100kΩ
MR
R1
Buffered RESET connects to System Components
PFI
PFO
2N3904
100kΩ
to µP
R2
RESET
+3.3V/+3.0V
VGND
+3.3V/+3.0V
VCC
VCC
R1 = VCC - 1.25 , VTRIP < 0
1.25 - VTRIP
R2
µP
RESET
RESET
4.7KΩ
+3.3V
MR
0V
V-
GND
GND
+3.3V
PFO
0V
VTRIP
V0V
Figure 18. Monitoring a Negative Voltage Supply
Date: 6-28-04
Figure 19. Interfacing to Microprocessors with
Bidirectional RESET I/O for the SP706
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© Copyright 2004 Sipex Corporation
Maximum Transient Duration
20.2
100
20.1
80
Vcc=3.3V
Transient Duration (µ
µS)
20.0
1nF Capacitor
VOUT TO GND
19.9
Supply Current (mA)
60
40
Above Line
RESET
Generated
20
NO
RESET
Generated
19.8
19.7
19.6
19.5
0
10
1000
100
10000
19.4
-60
Reset Overdrive (mV)
-40
-20
0
20
40
60
80
100
Temperature (°C)
Figure 20. Maximum Transient Duration Without
Causing a Reset Pulse vs. Reset Comparator Overdrive
Figure 21. Supply Current vs. Temperature
30
28
Supply Current (µ
µA)
26
24
22
20
18
16
14
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Figure 22. Supply Current vs. Supply Voltage
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
14
© Copyright 2004 Sipex Corporation
PACKAGE: PLASTIC
DUAL–IN–LINE
(NARROW)
E1 E
D1 = 0.005" min.
(0.127 min.)
A1 = 0.015" min.
(0.381min.)
D
A = 0.210" max.
(5.334 max).
C
A2
e = 0.100 BSC
(2.540 BSC)
Ø
L
B1
B
eA = 0.300 BSC
(7.620 BSC)
ALTERNATE
END PINS
(BOTH ENDS)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
Date: 6-28-04
8–PIN
A2
0.115/0.195
(2.921/4.953)
B
0.014/0.022
(0.356/0.559)
B1
0.045/0.070
(1.143/1.778)
C
0.008/0.014
(0.203/0.356)
D
0.355/0.400
(9.017/10.160)
E
0.300/0.325
(7.620/8.255)
E1
0.240/0.280
(6.096/7.112)
L
0.115/0.150
(2.921/3.810)
Ø
0°/ 15°
(0°/15°)
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
15
© Copyright 2004 Sipex Corporation
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(NARROW)
E
H
h x 45°
D
A
Ø
e
B
A1
L
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
Date: 6-28-04
8–PIN
A
0.053/0.069
(1.346/1.748)
A1
0.004/0.010
(0.102/0.249
B
0.014/0.019
(0.35/0.49)
D
0.189/0.197
(4.80/5.00)
E
0.150/0.157
(3.802/3.988)
e
0.050 BSC
(1.270 BSC)
H
0.228/0.244
(5.801/6.198)
h
0.010/0.020
(0.254/0.498)
L
0.016/0.050
(0.406/1.270)
Ø
0°/8°
(0°/8°)
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
16
© Copyright 2004 Sipex Corporation
PACKAGE:
0.0256
BSC
PLASTIC
MICRO SMALL
OUTLINE (µSOIC)
12.0˚
±4˚
0.012
±0.003
0.0965
±0.003
0.008
0˚ - 6˚
0.006
±0.006
0.006
±0.006
R .003
0.118
±0.004
0.16
±0.003
12.0˚
±4˚
0.01
0.020
0.020
1
0.0215
±0.006
0.037
Ref
3.0˚
±3˚
2
0.116
±0.004
0.034
±0.004
0.116
±0.004
0.040
±0.003
0.013
±0.005
0.118
±0.004
0.118
±0.004
0.004
±0.002
All package dimensions are in inches
50 USOIC devices per tube
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
17
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Model ....................................................................................... Temperature Range ................................................................................ Package
SP706PCP ..................................................................................... 0°C to +70°C ................................................................................... 8–pin PDIP
SP706PCN ..................................................................................... 0°C to +70°C ................................................................................ 8–pin NSOIC
SP706PCU ..................................................................................... 0°C to +70°C ................................................................................. 8-pin µSOIC
SP706RCP ..................................................................................... 0°C to +70°C ................................................................................... 8–pin PDIP
SP706RCN ..................................................................................... 0°C to +70°C ................................................................................ 8–pin NSOIC
SP706RCU ..................................................................................... 0°C to +70°C ................................................................................. 8-pin µSOIC
SP706SCP ..................................................................................... 0°C to +70°C ................................................................................... 8–pin PDIP
SP706SCN ..................................................................................... 0°C to +70°C ................................................................................ 8–pin NSOIC
SP706SCU ..................................................................................... 0°C to +70°C ................................................................................. 8-pin µSOIC
SP706TCP ..................................................................................... 0°C to +70°C ................................................................................... 8–pin PDIP
SP706TCN ..................................................................................... 0°C to +70°C ................................................................................ 8–pin NSOIC
SP706TCU ..................................................................................... 0°C to +70°C ................................................................................. 8-pin µSOIC
SP706PEP ...................................................................................
SP706PEN ...................................................................................
SP706PEU ...................................................................................
SP706REP ...................................................................................
SP706REN ...................................................................................
SP706REU ...................................................................................
SP706SEP ...................................................................................
SP706SEN ...................................................................................
SP706SEU ...................................................................................
SP706TEP ...................................................................................
SP706TEN ...................................................................................
SP706TEU ...................................................................................
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
SP708RCP ..................................................................................... 0°C
SP708RCN ..................................................................................... 0°C
SP708RCU ..................................................................................... 0°C
SP708SCP ..................................................................................... 0°C
SP708SCN ..................................................................................... 0°C
SP708SCU ..................................................................................... 0°C
SP708TCP ..................................................................................... 0°C
SP708TCN ..................................................................................... 0°C
SP708TCU ..................................................................................... 0°C
SP708REP ...................................................................................
SP708REN ...................................................................................
SP708REU ...................................................................................
SP708SEP ...................................................................................
SP708SEN ...................................................................................
SP708SEU ...................................................................................
SP708TEP ...................................................................................
SP708TEN ...................................................................................
SP708TEU ...................................................................................
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
-40°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
to
to
to
to
to
to
to
to
to
................................................................................. 8–pin PDIP
.............................................................................. 8–pin NSOIC
............................................................................... 8-pin µSOIC
................................................................................. 8–pin PDIP
.............................................................................. 8–pin NSOIC
............................................................................... 8-pin µSOIC
................................................................................. 8–pin PDIP
.............................................................................. 8–pin NSOIC
............................................................................... 8-pin µSOIC
................................................................................. 8–pin PDIP
.............................................................................. 8–pin NSOIC
............................................................................... 8-pin µSOIC
................................................................................... 8–pin PDIP
................................................................................ 8–pin NSOIC
................................................................................. 8-pin µSOIC
................................................................................... 8–pin PDIP
................................................................................ 8–pin NSOIC
................................................................................. 8-pin µSOIC
................................................................................... 8–pin PDIP
................................................................................ 8–pin NSOIC
................................................................................. 8-pin µSOIC
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
+85°C
................................................................................. 8–pin PDIP
.............................................................................. 8–pin NSOIC
............................................................................... 8-pin µSOIC
................................................................................. 8–pin PDIP
.............................................................................. 8–pin NSOIC
............................................................................... 8-pin µSOIC
................................................................................. 8–pin PDIP
.............................................................................. 8–pin NSOIC
............................................................................... 8-pin µSOIC
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP708TEU = standard; SP708TEU-L = lead free.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
18
© Copyright 2004 Sipex Corporation