May 15, 2003 Rev 3.0 IRMCV201 Complete Motion Control Verilog Library AcceleratorTM Verilog Code Development Tool Features Product Summary TM Accelerator architecture AC servo development system ServoDesignerTM graphical user interface for configuration, control and monitoring Verilog code library grouped into three segments: FOC blocks Motion peripheral blocks Communication blocks Flexible Target Silicon Field Orientation Control execution Versatile PWM module Sine or Space Vector PWM Communication options Fast SPI (5 MHz), Description IRMCV201 is a Verilog code development tool including a rich Verilog library and graphical user interface. The tool set is designed to facilitate motion control algorithm development including motion peripheral and communication modules. Flexible configuration allows the user to quickly realize hardware on an FPGA to achieve a high performance AC motor control system. Closed Loop Velocity Control, Sequencing Control Update Rate = PWM carrier frequency / 2 O I1 x I2 I1 I3 I3 I2 REF scale SPDKI Velocity Control Enable SPDKP INT_REF Feedforward path enable START STOP DIR Sequence Control FLTCLR SYNC RAMP VQLIM - PI IDREF IQLIM+ RS232C/ RS422 Interface RTS CTS SCK SDO SDI SPI Slave Interface CS 17 + PI + e Space Vector PWM VDS Dea d time Slip gain 4096 I2 I3 I1 I1 x I2 I3 Host Register Interface SpdScale + dt O FAULT InitZval + 3 Quadrature Decoding IQ ID 3 IQ scale 4096 I2 I3 O O I2 I1 x I2 I3 I1 I1 x I2 I1 I3 I3 ID scale Communication Modules Gate Signals PWMmode 2Pen Dtime PWMen AngleScale MaxEncCount Slip gain enable 0 Parallel Interface BRAKE 6 VQS jθ VD enable VDLIM Monitoring Registers 8 channel Serial A/D Interface INT_VD - VDLIM Configuration Registers VQ VD PI - CLK DATA GSenseL ModScl GSenseU CURKP - CNVST DC bus dynamic brake control CURKI IQREF Decel Rate RCV SND 2 Optional Current Sense 4096 - VQLIM + IQLIMAccel Rate FAULT PWM ACTIVE Data Address Control + MUX ADS7818 A/D interface DCV_FDBK + Reference Select 2 Closed Loop Current Control Update Rate = PWM carrier frequency x1 or x 2 +/-16383 = +/-max_speed INT_VQ 6 usec (200 sysclk) UART (57.6K or 1Mbit) Bilinear transformation based discretization Rapid prototyping with AcceleratorTM Hardware Platform EXT_REF FPGA or ASIC EncType InitZ Optional CurrentSense jθ e 2/3 +/-4095 = +/-rated ID for IM field flux Encoder Hall A/B/C Zpol IV IR2175 interface Motor Phase Current V IW IR2175 interface Motor Phase Current W Current Offset W 4096 +/-16383 = +/-4X of rated current for IQ Encoder A/B/Z INT_DAC1 INT_DAC2 INT_DAC3 INT_DAC4 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Current Offset V DAC_PWM1 4ch DAC module DAC_PWM2 DAC_PWM3 DAC_PWM4 1