CYPRESS CY7C43644AV-10AC

CY7C43644AV
CY7C43664AV
CY7C43684AV
3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with
Bus Matching
Features
• Fully asynchronous and simultaneous Read and Write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user selectable mode
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
• 3.3V high-speed, low-power, bidirectional, First-In
First-Out (FIFO) memories w/ bus matching capabilities
• 1K × 36 × 2 (CY7C43644AV)
• 4K × 36 × 2 (CY7C43664AV)
• 16K × 36 × 2 (CY7C43684AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
— ICC= 60 mA
— ISB= 10 mA
Table 1.
Logic Block Diagram
MBF1
CLKA
MBA
RT2
PRS1
FIFO1,
Mail1
Reset
Logic
Status
Flag Logic
AFA
SPM
FS0/SD
FS1/SEN
Programmable
Flag Offset
Registers
36
A0–35
EFB/ORB
AEB
36
Timing
Mode
AEA
Output
Register
FFB/IRB
AFB
Read
Pointer
Write
Pointer
B0–35
BE/FWFT
Status
Flag Logic
EFA/ORA
CLKB
CSB
W/RB
ENB
MBB
RTI
BM
SIZE
Read
Pointer
Write
Pointer
FFA/IRA
Port B
Control
Logic
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO 2)
FIFO1,
Mail1
Reset
Logic
Input
Register
MRS1
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO 1)
Input
Register
ENA
Output
W/RA
Register
Port A
Control
Logic
Bus Matching
Mail1
Register
CSA
MRS2
PRS2
Mail2
Register
MBF2
Cypress Semiconductor Corporation
Document #: 38-06025 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 26, 2002
CY7C43644AV
CY7C43664AV
CY7C43684AV
Table 1.
Pin Configuration[1]
TQFP
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
MBF1
VCC
AEB
AFB
VCC
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
NC
GND
FS1/SEN
MRS2
MBB
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
CSA
FFA/IRA
EFA/ORA
PRS1
Top View
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
RT2
A12
CY7C43644AV
CY7C43664AV
CY7C43684AV
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CLKB
PRS2
VCC
B35
B34
B33
B32
GND
NC
B31
B30
B29
B28
B27
B26
RT1
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
VCC
B15
B14
B13
B12
GND
B11
B10
GND
B6
VCC
B7
B8
B9
B2
B3
B4
B5
A9
A8
A7
A6
GND
A5
A4
A3
SPM
VCC
A2
A1
A0
GND
B0
B1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Note:
1. Pin-compatible to IDT7236X4 family.
Document #: 38-06025 Rev. *C
Page 2 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Functional Description
The CY7C436X4AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous FIFO memory which
supports clock frequencies up to 133 MHz and has Read
access times as fast as 6 ns. Two independent 1K/4K/16K ×
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be input and
output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or
Little Endian configurations.
The CY7C436X4AV is a synchronous (clocked) FIFO,
meaning each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X4AV: Master
Reset and Partial Reset. Master Reset initializes the Read and
Write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the Read and Write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own,
independent Partial Reset pin, PRS1 and PRS2.
The CY7C436X4AV have two modes of operation: In the CY
Standard mode, the first word written to an empty FIFO is
deposited into the memory array. A Read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through mode (FWFT), the
first long-word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no Read operation required
(nevertheless, accessing subsequent words does necessitate
a formal Read request). The state of the BE/FWFT pin during
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag (EFA/
ORA and EFB/ORB) and a combined Full/Input Ready flag
(FFA/IRA and FFB/IRB). The EF and FF functions are selected
in the CY Standard mode. EF indicates whether the memory
is empty and FF indicates whether the FIFO memory is full.
The IR and OR functions are selected in the First-Word FallThrough mode. IR indicates whether or not the FIFO has
available memory locations. OR shows whether the FIFO has
data available for reading or not. It marks the presence of valid
data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB are asserted when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB are asserted when a selected
number of words written to the memory achieve a predetermined “almost full state.” [2]
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFB are loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFB threshold can be set at 8, 16, or
64 locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. A Retransmit feature is available on these devices.
The CY7C436X4AV FIFOs are characterized for operation
from 0°C to 70°C commercial, and from –40°C to 85°C industrial. Input ESD protection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
CY7C43644/64/84AV
–7
CY7C43644/64/84AV
–10
CY7C43644/64/84AV
–15
Unit
133
100
66.7
MHz
6
8
10
ns
7.5
10
15
ns
Minimum Data or Enable Set-Up
3
4
5
ns
Minimum Data or Enable Hold
0
0
0
ns
Maximum Flag Delay
6
8
10
ns
60
60
60
mA
Active Power Supply
Current (ICC1)
Commercial
Industrial
60
Note:
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to two clock cycles for flag deassertion, but the flag will always
be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to Cypress’s
application note entitled “Designing with CY7C436xx Synchronous FIFOs” for more details on flag uncertainties.
Document #: 38-06025 Rev. *C
Page 3 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
CY7C43644AV
CY7C43664AV
CY7C43684AV
Density
1K × 36 × 2
4K × 36 × 2
16K × 36 × 2
Package
128 TQFP
128 TQFP
128 TQFP
Pin Definitions
Signal Name
Description
I/O
Function
A0–35
Port A Data
I/O 36-bit bidirectional data port for side A.
AEA
Port A Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the
number of words in FIFO2 is less than or equal to the value in the Almost Empty A
offset register, X2.[2]
AEB
Port B Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the
number of words in FIFO1 is less than or equal to the value in the Almost Empty B
offset register, X1.[2]
AFA
Port A Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKA (MHz). It is LOW when the
number of empty locations in FIFO1 is less than or equal to the value in the Almost Full
A offset register, Y1.[2]
AFB
Port B Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKB. It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.[2]
B0–35
Port B Data
I/O 36-bit bidirectional data port for side B.
BE/FWFT
Big Endian/
First-Word FallThrough Select
I
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word
on Port A is transferred to Port B first for A-to-B data flow. For data flowing from port B
to Port A, the first word/byte written to Port B will come out as the most significant word/
byte on port A. On the other hand, a LOW on BE will select Little Endian operation. In
this case, the least significant byte or word on Port A is transferred to Port B first for Ato-B data flow. Similarly, the first word/byte written into port B will come out as the least
significant word/byte on Port A for B-to-A data flow. After Master Reset, this pin selects
the timing mode. A HIGH on BE/FWFT selects CY Standard mode, a LOW selects
First-Word Fall-Through mode. Once the timing mode has been selected, the level on
this pin must be static throughout device operation.
BM
Bus Match
Select (Port A)
I
A HIGH on this pin enables either byte or word bus width on Port B, depending
on the state of SIZE. A LOW selects long word operation. BM works with SIZE and BE
to select the bus size and endian arrangement for Port B. The level of BM must be
static throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA
are all synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB
are all synchronized to the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to Read or Write
on Port A. The A0–35 are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to Read or Write
on Port B. The B0–35 are in the high-impedance state when CSB is HIGH.
EFA/ORA
Port A Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard mode, the EFA function is selected.
EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A0–35 outputs
available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of
CLKA.
Document #: 38-06025 Rev. *C
Page 4 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Pin Definitions (continued)
Signal Name
Description
I/O
Function
EFB/ORB
Port B Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard mode, the EFB function is selected.
EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B0–35 outputs
available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of
CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to Read or Write
data on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read or Write
data on Port B.
FFA/IRA
Port A Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard mode, the FFA function is selected.
FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA
function is selected. IRA indicates whether or not there is space available for writing to
the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard mode, the FFB function is selected.
FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB
function is selected. IRB indicates whether or not there is space available for writing to
the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
FS1/SEN
Flag Offset
Select 1/Serial
Enable
I
FS0/SD
Flag Offset
Select 0/Serial
Data
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit Writes required to program the offset registers
is 40 for the CY7C43644AV, 48 for the CY7C43664AV, and 56 for the CY7C43684AV.
The first bit Write stores the Y-register MSB and the last bit Write stores the X-register
LSB.
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A Read or Write
operation. When a Read operation is performed on Port A, a HIGH level on MBA
selects data from the Mail2 register for output and a LOW level selects FIFO2 output
register data for output. When a Write operation is performed on port A, a HIGH level
on MBA will write the data into Mail1 register, while a LOW level will write the data into
FIFO1.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B Read or Write
operation. When a Read operation is performed on Port B, a HIGH level on MBB
selects data from the Mail1 register for output and a LOW level selects FIFO1 output
register data for output. When a Write operation is performed on port B, a HIGH level
on MBB will write the data into Mail2 register, while a LOW level will write the data into
FIFO2.
MBF1
Mail1 Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the
Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is
set HIGH by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and
MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
FIFO1 Master
Reset
I
A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable
flag default offsets for FIFO1. It also configures Port B for bus size and endian
arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW.
Document #: 38-06025 Rev. *C
Page 5 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Pin Definitions (continued)
Signal Name
Description
I/O
Function
MRS2
FIFO2 Master
Reset
I
A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location
of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2
selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2
is LOW.
PRS1
FIFO1 Partial
Reset
I
A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
PRS2
FIFO2 Partial
Reset
I
A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location
of memory and sets the Port A output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RT1
Retransmit
FIFO1
I
A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by
bringing the Read pointer back to location zero. The user will still need to perform Read
operations to retransmit the data. Retransmit function applies to CY standard mode
only.
RT2
Retransmit
FIFO2
I
A LOW strobe on this pin will retransmit the data on FIFO2. This is achieved by
bringing the Read pointer back to location zero. The user will still need to perform Read
operations to retransmit the data. Retransmit function applies to CY standard mode
only.
SIZE
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A
LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM
and BE to select the bus size and endian arrangement for Port B. The level of SIZE
must be static throughout device operation.
SPM
Serial
Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA
Port A Write/
Read Select
I
A HIGH selects a Write operation and a LOW selects a Read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance
state when W/RA is HIGH.
W/RB
Port B Write/
Read Select
I
A LOW selects a Write operation and a HIGH selects a Read operation on Port B
for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance
state when W/RB is LOW.
Document #: 38-06025 Rev. *C
Page 6 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X4AV
undergoes a complete reset by taking its associated Master
Reset (MRS1, MRS2) input LOW for at least four Port A clock
(CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset inputs can switch asynchronously to
the clocks. A Master Reset initializes the internal Read and
Write pointers and forces the Full/Input Ready flag (FFA/IRA,
FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA,
EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and
the Almost Full flag (AFA, AFB) HIGH. A Master Reset also
forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox
register HIGH. After a Master Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two clock cycles to begin normal
operation. A Master Reset must be performed on the FIFO
after power up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X4AV
undergoes a limited reset by taking its associated Partial
Reset (PRS1, PRS2) input LOW for at least four Port A clock
(CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously to
the clocks. A Partial Reset initializes the internal Read and
Write pointers and forces the Full/Input Ready flag (FFA/IRA,
FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA,
EFB/ORB) LOW, the Almost Empty flag (AEA, AEB) LOW, and
the Almost Full flag (AFA, AFB) HIGH. A Partial Reset also
forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox
register HIGH. After a Partial Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two clock cycles to begin normal
operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
A HIGH on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Big
Endian arrangement. When data is moving in the direction
from Port A to Port B, the most significant byte (word) of the
long-word written to Port A will be transferred to Port B first;
the least significant byte (word) of the long word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port B to Port A, the byte (word) written to Port
B first will be transferred to Port A as the most significant byte
(word) of the long-word; the byte (word) written to Port B last
will be transferred to Port A as the least significant byte (word)
of the long-word.
A LOW on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long word written to Port A will be transferred to Port B first;
the most significant byte (word) of the long-word written to Port
A will be transferred to Port B last. When data is moving in the
direction from Port B to Port A, the byte (word) written to Port
B first will be transferred to port A as the least significant byte
(word) of the long-word; the byte (word) written to Port B last
will be transferred to Port A as the most significant byte (word)
of the long-word.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard mode or First-Word Fall-Through (FWFT) mode.
Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY
Standard mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal Read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT
mode. This mode uses the Output Ready function (ORA,
ORB) to indicate whether or not there is valid data at the data
outputs (A0–35 or B0–35). It also uses the Input Ready function
(IRA, IRB) to indicate whether or not the FIFO memory has any
free space for writing. In the FWFT mode, the first word written
to an empty FIFO goes directly to data outputs, no Read
request necessary. Subsequent words must be accessed by
performing a formal Read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Big Endian/First Word Fall Through (BE/FWFT)
Programming the Almost Empty and Almost Full Flags
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B. (Note that when Port B is
configured for a long word size, the Big Endian function has
no application and the BE input is a “Don’t Care.”)
Four registers in the CY7C436X4AV are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial
using the Serial Data (SD) input (see Table 3). To load a FIFO’s
Document #: 38-06025 Rev. *C
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Almost Empty flag and Almost Full flag offset registers with
one of the three preset values listed in Table 3, the Serial
Program Mode (SPM) and at least one of the flag-select inputs
must be HIGH during the LOW-to-HIGH transition of its Master
Reset input (MRS1 and MRS2). For example, to load the
preset value of 64 into X1 and Y1, SPM, FS0, and FS1 must
be HIGH when FIFO1 reset (MRS1) returns HIGH. Flag-offset
registers associated with FIFO2 are loaded with one of the
preset values in the same way with Master Reset (MRS2).
When using one of the preset values for the flag offsets, the
FIFOs can be reset simultaneously or at different times.
To program the X1, X2, Y1, and Y2 registers in parallel from
Port A, perform a Master Reset on both FIFOs simultaneously
with SPM HIGH and FS0 and FS1 LOW during the LOW-toHIGH transition of MRS1 and MRS2. After this reset is
complete, the first four Writes to FIFO1 do not store data in
RAM but load the offset registers in the order Y1, X1, Y2, X2.
The Port A data inputs used by the offset registers are (A0–9),
(A0–11), or (A0–13), for the CY7C436X4AV, respectively. The
highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for
the registers range from 0 to 1023 for the CY7C43644AV; 0 to
4095 for the CY7C43664AV; 0 to 16383 for the
CY7C43684AV.[2] After all the offset registers are programmed
from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH
and both FIFOs begin normal operation.
To program the X1, X2, Y1, and Y2 registers serially, initiate a
Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN
HIGH during the LOW-to-HIGH transition of MRS1 and MRS2.
After this reset is complete, the X and Y register values are
loaded bit-wise through the FS0/SD input on each LOW-toHIGH transition of CLKA that the FS1/SEN input is LOW. Forty,
forty-eight, or fifty-six bit Writes are needed to complete the
programming for the CY7C436X4AV, respectively. The four
registers are written in the order Y1, X1, Y2, and, finally, X2.
The first-bit Write stores the most significant bit of the Y1
register and the last-bit Write stores the least significant bit of
the X2 register.
When the option to program the offset registers serially is
chosen, the Port A Full/Input Ready (FFA/IRA) flag remains
LOW until all register bits are written. FFA/IRA is set HIGH by
the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO1 operation. The Port B Full/Input ready
(FFB/IRB) flag also remains LOW throughout the serial
programming process, until all register bits are written. FFB/
IRB is set HIGH by the LOW-to-HIGH transition of CLKB after
the last bit is loaded to allow normal FIFO2 operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0–35 inputs on a LOW-toHIGH transition of CLKA when CSA is LOW, W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read
from FIFO2 to the A0–35 outputs by a LOW-to-HIGH transition
of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA
is LOW, and EFA/ORA is HIGH (see Table 4). FIFO Reads and
Document #: 38-06025 Rev. *C
Writes on Port A are independent of any concurrent Port B
operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read select (W/RB). The B0–35
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active outputs when CSB
is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0–35 inputs on a LOW-toHIGH transition of CLKB when CSB is LOW, W/RB is LOW,
ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is
read from FIFO1 to the B0–35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 5).
FIFO Reads and Writes on Port B are independent of any
concurrent Port A operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read selects are only for enabling
Write and Read operations and are not related to highimpedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port’s Chip Select and Write/Read
select may change states during the set-up and hold time
window of the cycle.
When operating the FIFO in FWFT mode and the Output
Ready flag is LOW, the next word written is automatically sent
to the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a Read is selected using the port’s Chip
Select, Write/Read select, Enable, and Mailbox select.
When operating the FIFO in CY Standard mode, data residing
in the FIFO’s memory array is clocked to the output register
only when a Read is selected using the port’s Chip Select,
Write/Read select, Enable, and Mailbox select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is done to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA
and CLKB operate asynchronously to one another. EFA/ORA,
AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/
ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB.
Table 6 and Table 7 show the relationship of each port flag to
FIFO1 and FIFO2.
Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These are dual-purpose flags. In the FWFT mode, the Output
Ready (ORA, ORB) function is selected. When the Output
Ready flag is HIGH, new data is present in the FIFO output
register. When the Output Ready flag is LOW, the previous
data word remains in the FIFO output register and any FIFO
reads are ignored.
In the CY Standard mode, the Empty Flag (EFA, EFB) function
is selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word remains in
the FIFO output register and any FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
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and CY Standard modes, the FIFO Read pointer is incremented each time a new word is clocked to its output register.
The state machine that controls an Output Ready flag monitors
a Write pointer and Read pointer comparator that indicates
when the FIFO SRAM status is empty, empty + 1, or empty + 2.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
Flag synchronizing clock. Therefore, an Empty Flag is LOW if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty Flag HIGH; only then will data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
Write if the clock transition occurs at time tSKEW1 or greater
after the Write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT mode, the Input Ready
(IRA and IRB) function is selected. In CY Standard mode, the
Full Flag (FFA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
any Writes to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
Write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a Write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, full – 1, or full – 2. From the time a word is read from a
FIFO, its previous memory location is ready to be written to in
a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less
than two cycles of the Full/Input Ready flag synchronizing
clock have elapsed since the next memory Write location has
been read. The second LOW-to-HIGH transition on the Full/
Input Ready flag synchronizing clock after the Read sets the
Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a Read if
the clock transition occurs at time tSKEW1 or greater after the
Read. Otherwise, the subsequent clock cycle will be the first
synchronization cycle.
Document #: 38-06025 Rev. *C
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a Write pointer and
Read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty + 1, or almost empty + 2.
The Almost Empty state is defined by the contents of register
X1 for AEB and register X2 for AEA. These registers are
loaded with preset values during a FIFO reset, programmed
from Port A, or programmed serially (see Almost Empty flag
and Almost Full flag offset programming above). An Almost
Empty flag is LOW when its FIFO contains X or less words and
is HIGH when its FIFO contains (X + 2) or more words.[2]
The Almost Empty flag is set HIGH by the first LOW-to-HIGH
transition of its synchronizing clock after two FIFO Writes that
fills memory to the (X + 2) level. A LOW-to-HIGH transition of
an Almost Empty flag synchronizing clock begins the first
synchronization cycle if it occurs at time tSKEW2 or greater after
the Write that fills the FIFO to (X + 2) words. Otherwise, the
subsequent synchronizing clock cycle will be the first synchronization cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a Write pointer and Read pointer
comparator that indicates when the FIFO SRAM status is
almost full, almost full – 1, or almost full – 2. The Almost Full
state is defined by the contents of register Y1 for AFA and
register Y2 for AFB. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Full flag is LOW
when the number of words in its FIFO is greater than or equal
to (1024 – Y), (4096 – Y), or (16384 – Y) for the
CY7C436X4AV respectively. An Almost Full flag is HIGH when
the number of words in its FIFO is less than or equal to [1024
– (Y + 2)], [4096 – (Y + 2)], or [16384 – (Y + 2)], for the
CY7C436X4AV respectively.[2]
The Almost Full flag is set HIGH by the first LOW-to-HIGH
transition of its synchronizing clock after two FIFO reads that
reduces the number of words in memory to [1024/4096/16384
– (Y + 2)]. A LOW-to-HIGH transition of an Almost Full flag
synchronizing clock begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the Read that reduces
the number of words in memory to [1024/4096/16384 –
(Y + 2)]. Otherwise, the subsequent synchronizing clock cycle
will be the first synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0<35 data to the
Mail1 Register when a Port A Write is selected by CSA LOW,
W/RA HIGH, ENA HIGH, and MBA HIGH. If the selected Port
A bus size is also 36 bits, then the usable width of the Mail1
Register employs data lines A0<35. If the selected Port A bus
size is 18 bits, then the usable width of the Mail1 Register
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employs data lines A0<17. (In this case, A18<35 are “Don’t
Care” inputs.) If the selected Port A bus size is 9 bits, then the
usable width of the Mail1 Register employs data lines A0<8. (In
this case, A9<35 are “Don’t Care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0<35 data to the
Mail2 Register when a Port B Write is selected by CSB LOW,
W/RB LOW, ENB HIGH and MBB HIGH. If the selected Port B
bus size is also 36 bits, then the usable width of the Mail2
Register employs data lines B0–35. If the selected Port B bus
size is 18 bits, then the usable width of the Mail2 Register
employs data lines B0–17. (In this case, B18–35 are “Don’t Care”
inputs.) If the selected Port B bus size is 9 bits, then the usable
width of the Mail2 Register employs data lines B0<8. (In this
case, B9<35 are “Don’t Care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Any Attempt to write to a mail register
are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-toHIGH transition on CLKB when a Port B Read is selected by
CSB LOW, W/RB HIGH, ENB HIGH AND MBB HIGH. For a
36-bit bus size, 36 bits of mailbox data are placed on B0–35.
For an 18-bit bus size, 18 bits of mailbox data are placed on
B0–17. (In this case, B18–35 are indeterminate.) For a 9-bit bus
size, 9 bits of mailbox data are placed on B0–8. (In this case,
B9–35 are indeterminate.)
The Mail2 register Flag (MBF2) is set HIGH by a LOW-toHIGH transition on CLKA when a Port A Read is selected by
CSA LOW, W/RA LOW, ENA HIGH, MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0–17. (In this case, A18–35 are indeterminate.) For
a 9-bit bus size, 9 bits of mailbox data are placed on A0–8. (In
this case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be configured in a 36-bit long-word, 18-bit
word, or 9-bit byte format for data read from FIFO1 or written
to FIFO2. The levels applied to the Port B Bus Size Select
(SIZE) and the Bus Match Select (BM) determine the Port B
bus size. These levels should be static throughout FIFO
operation. Both bus size selections are implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either byteor word-size. They are referred to as Big Endian (most significant byte first) and Little Endian (least significant byte first).
The level applied to the Big Endian Select (BE) input during
the LOW-to-HIGH transition of MRS1 and MRS2 selects the
Document #: 38-06025 Rev. *C
endian method that will be active during FIFO operation. BE is
a “Don’t Care” input when the bus size selected for Port B is
long word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Bus-Matching operations are not available when transferring
data via mailbox registers. Furthermore, both the word- and
byte-size bus selections limit the width of the data bus that can
be used for mail register operations. In this case, only those
byte lanes belonging to the selected word- or byte-size bus
can carry mailbox data. The remaining data outputs will be
indeterminate. The remaining data inputs will be don’t care
inputs. For example, when a word-size bus is selected, then
mailbox data can be transmitted only between A0–17 and
B0–17. When a byte-size bus is selected, then mailbox data
can be transmitted only between A0–8 and B0–8.
Bus-Matching FIFO1 Reads
Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the entire longword immediately shifts to the FIFO1 output register. If byte or
word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO1 output
register, with the rest of the long-word stored in auxiliary
registers. In this case, subsequent FIFO1 reads output the rest
of the long word to the FIFO1 output register.
When reading data from FIFO1 in the byte or word format, the
unused B0–35 outputs are indeterminate.
Bus-Matching FIFO2 Writes
Data is written to the FIFO2 RAM in 36-bit long-word increments. Data written to FIFO2 with a byte or word bus size
stores the initial bytes or words in auxiliary registers. The
CLKB rising edge that writes the fourth byte or the second
word of long-word to FIFO2 also stores the entire long word in
FIFO2 RAM.
Reading from FIFO2 on Port A can only be in 36-bit format
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
function applies to CY Standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth minus 2/4/8 words between the reset of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT1, (RT2) resets the internal Read pointer to the first
physical location of the FIFO. CLKA and CLKB may be free
running but ENB (ENA) must be disabled during and tRTR after
the retransmit pulse. With every valid Read cycle after retransmit, previously accessed data is read and the Read pointer is
incremented until it is equal to the Write pointer. Flags are
governed by the relative locations of the Read and Write pointers and are updated during a retransmit cycle. Data written to
the FIFO after activation of RT1, (RT2) are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
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.
Table 2.
BYTE ORDER ON PORT A:
BE
BM
SIZE
X
L
X
A27–35
A18–26
A9–17
A
B
C
B27–35
B18–26
B9–17
A
B
C
A0–8
D
Write to FIFO
B0–8
D
Read from FIFO
(a) LONG-WORD SIZE
B27–35
BE
BM
SIZE
H
H
L
B18–26
B9–17
B0–8
B
A
B27–35
B18–26
B9–17
1st: Read from FIFO
B0–8
D
C
2nd: Read from FIFO
(b) WORD SIZE – BIG ENDIAN
B27–35
BE
BM
SIZE
L
H
L
B18–26
B9–17
B0–8
D
C
B27–35
B18–26
B9–17
B0–8
A
B
1st: Read from FIFO
2nd: Read from FIFO
(c) WORD SIZE – LITTLE ENDIAN
B27–35
BE
BM
SIZE
H
H
H
B18–26
B9–17
B0–8
A
B27–35
B18–26
B9–17
B0–8
B
B27–35
B18–26
B9–17
B18–26
B9–17
2nd: Read from FIFO
B0–8
C
B27–35
1st: Read from FIFO
3rd: Read from FIFO
B0–8
D
4th: Read from FIFO
(d) BYTE SIZE – BIG ENDIAN
B27–35
BE
BM
SIZE
L
H
H
B18–26
B9–17
B0–8
D
B27–35
B18–26
B9–17
B0–8
C
B27–35
B18–26
B9–17
B18–26
B9–17
2nd: Read from FIFO
B0–8
B
B27–35
1st: Read from FIFO
3rd: Read from FIFO
B0–8
A
4th: Read from FIFO
(e) BYTE SIZE – LITTLE ENDIAN
Document #: 38-06025 Rev. *C
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Table 3. Flag Programming
SPM
FS1/
SEN
FS0/ SD
H
H
H
H
H
H
H
H
H
L
H
L
H
L
L
L
L
MRS1
MRS2
X1 and Y1 Registers[3]
X2 andY2 Registers[4]
H
↑
X
64
X
H
X
↑
X
64
L
↑
X
16
X
L
X
↑
X
16
H
↑
X
8
X
H
X
↑
X
8
L
L
↑
↑
Parallel programming via Port A
Parallel programming via Port A
H
L
↑
↑
Serial programming via SD
Serial programming via SD
H
H
↑
↑
Reserved
Reserved
L
H
↑
↑
Reserved
Reserved
L
L
↑
↑
Reserved
Reserved
..
Table 4. Port A Enable Function
CSA
W/RA
ENA
MBA
CLKA
A0–35
Port Function
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
↑
In high-impedance state
FIFO1 Write
L
H
H
H
↑
In high-impedance state
Mail1 Write
L
L
L
L
X
Active, FIFO2 output register
None
L
L
H
L
↑
Active, FIFO2 output register
FIFO2 Read
L
L
L
H
X
Active, Mail2 register
None
L
L
H
H
↑
Active, Mail2 register
Mail2 Read (set MBF2 HIGH)
Table 5. Port B Enable Function
CSB
W/RB
ENB
MBB
CLKB
B0–35
Port Function
H
X
X
X
X
In high-impedance state
None
L
L
L
X
X
In high-impedance state
None
L
L
H
L
↑
In high-impedance state
FIFO2 Write
L
L
H
H
↑
In high-impedance state
Mail2 Write
L
H
L
L
X
Active, FIFO1 output register
None
L
H
H
L
↑
Active, FIFO1 output register
FIFO1 Read
L
H
L
H
X
Active, Mail1 register
None
L
H
H
H
↑
Active, Mail1 register
Mail1 Read (set MBF1 HIGH)
Notes:
3. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
4. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
Document #: 38-06025 Rev. *C
Page 12 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Table 6. FIFO1 Flag Operation (CY Standard and FWFT modes)
Number of Words in FIFO Memory[2, 5, 6, 7, 8]
CY7C43644AV
CY7C43664AV
Synchronized to CLKB
Synchronized to CLKA
CY7C43684AV
EFB/ORB
AEB
AFA
FFA/IRA
0
L
L
H
H
1 to X1
H
L
H
H
(X1 + 1) to [1024 – (X1 + 1) to [4096 – (X1 + 1) to [16384 –
(Y1 + 1)]
(Y1 + 1)]
(Y1 + 1)]
H
H
H
H
(1024 – Y1) to 1023 (4096 – Y1) to 4095
(16384 – Y1) to
16383
H
H
L
H
16384
H
H
L
L
0
0
1 to X1
1 to X1
1024
4096
Table 7. FIFO2 Flag Operation (CY Standard and FWFT modes)
Number of Words in FIFO Memory[2, 6, 7, 9, 10]
CY7C43644AV
CY7C43664AV
1 to X2
Synchronized to CLKB
CY7C43684AV
EFA/ORA
AEA
AFB
FFB/IRB
0
0
L
L
H
H
1 to X2
1 to X2
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
0
(X2 + 1) to [1024 –
(Y2 + 1)]
Synchronized to CLKA
(X2 + 1) to [4096 – (X2 + 1) to [16384 –
(Y2 + 1)]
(Y2 + 1)]
(1024 – Y2) to 1023 (4096 – Y2) to 4095
(16384 – Y2) to
16383
1024
4096
16384
Table 8. Data Size for Long-Word Writes to FIFO2
Size Mode[11]
Data Written to FIFO2
Data Read From FIFO2
BM
SIZE
BE
B27–35
B18–26
B9–17
B0–8
A27–35
A18–26
A9–17
A0–8
L
X
X
A
B
C
D
A
B
C
D
Table 9. Data Size for Word Writes to FIFO2
Size Mode[11]
Write No.
BM
SIZE
BE
H
L
H
H
L
L
Data Written to FIFO2
Data Read From FIFO2
B9–17
B0–8
A27–35
A18–26
A9–17
A0–8
1
A
B
A
B
C
D
2
C
D
1
C
D
A
B
C
D
2
A
B
Notes:
5. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset
or port A programming.
6. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
7. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to
the output register (no Read operation necessary), it is not included in the FIFO memory count.
8. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode.
9. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
10. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.quested to the output register (no
Read operation necessary), it is not included in the FIFO memory count.
11. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Document #: 38-06025 Rev. *C
Page 13 of 37
CY7C43644AV
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CY7C43684AV
Table 10. Data Size for Byte Writes to FIFO2
Size Mode[11]
Write No.
BM
SIZE
BE
H
H
H
H
H
Data Written to FIFO2
1
L
Data Read From FIFO2
B0–8
A27–35
A18–26
A9–17
A0–8
A
A
B
C
D
A
B
C
D
2
B
3
C
4
D
1
D
2
C
3
B
4
A
Table 11. Data Size for FIFO Long-Word Reads from FIFO1
Size Mode[11]
Data Written to FIFO1
Data Read From FIFO1
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
B27–35
B18–26
B9–17
B0–8
L
X
X
A
B
C
D
A
B
C
D
Table 12. Data Size for Word Reads from FIFO1
Size Mode[11]
Data Written to FIFO1
Read No.
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
H
L
H
A
B
C
D
H
L
L
A
B
C
D
Data Read From FIFO1
B9–17
B0–8
1
A
B
2
C
D
1
C
D
2
A
B
Table 13. Data Size for Byte Reads from FIFO1
Size Mode[11]
Data Written to FIFO1
Read No.
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
H
H
H
A
B
C
D
H
H
L
Document #: 38-06025 Rev. *C
A
B
C
D
Data Read From FIFO1
B0–8
1
A
2
B
3
C
4
D
1
D
2
C
3
B
4
A
Page 14 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Maximum Ratings[12, 14]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ..................................< 65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied..............................................< 55°C to +125°C
Supply Voltage to Ground Potential .............. < 0.5V to +7.0V
Range
Ambient
Temperature
VCC[15]
DC Voltage Applied to Outputs
in High Z State[13]....................................< 0.5V to VCC+0.5V
Commercial
0°C to +70°C
3.3V ± 10%
<40°C to +85°C
3.3V ± 10%
Industrial
DC Input Voltage[13] ................................< 0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
CY7C43644/64/84AV
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = 3.0V,
IOH = <2.0 mA
VOL
Output LOW Voltage
VCC = 3.0V,
IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Min.
Max.
Unit
2.4
V
0.5
V
2.0
VCC
V
<0.5
0.8
V
IIX
Input Leakage Current
VCC = Max.
<10
+10
µA
IOZL
IOZH
Output OFF, High Z Current
VSS < VO< VCC
<10
+10
µA
ICC1[16]
Active Power Supply Current
Commercial
60
mA
Industrial
60
mA
Commercial
10
mA
Industrial
10
mA
ISB[17]
Average Standby Current
Capacitance
[18]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
4
pF
8
pF
Note:
12. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
13. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
14. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
15. Operating VCC Range for –7 speed is 3.3V ± 5%.
16. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz.
Outputs are unloaded.
17. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
18. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06025 Rev. *C
Page 15 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Table 14.
AC Test Loads and Waveforms (–10 and –15)
R1 = 330Ω
ALL INPUT PULSES
3.3V
OUTPUT
3.0V
[19]
CL= 30 pF
R2 = 680Ω
90%
10%
90%
10%
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
≤ 3 ns
AC Test Loads and Waveforms (–7)
VCC/2
50Ω
ALL INPUT PULSES
3.0V
GND
I/O
90%
10%
90%
10%
≤ 3 ns
Z0 = 50Ω
≤ 3 ns
Switching Characteristics Over the Operating Range
Parameter
Description
CY7C43644/
64/84AV
–7
CY7C43644/
64/84AV
–10
CY7C43644/
64/84AV
–15
Min.
Min.
Min.
Max.
133
Max.
100
Max.
Unit
67
MHz
fS
Clock Frequency, CLKA or CLKB
tCLK
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
3.5
4
6
ns
tDS
Set-Up Time, A0–35 before CLKA↑ and B0–35 before
CLKB↑
3
4
5
ns
tENS
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑
3
4
5
ns
tRSTS
Set-Up Time, MRS1, MRS2, PRS1, PRS2, RT1 or
RT2 LOW before CLKA↑ or CLKB↑[20]
2.5
4
5
ns
tFSS
Set-Up Time, FS0 and FS1 before MRS1 and MRS2
HIGH
5
7
7.5
ns
tBES
Set-Up Time, BE/FWFT before MRS1 and MRS2
HIGH
5
7
7.5
ns
tSPMS
Set-Up Time, SPM before MRS1 and MRS2 HIGH
5
7
7.5
ns
tSDS
Set-Up Time, FS0/SD before CLKA↑
3
4
5
ns
tSENS
Set-Up Time, FS1/SEN before CLKA↑
3
4
5
ns
tFWS
Set-Up Time, BE/FWFT before CLKA↑
0
0
0
ns
tDH
Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑
0
0
0
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑
0
0
0
ns
Notes:
19. CL = 5 pF for tDIS.
20. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Document #: 38-06025 Rev. *C
Page 16 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Characteristics Over the Operating Range (continued)
Parameter
CY7C43644/
64/84AV
–7
CY7C43644/
64/84AV
–10
CY7C43644/
64/84AV
–15
Min.
Min.
Description
Min.
tRSTH
Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2
LOW after CLKA↑ or CLKB↑[20]
1
Max.
2
2
ns
tFSH
Hold Time, FS0 and FS1 after MRS1 and MRS2
HIGH
1
1
2
ns
tBEH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
1
1
2
ns
tSPMH
Hold Time, SPM after MRS1 and MRS2 HIGH
1
1
2
ns
tSDH
Hold Time, FS0/SD after CLKA↑
0
0
0
ns
tSENH
Hold Time, FS1/SEN after CLKA↑
0
0
0
ns
tSPH
Hold Time, FS1/SEN HIGH after MRS1 and MRS2
HIGH
1
1
2
ns
tSKEW1[21]
Skew Time between CLKA↑ and CLKB↑ for EFA/
ORA, EFB/ORB, FFA/IRA, and FFB/IRB
5
5
7.5
ns
tSKEW2[21]
Skew Time between CLKA↑ and CLKB↑ for AEA,
AEB, AFA, AFB
7
8
12
ns
tA
Access Time, CLKA↑ to A0–35 and CLKB↑ to B0–35
1
6
1
8
3
10
ns
tWFF
Propagation Delay Time, CLKA↑ to FFA/IRA and
CLKB↑ to FFB/IRB
1
6
1
8
2
10
ns
tREF
Propagation Delay Time, CLKA↑ to EFA/ORA and
CLKB↑ to EFB/ORB
1
6
1
8
2
10
ns
tPAE
Propagation Delay Time, CLKA↑ to AEA and
CLKB↑ to AEB
1
6
1
8
1
10
ns
tPAF
Propagation Delay Time, CLKA↑ to AFA and CLKB↑
to AFB
1
6
1
8
1
10
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
0
6
0
8
0
12
ns
tPMR
Propagation Delay Time, CLKA↑ to B0–35[22] and
CLKB↑ to A0–35[23]
1
7
2
11
3
12
ns
tMDV
Propagation Delay Time, MBA to A0–35 Valid and
MBB to B0–35 Valid
1
6
2
9
3
11
ns
tRSF
Propagation Delay Time, MRS1 or PRS1 LOW to
AEB LOW, AFA HIGH, FFA / IRA LOW, EFB /ORB
LOW and MBF1 HIGH and MRS2 or PRS2 LOW to
AEA LOW, AFB HIGH, FFB / IRB LOW, EFA /ORA
LOW and MBF2 HIGH
1
6
1
10
1
15
ns
tEN
Enable Time, CSA or W/RA LOW to A0–35 Active
and CSB LOW and W/RB HIGH to B0–35 Active
1
6
2
8
2
10
ns
tDIS[19]
Disable Time, CSA or W/RA HIGH to A0–35 at High
Impedance and CSB HIGH or W/RB LOW to B0–35
at High Impedance
1
5
1
6
1
8
ns
tRTR
Retransmit Recovery Time
90
90
Max.
90
Max.
Unit
ns
Notes:
21. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
22. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
23. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH
Document #: 38-06025 Rev. *C
Page 17 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight
[24, 25]
CLKA
CLKB
tRSTS
tRSTH
MRS1
tBES
BE/FWFT
tBEH
BE
tSPMS
tFWS
FWFT
tSPMH
SPM
tFSS
FS1/SEN,
FS0/SD
tFSH
tRSF
tWFF
FFA/IRA
tRSF
EFB/ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
FIFO1 Partial Reset (CY Standard and FWFT Modes)[26, 27]
CLKA
CLKB
tRSTH
tRSTS
PRS1
tRSF
tWFF
FFA/IRA
tRSF
EFB/ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
Notes:
24. Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
25. PRS1 must be HIGH during Master Reset.
Document #: 38-06025 Rev. *C
Page 18 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes) [28]
CLKA
MRS1, MRS2
tFSS
tFSH
tFSS
tFSH
SPM
FS1/SEN,
FS0/SD
tWFF
FFA/IRA
tENS
tENH
tSKEW1[29]
ENA
tDS
tDH
A0 − 35
AFA Offset (Y1) AEB Offset (X1) AFB Offset (Y2) AEA Offset (X2) First Word to FIFO1
CLKB
tWFF
FFB/IRB
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes) [30, 31]
CLKA
MRS1, MRS2
tFS tFS
SPM
tWFF
tSKEW1
FFA/IRA
tFSS
tSPH
tSENS
tSENH
tSENStSEN
FS1/SEN
tFSS tFSH
tSDS
tSDH
FS0/SD [31]
AFA Offset (Y1) MSB
tSDS
tSDH
AEA Offset (X2) LSB
CLKB
tWFF
FFB/IRB
Notes:
26. Partial Reset is performed in the same manner for FIFO2.
27. MRS1 must be HIGH during Partial Reset.
28. CSAU = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in parallel
when FFA/IRA is HIGH.
29. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.
Document #: 38-06025 Rev. *C
Page 19 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tCLK
tCLKL
tCLKH
CLKA
FFA/IRA
HIGH
tENS tENH
CSA
tENS tENH
W/RA
[32]
tENS tENH
MBA
tENS tENH
tENS tENH
tENS tENH
ENA
tDS
A0–35
tDH
W2[33]
W1[33]
Port B Long-Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tCLKH
tCLK
tCLKL
CLKB
FFB/IRB
HIGH
tENS tENH
CSB
[34]
tENS tENH
W/RB
tENS tENH
MBB
tENS tENH
tENS tENH
tENS tENH
ENB
tDS
B0−35
tDH
W1[35]
W2[35]
Notes:
30. It is not necessary to program offset register bits on consecutive clock cycles. Attempts to write into FIFO memory are ignored until FFA/IRA is set HIGH.
31. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
32. If W/RA switches from Read to Write before the assertion of CSA, tENS = tDIS + tENS.
33. Written to FIFO1.
Document #: 38-06025 Rev. *C
Page 20 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
Port B Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKB
FFB/IRB
HIGH
tENS
tENH
CSB
tENS
[34]
W/RB
tENS tENH
MBB
tENS tENH
tENS
tENH
ENB
tDS
tDH
B0–17
Port B Byte Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKB
FFB/IRB
HIGH
tENH
tENS
CSB
[34]
tENS
W/RB
tENS tENH
tENH
MBB
tENS tENH
tENS
tENH
ENB
tDS tDH
B0–8
Note:
34. If W/RB switches from Read to Write before the assertion of CSB, tENS = tDIS + tENS.
35. Written to FIFO2.
Document #: 38-06025 Rev. *C
Page 21 of 37
CY7C43644AV
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CY7C43684AV
Switching Waveforms (continued)
Port B Long-Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
EFB/ORB
CSB
[34]
W/RB
MBB
tEN
tENH
tEN
tEN
tENH
tEN
ENB
tEN
B0–35
(Standard Mode)
OR
B0–35
tMDV
tA
Previous Data
tEN
tMDV
W1[36]
No Operation
tDIS
W2[36]
tDIS
tA
tA
W1[36]
(FWFT Mode)
tA
W3[36]
W2[36]
Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[37]
CLKB
EFB/ORB
CSB
[34]
W/RB
MBB
tENS tENH
ENB
B0–17
tEN
tMDV
(Standard Mode)
OR
B0–17
tEN
(FWFT Mode)
tMDV
tA
tA
Previous
tA
Read 1
Read 1
No Operation
Read 2
tA
Read 2
tDIS
tDIS
Read 3
Note:
36. Read From FIFO1.
Document #: 38-06025 Rev. *C
Page 22 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes) [38]
CLKB
EFB/ORB
HIGH
CSB
[34]
W/RB
MBB
tEN tENH
ENB
tEN
B0–8
(Standard Mode)
OR
B0–8
tEN
tA No Operation tDIS
tMDV
tA
tA
tA
tMDV
Previous
tA
Read 1
tA
Read 2
tA
Read 3
tA
Read 1
Read 2
Read 3
Read 4
(FWFT Mode)
Read 4
tDIS
Read 5
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tCLKH
tCLK
tCLKL
CLKA
EFA/ORA
HIGH
CSA
[32]
W/RA
MBA
tENS tENH
tENS tENH
tENS
tENH
ENA
A0−35
(Standard Mode)
OR
tEN
tMDV
tEN
tMDV
tA
Previous Data
A0−35
(FWFT Mode)
tA
tDIS
tA
W2[39]
tDIS
W2[39
W1[39]
tA
W1[39]
No Operation
W3[39]
Notes:
37. Unused word B18–35 contains all zeroes for word-size reads.
38. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
39. Read From FIFO2.
Document #: 38-06025 Rev. *C
Page 23 of 37
CY7C43644AV
CY7C43664AV
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Switching Waveforms (continued)
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)[40]
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
W/RA
HIGH
tEN tENH
MBA
tEN tENH
ENA
FFA/IRA
HIGH
tDS tDH
A0–35
W1
tSKEW1[41]
CLKB
tCLKH
tCLKL
tCLK
EFB/ORB
CSB
W/RB
MBB
tREF
tREF
FIFO1 Empty
LOW
HIGH
LOW
tEN tENH
ENB
tA
B0–35
Old Data in FIFO1 Output Register
W1
Notes:
40. If Port B size is word or byte, EFB is set LOW by the last word or byte Read from FIFO1, respectively.
41. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Document #: 38-06025 Rev. *C
Page 24 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
EFB Flag Timing and First Data Read Fall Through when FIFO1 is
Empty (CY Standard Mode)
[40]
tCLK
tCLKH
tCLKL
CLKA
CSA
W/RA
LOW
HIGH
tEN tENH
MBA
tENStENH
ENA
FFA/IRA
HIGH
tDS tDH
A0–35
W1
tSKEW1[42]
CLKB
tCLKH
tCLKL
tCLK
EFB/ORB
CSB
W/RB
MBB
tREF
tREF
FIFO1 Empty
LOW
HIGH
LOW
tEN tENH
ENB
tA
B0–35
W1
Note:
42. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06025 Rev. *C
Page 25 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
(FWFT Mode) [43]
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
W/RB
LOW
tEN tENH
MBB
tENStENH
ENB
FFB/IRB
HIGH
tDS tDH
B0–35
W1
tSKEW1[44]
CLKA
tCLKH
tCLKL
tCLK
EFA/ORA
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tREF
tREF
tENStENH
ENA
tA
A0–35
Old Data in FIFO2 Output Register
W1
Notes:
43. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
44. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load
of the first word to the output register may occur one CLKA cycle later than shown.
Document #: 38-06025 Rev. *C
Page 26 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode) [43]
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
W/RB
LOW
tENStENH
MBB
tENStENH
ENB
FFB/IRB
HIGH
tDS tDH
B0–35
W1
t
tSKEW1[45] CLKH
tCLKL
CLKA
tCLK
EFA/ORA
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tREF
tREF
tEN tENH
ENA
tA
A0–35
W1
Note:
45. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06025 Rev. *C
Page 27 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode) [43]
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
W/RB
HIGH
MBB
LOW
tENStENH
ENB
EFB/ORB
HIGH
tA
B0–35
Previous Word in
Next Word From FIFO1
FIFO1 Output Register
tCLKH tCLKL
[46]
tSKEW1
CLKA
tCLK
FFA/IRA
FIFO1 Full
CSA
LOW
W/RA
HIGH
tWFF
tWFF
tENStENH
MBA
tEN tENH
ENA
tDS tDH
A0–35
To FIFO1
Note:
46. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Document #: 38-06025 Rev. *C
Page 28 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode) [43]
tCLK
tCLKH
tCLK
CLKB
CSB
LOW
W/RB
HIGH
MBB
LOW
tEN tENH
ENB
EFB/ORB
HIGH
tA
B0–35
CLKA
Previous Word in FIFO1
Next Word From FIFO1
Output Register
tCLKH tCLKL
[47]
tSKEW1
tCLK
FFA/IRA
FIFO1 Full
CSA
LOW
W/RA
HIGH
tWFF
tWFF
tENS tENH
MBA
tENS tENH
ENA
tDS tDH
A0−35
Note:
47. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06025 Rev. *C
Page 29 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode) [48]
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENS tENH
ENA
EFA/ORA
HIGH
tA
A0–35
CLKB
Next Word From FIFO2
Previous Word in FIFO2
tCLKH tCLK
Output Register
tSKEW1[49]
tCLK
FFB/IRB
FIFO2 Full
CSB
LOW
W/RB
LOW
tWFF
tWFF
tENS tENH
MBB
tEN tENH
ENB
tDS tDH
B0–35
To FIFO2
Notes:
48. If Port B size is word or byte, IRB is set LOW by the last word or byte Write of the long-word, respectively.
49. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06025 Rev. *C
Page 30 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode) [50]
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENStENH
ENA
EFA/ORA
HIGH
tA
A0–35
CLKB
Next Word From FIFO2
Previous Word in FIFO2
Output Register
tCLKH tCLKL
[51]
tSKEW1
tCLK
FFB/IRB
FIFO2 Full
CSB
LOW
W/RB
LOW
tWFF
tWFF
tENS tENH
MBB
tENS tENH
ENB
tDS tDH
B0–35
To FIFO2
Notes:
50. If Port B size is word or byte, FFB is set LOW by the last word or byte Write of the long-word, respectively.
51. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06025 Rev. *C
Page 31 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
Timing for AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes) [52, 53]
CLKA
tENS
tENH
tENS
tENH
X1 Words in FIFO
ENA
tSKEW2[54]
CLKB
tPAE
AEB
X1 Word in FIFO1
(X1 + 1) Words in
FIFO1
tPAE
(X1 + 2)Words in
FIFO1
tENH tENS
(X1 + 2) Words in
FIFO1
tENS
tENH
ENB
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes) [55, 56]
CLKB
tENS
tENH
tENS
tENH
X2 Words in FIFO
ENB
tSKEW2[57]
CLKA
tPAE
AEA
X2 Word in FIFO2
(X2 + 1) Words in
FIFO2
tPAE
(X2 + 2) Words in
FIFO2
tENS
(X2 + 2) Words in FIFO2
tENH tENS
tENH
ENA
Notes:
52. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
Read from the FIFO.
53. If Port B size is word or byte, AEB is set LOW by the last word or byte Read from FIFO1, respectively.
54. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
55. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
Read from the FIFO.
56. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long-word, respectively.
57. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
Document #: 38-06025 Rev. *C
Page 32 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
[2, 56, 58, 59]
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
tSKEW2[60]
CLKA
tENS
tENH
ENA
tPAF
AFA
[D – (Y1 + 1)] Words in FIFO1
tPAF
(D – Y1)Words in FIFO1
CLKB
tENS
tENH
tENS
[D – (Y1 + 2)] Words in
FIFO1
tENH
ENB
Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)[2, 55, 59, 61]
tSKEW2[62]
CLKB
tENS
tENH
ENB
tPAF
AFB
[D – (Y2 + 1)] Words in FIFO2
tPAF
[D – (Y2 + 2)] words in
FIFO2
(D – Y2) Words in
FIFO2
CLKA
tENS
tENH
tENS
tENH
ENA
Notes:
58. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
Read from the FIFO.
59. D = Maximum FIFO Depth = 1K for the CY7C43644AV, 4K for the CY7C43664AV, and 16K for the CY7C43684AV.
60. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
61. If Port B size is word or byte, AFB is set LOW by the last word or byte Write of the long-word, respectively.
62. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
Document #: 38-06025 Rev. *C
Page 33 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)[63]
CLKA
tENS
tENH
CSA
W/RA
tENS
tENH
tENS
tENH
tENS
tENH
tDS
tDH
[32]
MBA
ENA
A0–35
W1
CLKB
tPMF
tPMF
MBF1
CSB
W/RB
[34]
MBB
tENS
tENH
ENB
tEN
B0-35
tMDV
FIFO1 Output
Register
tPMR
tDIS
W1 (Remains valid in Mail1 Register after Read)
Note:
63. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “Don’t Care” inputs). In this first case B0–17 will have valid
data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “Don’t Care” inputs). In
this second case, B0–8 will have valid data (B9–35 will be indeterminate).
Document #: 38-06025 Rev. *C
Page 34 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Switching Waveforms (continued)
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) [64]
CLKB
tENS
tENH
tENS
tENH
CSB
[34]
W/RB
tENS tENH
MBB
tENS tENH
ENB
tDS
B0–35
tDH
W1
CLKA
tPMF
tPMF
MBF2
CSA
W/RA
[32]
MBA
tENS
tENH
ENA
tMDV
tEN
A0−35
FIFO1 Retransmit Timing
CLKA
FIFO2 Output
Register
tDIS
tPMR
W1 (Remains valid in Mail2 Register after Read)
[65, 66, 67, 68,69]
CLKB
tRSTS
RT1
tRSTH
t RTR
ENB
EFB/FFA
Notes:
64. If Port B is configured for word size, data can be written to the Mail2 register using B0–17 (B18–35 are “Don’t Care” inputs). In this first case A0–17 will have valid
data (A18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are “Don’t Care” inputs). In
this second case, A0–8 will have valid data (A9–35 will be indeterminate).
65. Retransmit is performed in the same manner for FIFO2.
66. Clocks are free running in this case. CY standard mode only. Write operation should be prohibited one Write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e, when RT1 is LOW and tRTR after the RT1 rising edge.
67. The Empty and Full flags may change state during Retransmit as a result of the offset of the Read and Write pointers, but the Empty and Full flags will be valid
at tRTR.
68. For the AEA, AEB, AFA,and AFB flags, two clock cycle are necessary after tRTR to update these flags.
69. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
the Retransmit setup.
Document #: 38-06025 Rev. *C
Page 35 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Ordering Information
3.3V 1K ×36 ×2 Bidirectional Synchronous FIFO with Bus Matching
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
7
CY7C43644AV–7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43644AV–10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43644AV–15AC
A128
128-lead Thin Quad Flat Package
Commercial
3.3V 4K ×36 ×2 Bidirectional Synchronous FIFO with Bus Matching
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
7
CY7C43664AV–7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43664AV–10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43664AV–15AC
A128
128-lead Thin Quad Flat Package
Commercial
3.3V 16K ×36 ×2 Bidirectional Synchronous FIFO with Bus Matching
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
7
CY7C43684AV–7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43684AV–10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43684AV–15AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43684AV–10AI
A128
128-lead Thin Quad Flat Package
Industrial
Package Diagram
128-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06025 Rev. *C
Page 36 of 37
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C43644AV
CY7C43664AV
CY7C43684AV
Document Title: CY7C43644AV/CY7C43664AV/CY7C43684AV 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
with Bus Matching
Document Number: 38-06025
REV.
ECN NO.
Issue Date
Orig. of
Change
**
107506
05/24/01
KTM
*A
109943
02/06/02
FSG
Preliminary to final
*B
117209
08/22/02
OOR
Added footnote to retransmit timing, and added note to retransmit section
*C
122277
12/26/02
RBI
Document #: 38-06025 Rev. *C
Description of Change
Change from Spec #: 38-00777 to 38-06025
Power up requirements added to Maximum Ratings Information
Page 37 of 37