CY7C281A 1K x 8 PROM Features packages respectively. The CY7C281A is also available in a 28-pin leadless chip carrier. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. • CMOS for optimum speed/power • High speed — 25 ns (Commercial) • Low power • • • • • • — 495 mW (Commercial) EPROM technology 100% programmable Slim 300-mil or standard 600-mil DIP or 28-pin LCC 5V ±10% VCC, commercial and military TTL-compatible I/O Direct replacement for bipolar PROMs Capable of withstanding >2001V static discharge Functional Description The CY7C281A is a high-performance 1024-word by 8-bit CMOS PROMs. It is packaged in 300-mil and 600-mil-wide The CY7C281A is a plug-in replacements for bipolar devices and offer the advantages of lower power, superior performance, and programming yield. The EPROM cell requires only 12.5V for the super voltage, and low current requirements allow for gang programming. The EPROM cells allow each memory location to be tested 100% because each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming, the product will meet DC and AC specification limits. Reading is accomplished by placing an active LOW signal on CS1 and CS2, and active HIGH signals on CS3 and CS4. The contents of the memory location addressed by the address lines (A0−A9) will become available on the output lines (O0−O7). LogicBlockDiagram Pin Configurations A8 A7 A6 O6 ROW DECODER PROGRAMMABLE ARRAY MULTIPLEXER A5 A4 O5 A3 A2 A1 A0 DIP Top View O7 A9 O4 COLUMN DECODER O3 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND O0 CS1 CS2 Cypress Semiconductor Corporation Document #: 38-04003 Rev. *C 15 14 13 A5 A6 A7 NC VCC A8 A9 A4 A3 A2 A1 A0 NC O0 4 3 2 1 28 27 26 25 5 24 6 23 7 7C281A 22 8 21 9 20 10 19 11 12 1314151617 18 CS1 CS2 CS3 CS4 NC O7 O6 O1 O2 GND NC O3 O4 O5 CS3 CS4 10 11 12 VCC A8 A9 CS1 CS2 CS3 CS4 O7 O6 O5 O4 O3 LCC/PLCC Top View O2 O1 24 1 23 2 22 3 21 4 20 5 6 7C281A 19 18 7 17 8 16 9 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 16, 2006 [+] Feedback CY7C281A Selection Guide 7C281A-25 Maximum Access Time Maximum Operating Current Commercial 7C281A-30 Unit 25 30 ns 100 100 mA Maximum Ratings[1] DC Program Voltage (Pins 18, 20) ............................... 13.0V Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................−65°C to +150°C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied..................................................−55°C to +125°C Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ±10% Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V DC Input Voltage .................................................−3.0V to +7.0V Electrical Characteristics Over the Operating Range[2,3] 7C281A-25 Parameter Description Test Conditions Min. Max. 7C281A-30 Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 16.0 mA VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs IIX Input Current GND < VIN < VCC −10 +10 IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled −10 +10 IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND −20 −90 ICC Power Supply Current VCC = Max., IOUT = 0 mA VPP Program Voltage 12 VIHP Program HIGH Voltage 3.0 VILP Program LOW Voltage 0.4 0.4 V IPP Program Supply Current 50 50 mA 2.4 2.4 0.4 2.0 V 2.0 0.8 Commercial V 0.4 0.8 V −10 +10 µA −10 +10 µA −20 −90 mA 100 mA 13 V 100 13 V 12 3.0 V Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. See the last page of this specification for Group A subgroup testing information. 3. See “Introduction to CMOS PROMs” in this Data Book for general information on testing. 4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document #: 38-04003 Rev. *C Page 2 of 8 [+] Feedback CY7C281A AC Test Loads and Waveforms[3] R1 250Ω R1 250Ω 5V 5V OUTPUT OUTPUT R2 167Ω 30pF 5 pF INCLUDING JIG AND SCOPE R2 167Ω 90% 10% 90% 10% GND ≤ 5 ns INCLUDING JIG AND SCOPE (a) NormalLoad Equivalent to: ALL INPUT PULSES 3.0V ≤ 5 ns (b) High Z Load THÉVENIN EQUIVALENT 100Ω OUTPUT 2.0V Switching Characteristics Over the Operating Range[1,3] 7C281A-25 Parameter Description Min. Max. 7C281A-30 Max. Unit tAA Address to Output Valid 25 Min. 30 ns tHZCS Chip Select Inactive to High Z 15 20 ns tACS Chip Select Active to Output Valid 15 20 ns Switching Waveforms A0 − A9 ADDRESS CS3, CS4 CS1, CS2 SELECTED DESELECTED tAA tHZCS SELECTED tACS O0 −O7 DATA Document #: 38-04003 Rev. *C Page 3 of 8 [+] Feedback CY7C281A Programming Information programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. Programming support is available from Cypress as well as from a number of third party software vendors. For detailed Table 1. Mode Selection Pin Function[5] Read or Output Disable A9–A0 CS4 CS3 CS2 CS1 O7–O0 Other A9–A0 PGM VFY VPP CS1 D7–D0 Read A9–A0 VIH VIH VIL VIL O7–O0 Output Disable A9–A0 X X VIH X High Z Output Disable A9–A0 X VIL X X High Z Output Disable A9–A0 VIL X X X High Z Output Disable A9–A0 X X X VIH High Z Program A9–A0 VILP VIHP VPP VILP D7–D0 Program Verify A9–A0 VIHP VILP VPP VILP O7–O0 Program Inhibit A9–A0 VIHP VIHP VPP VILP High Z Intelligent Program A9–A0 VILP VIHP VPP VILP D7–D0 Blank Check A9–A0 VIHP VILP VPP VILP Zeros Mode Figure 1. Programming Pinouts GND 24 1 23 2 22 3 21 4 20 5 7C281A 19 6 18 7 17 8 16 9 15 10 14 11 12 13 VCC A8 A9 CS1 VPP VFY PGM D7 D6 D5 D4 D3 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 4 3 2 1 28 27 26 25 24 23 7C281A 22 21 20 19 121314151617 18 CS1 VPP VFY PGM NC D7 D6 D1 D2 GND NC D3 D4 D5 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 PLCC Top View A5 A6 A7 NC VCC A8 A9 DIP Top View Note 5. X = “don’t care” but not to exceed VCC ±5%. Document #: 38-04003 Rev. *C Page 4 of 8 [+] Feedback CY7C281A Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 TA =25°C f = fMAX 0.8 0.6 4.0 4.5 5.0 5.5 1.1 1.0 0.9 0.8 −55 6.0 1.6 1.4 1.2 1.0 0.8 125 TA =25°C 0.4 4.0 5.0 50 25.0 40 30 20 15.0 10.0 VCC =4.5V TA =25°C 5.0 1.0 2.0 3.0 6.0 20.0 10 0 5.5 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 0 4.5 SUPPLYVOLTAGE(V) 60 0.0 4.0 0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 200 400 600 800 1000 CAPACITANCE (pF) I CC vs.CYCLE PERIOD 175 1.02 150 1.00 125 100 75 VCC =5.0V TA =25°C 25 0 0.0 0.6 OUTPUT SOURCE CURRENT vs. VOLTAGE NORMALIZED ICC OUTPUT SINK CURRENT (mA) AMBIENT TEMPERATURE (°C) 50 0.8 125 DELTA t AA (ns) OUTPUT SOURCE CURRENT (mA) NORMALIZED ACCESS TIME NORMALIZED ACCESSTIME vs.TEMPERATURE 25 25 1.0 AMBIENT TEMPERATURE(°C) SUPPLYVOLTAGE(V) 0.6 −55 1.2 NORMALIZED ACCESS TIME 1.2 NORMALIZED ICC NORMALIZED I CC 1.6 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE VCC =5.5V TA =25°C 0.98 0.96 0.94 0.92 0.90 1.0 2.0 3.0 OUTPUT VOLTAGE (V) Document #: 38-04003 Rev. *C 4.0 0.88 0 25 50 75 100 CYCLE PERIOD (ns) Page 5 of 8 [+] Feedback CY7C281A Ordering Information Speed (ns) Ordering Code Package Name Operating Range Package Type 25 CY7C281A-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial 30 CY7C281A-30PC P13 24-Lead (300-Mil) Molded DIP Commercial Package Diagrams Figure 2. 28-Lead Plastic Leaded Chip Carrier J64 51-85001-*A Document #: 38-04003 Rev. *C Page 6 of 8 [+] Feedback CY7C281A Package Diagrams Figure 3. 24-Lead (300-Mil) PDIP P13 51-85013-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-04003 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C281A Document History Page Document Title: CY7C281A 1K x 8 PROM Document Number: 38-04003 ECN NO. Issue Date Orig. of Change ** 113859 03/06/02 DSG Changed from Spec number: 38-00227 to 38-04003 *A 118902 10/09/02 GBI Updated ordering information REV. Description of Change *B 122244 12/27/02 RBI Added power up requirements to Maximum ratings information *C 499538 See ECN PCI Updated ordering information Document #: 38-04003 Rev. *C Page 8 of 8 [+] Feedback