CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • QDR-II operates with 1.5 cycle read latency when the DLL is enabled • Operates like a QDR-I device with 1 cycle read latency in DLL off mode • Available in x 8, x 9, x 18, and x 36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Offered in both lead-free and non-lead free packages • Variable drive HSTL output buffers The CY7C1310CV18, CY7C1910CV18, CY7C1312CV18 and CY7C1314CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1310CV18) or 9-bit words (CY7C1910CV18) or 18-bit words (CY7C1312CV18) or 36-bit words (CY7C1314CV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Configurations CY7C1310CV18 – 2M x 8 CY7C1910CV18 – 2M x 9 CY7C1312CV18 – 1M x 18 CY7C1314CV18 – 512K x 36 Cypress Semiconductor Corporation Document #: 001-07164 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 20, 2006 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Logic Block Diagram (CY7C1310CV18) D[7:0] CLK Gen. DOFF Address Register Read Add. Decode K K Write Add. Decode 20 Write Reg 1M x 8 Array Address Register Write Reg 1M x 8 Array A(19:0) 8 RPS Control Logic C C Read Data Reg. 16 VREF WPS NWS[1:0] CQ CQ 8 Reg. Control Logic A(19:0) 20 Reg. 8 8 8 Reg. Q[7:0] 8 Logic Block Diagram (CY7C1910CV18) K K CLK Gen. DOFF VREF WPS BWS[0] Address Register Read Add. Decode 20 Write Reg 1M x 9 Array Address Register Write Reg 1M x 9 Array A(19:0) 9 Write Add. Decode D[8:0] 20 A(19:0) RPS Control Logic C C Read Data Reg. CQ CQ 18 Control Logic 9 Reg. 9 Reg. 9 Document #: 001-07164 Rev. *B Reg. 9 Q [8:0] 9 Page 2 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Logic Block Diagram (CY7C1312CV18) D[17:0] K K CLK Gen. DOFF Address Register Read Add. Decode 19 Write Reg 512K x 18 Array A(18:0) Write Reg 512K x 18 Array Address Register Write Add. Decode 18 RPS Control Logic C C Read Data Reg. 36 VREF WPS BWS[1:0] CQ CQ 18 Reg. Control Logic A(18:0) 19 18 Reg. 18 18 Reg. Q[17:0] 18 Logic Block Diagram (CY7C1314CV18) D[35:0] CLK Gen. DOFF VREF WPS BWS[3:0] Address Register Read Add. Decode K K Write Add. Decode 18 Write Reg 256K x 36 Array Address Register Write Reg 256K x 36 Array A(17:0) 36 RPS Control Logic C C Read Data Reg. 72 36 CQ CQ 36 Reg. Control Logic A(17:0) 18 Reg. 36 Reg. 36 36 Q[35:0] Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 250 200 167 MHz Maximum Operating Current 600 550 500 mA Document #: 001-07164 Rev. *B Page 3 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Pin Configurations 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1310CV18 (2M x 8) A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 CQ NC/72M NC WPS A NWS1 NC/288M K NC A NC A NC NC/36M NC CQ Q3 NC D4 NC NC VSS VSS A VSS VSS NC VSS K A VSS RPS A NC NC NC/144M NWS0 A VSS NC NC NC D3 NC NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 NC NC NC VDDQ VDD VSS VDD VDDQ NC NC DOFF NC D5 VREF NC Q5 VDDQ NC VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ NC NC VDDQ NC NC VREF Q1 NC NC ZQ D1 NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 NC NC NC D7 NC NC VSS VSS VSS A VSS A VSS A VSS VSS NC NC NC NC D0 NC NC NC Q7 A A C A A NC NC NC TDO TCK A A A C A A A TMS TDI 9 10 11 CY7C1910CV18 (2M x 9) A B C D E F G H J K L M N P R 1 2 3 4 CQ NC 5 6 7 8 NC/72M A NC NC WPS NC K NC/144M RPS A NC/36M CQ A NC/288M K BWS0 A NC NC Q4 NC NC NC D5 NC VSS VSS A A VSS A VSS VSS VSS NC VSS NC NC D4 NC NC NC Q5 NC NC NC NC VDDQ VSS VSS VSS VDDQ NC D3 Q3 VDDQ VDD VSS VDDQ VDD VDD VDD VSS VSS VSS VDDQ VDDQ VDDQ NC NC VDDQ NC NC VDDQ VDDQ VDDQ VDD VDD VDD VDD NC VREF Q2 NC NC ZQ D2 DOFF NC D6 VREF NC Q6 VDDQ NC NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC NC NC NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 NC NC NC D8 NC NC VSS VSS VSS A VSS A VSS A VSS VSS NC NC NC NC D1 NC NC NC Q8 A A C A A NC D0 Q0 TDO TCK A A A C A A A TMS TDI Document #: 001-07164 Rev. *B Page 4 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Pin Configurations (continued) 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1312CV18 (1M x 18) 1 A B C D E F G H J K L M N P R CQ 2 3 NC/144M NC/36M 4 5 6 7 8 9 10 11 WPS BWS1 K NC/288M RPS A NC/72M CQ NC Q9 D9 A NC K BWS0 A NC NC Q8 NC NC NC D11 D10 A VSS A VSS A VSS VSS VSS NC Q10 VSS VSS NC Q7 NC D8 D7 NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 NC NC Q12 D12 VDDQ VDD VSS VDDQ Q13 VDDQ D14 VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDDQ VDDQ VDDQ NC NC VDDQ NC NC D13 VREF NC VDD VDD VDD VDD Q5 D5 ZQ D4 NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 NC NC NC D17 D16 Q16 VSS VSS VSS A VSS A VSS A VSS VSS NC NC Q1 NC D2 D1 NC NC Q17 A A C A A NC D0 Q0 TDO TCK A A A C A A A TMS TDI 9 10 11 DOFF NC NC VREF Q4 CY7C1314CV18 (512K x 36) 1 A B C D E F G H J K L M N P R CQ Q27 2 3 NC/288M NC/72M 4 5 6 7 8 WPS BWS2 K BWS1 RPS NC/36M NC/144M CQ Q18 D18 A BWS3 A D17 Q17 Q8 Q28 D20 D19 Q19 VSS VSS A VSS K A VSS BWS0 D27 D28 A VSS VSS VSS D16 Q16 Q7 D15 D8 D7 Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 Q30 Q21 D21 VDDQ VDD VSS Q22 VDDQ D23 VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDDQ VDDQ VDDQ D14 Q13 VDDQ D12 Q14 D22 VREF Q31 VDD VDD VDD VDD VDDQ D30 Q5 D5 ZQ D4 Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 D33 D34 Q34 D26 D25 Q25 VSS VSS VSS A VSS A VSS A VSS VSS D10 Q10 Q1 D9 D2 D1 Q35 D35 Q26 A A C A A Q9 D0 Q0 TDO TCK A A A C A A A TMS TDI DOFF D31 Document #: 001-07164 Rev. *B D13 VREF Q4 Page 5 of 26 [+] Feedback PRELIMINARY CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Pin Definitions I/O Pin Description D[x:0] Pin Name InputSynchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1310CV18 - D[7:0] CY7C1910CV18 - D[8:0] CY7C1312CV18 - D[17:0] CY7C1314CV18 - D[35:0] WPS InputSynchronous Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. Nibble Write Select 0, 1 − active LOW. (CY7C1310CV18 Only) Sampled on the rising edge of the K and K clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations.Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device. NWS0,NWS1 BWS0, BWS1, BWS2, BWS3 InputSynchronous Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1910CV18 − BWS0 controls D[8:0] CY7C1312CV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]. CY7C1314CV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputSynchronous Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) clocks during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310CV18, 2M x 9 (2 arrays each of 1M x 9) for CY7C1910CV18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1312CV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314CV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1310CV18 and CY7C1910CV18, 19 address inputs for CY7C1312CV18 and 18 address inputs for CY7C1314CV18. These inputs are ignored when the appropriate port is deselected. Q[x:0] OutputsSynchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically tri-stated. CY7C1310CV18 − Q[7:0] CY7C1910CV18 − Q[8:0] CY7C1312CV18 − Q[17:0] CY7C1314CV18 − Q[35:0] RPS InputSynchronous Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Document #: 001-07164 Rev. *B Page 6 of 26 [+] Feedback PRELIMINARY CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Pin Definitions (continued) Pin Name I/O Pin Description K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. For normal operation, this pin can be connected to a pull-up through a 10-Kohm or less pull-up resistor. The device will behave in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing. TDO Output TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/36M N/A Not connected to the die. Can be tied to any voltage level. NC/72M N/A Not connected to the die. Can be tied to any voltage level. NC/144M N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level. VREF InputReference VDD Power Supply VSS Ground VDDQ Power Supply TDO for JTAG. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the core of the device. Ground for the device. Power supply inputs for the outputs of the device. Functional Overview The CY7C1310CV18, CY7C1910CV18, CY7C1312CV18 and CY7C1314CV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access Document #: 001-07164 Rev. *B consists of two 8-bit data transfers in the case CY7C1310CV18, two 9-bit data transfers in the case CY7C1910CV18,two 18-bit data transfers in the case CY7C1312CV18 and two 36-bit data transfers in the case CY7C1314CV18, in one clock cycle. of of of of This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then the device will behave in QDR-I mode with a read latency of one clock cycle. Accesses for both ports are initiated on the rising edge of the positive Input Clock (K). All synchronous input timings are referenced from the rising edge of the input clocks (K and K) Page 7 of 26 [+] Feedback PRELIMINARY and all output timings are referenced to the rising edge of output clocks (C and C or K and K when in single clock mode). All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1312CV18 is described in the following sections. The same basic descriptions apply to CY7C1310CV18 CY7C1910CV18 and CY7C1314CV18. Read Operations CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1312CV18 can be used with a single clock that controls both the input and output registers. In this mode, the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. The CY7C1312CV18 is organized internally as 2 arrays of 512K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address is latched on the rising edge of the K Clock. The address presented to Address inputs is stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C and C or K and K when in single clock mode). Concurrent Transactions Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Output Clocks (C/C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. The CY7C1312CV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Write Operations The Read and Write ports on the CY7C1312CV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Depth Expansion Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the same K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the address is latched and the information presented to D[17:0] is stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Programmable Impedance Byte Write Operations Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock (C/C) of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Byte Write operations are supported by the CY7C1312CV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Document #: 001-07164 Rev. *B An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V.The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Page 8 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device will behave in QDR-I mode (with one cycle latency and a longer access time). For information refer to the application note “DLL Considerations in QDRII/DDRII”. Application Example[1] R = 250οηµσ SRAM #1 Vt D A R R P S # W P S # B W S # ZQ CQ/CQ# Q C C# K K# SRAM #4 R P S # D A DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# W P S # B W S # ZQ R = 250οηµσ CQ/CQ# Q C C# K K# Vt Vt R Delayed K Delayed K# R R = 50οηµσ Vt = Vddq/2 Truth Table[2, 3, 4, 5, 6, 7] Operation K RPS WPS Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges. L-H X L D(A + 0) at K(t) ↑ D(A + 1) at K(t) ↑ Read Cycle: Load address on the rising edge of K clock; wait one and a half cycle; read data on C and C rising edges. L-H L X Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑ NOP: No Operation L-H H H D=X Q = High-Z D=X Q = High-Z Stopped X X Previous State Previous State Standby: Clock Stopped DQ DQ Notes: 1. The above application shows four QDR-II being used. 2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. Document #: 001-07164 Rev. *B Page 9 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Write Cycle Descriptions (CY7C1310CV18 and CY7C1312CV18) [2, 8] BWS0/NWS0 BWS1/NWS1 K K L L L-H – L L – L H L-H L H – H L L-H H L – H H L-H H H – Comments During the Data portion of a Write sequence: CY7C1310CV18 − both nibbles (D[7:0]) are written into the device, CY7C1312CV18 − both bytes (D[17:0]) are written into the device. L-H During the Data portion of a Write sequence: CY7C1310CV18 − both nibbles (D[7:0]) are written into the device, CY7C1312CV18 − both bytes (D[17:0]) are written into the device. – During the Data portion of a Write sequence: CY7C1310CV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1312CV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L-H During the Data portion of a Write sequence: CY7C1310CV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1312CV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. – During the Data portion of a Write sequence: CY7C1310CV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1312CV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. L-H During the Data portion of a Write sequence: CY7C1310CV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1312CV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. – No data is written into the devices during this portion of a Write operation. L-H No data is written into the devices during this portion of a Write operation. Note: 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: 001-07164 Rev. *B Page 10 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Write Cycle Descriptions (CY7C1314CV18) BWS0 BWS1 BWS2 BWS3 K K - L L L L L-H L L L L - L H H H L-H L H H H - H L H H L-H H L H H - H H L H L-H H H L H - H H H L L-H H H H L - H H H H L-H H H H H - [2, 8] Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. - During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. - During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. - No data is written into the device during this portion of a Write operation. L-H No data is written into the device during this portion of a Write operation. Write Cycle Descriptions (CY7C1910CV18) [2, 8] BWS0 K K Comments L L-H – During the Data portion of a Write sequence: CY7C1910CV18 − the single byte (D[8:0]) is written into the device L – L-H During the Data portion of a Write sequence: CY7C1910CV18 − the single byte (D[8:0]) is written into the device, H L-H – No data is written into the devices during this portion of a Write operation. H – L-H No data is written into the devices during this portion of a Write operation. Document #: 001-07164 Rev. *B Page 11 of 26 [+] Feedback PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Test Access Port—Test Clock Boundary Scan Register The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document #: 001-07164 Rev. *B The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 12 of 26 [+] Feedback PRELIMINARY is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. Document #: 001-07164 Rev. *B Page 13 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-07164 Rev. *B Page 14 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min. VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 VOH2 Output HIGH Voltage IOH = −100 µA 1.6 VOL1 Output LOW Voltage IOL = 2.0 mA IOL = 100 µA VOL2 Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IX Input and OutputLoad Current GND ≤ VI ≤ VDD Max. Unit V V 0.4 V 0.2 V 0.65VDD VDD + 0.3 V –0.3 0.35VDD V −5 5 µA Notes: 10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 11. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 12. All voltage referenced to Ground. Document #: 001-07164 Rev. *B Page 15 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[13, 14] Parameter Description Min. Max. Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns 50 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 0 ns ns TAP Timing and Test Conditions[13] 0.9V 50Ω ALL INPUT PULSES 1.8V TDO 0.9V Z0 = 50Ω 0V CL = 20 pF tTH tTL GND (a) Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV tTDOX Notes: 13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. 14. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. Document #: 001-07164 Rev. *B Page 16 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Identification Register Definitions Value Instruction Field CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 001 001 001 001 Revision Number (31:29) Cypress Device ID (28:12) Description Version number. 11010011010000101 1101011010001101 11010011010010101 11010011010100101 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 00000110100 1 1 1 1 ID Register Presence (0) Unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan Cells 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 001-07164 Rev. *B Page 17 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 11F 58 5A 86 3J 3 7P 31 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 1K 5 7R 33 10F 61 4B 89 2L 6 8R 34 11E 62 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43 11C 71 1D 99 2P 16 9N 44 9B 72 2C 100 1P 17 11L 45 10B 73 3E 101 3R 18 11M 46 11A 74 2D 102 4R 19 9L 47 Internal 75 2E 103 4P 20 10L 48 9A 76 1E 104 5P 21 11K 49 8B 77 2F 105 5N 22 10K 50 7C 78 3F 106 5R 23 9J 51 6C 79 1G 24 9K 52 8A 80 1F 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1J Document #: 001-07164 Rev. *B Page 18 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Power-up Sequence in QDR-II SRAM[15] QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. DLL Constraints • DLL uses K clock as its synchronizing input. The input should have low phase jitter, which is specified as tKC Var. • The DLL will function at frequencies down to 80 MHz. Power-up Sequence • Apply power and drive DOFF LOW (All other inputs can be HIGH or LOW) — Apply VDD before VDDQ • If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency — Apply VDDQ before VREF or at the same time as VREF • After the power and clock (K, K) are stable take DOFF HIGH • The additional 1024 cycles of clocks are required for the DLL to lock. ~ ~ Power-up Waveforms K K ~ ~ Unstable Clock > 1024 Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix High (or tied to VDDQ) Note: 15. During Power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. Document #: 001-07164 Rev. *B Page 19 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied............................................... –10°C to +85°C Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC Voltage Applied to Outputs in High-Z State .................................... –0.5V to VDDQ + 0.3V Range Ambient Temperature (TA) VDD[18] VDDQ[18] 0°C to +70°C 1.8 ± 0.1 V 1.4V to VDD Com’l Ind’l –40°C to +85°C DC Input Voltage[11] ...............................–0.5V to VDD + 0.3V Electrical Characteristics Over the Operating Range[12, 18] DC Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL VOH(LOW) Test Conditions Typ. Max. Unit 1.7 1.8 1.9 V 1.4 1.5 VDD V Note 16 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V Output LOW Voltage Note 17 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V IOL = 0.1 mA, Nominal Impedance VOL(LOW) Output LOW Voltage VIH Input HIGH Voltage[11] Voltage[11] VIL Input LOW IX Input Leakage Current GND ≤ VI ≤ VDDQ IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VREF Input Reference Voltage[19] Typical Value = 0.75V IDD VDD Operating Supply ISB1 Min. Automatic Power-down Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VSS 0.2 V VREF + 0.1 VDDQ+0.3 V –0.3 VREF – 0.1 V −5 5 µA −5 5 µA 0.95 V 167 MHz 500 mA 200 MHz 550 mA 0.68 0.75 250 MHz 600 mA Max. VDD, Both Ports 167 MHz Deselected, VIN ≥ VIH 200 MHz or VIN ≤ VIL f = fMAX = 250 MHz 1/tCYC, Inputs Static 240 mA 260 mA 280 mA AC Input Requirements Over the Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage VREF + 0.2 – – V VIL Input LOW Voltage – – VREF - 0.2 V Capacitance[20] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max. Unit 5 pF 6 pF 7 pF Notes: 16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs. 17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 18. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH< VDD and VDDQ< VDD. 19. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller. 20. Tested initially and after any design or process change that may affect these parameters. Document #: 001-07164 Rev. *B Page 20 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Thermal Resistance[20] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 165 FBGA Package Unit 28.51 °C/W 5.91 °C/W AC Test Loads and Waveforms VREF = 0.75V VREF 0.75V VREF OUTPUT Z0 = 50Ω Device Under Test RL = 50Ω VREF = 0.75V ZQ R = 50Ω ALL INPUT PULSES 1.25V 0.75V OUTPUT Device Under Test ZQ RQ = 250Ω (a) 0.75V INCLUDING JIG AND SCOPE 5 pF [21] 0.25V Slew Rate = 2 V/ns RQ = 250Ω (b) Note: 21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads Document #: 001-07164 Rev. *B Page 21 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Switching Characteristics Over the Operating Range[21, 22] 250 MHz Cypress Consortium Parameter Parameter Description VDD(Typical) to the first Access[23] tPOWER Min. Max. 1 200 MHz Min. Max. 1 167 MHz Min. Max. 1 Unit ms tCYC tKHKH K Clock and C Clock Cycle Time 4.0 6.3 5.0 7.9 6.0 7.9 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 1.6 – 2.0 – 2.4 – ns tKL tKLKH Input Clock (K/K and C/C) LOW 1.6 – 2.0 – 2.4 – ns tKHKH tKHKH K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) 1.8 – 2.2 – 2.7 – ns tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 1.8 0.0 2.2 0.0 2.7 ns Set-up Times tSA tAVKH Address Set-up to Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns tSC tIVKH Control Set-up to K Clock Rise (RPS, WPS) 0.35 – 0.4 – 0.5 – ns tSCDDR tIVKH Double Data Rate Control Set-up to Clock (K/K) Rise (BWS0, BWS1, BWS3, BWS4) 0.35 – 0.4 – 0.5 – ns tSD[24] tDVKH D[X:0] Set-up to Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns Hold Times tHA tKHAX Address Hold after Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns tHC tKHIX Control Hold after K Clock Rise (RPS, WPS) 0.35 – 0.4 – 0.5 – ns tHCDDR tKHIX Double Data Rate Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS3, BWS4) 0.35 – 0.4 – 0.5 – ns tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns Output Times tCO tCHQV C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid – 0.45 – 0.45 – 0.50 ns tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to Active) –0.45 – -0.45 – -0.50 – ns tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.50 ns tCQOH tCHCQX Echo Clock Hold after C/C Clock Rise –0.45 – –0.45 – –0.50 – ns tCQD tCQHQV Echo Clock High to Data Valid – 0.30 – 0.35 – 0.40 ns tCQDOH tCQHQX Echo Clock High to Data Invalid –0.30 – –0.35 – –0.40 – ns tCQH tCQHCQL Output Clock (CQ/CQ) HIGH[25] 1.55 – 1.95 – 2.45 – ns tCQHCQH tCQHCQH 1.55 – 1.95 – 2.45 – ns tCHZ tCHQZ – 0.45 – 0.45 – 0.50 ns tCLZ tCHQX1 CQ Clock Rise to CQ Clock Rise[25] (rising edge to rising edge) Clock (C/C) Rise to High-Z (Active to High-Z)[26,27] Clock (C/C) Rise to Low-Z[26,27] –0.45 – –0.45 – –0.50 – ns tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – cycles tKC Reset tKC Reset K Static to DLL Reset 30 – 30 – 30 – ns DLL Timing Notes: 22. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 23. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 24. For D2 data signal on CY7C1910CV18 device, tSD is 0.5ns for 200MHz, and 250MHz frequencies. 25. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) ia already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production 26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 27. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. Document #: 001-07164 Rev. *B Page 22 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Switching Waveforms[28, 29, 30] Read/Write/Deselect Sequence READ WRITE READ WRITE READ WRITE NOP WRITE NOP 1 2 3 4 5 6 7 8 9 10 K tKH tKL tKHKH tCYC K RPS tSC t HC WPS A D A1 A2 tSA tHA tSA tHA D11 D30 A0 D10 A3 A4 A5 D31 D50 D51 tSD Q00 t CLZ C tKL tKH tKHCH D60 D61 tSD tHD tHD Q tKHCH A6 Q01 tDOH tCO Q20 Q21 Q41 Q40 tCQDOH t CHZ tCQD t CYC tKHKH C tCQOH tCCQO CQ tCQOH tCCQO tCQH tCQHCQH CQ DON’T CARE UNDEFINED Notes: 28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1. 29. Outputs are disabled (High-Z) one clock cycle after a NOP. 30. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document #: 001-07164 Rev. *B Page 23 of 26 [+] Feedback PRELIMINARY CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed (MHz) 250 Ordering Code CY7C1310CV18-250BZC Package Diagram Operating Range Package Type 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1910CV18-250BZC CY7C1312CV18-250BZC CY7C1314CV18-250BZC 250 CY7C1310CV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free Commercial CY7C1910CV18-250BZXC CY7C1312CV18-250BZXC CY7C1314CV18-250BZXC 250 CY7C1310CV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free Industrial CY7C1910CV18-250BZI CY7C1312CV18-250BZI CY7C1314CV18-250BZI 250 CY7C1310CV18-250BZXI CY7C1910CV18-250BZXI CY7C1312CV18-250BZXI CY7C1314CV18-250BZXI 200 CY7C1310CV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1910CV18-200BZC CY7C1312CV18-200BZC CY7C1314CV18-200BZC 200 CY7C1310CV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free Commercial CY7C1910CV18-200BZXC CY7C1312CV18-200BZXC CY7C1314CV18-200BZXC 200 CY7C1310CV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free Industrial CY7C1910CV18-200BZI CY7C1312CV18-200BZI CY7C1314CV18-200BZI 200 CY7C1310CV18-200BZXI CY7C1910CV18-200BZXI CY7C1312CV18-200BZXI CY7C1314CV18-200BZXI 167 CY7C1310CV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1910CV18-167BZC CY7C1312CV18-167BZC CY7C1314CV18-167BZC 167 CY7C1310CV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free Commercial CY7C1910CV18-167BZXC CY7C1312CV18-167BZXC CY7C1314CV18-167BZXC Document #: 001-07164 Rev. *B Page 24 of 26 [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Ordering Information (continued) “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed (MHz) 167 Package Diagram Ordering Code CY7C1310CV18-167BZI Operating Range Package Type 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free Industrial CY7C1910CV18-167BZI CY7C1312CV18-167BZI CY7C1314CV18-167BZI 167 CY7C1310CV18-167BZXI CY7C1910CV18-167BZXI CY7C1312CV18-167BZXI CY7C1314CV18-167BZXI Package Diagram 165-ball FBGA (13 x 15 x 1.4 mm) (51-85180) BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.25 C 0.15(4X) NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC 51-85180-*A 0.35±0.06 0.36 SEATING PLANE C QDR RAMs and Quad Data Rate QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 001-07164 Rev. *B Page 25 of 26 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY Document History Page Document Title: CY7C1310CV18/CY7C1910CV18/CY7C1312CV18/CY7C1314CV18 18-Mbit QDR- II™ SRAM 2-Word Burst Architecture Document Number: 001-07164 REV. ECN No. Issue Date Orig. of Change Description of Change ** 433284 See ECN NXR New data sheet *A 462615 See ECN NXR Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform *B 503690 See ECN VKN Minor change: Moved data sheet to web Document #: 001-07164 Rev. *B Page 26 of 26 [+] Feedback