FAIRCHILD 74LCX760MSA

Revised March 2005
74LCX760
Low Voltage Buffer/Line Driver
with 5V Tolerant Inputs and Open Drain Outputs
General Description
Features
The LCX760 is the Open Drain version of the LCX244. The
LCX760 contains eight non-inverting buffers with 3-STATE
outputs. The device may be employed as a memory
address driver, clock driver and bus-oriented transmitter/
receiver. The LCX760 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
signal environment.
■ Open drain version of the LCX244
The LCX760 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining
CMOS low power dissipation.
■ 24 mA output drive (VCC
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V VCC specifications provided
■ 8.0 ns tPD max (VCC
3.3V), 10 PA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up conforms to JEDEC JED78
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package Number
74LCX760WM
74LCX760SJ
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX760MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX760MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2005 Fairchild Semiconductor Corporation
DS500413
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74LCX760 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs
July 2001
74LCX760
Pin Descriptions
Pin Names
Description
OE1, OE2
3-STATE Output Enable Inputs
I0–I7
Inputs
O0–O7
Outputs
Truth Tables
Inputs
OE1
Outputs
In
(Pins 12, 14, 16, 18)
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE2
In
L
L
L
L
H
H
H
X
Z
(Pins 3, 5, 7, 9)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
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Symbol
Parameter
Value
VCC
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
Conditions
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
50
50
IO
DC Output Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
Units
V
V
Output in HIGH or LOW State (Note 3)
VI GND
V
mA
VO GND
mA
VO ! VCC
50
mA
r100
r100
65 to 150
mA
mA
qC
Recommended Operating Conditions (Note 4)
Symbol
VCC
Parameter
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
Supply Voltage
Units
V
VI
Input Voltage
0
5.5
V
VO
Output Voltage
0
5.5
V
IOL
Output Current
TA
Free-Air Operating Temperature
't/'V
Input Edge Rate, VIN
0.8V–2.0V, VCC
VCC
3.0V 3.6V
24
VCC
2.7V 3.0V
12
VCC
2.3V 2.7V
8
mA
40
85
qC
0
10
ns/V
3.0V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Unused inputs or I/Os must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOL
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
LOW Level Output Voltage
VCC
TA
40qC to 85qC
(V)
Min
2.3 2.7
1.7
2.7 3.6
2.0
V
2.3 2.7
0.7
2.7 3.6
0.8
2.3 3.6
0.2
IOL
100 PA
IOL
8 mA
2.3
0.6
IOL
12 mA
2.7
0.4
IOL
16 mA
3.0
0.4
IOL
24 mA
II
Input Leakage Current
0 d VI d 5.5V
IOZ
3-STATE Output Leakage
0 d VO d 5.5V
VI
V IH or VIL
IOFF
Power-Off Leakage Current
VI or VO
ICC
Quiescent Supply Current
VI
5.5V
V CC or GND
3.6V d VI, VO d 5.5V (Note 5)
'ICC
Increase in ICC per Input
VIH
VCC 0.6V
IOHZ
Off State Current
VO
5.5
Units
Max
V
V
3.0
0.55
2.3 3.6
r5.0
PA
2.3 3.6
r5.0
PA
PA
0
10
2.3 3.6
10
2.3 3.6
r10
2.3 3.6
500
PA
2 - 3.6
10
PA
PA
Note 5: Outputs disabled or 3-STATE only.
3
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74LCX760
Absolute Maximum Ratings(Note 2)
74LCX760
AC Electrical Characteristics
TA
Symbol
Parameter
VCC
40qC to 85qC, RL 500:
3.3V r 0.3V
CL 50 pF
VCC
2.7V
CL
50 pF
VCC
CL
2.5V r 0.2
Units
30 pF
Min
Max
Min
Max
Min
Max
tPZL
Propagation Delay
0.5
8.0
0.5
9.0
0.5
10.0
tPLZ
Data to Output
0.5
7.0
0.5
8.0
0.5
8.4
tPZL
Output Enable Time
0.5
8.0
0.5
9.0
0.5
10.0
ns
0.5
7.0
0.5
8.0
0.5
8.4
ns
OEn to Out
tPLZ
Output Disable Time
OEn to Out
tOSHL
Output to Output Skew
1.0
tOSLH
(Note 6)
1.0
ns
ns
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
VCC
Conditions
TA
25qC
(V)
Typical
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
Units
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
Open, VI
COUT
Output Capacitance
VCC
3.3V, VI
0V or VCC
CPD
Power Dissipation Capacitance
VCC
3.3V, VI
0V or VCC, f
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0V or VCC
10 MHz
Typical
Units
7
pF
8
pF
10
pF
74LCX760
AC LOADING and WAVEFORMS
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPZL, tPLZ
Switch
6V at VCC 3.3 r 0.3V
VCC x 2 at VCC 2.5 r 0.2V
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
VCC
3.3V r 0.3V
2.7V
2.5V r 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL 0.3V
VOL 0.3V
VOL 0.15V
Vy
VOH 0.3V
VOH 0.3V
VOH 0.15V
5
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74LCX760
Schematic Diagram Generic for LCX Family (output pull-up circuitry is not applicable to open drain versions)
FIGURE 3.
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74LCX760
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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74LCX760
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
74LCX760
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
9
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74LCX760 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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