CYPRESS CY7C145-55AC

fax id: 5205
1CY 7C14 4
CY7C145
CY7C144
8K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
• True Dual-Ported memory cells which allow
simultaneous reads of the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master/Slave select pin allows bus width expansion to
16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
• Pin compatible and functionally equivalent to
IDT7005/IDT7015
Functional Description
are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5
can be utilized as a standalone 64/72-Kbit dual-port static
RAM or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip enable (CE) pin or SEM pin.
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/W L
R/W R
CE L
OE L
CE R
OE R
(7C145) I/O8L
I/O7L
I/O
CONTROL
I/O0L
BUSYL
I/O 8R(7C145)
I/O 7R
I/O
CONTROL
I/O 0R
[1, 2]
BUSY R
A 12L
[1, 2]
A 12R
ADDRESS
DECODER
A 0L
CEL
OEL
MEMORY
ARRAY
ADDRESS
DECODER
INTERRUPT
SEMAPHORE
ARBITRATION
A 0R
CE R
OE R
R/W L
R/W R
SEM L
INT L [2]
SEM R
INT R [2]
C144-1
M/S
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 1996
CY7C145
CY7C144
Pin Configurations
68-Pin PLCC
Top View
9 8 7 6
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
CY7C144/5
52
51
50
49
48
47
46
45
44
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
C144-2
64-Pin TQFP
Top View
I/O2L
1
48
A4L
I/O3L
I/O4L
2
47
3
4
46
45
A3L
A2L
5
44
A0L
I/O6L
I/O7L
6
43
7
42
INTL
BUSYL
GND
M/S
I/O5L
GND
A1L
VCC
8
GND
I/O0R
I/O1R
9
10
40
39
11
38
INTR
I/O2R
12
37
VCC
13
36
A0R
A1R
I/O3R
I/O4R
14
15
35
34
A2R
I/O5R
16
33
A4R
CY7C144
41
BUSYR
A3R
C144-3
Notes:
3. I/O8R on the CY7C145.
4. I/O8L on the CY7C145.
2
CY7C145
CY7C144
Pin Configurations (continued)
80-Pin TQFP
Top View
NC
I/O 2L
I/O 3L
1
60
2
59
I/O 4L
3
4
58
57
I/O 5L
5
56
A3L
A2L
GND
I/O 6L
6
55
A1L
7
54
A0L
I/O 7L
8
53
V CC
9
10
52
51
NC
A5L
A4L
11
50
INTL
BUSYL
GND
M/S
12
49
BUSYR
13
48
INTR
I/O2R
14
47
V CC
15
16
46
45
A0R
A1R
17
44
I/O 5R
I/O 6R
18
19
43
42
A4R
NC
20
41
NC
NC
GND
I/O0R
I/O1R
I/O 3R
I/O 4R
CY7C145
A2R
A3R
NC
C144-4
Pin Definitions
Left Port
Right Port
Description
I/O0L−7L(8L)
I/O0R−7R(8R)
Data bus Input/Output
A0L−12L
A0R−12R
Address Lines
CEL
CER
Chip Enable
OEL
OER
Output Enable
R/WL
R/WR
Read/Write Enable
SEML
SEMR
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O0 pin is used when writing to a
semaphore. Semaphores are requested by writing a 0 into the respective
location.
INTL
INTR
Interrupt Flag. INTL is set when right port writes location 1FFE and is
cleared when left port reads location 1FFE. INTR is set when left port writes
location 1FFF and is cleared when right port reads location 1FFF.
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
3
CY7C145
CY7C144
Selection Guide
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Maximum Access Time (ns)
15
25
35
55
Maximum Operating
Current (mA)
220
180
160
160
Maximum Standby
Current for ISB1 (mA)
60
40
30
30
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Range
Ambient
Temperature
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
VCC
Commercial
0°C to +70°C
5V ± 10%
DC Input Voltage[5] ..............................................−0.5V to +7.0V
Industrial
−40°C to +85°C
5V ± 10%
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Electrical Characteristics Over the Operating Range
7C144-15
7C145-15
Parameter
Description
Test Conditions
Min.
VCC = Min., IOH = −4.0 mA
VCC = Min., IOL = 4.0 mA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
IOZ
Output Leakage Current
ICC
Operating Current
ISB1
Standby Current
(Both Ports TTL Levels)
CEL and CER > VIH,
f = fMAX[7]
Com’l
ISB2
Standby Current
(One Port TTL Level)
CEL or CER > VIH,
f = fMAX[7]
Com’l
ISB3
Standby Current
Both Ports
(Both Ports CMOS Levels) CE and CER > VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0[7]
Com’l
Standby Current
(One Port CMOS Level)
Com’l
ISB4
Max.
2.4
7C144-25
7C145-25
Min.
0.4
2.2
0.4
V
0.8
V
+10
−10
+10
µA
−10
+10
−10
+10
µA
180
mA
220
190
60
40
130
110
mA
50
Ind
mA
120
15
Ind
Ind
V
−10
Ind
One Port
CEL or CER > VCC – 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V, Active
Port Outputs, f = fMAX[7]
Unit
V
2.2
0.8
GND < VI < VCC
Outputs Disabled, GND < VO < VCC
VCC = Max., IOUT = 0 mA
Com’l
Outputs Disabled
Ind
Max.
2.4
15
mA
30
125
100
mA
115
Notes:
5. Pulse width < 20 ns.
6. TA is the “instant on” case temperature.
7. fMAX = 1/t RC = All inputs cycling at f = 1/t RC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS
level standby I SB3 .
4
CY7C145
CY7C144
Electrical Characteristics Over the Operating Range (continued)
7C144-35
7C145-35
Parameter
Description
Test Conditions
Min.
7C144-55
7C145-55
Max.
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
IOZ
Output Leakage Current
ICC
Operating Current
ISB1
Standby Current
(Both Ports TTL Levels)
CEL and CER > VIH,
f = fMAX[7]
Com’l
ISB2
Standby Current
(One Port TTL Level)
CEL or CER > VIH,
f = fMAX[7]
ISB3
Standby Current
Both Ports
(Both Ports CMOS Levels) CE and CER > VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0[7]
Standby Current
(One Port CMOS Level)
Com’l
90
90
Ind
100
100
ISB4
2.4
2.4
0.4
V
2.2
0.8
V
0.8
V
−10
+10
−10
+10
µA
−10
+10
−10
+10
µA
160
160
mA
180
180
30
30
Ind
40
40
Com’l
100
100
Ind
110
110
Com’l
15
15
Ind
30
30
GND < VI < VCC
Outputs Disabled, GND < VO < VCC
VCC = Max., IOUT = 0 mA
Com’l
Outputs Disabled
Ind
One Port
CEL or CER > VCC – 0.2V,
VIN > VCC – 0.2V or
VIN < 0.2V, Active
Port Outputs, f = fMAX[7]
V
0.4
2.2
mA
mA
mA
mA
]
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
V CC = 5.0V
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
5
Unit
Max.
Unit
10
pF
15
pF
CY7C145
CY7C144
AC Test Loads and Waveforms
5V
5V
R1=893Ω
R1=893Ω
RTH =250Ω
OUTPUT
OUTPUT
C = 30 pF
OUTPUT
C = 5 pF
C=30pF
R2=347Ω
R2=347Ω
VTH =1.4V
(a) Normal Load (Load1)
(c) Three-State Delay (Load 3)
(b) Thévenin Equivalent (Load 1)
C144-5
C144-6
C144-7
ALL INPUT PULSES
OUTPUT
3.0V
C = 30 pF
GND
10%
90%
10%
90%
≤ 3 ns
≤ 3 ns
Load (Load 2)
C144-9
C144-8
Switching Characteristics Over the Operating Range[9]
7C144-15
7C145-15
Parameter
Description
Min.
7C144-25
7C145-25
Max.
Min.
Max.
7C144-35
7C145-35
Min.
Max.
7C144-55
7C145-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address
Change
tACE
CE LOW to Data Valid
15
25
35
55
ns
OE LOW to Data Valid
10
15
20
25
ns
tDOE
tLZOE
[10, 11,12]
tHZOE[10, 11,12]
tLZCE[10, 11,12]
tHZCE[10, 11,12]
tPU[12]
tPD[12]
OE Low to Low Z
15
15
CE LOW to Power-Up
CE HIGH to Power-Down
3
3
10
35
15
0
0
15
20
ns
25
20
ns
ns
25
0
35
ns
ns
3
0
25
55
3
3
15
ns
3
3
3
10
55
3
3
3
CE HIGH to High Z
35
25
3
OE HIGH to High Z
CE LOW to Low Z
25
ns
ns
55
ns
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI /IOH and 30-pF load capacitance.
10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than t LZOE .
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
6
CY7C145
CY7C144
Switching Characteristics Over the Operating Range[9] (continued)
7C144-15
7C145-15
Parameter
Description
Min.
7C144-25
7C145-25
Max.
Min.
Max.
7C144-35
7C145-35
Min.
Max.
7C144-55
7C145-55
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
15
25
35
55
ns
tSCE
CE LOW to Write End
12
20
30
45
ns
tAW
Address Set-Up to Write End
12
20
30
45
ns
tHA
Address Hold From Write
End
2
2
2
2
ns
tSA
Address Set-Up to Write
Start
0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
40
ns
tSD
Data Set-Up to Write End
10
15
15
25
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[11,12]
R/W LOW to High Z
tLZWE[11,12]
tWDD[13]
tDDD[13]
R/W HIGH to Low Z
10
15
3
3
20
3
25
3
ns
ns
Write Pulse to Data Delay
30
50
60
70
ns
Write Data Valid to Read
Data Valid
25
30
35
40
ns
BUSY TIMING[14]
tBLA
BUSY LOW from Address
Match
15
20
20
30
ns
tBHA
BUSY HIGH from Address
Mismatch
15
20
20
30
ns
tBLC
BUSY LOW from CE LOW
15
20
20
30
ns
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
5
5
5
5
ns
tWB
R/W LOW after BUSY LOW
0
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
20
30
30
ns
tBDD
BUSY HIGH to Data Valid
15
20
20
30
ns
15
25
35
55
ns
INTERRUPT TIMING[14]
tINS
INT Set Time
15
25
25
35
ns
tINR
INT Reset Time
15
25
25
35
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE
or SEM)
tSWRD
SEM Flag Write to Read Time
5
5
5
5
ns
tSPS
SEM Flag Contention
Window
5
5
5
5
ns
10
10
15
20
Notes:
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
7
ns
CY7C145
CY7C144
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[15, 16]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C144-10
Read Cycle No. 2 (Either Port CE/OE Access)[15, 17, 18]
SEM or CE
tHZCE
tACE
OE
tLZOE
tHZOE
tDOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
C144-11
Read Timing with Port-to-Port Delay
(M/S=L)[19, 20]
tWC
ADDRESSR
MATCH
t
R/WR
PWE
t
DATAIN R
ADDRESSL
t
SD
HD
VALID
MATCH
tDDD
DATA OUTL
VALID
tWDD
C144-12
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
18. CE L = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
19. BUSY = HIGH for the writing port.
20. CE L = CE R = LOW.
8
CY7C145
CY7C144
Switching Waveforms (continued)
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]
tWC
ADDRESS
tSCE
SEM OR CE
tHA
tAW
tPWE
R/W
tSA
tSD
DATA IN
tHD
DATA VALID
OE
t
tHZOE
LZOE
HIGH IMPEDANCE
DATA OUT
C144-13
Write Cycle No. 2: R/W Three-State Data I/Os (Either
Port)[21, 23, 24]
tWC
ADDRESS
tSCE
tHA
SEM OR CE
tSA
tAW
tPWE
R/W
tSD
tHD
DATAVALID
DATA IN
tHZWE
tLZWE
HIGH IMPEDANCE
DATA OUT
C144-14
Notes:
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates
the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t PWE or (tHZWE + t SD) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply
and the write pulse can be as short as the specified t PWE .
23. R/W must be HIGH during all address transitions.
24. Data I/O pins enter high impedance when OE is held LOW during write.
9
CY7C145
CY7C144
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[25]
tAA
A0−A 2
VALID ADDRESS
VALID ADDRESS
tAW
tACE
tHA
SEM
tOHA
tSCE
tSOP
tSD
I/O0
DATA IN VALID
tSA
DATA OUT VALID
tHD
tPWE
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
C144-15
Semaphore Contention[26, 27, 28]
A0L−A 2L
MATCH
R/WL
SEML
tSPS
A0R−A 2R
MATCH
R/WR
SEM R
C144-16
Notes:
25. CE = HIGH for the duration of the above timing (both write and read cycle).
26. I/O0R = I/O0L = LOW (request semaphore); CE R = CE L = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
10
CY7C145
CY7C144
Switching Waveforms (continued)
Read with BUSY (M/S=HIGH)[20]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tHD
tSD
DATAINR
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
C144–17
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
C144–18
11
CY7C145
CY7C144
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[29]
CEL Valid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
C144-19
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
C144-20
Busy Timing Diagram No. 2 (Address Arbitration)[29]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESS R
tBLA
tBHA
BUSY R
C144-21
Right Address Valid First:
tRC or tWC
ADDRESS R
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESS L
tBLA
tBHA
BUSYL
C144-22
Notes:
29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
12
CY7C145
CY7C144
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
ADDRESS L
tWC
WRITE 1FFF
[30]
tHA
CE L
R/W L
INT R
tINS [31]
C144-23
Right Side Clears INT R:
tRC
ADDRESS R
READ 1FFF
CER
tINR [31]
R/WR
OE R
INTR
C144-24
Right Side Sets INT L:
tWC
ADDRESS R
WRITE 1FFE
tHA
CE R
[30]
R/W R
INT L
tINS [31]
C144-25
Left Side Clears INTL:
tRC
ADDRESS R
READ 1FFE
CEL
tINR [31]
R/WL
OEL
INTL
C144-26
Notes:
30. tHA depends on which enable pin (CEL or R/WL ) is deasserted first.
31. tINS or tINR depends on which enable pin (CE L or R/WL) is asserted last.
13
CY7C145
CY7C144
Architecture
in master mode are push-pull outputs and do not require pull-up resistors to operate.
The CY7C144/5 consists of a an array of 8K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a
BUSY pin is provided on each port. Two interrupt (INT) pins
can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C144/5 can function as
a Master (BUSY pins are outputs) or as a slave (BUSY pins
are inputs). The CY7C144/5 has an automatic power-down
feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read
from the device.
Master/Slave
An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external components.Writing of slave devices must be delayed until after the BUSY
input has settled. Otherwise, the slave chip may begin a write cycle
during a contention situation.When presented a HIGH input, the M/S
pin allows the device to be used as a master and therefore the BUSY
line is an output. BUSY can then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C144/5 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore. The
semaphore value will be available tSWRD + tDOE after the rising edge
of the semaphore write. If the left port was successful (reads a 0), it
assumes control over the shared resource, otherwise (reads a 1) it
assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore
(by writing a 1), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore, a 1 is
written to cancel its request.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising
edge of R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle
No.1 waveform) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE
is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized
in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on
the port tDDD after the data is presented on the other port.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE must
remain HIGH during SEM LOW). A0–2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other address pins have no effect.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE are asserted. If the user of the CY7C144/5 wishes to access a semaphore flag, then the SEM pin must be asserted
instead of the CE pin.
When writing to the semaphore, only I/O0 is used. If a 0 is written
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the left
port now relinquishes control by writing a 1 to the semaphore, the
semaphore will be set to 1 for both sides. However, if the right port
had requested the semaphore (written a 0) while the left port had
control, the right port would immediately own the semaphore as soon
as the left port released it. Table 3 shows sample semaphore operations.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s interrupt flag (INTR) is set. This flag is cleared when the right port reads
that same location. Setting the left port’s interrupt flag (INTL) is accomplished when the right port writes to location 1FFE. This flag is cleared
when the left port reads location 1FFE. The message at 1FFF or
1FFE is user-defined. See Table 2 for input requirements for INT.
INTR and INTL are push-pull outputs and do not require pull-up resistors to operate.
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely
be obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
Busy
The CY7C144/5 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of each
other the Busy logic will determine which port has access. If tPS is
violated, one port will definitely gain permission to the location, but it
is not guaranteed which one. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW. BUSYL and BUSYR
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All Semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
14
CY7C145
CY7C144
Table 1. Non-Contending Read/Write.
Inputs
Outputs
CE
R/W
OE
SEM
H
X
X
H
High Z
Power-Down
H
H
L
L
Data Out
Read Data in
Semaphore
X
X
H
X
High Z
I/O Lines Disabled
X
L
Data In
Write to Semaphore
H
I/O0−7/8
Operation
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH).
Left Port
Function
Right Port
R/W
CE
OE
A0−12
INT
R/W
CE
OE
A0−12
INT
Set Left INT
X
X
X
X
L
L
L
X
1FFE
X
Reset Left INT
X
L
L
1FFE
H
X
L
L
X
X
Set Right INT
L
L
X
1FFF
X
X
X
X
X
L
Reset Right INT
X
X
X
X
X
X
L
L
1FFF
H
Table 3. Semaphore Operation Example.
Function
I/O0-7/8 Left
I/O0-7/8 Right
No action
1
1
Semaphore free
Left port writes semaphore
0
1
Left port obtains semaphore
Right port writes 0 to semaphore
0
1
Right side is denied access
Left port writes 1 to semaphore
1
0
Right port is granted access to semaphore
Left port writes 0 to semaphore
1
0
No change. Left port is denied access
Right port writes 1 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore address
Right port writes 0 to semaphore
1
0
Right port obtains semaphore
Right port writes 1 to semaphore
1
1
No port accessing semaphore
Left port writes 0 to semaphore
0
1
Left port obtains semaphore
Left port writes 1 to semaphore
1
1
No port accessing semaphore
15
Status
CY7C145
CY7C144
Typical DC and AC Characteristics
1.4
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
200
1.2
ICC
1.2
1.0
ICC
1.0
160
ISB3
0.8
ISB3
120
0.8
0.6
VCC =5.0V
VIN =5.0V
0.6
0.4
0.4
40
0.2
0.2
0.0
4.0
4.5
5.0
5.5
6.0
VCC =5.0V
TA =25°C
80
0
0.6
−55
25
0
125
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.4
1.6
1.3
1.4
2.0
3.0
4.0
5.0
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
1.2
1.2
80
1.1
1.0
60
1.0
TA =25°C
VCC =5.0V
40
0.8
0.9
0.8
4.0
4.5
5.0
5.5
6.0
0.6
−55
25
125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
0
0.0
1.0
4.0
5.0
NORMALIZED ICC vs. CYCLE TIME
VCC =5.0V
TA =25°C
VIN =0.5V
1.0
20.0
15.0
0.50
0.75
10.0
0.25
VCC =4.5V
TA =25°C
5.0
0.0
3.0
OUTPUT VOLTAGE (V)
25.0
0.75
2.0
1.25
30.0
1.00
VCC =5.0V
TA =25°C
20
0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
5.0
0
0
200
400
600
800 1000
CAPACITANCE (pF)
16
0.50
10
28
40
CYCLE FREQUENCY (MHz)
66
CY7C145
CY7C144
Ordering Information
8K x8 Dual-Port SRAM
Speed
(ns)
15
25
35
55
Ordering Code
Package
Name
Package Type
CY7C144-15AC
A65
64-Lead Thin Quad Flat Pack
CY7C144-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C144-25AC
A65
64-Lead Thin Quad Flat Pack
CY7C144-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C144-25AI
A65
64-Lead Thin Quad Flat Pack
CY7C144-25JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C144-35AC
A65
64-Lead Thin Quad Flat Pack
CY7C144-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C144-35AI
A65
64-Lead Thin Quad Flat Pack
CY7C144-35JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C144-55AC
A65
64-Lead Thin Quad Flat Pack
CY7C144-55JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C144-55AI
A65
64-Lead Thin Quad Flat Pack
CY7C144-55JI
J81
68-Lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
8K x9 Dual-Port SRAM
Speed
(ns)
Ordering Code
15
CY7C145-15AC
25
35
55
Package
Name
Package Type
A80
80-Lead Thin Quad Flat Pack
CY7C145-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C145-25AC
A80
80-Lead Thin Quad Flat Pack
CY7C145-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C145-25AI
A80
80-Lead Thin Quad Flat Pack
CY7C145-25JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C145-35AC
A80
80-Lead Thin Quad Flat Pack
CY7C145-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C145-35AI
A80
80-Lead Thin Quad Flat Pack
CY7C145-35JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C145-55AC
A80
80-Lead Thin Quad Flat Pack
CY7C145-55JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C145-55AI
A80
80-Lead Thin Quad Flat Pack
CY7C145-55JI
J81
68-Lead Plastic Leaded Chip Carrier
17
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7C145
CY7C144
Package Diagrams
64-Pin Thin Plastic Quad Flat Pack A65
80-Pin Thin Plastic Quad Flat Pack A80
18
CY7C145
CY7C144
Package Diagrams (continued)
68-Lead Plastic Leaded ChipCarrierJ81
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.