74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs tm Features General Description ■ High speed: fMAX = 140MHz (Typ.) at TA = 25°C ■ High noise immunity: VIH = 2.0V, VIL = 0.8V The VHCT374A is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. ■ Power down protection is provided on all inputs and outputs Low power dissipation: ICC = 4µA (Max.) @ TA = 25°C ■ ■ Pin and function compatible with 74HCT374 Protection circuits ensure that 0V to 7V can be applied to the input and output(1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Note: 1. Outputs in OFF-State. Ordering Information Order Number 74VHCT374AM 74VHCT374ASJ 74VHCT374AMTC Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Description Pin Names D0–D7 ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 Description Data Inputs CP Clock Pulse Input 3-STATE OE Output Enable Input 3-STATE O0–O7 Outputs www.fairchildsemi.com 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs May 2007 Functional Description IEEE/IEC The VHCT374A consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs Outputs OE On H L H L L L H Z Dn X CP X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 2 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Logic Symbol Symbol Parameter Rating VCC Supply Voltage –0.5V to +7.0V VIN DC Input Voltage –0.5V to +7.0V VOUT DC Output Voltage Note 2 –0.5V to VCC + 0.5V Note 3 –0.5V to +7.0V IIK Input Diode Current –20mA IOK Output Diode Current(4) ±20mA IOUT DC Output Current ±25mA ICC DC VCC / GND Current TSTG TL ±75mA Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 seconds) 260°C Recommended Operating Conditions(5) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT Parameter Rating Supply Voltage 4.5V to +5.5V Input Voltage 0V to +5.5V Output Voltage Note 2 0V to VCC Note 3 0V to 5.5V TOPR Operating Temperature –40°C to +85°C t r, t f Input Rise and Fall Time, VCC = 5.0V ± 0.5V 0ns/V ~ 20ns/V Notes: 2. HIGH or LOW state. IOUT absolute maximum rating must be observed. 3. When outputs are in OFF-State or when VCC = 0V. 4. VOUT < GND, VOUT > VCC (Outputs Active). 5. Unused inputs must be held HIGH or LOW. They may not float. ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 3 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = –40°C to +85°C TA = 25°C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 4.5 2.0 5.5 2.0 VIL LOW Level Input Voltage 2.0 V 2.0 0.8 0.8 5.5 0.8 0.8 4.5 LOW Level Output Voltage 4.5 IOZ 3-STATE Output OFF-State Current 5.5 VOL Min. Typ. Max. Min. Max. Units 4.5 HIGH Level Output Voltage VOH Conditions VIN = VIH IOH = –50µA or VIL IOH = –8mA 4.40 4.50 4.40 3.94 VIN = VIH IOL = +50µA or VIL IOL = +8mA V V 3.80 0.0 0.1 0.1 0.36 0.44 V VIN = VIH or VIL, VOUT = VCC or GND ±0.25 ±2.5 µA IIN Input Leakage Current 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA ICC Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 µA ICCT Maximum ICC /Input 5.5 VIN = 3.4V, Other Inputs = VCC or GND 1.35 1.50 mA IOFF Output Leakage Current (Power Down State) 0.0 VOUT = 5.5V 0.5 5.0 µA Noise Characteristics TA = 25°C Symbol Parameter VCC (V) Conditions Typ. Limits Units Quiet Output Maximum Dynamic VOL 5.0 CL = 50pF 1.2 1.6 V VOLV(6) Quiet Output Minimum Dynamic VOL 5.0 CL = 50pF –1.2 –1.6 V VIHD(6) Minimum HIGH Level Dynamic Input Voltage 5.0 CL = 50pF 2.0 V VILD(6) Maximum LOW Level Dynamic Input Voltage 5.0 CL = 50pF 0.8 V VOLP (6) Note: 6. Parameter guaranteed by design. ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 4 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs DC Electrical Characteristics TA = –40°C to +85°C TA = 25°C Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ Parameter Conditions Propagation Delay Time 5.0 ± 0.5 3-STATE Output Enable Time 5.0 ± 0.5 3-STATE Output Disable Time 5.0 ± 0.5 tOSLH, tOSHL Output to Output Skew fMAX VCC (V) Maximum Clock Frequency Min. Typ. Max. Min. Max. CL = 15pF 4.1 9.4 1.0 10.5 CL = 50pF 5.6 10.4 1.0 11.5 Units ns RL = 1kΩ CL = 15pF 6.5 10.2 1.0 11.5 CL = 50pF 7.3 11.2 1.0 12.5 RL = 1kΩ CL = 50pF 7.0 11.2 1.0 12.0 ns 1.0 ns 5.0 ± 0.5 (7) 1.0 5.0 ± 0.5 CL = 15pF 90 140 80 CL = 50pF 85 130 75 ns MHz Input Capacitance VCC = Open 4 COUT Output Capacitance VCC = 5.0V 9 pF CPD Power Dissipation Capacitance (8) 25 pF CIN 10 10 pF Notes: 7. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min| 8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pcs. of the octal D Flip-Flop operates can be calculated by the equation: CPD(total) = 20 + 12m AC Operating Requirements TA = 25°C Symbol Parameter tW(H), tW(L) Minimum Pulse Width (CP) Typ. Max. TA = –40°C to +85°C VCC (V) Min. Min. Max. Units 5.0 ± 0.5 6.5 8.5 ns tS Minimum Set-up Time 5.0 ± 0.5 2.5 2.5 ns tH Minimum Hold Time 5.0 ± 0.5 2.5 2.5 ns ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 5 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs AC Electrical Characteristics 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 6 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 7 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 8 ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ 2 E CMOS™ ® EcoSPARK EnSigna™ FACT Quiet Series™ ® FACT ® FAST FASTr™ FPS™ ® FRFET GlobalOptoisolator™ GTO™ HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ Motion-SPM™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC ® OPTOPLANAR PACMAN™ PDP-SPM™ POP™ ® Power220 ® Power247 PowerEdge™ PowerSaver™ Power-SPM™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ ® The Power Franchise TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ ® UHC UniFET™ VCX™ Wire™ ™ TinyBoost™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I27 ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 www.fairchildsemi.com 9 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.