TE X A S I NS TRUM E NTS - P RO DUCTION D ATA Stellaris® LM3S6730 Microcontroller D ATA SHE E T D S -LM 3S 6730 - 7 0 0 7 C opyri ght © 2007-2010 Texas Instruments Incorporated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table of Contents Revision History ............................................................................................................................. 16 About This Document .................................................................................................................... 20 Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 20 20 20 20 1 Architectural Overview .......................................................................................... 23 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 Product Features .......................................................................................................... Target Applications ........................................................................................................ High-Level Block Diagram ............................................................................................. Functional Overview ...................................................................................................... ARM Cortex™-M3 ......................................................................................................... Motor Control Peripherals .............................................................................................. Analog Peripherals ........................................................................................................ Serial Communications Peripherals ................................................................................ System Peripherals ....................................................................................................... Memory Peripherals ...................................................................................................... Additional Features ....................................................................................................... Hardware Details .......................................................................................................... 2 ARM Cortex-M3 Processor Core ........................................................................... 36 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Block Diagram .............................................................................................................. Functional Description ................................................................................................... Serial Wire and JTAG Debug ......................................................................................... Embedded Trace Macrocell (ETM) ................................................................................. Trace Port Interface Unit (TPIU) ..................................................................................... ROM Table ................................................................................................................... Memory Protection Unit (MPU) ....................................................................................... Nested Vectored Interrupt Controller (NVIC) .................................................................... 3 Memory Map ........................................................................................................... 42 4 Interrupts ................................................................................................................. 44 5 JTAG Interface ........................................................................................................ 47 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.4 5.4.1 5.4.2 Block Diagram .............................................................................................................. Functional Description ................................................................................................... JTAG Interface Pins ...................................................................................................... JTAG TAP Controller ..................................................................................................... Shift Registers .............................................................................................................. Operational Considerations ............................................................................................ Initialization and Configuration ....................................................................................... Register Descriptions .................................................................................................... Instruction Register (IR) ................................................................................................. Data Registers .............................................................................................................. 6 System Control ....................................................................................................... 59 6.1 6.1.1 Functional Description ................................................................................................... 59 Device Identification ...................................................................................................... 59 April 04, 2010 23 29 29 31 31 31 32 32 33 34 35 35 37 37 37 38 38 38 38 38 48 48 48 50 51 51 54 54 54 56 3 Texas Instruments-Production Data Table of Contents 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 Reset Control ................................................................................................................ Power Control ............................................................................................................... Clock Control ................................................................................................................ System Control ............................................................................................................. Initialization and Configuration ....................................................................................... Register Map ................................................................................................................ Register Descriptions .................................................................................................... 7 Internal Memory ................................................................................................... 116 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 7.6 Block Diagram ............................................................................................................ 116 Functional Description ................................................................................................. 116 SRAM Memory ............................................................................................................ 116 Flash Memory ............................................................................................................. 117 Flash Memory Initialization and Configuration ............................................................... 118 Flash Programming ..................................................................................................... 118 Nonvolatile Register Programming ............................................................................... 119 Register Map .............................................................................................................. 120 Flash Register Descriptions (Flash Control Offset) ......................................................... 120 Flash Register Descriptions (System Control Offset) ...................................................... 128 8 General-Purpose Input/Outputs (GPIOs) ........................................................... 141 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.3 8.4 Functional Description ................................................................................................. 141 Data Control ............................................................................................................... 142 Interrupt Control .......................................................................................................... 143 Mode Control .............................................................................................................. 144 Commit Control ........................................................................................................... 144 Pad Control ................................................................................................................. 144 Identification ............................................................................................................... 144 Initialization and Configuration ..................................................................................... 144 Register Map .............................................................................................................. 145 Register Descriptions .................................................................................................. 147 9 General-Purpose Timers ...................................................................................... 182 9.1 9.2 9.2.1 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 9.5 Block Diagram ............................................................................................................ Functional Description ................................................................................................. GPTM Reset Conditions .............................................................................................. 32-Bit Timer Operating Modes ...................................................................................... 16-Bit Timer Operating Modes ...................................................................................... Initialization and Configuration ..................................................................................... 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 16-Bit Input Edge Count Mode ..................................................................................... 16-Bit Input Edge Timing Mode .................................................................................... 16-Bit PWM Mode ....................................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 10 Watchdog Timer ................................................................................................... 218 10.1 10.2 Block Diagram ............................................................................................................ 219 Functional Description ................................................................................................. 219 4 59 62 64 67 68 68 69 182 183 184 184 185 189 189 190 190 191 191 192 192 193 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 10.3 10.4 10.5 Initialization and Configuration ..................................................................................... 220 Register Map .............................................................................................................. 220 Register Descriptions .................................................................................................. 221 11 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 242 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.3 11.4 11.5 Block Diagram ............................................................................................................ Functional Description ................................................................................................. Transmit/Receive Logic ............................................................................................... Baud-Rate Generation ................................................................................................. Data Transmission ...................................................................................................... Serial IR (SIR) ............................................................................................................. FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Loopback Operation .................................................................................................... IrDA SIR block ............................................................................................................ Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 12 Synchronous Serial Interface (SSI) .................................................................... 283 12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.3 12.4 12.5 Block Diagram ............................................................................................................ Functional Description ................................................................................................. Bit Rate Generation ..................................................................................................... FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Frame Formats ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 13 Ethernet Controller .............................................................................................. 320 13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.3 13.3.1 13.3.2 13.4 13.5 13.6 Block Diagram ............................................................................................................ 320 Functional Description ................................................................................................. 321 MAC Operation ........................................................................................................... 321 Internal MII Operation .................................................................................................. 325 PHY Operation ............................................................................................................ 325 Interrupts .................................................................................................................... 326 Initialization and Configuration ..................................................................................... 327 Hardware Configuration ............................................................................................... 327 Software Configuration ................................................................................................ 328 Ethernet Register Map ................................................................................................. 328 Ethernet MAC Register Descriptions ............................................................................. 330 MII Management Register Descriptions ......................................................................... 348 14 Analog Comparators ............................................................................................ 367 14.1 14.2 14.2.1 14.3 14.4 14.5 Block Diagram ............................................................................................................ Functional Description ................................................................................................. Internal Reference Programming .................................................................................. Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. April 04, 2010 243 243 243 244 245 245 246 246 247 247 247 248 249 283 283 284 284 284 285 292 293 294 367 368 368 369 370 370 5 Texas Instruments-Production Data Table of Contents 15 Pin Diagram .......................................................................................................... 378 16 Signal Tables ........................................................................................................ 380 16.1 16.2 100-Pin LQFP Package Pin Tables ............................................................................... 380 108-Pin BGA Package Pin Tables ................................................................................ 390 17 Operating Characteristics ................................................................................... 402 18 Electrical Characteristics .................................................................................... 403 18.1 18.1.1 18.1.2 18.1.3 18.1.4 18.1.5 18.1.6 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 18.2.8 18.2.9 DC Characteristics ...................................................................................................... 403 Maximum Ratings ....................................................................................................... 403 Recommended DC Operating Conditions ...................................................................... 403 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 404 GPIO Module Characteristics ....................................................................................... 404 Power Specifications ................................................................................................... 404 Flash Memory Characteristics ...................................................................................... 405 AC Characteristics ....................................................................................................... 406 Load Conditions .......................................................................................................... 406 Clocks ........................................................................................................................ 406 JTAG and Boundary Scan ............................................................................................ 407 Reset ......................................................................................................................... 409 Sleep Modes ............................................................................................................... 411 General-Purpose I/O (GPIO) ........................................................................................ 411 Synchronous Serial Interface (SSI) ............................................................................... 411 Ethernet Controller ...................................................................................................... 413 Analog Comparator ..................................................................................................... 416 A Serial Flash Loader .............................................................................................. 417 A.1 A.2 A.2.1 A.2.2 A.3 A.3.1 A.3.2 A.3.3 A.4 A.4.1 A.4.2 A.4.3 A.4.4 A.4.5 A.4.6 Serial Flash Loader ..................................................................................................... Interfaces ................................................................................................................... UART ......................................................................................................................... SSI ............................................................................................................................. Packet Handling .......................................................................................................... Packet Format ............................................................................................................ Sending Packets ......................................................................................................... Receiving Packets ....................................................................................................... Commands ................................................................................................................. COMMAND_PING (0X20) ............................................................................................ COMMAND_GET_STATUS (0x23) ............................................................................... COMMAND_DOWNLOAD (0x21) ................................................................................. COMMAND_SEND_DATA (0x24) ................................................................................. COMMAND_RUN (0x22) ............................................................................................. COMMAND_RESET (0x25) ......................................................................................... B Register Quick Reference ................................................................................... 422 C Ordering and Contact Information ..................................................................... 435 C.1 C.2 C.3 C.4 Ordering Information .................................................................................................... Part Markings .............................................................................................................. Kits ............................................................................................................................. Support Information ..................................................................................................... D Package Information ............................................................................................ 437 6 417 417 417 417 418 418 418 418 419 419 419 419 420 420 420 435 435 436 436 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 11-2. Figure 11-3. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 12-12. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 14-1. Figure 14-2. Figure 14-3. Figure 15-1. Figure 15-2. ® Stellaris LM3S6730 Microcontroller High-Level Block Diagram ............................. 30 CPU Block Diagram ............................................................................................. 37 TPIU Block Diagram ............................................................................................ 38 JTAG Module Block Diagram ................................................................................ 48 Test Access Port State Machine ........................................................................... 51 IDCODE Register Format ..................................................................................... 57 BYPASS Register Format .................................................................................... 57 Boundary Scan Register Format ........................................................................... 58 Basic RST Configuration ...................................................................................... 60 External Circuitry to Extend Power-On Reset ........................................................ 61 Reset Circuit Controlled by Switch ........................................................................ 61 Power Architecture .............................................................................................. 63 Main Clock Tree .................................................................................................. 65 Flash Block Diagram .......................................................................................... 116 GPIO Port Block Diagram ................................................................................... 142 GPIODATA Write Example ................................................................................. 143 GPIODATA Read Example ................................................................................. 143 GPTM Module Block Diagram ............................................................................ 183 16-Bit Input Edge Count Mode Example .............................................................. 187 16-Bit Input Edge Time Mode Example ............................................................... 188 16-Bit PWM Mode Example ................................................................................ 189 WDT Module Block Diagram .............................................................................. 219 UART Module Block Diagram ............................................................................. 243 UART Character Frame ..................................................................................... 244 IrDA Data Modulation ......................................................................................... 246 SSI Module Block Diagram ................................................................................. 283 TI Synchronous Serial Frame Format (Single Transfer) ........................................ 286 TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 286 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 287 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 287 Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 288 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 289 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 289 Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 290 MICROWIRE Frame Format (Single Frame) ........................................................ 291 MICROWIRE Frame Format (Continuous Transfer) ............................................. 292 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 292 Ethernet Controller ............................................................................................. 321 Ethernet Controller Block Diagram ...................................................................... 321 Ethernet Frame ................................................................................................. 322 Interface to an Ethernet Jack .............................................................................. 327 Analog Comparator Module Block Diagram ......................................................... 367 Structure of Comparator Unit .............................................................................. 368 Comparator Internal Reference Structure ............................................................ 369 100-Pin LQFP Package Pin Diagram .................................................................. 378 108-Ball BGA Package Pin Diagram (Top View) ................................................... 379 April 04, 2010 7 Texas Instruments-Production Data Table of Contents Figure 18-1. Figure 18-2. Figure 18-3. Figure 18-4. Figure 18-5. Figure 18-6. Figure 18-7. Figure 18-8. Figure 18-9. Figure 18-10. Load Conditions ................................................................................................ 406 JTAG Test Clock Input Timing ............................................................................. 408 JTAG Test Access Port (TAP) Timing .................................................................. 409 JTAG TRST Timing ............................................................................................ 409 External Reset Timing (RST) .............................................................................. 410 Power-On Reset Timing ..................................................................................... 410 Brown-Out Reset Timing .................................................................................... 410 Software Reset Timing ....................................................................................... 410 Watchdog Reset Timing ..................................................................................... 411 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 412 Figure 18-11. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 412 Figure 18-12. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 413 Figure 18-13. External XTLP Oscillator Characteristics ............................................................. 415 Figure D-1. 100-Pin LQFP Package ...................................................................................... 437 Figure D-2. 108-Ball BGA Package ...................................................................................... 439 8 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller List of Tables Table 1. Table 2. Table 3-1. Table 4-1. Table 4-2. Table 5-1. Table 5-2. Table 6-1. Table 7-1. Table 7-2. Table 7-3. Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Table 9-3. Table 10-1. Table 11-1. Table 12-1. Table 13-1. Table 13-2. Table 14-1. Table 14-2. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 16-5. Table 16-6. Table 16-7. Table 16-8. Table 17-1. Table 17-2. Table 17-3. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 18-5. Table 18-6. Table 18-7. Table 18-8. Table 18-9. Table 18-10. Table 18-11. Revision History .................................................................................................. 16 Documentation Conventions ................................................................................ 20 Memory Map ....................................................................................................... 42 Exception Types .................................................................................................. 44 Interrupts ............................................................................................................ 45 JTAG Port Pins Reset State ................................................................................. 49 JTAG Instruction Register Commands ................................................................... 54 System Control Register Map ............................................................................... 68 Flash Protection Policy Combinations ................................................................. 117 User-Programmable Flash Memory Resident Registers ....................................... 119 Flash Register Map ............................................................................................ 120 GPIO Pad Configuration Examples ..................................................................... 145 GPIO Interrupt Configuration Example ................................................................ 145 GPIO Register Map ........................................................................................... 146 Available CCP Pins ............................................................................................ 183 16-Bit Timer With Prescaler Configurations ......................................................... 186 Timers Register Map .......................................................................................... 192 Watchdog Timer Register Map ............................................................................ 220 UART Register Map ........................................................................................... 248 SSI Register Map .............................................................................................. 293 TX & RX FIFO Organization ............................................................................... 323 Ethernet Register Map ....................................................................................... 329 Internal Reference Voltage and ACREFCTL Field Values ..................................... 369 Analog Comparators Register Map ..................................................................... 370 Signals by Pin Number ....................................................................................... 380 Signals by Signal Name ..................................................................................... 383 Signals by Function, Except for GPIO ................................................................. 387 GPIO Pins and Alternate Functions ..................................................................... 389 Signals by Pin Number ....................................................................................... 390 Signals by Signal Name ..................................................................................... 394 Signals by Function, Except for GPIO ................................................................. 398 GPIO Pins and Alternate Functions ..................................................................... 400 Temperature Characteristics ............................................................................... 402 Thermal Characteristics ..................................................................................... 402 ESD Absolute Maximum Ratings ........................................................................ 402 Maximum Ratings .............................................................................................. 403 Recommended DC Operating Conditions ............................................................ 403 LDO Regulator Characteristics ........................................................................... 404 GPIO Module DC Characteristics ........................................................................ 404 Detailed Power Specifications ............................................................................ 405 Flash Memory Characteristics ............................................................................ 405 Phase Locked Loop (PLL) Characteristics ........................................................... 406 Actual PLL Frequency ........................................................................................ 406 Clock Characteristics ......................................................................................... 407 Crystal Characteristics ....................................................................................... 407 JTAG Characteristics ......................................................................................... 407 April 04, 2010 9 Texas Instruments-Production Data Table of Contents Table 18-12. Table 18-13. Table 18-14. Table 18-15. Table 18-16. Table 18-17. Table 18-18. Table 18-19. Table 18-20. Table 18-21. Table 18-22. Table 18-23. Table 18-24. Table 18-25. Table 18-26. Table C-1. Reset Characteristics ......................................................................................... Sleep Modes AC Characteristics ......................................................................... GPIO Characteristics ......................................................................................... SSI Characteristics ............................................................................................ 100BASE-TX Transmitter Characteristics ............................................................ 100BASE-TX Transmitter Characteristics (informative) ......................................... 100BASE-TX Receiver Characteristics ................................................................ 10BASE-T Transmitter Characteristics ................................................................ 10BASE-T Transmitter Characteristics (informative) ............................................. 10BASE-T Receiver Characteristics .................................................................... Isolation Transformers ....................................................................................... Ethernet Reference Crystal ................................................................................ External XTLP Oscillator Characteristics ............................................................. Analog Comparator Characteristics ..................................................................... Analog Comparator Voltage Reference Characteristics ........................................ Part Ordering Information ................................................................................... 10 409 411 411 411 413 413 413 414 414 414 414 415 416 416 416 435 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller List of Registers System Control .............................................................................................................................. 59 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Device Identification 0 (DID0), offset 0x000 ....................................................................... 70 Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 72 LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 73 Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 74 Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 75 Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 76 Reset Cause (RESC), offset 0x05C .................................................................................. 77 Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 78 XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 82 Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 83 Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 85 Device Identification 1 (DID1), offset 0x004 ....................................................................... 86 Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 88 Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 89 Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 91 Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 93 Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 95 Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 97 Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 98 Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 99 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 102 Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 104 Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 106 Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 108 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 110 Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 112 Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 113 Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 114 Internal Memory ........................................................................................................................... 116 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Flash Memory Address (FMA), offset 0x000 .................................................................... Flash Memory Data (FMD), offset 0x004 ......................................................................... Flash Memory Control (FMC), offset 0x008 ..................................................................... Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... USec Reload (USECRL), offset 0x140 ............................................................................ Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... User Debug (USER_DBG), offset 0x1D0 ......................................................................... User Register 0 (USER_REG0), offset 0x1E0 .................................................................. User Register 1 (USER_REG1), offset 0x1E4 .................................................................. Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... April 04, 2010 121 122 123 125 126 127 129 130 131 132 133 134 135 136 11 Texas Instruments-Production Data Table of Contents Register 15: Register 16: Register 17: Register 18: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 137 138 139 140 General-Purpose Input/Outputs (GPIOs) ................................................................................... 141 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 148 GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 149 GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 150 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 151 GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 152 GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 153 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 154 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 155 GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 156 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 157 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 159 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 160 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 161 GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 162 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 163 GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 164 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 165 GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 166 GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 167 GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 168 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 170 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 171 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 172 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 173 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 174 GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 175 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 176 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 177 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 178 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 179 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 180 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 181 General-Purpose Timers ............................................................................................................. 182 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ GPTM Control (GPTMCTL), offset 0x00C ........................................................................ GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 12 194 195 197 199 202 204 205 206 208 209 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 210 211 212 213 214 215 216 217 Watchdog Timer ........................................................................................................................... 218 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... Watchdog Value (WDTVALUE), offset 0x004 ................................................................... Watchdog Control (WDTCTL), offset 0x008 ..................................................................... Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. Watchdog Test (WDTTEST), offset 0x418 ....................................................................... Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 242 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: UART Data (UARTDR), offset 0x000 ............................................................................... UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... UART Flag (UARTFR), offset 0x018 ................................................................................ UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... UART Line Control (UARTLCRH), offset 0x02C ............................................................... UART Control (UARTCTL), offset 0x030 ......................................................................... UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... April 04, 2010 250 252 254 256 257 258 259 261 263 265 267 268 269 271 272 273 274 275 13 Texas Instruments-Production Data Table of Contents Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 276 277 278 279 280 281 282 Synchronous Serial Interface (SSI) ............................................................................................ 283 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. SSI Control 1 (SSICR1), offset 0x004 .............................................................................. SSI Data (SSIDR), offset 0x008 ...................................................................................... SSI Status (SSISR), offset 0x00C ................................................................................... SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 295 297 299 300 302 303 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 Ethernet Controller ...................................................................................................................... 320 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 14 331 334 335 336 337 339 340 341 343 344 345 346 347 348 349 351 353 354 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 ............................................................................................................................. Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 ..................................................................................................... Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 ............................................................................................................................. Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 .............................................................................................................................. Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 355 357 358 359 361 363 364 365 366 Analog Comparators ................................................................................................................... 367 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... April 04, 2010 371 372 373 374 375 375 376 376 15 Texas Instruments-Production Data Revision History Revision History The revision history table notes changes made between the indicated revisions of the LM3S6730 data sheet. Table 1. Revision History Date Revision March 2008 2550 Description Started tracking revision history. April 2008 2881 ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating Characteristics chapter. ■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock. ■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical Characteristics" chapter. ■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter. ■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical Characteristics" chapter was changed from 4 to 3. ■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data sheets incorrectly noted it as 30 kHz ± 30%). ■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value. ■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly noted the reset was 0x0 (MOSC). ■ A note on high-current applications was added to the GPIO chapter: For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. ■ A note on Schmitt inputs was added to the GPIO chapter: Pins configured as digital inputs are Schmitt-triggered. ■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables. ■ The "Differential Sampling Range" figures in the ADC chapter were clarified. ■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected: ■ – The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins. – The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams. Additional minor data sheet clarifications and corrections. 16 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 1. Revision History (continued) Date Revision May 2008 2972 July 2008 August 2008 October 2008 November 2008 January 2009 April 2009 3108 3447 4149 4283 4660 5367 Description ■ As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported: TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit fields in the MR23 register are now marked as reserved. ■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use the LDO output as the source of VDD25 input. ■ As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS. A 12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future device revisions (see “Functional Description” on page 321). ■ Additional minor data sheet clarifications and corrections. ■ Corrected resistor value in ERBIAS signal description. ■ Additional minor data sheet clarifications and corrections. ■ Added note on clearing interrupts to Interrupts chapter. ■ Added Power Architecture diagram to System Control chapter. ■ Additional minor data sheet clarifications and corrections. ■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG) register. ■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the Internal Memory chapter. The correct value is 0x0000.0006. ■ In the Ethernet chapter, major improvements were made including a rewrite of the conceptual information and the addition of new figures to clarify how to use the Ethernet Controller interface. ■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter. ■ Revised High-Level Block Diagram. ■ Additional minor data sheet clarifications and corrections were made. ■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W. ■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there is no data in the TX FIFO. ■ Added "Hardware Configuration" section to Ethernet Controller chapter. ■ Additional minor data sheet clarifications and corrections. ■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 53). ■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. ■ Added "GPIO Module DC Characteristics" table (see Table 18-4 on page 404). ■ Additional minor data sheet clarifications and corrections. April 04, 2010 17 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision July 2009 5902 Description ■ Clarified Power-on reset and RST pin operation; added new diagrams. ■ Clarified explanation of nonvolatile register programming in Internal Memory chapter. ■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1 registers. ■ Added description for Ethernet PHY power-saving modes. ■ Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register. ■ Changed buffer type for WAKE pin to TTL and HIB pin to OD. ■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR (Internal voltage reference error) parameter. ■ Additional minor data sheet clarifications and corrections. July 2009 5920 Corrected ordering numbers. October 2009 6462 ■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers because the module resets in 32-bit mode. ■ Made these changes to the Electrical Characteristics chapter: January 2010 6712 – Removed VSIH and VSIL parameters from Operating Conditions table. – Added table showing actual PLL frequency depending on input crystal. – Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS. – Changed SSI set up and hold times to be expressed in system clocks, not ns. ■ In "System Control" section, clarified Debug Access Port operation after Sleep modes. ■ Clarified wording on Flash memory access errors. ■ Added section on Flash interrupts. ■ Clarified operation of SSI transmit FIFO. ■ Made these changes to the Operating Characteristics chapter: ■ – Added storage temperature ratings to "Temperature Characteristics" table – Added "ESD Absolute Maximum Ratings" table Made these changes to the Electrical Characteristics chapter: – In "Flash Memory Characteristics" table, corrected Mass erase time – Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) – In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time 18 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 1. Revision History (continued) Date Revision April 2010 7007 Description ■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed field width to 7 bits. ■ Removed erroneous text about restoring the Flash Protection registers. ■ Added note about RST signal routing. ■ Clarified the function of the TnSTALL bit in the GPTMCTL register. ■ Corrected XTALNPHY pin description. ■ Additional minor data sheet clarifications and corrections. April 04, 2010 19 Texas Instruments-Production Data About This Document About This Document This data sheet provides reference information for the LM3S6730 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents ® The following related documents are available on the documentation CD or from the Stellaris web site at www.ti.com/stellaris: ■ ARM® CoreSight Technical Reference Manual ■ ARM® Cortex™-M3 Errata ■ ARM® Cortex™-M3 Technical Reference Manual ■ ARM® v7-M Architecture Application Level Reference Manual ■ Stellaris® Graphics Library User's Guide ■ Stellaris® Peripheral Driver Library User's Guide ■ Stellaris® Errata The following related documents are also referenced: ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 2 on page 20. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. bit A single bit in a register. 20 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 2. Documentation Conventions (continued) Notation Meaning bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 42. Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1S Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). deassert a signal Change the value of the signal from the logically True state to the logically False state. SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. Numbers April 04, 2010 21 Texas Instruments-Production Data About This Document Table 2. Documentation Conventions (continued) Notation Meaning X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. 0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 22 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 1 Architectural Overview ® The Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. ® The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity ® capabilities. The Stellaris LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC and PHY available in an ARM architecture MCU. The LM3S6730 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. In addition, the LM3S6730 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S6730 microcontroller is code-compatible ® to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page ® 435 for ordering information for Stellaris family devices. 1.1 Product Features The LM3S6730 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 50-MHz operation – Hardware-division and single-cycle-multiplication – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 21 interrupts with eight priority levels April 04, 2010 23 Texas Instruments-Production Data Architectural Overview – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ ARM® Cortex™-M3 Processor Core – Compact core. – Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. – Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. – Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. – Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining – Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. – Migration from the ARM7™ processor family for better performance and power efficiency. – Full-featured debug solution • Serial Wire JTAG Debug Port (SWJ-DP) • Flash Patch and Breakpoint (FPB) unit for implementing breakpoints • Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling • Instrumentation Trace Macrocell (ITM) for support of printf style debugging • Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer – Optimized for single-cycle flash usage – Three sleep modes with clock gating for low power – Single-cycle multiply instruction and hardware divide – Atomic operations – ARM Thumb2 mixed 16-/32-bit instruction set – 1.25 DMIPS/MHz ■ JTAG 24 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller – IEEE 1149.1-1990 compatible Test Access Port (TAP) controller – Four-bit Instruction Register (IR) chain for storing JTAG instructions – IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST – ARM additional instructions: APACC, DPACC and ABORT – Integrated ARM Serial Wire Debug (SWD) ■ Internal Memory – 128 KB single-cycle flash • User-managed flash block protection on a 2-KB block basis • User-managed flash data programming • User-defined and managed flash-protection block – 64 KB single-cycle SRAM ■ GPIOs – 23-46 GPIOs, depending on configuration – 5-V-tolerant input/outputs – Programmable control for GPIO interrupts • Interrupt generation masking • Edge-triggered on rising, falling, or both • Level-sensitive on High or Low values – Bit masking in both read and write operations through address lines – Pins configured as digital inputs are Schmitt-triggered. – Programmable control for GPIO pad configuration • Weak pull-up or pull-down resistors • 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications • Slew rate control for the 8-mA drive • Open drain enables • Digital input enables ■ General-Purpose Timers – Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: April 04, 2010 25 Texas Instruments-Production Data Architectural Overview • As a single 32-bit timer • As one 32-bit Real-Time Clock (RTC) to event capture • For Pulse Width Modulation (PWM) – 32-bit Timer modes • Programmable one-shot timer • Programmable periodic timer • Real-Time Clock when using an external 32.768-KHz clock as the input • User-enabled stalling when the controller asserts CPU Halt flag during debug – 16-bit Timer modes • General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) • Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug – 16-bit Input Capture modes • Input edge count capture • Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ UART – Fully programmable 16C550-type UART with IrDA support – Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading 26 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller – Programmable baud-rate generator allowing speeds up to 3.125 Mbps – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – False-start bit detection – Line-break generation and detection – Fully programmable serial interface characteristics • 5, 6, 7, or 8 data bits • Even, odd, stick, or no-parity bit generation/detection • 1 or 2 stop bit generation – IrDA serial-IR (SIR) encoder/decoder providing • Programmable use of IrDA Serial Infrared (SIR) or UART input/output • Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex • Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations • Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Synchronous Serial Interface (SSI) – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing ■ 10/100 Ethernet Controller – Conforms to the IEEE 802.3-2002 specification • 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line • 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler • Full-featured auto-negotiation April 04, 2010 27 Texas Instruments-Production Data Architectural Overview – Multiple operational modes • Full- and half-duplex 100 Mbps • Full- and half-duplex 10 Mbps • Power-saving and power-down modes – Highly configurable • Programmable MAC address • LED activity selection • Promiscuous mode support • CRC error-rejection control • User-configurable interrupts – Physical media manipulation • Automatic MDI/MDI-X cross-over correction • Register-programmable transmit amplitude • Automatic polarity correction and 10BASE-T signal reception ■ Analog Comparators – Two independent integrated analog comparators – Configurable for output to drive an output pin or generate an interrupt – Compare external pin input to external pin input or to internal programmable voltage reference – Compare a test voltage against any one of these voltages • An individual external reference voltage • A shared single external reference voltage • A shared internal reference voltage ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources 28 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller – Power-on reset (POR) – Reset pin assertion – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package ■ Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram ® Figure 1-1 on page 30 depicts the features on the Stellaris LM3S6730 microcontroller. April 04, 2010 29 Texas Instruments-Production Data Architectural Overview ® Figure 1-1. Stellaris LM3S6730 Microcontroller High-Level Block Diagram JTAG/SWD ARM® Cortex™-M3 System Control and Clocks DCode bus Flash (128 KB) (50 MHz) ICode bus NVIC MPU System Bus LM3S6730 Bus Matrix SRAM (64 KB) SYSTEM PERIPHERALS GeneralPurpose Timers (3) Watchdog Timer (1) SSI (1) Advanced Peripheral Bus (APB) GPIOs (23-46) SERIAL PERIPHERALS UART (1) Ethernet MAC/PHY ANALOG PERIPHERALS Analog Comparators (2) 30 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 1.4 Functional Overview The following sections provide an overview of the features of the LM3S6730 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 435. 1.4.1 ARM Cortex™-M3 1.4.1.1 Processor Core (see page 36) ® All members of the Stellaris product family, including the LM3S6730 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. “ARM Cortex-M3 Processor Core” on page 36 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.1.2 System Timer (SysTick) (see page 39) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 Nested Vectored Interrupt Controller (NVIC) (see page 44) The LM3S6730 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 21 interrupts. “Interrupts” on page 44 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S6730 controller features Pulse Width Modulation (PWM) outputs. April 04, 2010 31 Texas Instruments-Production Data Architectural Overview 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S6730, PWM motion control functionality can be achieved through: ■ The motion control features of the general-purpose timers using the CCP pins CCP Pins (see page 188) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.3 Analog Peripherals For support of analog signals, the LM3S6730 microcontroller offers two analog comparators. 1.4.3.1 Analog Comparators (see page 367) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S6730 microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt . A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. 1.4.4 Serial Communications Peripherals The LM3S6730 controller supports both asynchronous and synchronous serial communications with: ■ One fully programmable 16C550-type UART ■ One SSI module ■ Ethernet controller 1.4.4.1 UART (see page 242) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. 32 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller The LM3S6730 controller includes one fully programmable 16C550-type UARTthat supports data transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 283) Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications interface. The LM3S6730 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 Ethernet Controller (see page 320) Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction. 1.4.5 System Peripherals 1.4.5.1 Programmable GPIOs (see page 141) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. ® The Stellaris GPIO module is comprised of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 23-46 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 380 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in April 04, 2010 33 Texas Instruments-Production Data Architectural Overview both read and write operations through address lines. Pins configured as digital inputs are Schmitt-triggered. 1.4.5.2 Three Programmable Timers (see page 182) Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (see page 218) A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. ® The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S6730 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.6.1 SRAM (see page 116) The LM3S6730 static random access memory (SRAM) controller supports 64 KB SRAM. The internal ® SRAM of the Stellaris devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (see page 117) The LM3S6730 Flash controller supports 128 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 34 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 1.4.7 Additional Features 1.4.7.1 Memory Map (see page 42) A memory map lists the location of instructions and data in memory. The memory map for the LM3S6730 controller can be found in “Memory Map” on page 42. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map. 1.4.7.2 JTAG TAP Controller (see page 47) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. ® The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG ® ® instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO ® outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive ® programming for the ARM, Stellaris , and unimplemented JTAG instructions. 1.4.7.3 System Control and Clocks (see page 59) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 378 ■ “Signal Tables” on page 380 ■ “Operating Characteristics” on page 402 ■ “Electrical Characteristics” on page 403 ■ “Package Information” on page 437 April 04, 2010 35 Texas Instruments-Production Data ARM Cortex-M3 Processor Core 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer ■ Optimized for single-cycle flash usage ■ Three sleep modes with clock gating for low power ■ Single-cycle multiply instruction and hardware divide ■ Atomic operations ■ ARM Thumb2 mixed 16-/32-bit instruction set ■ 1.25 DMIPS/MHz ® The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. 36 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual. 2.1 Block Diagram Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep ARM Cortex-M3 CM3 Core Debug Instructions Data Trace Port Interface Unit Memory Protection Unit Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace 2.2 Adv. HighPerf. Bus Access Port Private Peripheral Bus (external) ROM Table Private Peripheral Bus (internal) Serial Wire JTAG Debug Port Serial Wire Output Trace Port (SWO) Adv. Peripheral Bus Bus Matrix I-code bus D-code bus System bus Functional Description Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. ® This section describes the Stellaris implementation. Texas Instruments has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 37. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow. 2.2.1 Serial Wire and JTAG Debug Texas Instruments has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. April 04, 2010 37 Texas Instruments-Production Data ARM Cortex-M3 Processor Core 2.2.2 Embedded Trace Macrocell (ETM) ® ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace ® Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2 on page 38. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram 2.2.4 Debug ATB Slave Port ATB Interface APB Slave Port APB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The Memory Protection Unit (MPU) is included on the LM3S6730 controller and supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC): ■ Facilitates low-latency exception and interrupt handling ■ Controls power management ■ Implements system control registers 38 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference Manual). Any other user-mode access causes a bus fault. All NVIC registers are accessible using byte, halfword, and word unless otherwise stated. 2.2.6.1 Interrupts The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The LM3S6730 microcontroller supports 21 interrupts with eight priority levels. 2.2.6.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. Functional Description The timer consists of three registers: ■ A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ The reload value for the counter, used to provide the counter's wrap value. ■ The current value of the counter. ® A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris devices. When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks. Writing a value of zero to the Reload Value register disables the counter on the next wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. April 04, 2010 39 Texas Instruments-Production Data ARM Cortex-M3 Processor Core If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect to a reference clock. The reference clock can be the core clock or an external clock source. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The reset is 0x0000.0000. Bit/Field Name Type Reset Description 31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 COUNTFLAG R/W 0 Count Flag Returns 1 if timer counted to 0 since last time this was read. Clears on read by application. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 15:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 CLKSOURCE R/W 0 Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 Core clock If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are unpredictable. 1 TICKINT R/W 0 Tick Interrupt Value Description 0 ENABLE R/W 0 0 Counting down to 0 does not generate the interrupt request to the NVIC. Software can use the COUNTFLAG to determine if ever counted to 0. 1 Counting down to 0 pends the SysTick handler. Enable Value Description 0 Counter disabled. 1 Counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. SysTick Reload Value Register Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. 40 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. For example, if a tick is next required after 400 clock pulses, 400 must be written into the RELOAD. Bit/Field Name Type Reset Description 31:24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 RELOAD R/W - Reload Value to load into the SysTick Current Value Register when the counter reaches 0. SysTick Current Value Register Use the SysTick Current Value Register to find the current value in the register. Bit/Field Name Type Reset Description 31:24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 CURRENT W1C - Current Value Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. SysTick Calibration Value Register The SysTick Calibration Value register is not implemented. April 04, 2010 41 Texas Instruments-Production Data Memory Map 3 Memory Map The memory map for the LM3S6730 controller is provided in Table 3-1 on page 42. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. a Table 3-1. Memory Map Start End Description 0x0000.0000 0x0001.FFFF On-chip flash 0x0002.0000 0x1FFF.FFFF Reserved For details on registers, see page ... Memory b 120 c 0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAM 120 0x2001.0000 0x21FF.FFFF Reserved - 0x2200.0000 0x221F.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 116 0x2220.0000 0x3FFF.FFFF Reserved - 0x4000.0000 0x4000.0FFF Watchdog timer 221 0x4000.1000 0x4000.3FFF Reserved - 0x4000.4000 0x4000.4FFF GPIO Port A 147 0x4000.5000 0x4000.5FFF GPIO Port B 147 0x4000.6000 0x4000.6FFF GPIO Port C 147 0x4000.7000 0x4000.7FFF GPIO Port D 147 0x4000.8000 0x4000.8FFF SSI0 294 0x4000.9000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 249 0x4000.D000 0x4001.FFFF Reserved - 0x4002.0000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 147 0x4002.5000 0x4002.5FFF GPIO Port F 147 0x4002.6000 0x4002.6FFF GPIO Port G 147 0x4002.7000 0x4002.FFFF Reserved - 0x4003.0000 0x4003.0FFF Timer0 193 0x4003.1000 0x4003.1FFF Timer1 193 0x4003.2000 0x4003.2FFF Timer2 193 0x4003.3000 0x4003.BFFF Reserved - 0x4003.C000 0x4003.CFFF Analog Comparators 367 0x4003.D000 0x4004.7FFF Reserved - 0x4004.8000 0x4004.8FFF Ethernet Controller 330 0x4004.9000 0x400F.CFFF Reserved - 0x400F.D000 0x400F.DFFF Flash control 120 FiRM Peripherals Peripherals 42 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 3-1. Memory Map (continued) Start End Description For details on registers, see page ... 0x400F.E000 0x400F.EFFF System control 69 0x400F.F000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0xDFFF.FFFF Reserved - 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) ARM® Cortex™-M3 Technical Reference Manual 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) ARM® Cortex™-M3 Technical Reference Manual 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) ARM® Cortex™-M3 Technical Reference Manual 0xE000.3000 0xE000.DFFF Reserved - 0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC) ARM® Cortex™-M3 Technical Reference Manual 0xE000.F000 0xE003.FFFF Reserved - 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) ARM® Cortex™-M3 Technical Reference Manual 0xE004.1000 0xFFFF.FFFF Reserved - Private Peripheral Bus a. All reserved space returns a bus fault when read or written. b. The unavailable flash will bus fault throughout this range. c. The unavailable SRAM will bus fault throughout this range. April 04, 2010 43 Texas Instruments-Production Data Interrupts 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 on page 44 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 21 interrupts (listed in Table 4-2 on page 45). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You also can group priorities by splitting priority levels into pre-emption priorities and subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. Important: It may take several processor cycles after a write to clear an interrupt source in order for NVIC to see the interrupt source de-assert. This means if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts. Table 4-1. Exception Types Exception Type Vector Number a Description Stack top is loaded from first entry of vector table on reset. Priority - 0 - Reset 1 -3 (highest) Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. Non-Maskable Interrupt (NMI) 2 -2 Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producible by software, using the NVIC Interrupt Control State register. Hard Fault 3 -1 Memory Management 4 settable All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed. 44 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 4-1. Exception Types (continued) Exception Type a Vector Number Bus Fault Priority 5 Description settable Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Usage Fault 6 - settable Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. 7-10 - SVCall 11 settable System service call with SVC instruction. This is synchronous. Debug Monitor 12 settable Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. - 13 - PendSV 14 settable Pendable request for system service. This is asynchronous and only pended by software. SysTick 15 settable System tick timer has fired. This is asynchronous. 16 and above settable Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 on page 45 lists the interrupts on the LM3S6730 controller. Interrupts Reserved. Reserved. a. 0 is the default priority for all the settable priorities. Table 4-2. Interrupts Vector Number Interrupt Number (Bit in Interrupt Registers) Description 0-15 - Processor exceptions 16 0 GPIO Port A 17 1 GPIO Port B 18 2 GPIO Port C 19 3 GPIO Port D 20 4 GPIO Port E 21 5 UART0 22 6 Reserved 23 7 SSI0 24-33 8-17 34 18 Watchdog timer 35 19 Timer0 A 36 20 Timer0 B 37 21 Timer1 A 38 22 Timer1 B 39 23 Timer2 A 40 24 Timer2 B 41 25 Analog Comparator 0 42 26 Analog Comparator 1 43 27 Reserved 44 28 System Control Reserved April 04, 2010 45 Texas Instruments-Production Data Interrupts Table 4-2. Interrupts (continued) Vector Number Interrupt Number (Bit in Interrupt Registers) Description 45 29 Flash Control 46 30 GPIO Port F 47 31 GPIO Port G 48-57 32-41 58 42 59-70 43-54 Reserved Ethernet Controller Reserved 46 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. ® The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG ® ® instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO ® outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive ® programming for the ARM, Stellaris , and unimplemented JTAG instructions. ® The Stellaris JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG controller. April 04, 2010 47 Texas Instruments-Production Data JTAG Interface 5.1 Block Diagram Figure 5-1. JTAG Module Block Diagram TRST TCK TMS TDI TAP Controller Instruction Register (IR) BYPASS Data Register TDO Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register Cortex-M3 Debug Port 5.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 48. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 54 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 407 for JTAG timing diagrams. 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1 on page 49. Detailed information on each pin follows. 48 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 5-1. JTAG Port Pins Reset State 5.2.1.1 Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TRST Input Enabled Disabled N/A N/A TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 5.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 5.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2 on page 51. By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. April 04, 2010 49 Texas Instruments-Production Data JTAG Interface 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 5.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 5-2 on page 51. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. 50 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 5-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 0 Select DR Scan 1 Select IR Scan 1 0 1 Capture DR 1 Capture IR 0 0 Shift DR Shift IR 0 1 Exit 1 DR Exit 1 IR 1 Pause IR 0 1 Exit 2 DR 0 1 0 Exit 2 IR 1 1 Update DR 5.2.3 1 0 Pause DR 1 0 1 0 0 1 0 0 Update IR 1 0 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 54. 5.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. April 04, 2010 51 Texas Instruments-Production Data JTAG Interface 5.2.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 157) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 167) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 168) have been set to 1. Recovering a "Locked" Device Note: Performing the sequence below causes the nonvolatile registers discussed in “Nonvolatile Register Programming” on page 119 to be restored to their factory default values. The mass erase of the flash memory caused by the below sequence occurs prior to the nonvolatile registers being restored. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Perform the JTAG-to-SWD switch sequence. 3. Perform the SWD-to-JTAG switch sequence. 4. Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. 52 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 11. Perform the SWD-to-JTAG switch sequence. 12. Release the RST signal. 13. Wait 400 ms. 14. Power-cycle the device. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 53. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence in the section called “JTAG-to-SWD Switching” on page 53 must be performed. 5.2.4.2 Communication with JTAG/SWD Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. 5.2.4.3 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. April 04, 2010 53 Texas Instruments-Production Data JTAG Interface 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 5.3 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG pins (PB7 andPC[3:0]) should be reverted to their default settings. 5.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 5.4.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2 on page 54. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 5-2. JTAG Instruction Register Commands IR[3:0] Instruction 0000 EXTEST Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0001 INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 54 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 5-2. JTAG Instruction Register Commands (continued) 5.4.1.1 IR[3:0] Instruction 0010 SAMPLE / PRELOAD Description Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. 1000 ABORT Shifts data into the ARM Debug Port Abort Register. 1010 DPACC Shifts data into and out of the ARM DP Access Register. 1011 APACC Shifts data into and out of the ARM AC Access Register. 1110 IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 1111 BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. EXTEST Instruction The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 5.4.1.2 INTEST Instruction The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 5.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with April 04, 2010 55 Texas Instruments-Production Data JTAG Interface each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 57 for more information. 5.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 58 for more information. 5.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 58 for more information. 5.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 58 for more information. 5.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 57 for more information. 5.4.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 57 for more information. 5.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 56 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 5.4.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-3 on page 57. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 5-3. IDCODE Register Format 31 TDI 5.4.2.2 28 27 12 11 Version Part Number 1 0 Manufacturer ID 1 TDO BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-4 on page 57. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. Figure 5-4. BYPASS Register Format 0 TDI 5.4.2.3 0 TDO Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 58. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. April 04, 2010 57 Texas Instruments-Production Data JTAG Interface Figure 5-5. Boundary Scan Register Format TDI I N O U T O E ... GPIO PB6 5.4.2.4 I N O U T GPIO m O E I N RST I N O U T GPIO m+1 O E ... I N O U T O TDO E GPIO n APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 58 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 59 ■ Local control, such as reset (see “Reset Control” on page 59), power (see “Power Control” on page 62) and clock control (see “Clock Control” on page 64) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 67 6.1.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 6.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 6.1.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion, see “External RST Pin” on page 60. 2. Power-on reset (POR), see “Power-On Reset (POR)” on page 59. 3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 61. 4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 62. 5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 62. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. 6.1.2.3 Power-On Reset (POR) Note: The power-on reset also resets the JTAG controller. An external reset does not. April 04, 2010 59 Texas Instruments-Production Data System Control The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 60. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset timing is shown in Figure 18-6 on page 410. 6.1.2.4 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 6-1 on page 60. Figure 6-1. Basic RST Configuration VDD Stellaris® RPU RST RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see “JTAG Interface” on page 47). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see “Reset” on page 409). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 6-2 on page 61. 60 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 6-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RPU RST C1 RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF If the application requires the use of an external reset switch, Figure 6-3 on page 61 shows the proper circuitry to use. Figure 6-3. Reset Circuit Controlled by Switch VDD Stellaris® RPU RST C1 RS Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 18-5 on page 410. 6.1.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivalent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt April 04, 2010 61 Texas Instruments-Production Data System Control handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 18-7 on page 410. 6.1.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 67). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 18-8 on page 410. 6.1.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The watchdog reset timing is shown in Figure 18-9 on page 411. 6.1.3 Power Control ® The Stellaris microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides 62 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Figure 6-4 on page 63 shows the power architecture. Note: On the printed circuit board, use the LDO output as the source of VDD25 input. In addition, the LDO requires decoupling capacitors. See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 404. Figure 6-4. Power Architecture VDD VCCPHY VCCPHY VCCPHY GNDPHY Ethernet PHY VCCPHY VDD25 GNDPHY GNDPHY VDD25 VDD25 GNDPHY GND Internal Logic and PLL VDD25 GND GND GND LDO Low-noise LDO +3.3V VDDA VDDA Analog circuits (ADC, analog comparators) VDD GNDA GND VDD VDD GNDA GND I/O Buffers VDD GND GND April 04, 2010 63 Texas Instruments-Production Data System Control 6.1.4 Clock Control System control determines the control of clocks in this part. 6.1.4.1 Fundamental Clock Sources There are multiple clock sources for use in the device: ■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit field in the RCC register (see page 78). ■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. Figure 6-5 on page 65 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. 64 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 6-5. Main Clock Tree USEPWMDIV a PWMDW a PWM Clock XTALa PWRDN b MOSCDIS a PLL (400 MHz) Main OSC USESYSDIV a,d ÷2 IOSCDIS a System Clock Internal OSC (12 MHz) SYSDIV b,d ÷4 BYPASS Internal OSC (30 kHz) Hibernation Module (32.768 kHz) b,d PWRDN OSCSRC b,d ADC Clock ÷ 25 ÷ 50 CAN Clock a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. Note: 6.1.4.2 The figure above shows all features available on all Stellaris® Fury-class devices. Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 78) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. April 04, 2010 65 Texas Instruments-Production Data System Control 6.1.4.3 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency, and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 82). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 18-8 on page 406 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) on page 78 describes the available crystal choices and default programming of the PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 6.1.4.4 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 78 and page 83). 6.1.4.5 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 18-7 on page 406). During the relock time, the affected PLL is not usable as a clock reference. The PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. 66 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 6.1.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. There are four levels of operation for the device defined as: ■ Run Mode. In Run mode, the controller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. April 04, 2010 67 Texas Instruments-Production Data System Control Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. 6.2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 6.3 Register Map Table 6-1 on page 68 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 6-1. System Control Register Map Description See page Offset Name Type Reset 0x000 DID0 RO - Device Identification 0 70 0x004 DID1 RO - Device Identification 1 86 0x008 DC0 RO 0x00FF.003F Device Capabilities 0 88 0x010 DC1 RO 0x0000.309F Device Capabilities 1 89 68 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 6-1. System Control Register Map (continued) Offset Name 0x014 Reset DC2 RO 0x0307.0011 Device Capabilities 2 91 0x018 DC3 RO 0x8F00.0FC0 Device Capabilities 3 93 0x01C DC4 RO 0x5000.007F Device Capabilities 4 95 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 72 0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 73 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 112 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 113 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 114 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 74 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 75 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 76 0x05C RESC R/W - Reset Cause 77 0x060 RCC R/W 0x0780.3AD1 Run-Mode Clock Configuration 78 0x064 PLLCFG RO - XTAL to PLL Translation 82 0x070 RCC2 R/W 0x0780.2810 Run-Mode Clock Configuration 2 83 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 97 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 100 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 106 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 98 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 102 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 108 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 99 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 104 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 110 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 85 6.4 Description See page Type Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. April 04, 2010 69 Texas Instruments-Production Data System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset 31 30 28 27 26 VER reserved Type Reset 29 25 24 23 22 21 20 reserved 18 17 16 CLASS RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - MAJOR Type Reset 19 MINOR Bit/Field Name Type Reset 31 reserved RO 0 30:28 VER RO 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description 0x1 Second version of the DID0 register format. 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 CLASS RO 0x1 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x1 Stellaris® Fury-class devices. 70 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 15:8 MAJOR RO - Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 7:0 MINOR RO - Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. April 04, 2010 71 Texas Instruments-Production Data System Control Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORIOR reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 BORIOR R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 72 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 VADJ Bit/Field Name Type Reset 31:6 reserved RO 0 5:0 VADJ R/W 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value VOUT (V) 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 April 04, 2010 73 Texas Instruments-Production Data System Control Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORRIS reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PLLLRIS RO 0 RO 0 reserved Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORRIS RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 74 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORIM reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset PLLLIM RO 0 R/W 0 reserved Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLIM R/W 0 PLL Lock Interrupt Mask This bit specifies whether a PLL Lock interrupt is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORIM R/W 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 75 Texas Instruments-Production Data System Control Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 74). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORMIS reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset reserved Type Reset PLLLMIS RO 0 R/W1C 0 reserved Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLMIS R/W1C 0 PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORMIS R/W1C 0 BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 76 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SW WDT BOR POR EXT RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - R/W - reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SW R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 3 WDT R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 2 BOR R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 1 POR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 0 EXT R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. April 04, 2010 77 Texas Instruments-Production Data System Control Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x0780.3AD1 31 30 29 28 26 25 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 15 14 13 12 11 10 PWRDN reserved BYPASS reserved R/W 1 RO 1 R/W 1 RO 0 reserved Type Reset reserved Type Reset RO 0 RO 0 27 24 23 R/W 1 R/W 1 R/W 1 9 8 R/W 1 R/W 0 ACG 21 20 19 R/W 0 RO 0 RO 0 RO 0 7 6 5 4 3 R/W 1 R/W 1 R/W 0 R/W 1 RO 0 SYSDIV 22 Name Type Reset 31:28 reserved RO 0x0 27 ACG R/W 0 17 16 RO 0 RO 0 RO 0 2 1 0 reserved USESYSDIV XTAL Bit/Field 18 OSCSRC reserved RO 0 IOSCDIS MOSCDIS R/W 0 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 78 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 26:23 SYSDIV R/W 0xF Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. Although the PLL VCO frequency is 400 MHz, it is predivided by 2 before the divisor is applied. Value Divisor (BYPASS=1) Frequency (BYPASS=0) 0x0 reserved reserved 0x1 /2 reserved 0x2 /3 reserved 0x3 /4 50 MHz 0x4 /5 40 MHz 0x5 /6 33.33 MHz 0x6 /7 28.57 MHz 0x7 /8 25 MHz 0x8 /9 22.22 MHz 0x9 /10 20 MHz 0xA /11 18.18 MHz 0xB /12 16.67 MHz 0xC /13 15.38 MHz 0xD /14 14.29 MHz 0xE /15 13.33 MHz 0xF /16 12.5 MHz (default) When reading the Run-Mode Clock Configuration (RCC) register (see page 78), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value is allowed to divide a non-PLL source. 22 USESYSDIV R/W 0 Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. 21:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 PWRDN R/W 1 PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 79 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 11 BYPASS R/W 1 PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. 10 reserved RO 0 9:6 XTAL R/W 0xB Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Value Crystal Frequency (MHz) Not Using the PLL 5:4 OSCSRC R/W 0x1 Crystal Frequency (MHz) Using the PLL 0x0 1.000 reserved 0x1 1.8432 reserved 0x2 2.000 reserved 0x3 2.4576 reserved 0x4 3.579545 MHz 0x5 3.6864 MHz 0x6 4 MHz 0x7 4.096 MHz 0x8 4.9152 MHz 0x9 5 MHz 0xA 5.12 MHz 0xB 6 MHz (reset value) 0xC 6.144 MHz 0xD 7.3728 MHz 0xE 8 MHz 0xF 8.192 MHz Oscillator Source Selects the input source for the OSC. The values are: Value Input Source 0x0 MOSC Main oscillator 0x1 IOSC Internal oscillator (default) 0x2 IOSC/4 Internal oscillator / 4 (this is necessary if used as input to PLL) 0x3 30 kHz 30-KHz internal oscillator For additional oscillator sources, see the RCC2 register. 80 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 3:2 reserved RO 0x0 1 IOSCDIS R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 0 MOSCDIS R/W 1 Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). April 04, 2010 81 Texas Instruments-Production Data System Control Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 78). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO - RO - RO - RO - RO - 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - reserved Type Reset reserved Type Reset RO 0 RO 0 F Bit/Field Name Type Reset 31:14 reserved RO 0x0 13:5 F RO - R Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL’s F input. 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 82 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit positions as they do within the RCC register as LSB-justified. The SYSDIV2 field is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. The PLL VCO frequency is 400 MHz. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2810 31 30 USERCC2 Type Reset R/W 0 RO 0 15 14 reserved Type Reset RO 0 29 28 27 26 reserved RO 0 25 24 23 22 21 20 SYSDIV2 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 10 9 8 7 6 13 12 11 PWRDN2 reserved BYPASS2 R/W 1 RO 0 R/W 1 reserved RO 0 19 18 17 16 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 RO 0 RO 0 OSCSRC2 RO 0 RO 0 Bit/Field Name Type Reset Description 31 USERCC2 R/W 0 Use RCC2 R/W 0 R/W 0 reserved R/W 1 RO 0 RO 0 When set, overrides the RCC register fields. 30:29 reserved RO 0 28:23 SYSDIV2 R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. Although the PLL VCO frequency is 400 MHz, it is predivided by 2 before the divisor is applied. This field is wider than the RCC register SYSDIV field in order to provide additional divisor values. This permits the system clock to be run at much lower frequencies during Deep Sleep mode. For example, where the RCC register SYSDIV encoding of 1111 provides /16, the RCC2 register SYSDIV2 encoding of 111111 provides /64. 22:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 PWRDN2 R/W 1 Power-Down PLL When set, powers down the PLL. 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 83 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 11 BYPASS2 R/W 1 Bypass PLL When set, bypasses the PLL for the clock source. 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 OSCSRC2 R/W 0x1 Oscillator Source Selects the input source for the OSC. The values are: Value Description 0x0 MOSC Main oscillator 0x1 IOSC Internal oscillator 0x2 IOSC/4 Internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator 3:0 reserved RO 0 0x4 Reserved 0x5 Reserved 0x6 Reserved 0x7 Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 84 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 reserved Type Reset 25 24 23 22 21 20 DSDIVORIDE 18 17 16 reserved RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 DSOSCSRC RO 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28:23 DSDIVORIDE R/W 0x0F R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 22:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 DSOSCSRC R/W 0x0 Clock Source Specifies the clock source during Deep-Sleep mode. Value Description 0x0 MOSC Use main oscillator as source. 0x1 IOSC Use internal 12-MHz oscillator as source. 0x2 Reserved 0x3 30 kHz Use 30-kHz internal oscillator as source. 3:0 reserved RO 0x0 0x4 Reserved 0x5 Reserved 0x6 Reserved 0x7 Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 85 Texas Instruments-Production Data System Control Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 31 30 29 28 27 26 RO 0 15 25 24 23 22 21 20 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 14 13 12 11 10 9 8 7 6 5 4 RO 0 RO 0 RO 0 RO 0 RO 0 RO - RO - RO - VER Type Reset FAM PINCOUNT Type Reset RO 0 RO 1 18 17 16 RO 0 RO 0 RO 1 RO 1 3 2 1 0 PARTNO reserved RO 0 19 TEMP Bit/Field Name Type Reset 31:28 VER RO 0x1 RO - PKG ROHS RO - RO 1 QUAL RO - RO - Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 27:24 FAM RO 0x0 Second version of the DID1 register format. Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 23:16 PARTNO RO 0xA3 Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0xA3 LM3S6730 15:13 PINCOUNT RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin or 108-ball package 86 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset Description 12:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 TEMP RO - Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 4:3 PKG RO - 0x0 Commercial temperature range (0°C to 70°C) 0x1 Industrial temperature range (-40°C to 85°C) 0x2 Extended temperature range (-40°C to 105°C) Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 2 ROHS RO 1 0x0 SOIC package 0x1 LQFP package 0x2 BGA package RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1:0 QUAL RO - Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified April 04, 2010 87 Texas Instruments-Production Data System Control Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.003F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 SRAMSZ Type Reset FLASHSZ Type Reset RO 0 Bit/Field Name Type Reset Description 31:16 SRAMSZ RO 0x00FF SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00FF 64 KB of SRAM 15:0 FLASHSZ RO 0x003F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x003F 128 KB of Flash 88 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0000.309F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 PLL WDT SWO SWD JTAG RO 1 RO 1 RO 1 RO 1 RO 1 reserved Type Reset MINSYSDIV Type Reset reserved RO 1 MPU Bit/Field Name Type Reset 31:16 reserved RO 0 15:12 MINSYSDIV RO 0x3 RO 1 reserved RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 11:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 MPU RO 1 MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the ARM Cortex-M3 Technical Reference Manual for details on the MPU. 6:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 PLL RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 3 WDT RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. April 04, 2010 89 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 2 SWO RO 1 Description SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 1 SWD RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 0 JTAG RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. 90 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x0307.0011 31 30 29 RO 0 RO 0 RO 0 15 14 RO 0 RO 0 28 27 26 RO 0 RO 0 RO 0 13 12 11 10 RO 0 RO 0 RO 0 reserved Type Reset 25 24 23 22 COMP1 COMP0 RO 1 RO 1 RO 0 RO 0 9 8 7 RO 0 RO 0 RO 0 21 20 19 RO 0 RO 0 RO 0 6 5 4 3 RO 0 RO 0 reserved reserved Type Reset RO 0 SSI0 RO 1 18 17 16 TIMER2 TIMER1 TIMER0 RO 1 RO 1 RO 1 2 1 0 reserved RO 0 RO 0 UART0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 24 COMP0 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 23:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 RO 1 Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present. 17 TIMER1 RO 1 Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 16 TIMER0 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 15:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 RO 1 SSI0 Present When set, indicates that SSI module 0 is present. April 04, 2010 91 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 UART0 RO 1 UART0 Present When set, indicates that UART module 0 is present. 92 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x8F00.0FC0 31 30 32KHZ Type Reset 29 28 reserved 26 25 24 23 22 21 20 19 18 17 16 CCP3 CCP2 CCP1 CCP0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 27 C1O RO 0 RO 0 C1PLUS C1MINUS RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31 32KHZ RO 1 C0O RO 1 reserved C0PLUS C0MINUS RO 1 RO 1 reserved Description 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. 30:28 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27 CCP3 RO 1 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 26 CCP2 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 25 CCP1 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 24 CCP0 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 23:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 C1O RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. 10 C1PLUS RO 1 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 9 C1MINUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. April 04, 2010 93 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 8 C0O RO 1 Description C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 7 C0PLUS RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 6 C0MINUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 5:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 94 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x5000.007F Type Reset 31 30 29 28 27 26 25 24 23 22 reserved EPHY0 reserved EMAC0 RO 0 RO 1 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 RO 0 RO 0 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved reserved Type Reset 21 RO 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 RO 1 Ethernet PHY0 Present When set, indicates that Ethernet PHY module 0 is present. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 RO 1 Ethernet MAC0 Present When set, indicates that Ethernet MAC module 0 is present. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG RO 1 GPIO Port G Present When set, indicates that GPIO Port G is present. 5 GPIOF RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 4 GPIOE RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 3 GPIOD RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. April 04, 2010 95 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 1 GPIOB RO 1 Description GPIO Port B Present When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. 96 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 reserved Type Reset reserved Type Reset reserved RO 0 RO 1 reserved RO 0 RO 0 WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 97 Texas Instruments-Production Data System Control Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved RO 0 RO 0 WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 98 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved RO 0 RO 0 WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 99 Texas Instruments-Production Data System Control Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 RO 0 RO 0 RO 0 15 14 RO 0 RO 0 28 27 26 RO 0 RO 0 RO 0 13 12 11 10 RO 0 RO 0 RO 0 reserved Type Reset 25 24 23 22 COMP1 COMP0 R/W 0 R/W 0 RO 0 RO 0 9 8 7 RO 0 RO 0 RO 0 21 20 19 RO 0 RO 0 RO 0 6 5 4 3 RO 0 RO 0 reserved reserved Type Reset RO 0 SSI0 R/W 0 18 17 16 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 2 1 0 reserved RO 0 RO 0 UART0 RO 0 R/W 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 100 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. April 04, 2010 101 Texas Instruments-Production Data System Control Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 COMP1 COMP0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 23 22 21 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 20 19 reserved RO 0 RO 0 4 3 SSI0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 18 17 16 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 2 1 reserved RO 0 RO 0 0 UART0 RO 0 R/W 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 102 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. April 04, 2010 103 Texas Instruments-Production Data System Control Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 COMP1 COMP0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 23 22 21 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 20 19 reserved RO 0 RO 0 4 3 SSI0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 18 17 16 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 2 1 reserved RO 0 RO 0 0 UART0 RO 0 R/W 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 104 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. April 04, 2010 105 Texas Instruments-Production Data System Control Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 27 26 25 24 23 22 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 RO 0 RO 0 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved reserved Type Reset 21 RO 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 106 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 5 GPIOF R/W 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. April 04, 2010 107 Texas Instruments-Production Data System Control Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 15 14 13 12 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset 22 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 108 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 6 GPIOG R/W 0 Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. April 04, 2010 109 Texas Instruments-Production Data System Control Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 15 14 13 12 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset 22 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 110 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 6 GPIOG R/W 0 Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. April 04, 2010 111 Texas Instruments-Production Data System Control Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Reset Control Reset control for Watchdog unit. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 112 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 RO 0 RO 0 RO 0 15 14 RO 0 RO 0 28 27 26 RO 0 RO 0 RO 0 13 12 11 10 RO 0 RO 0 RO 0 reserved Type Reset 25 24 23 22 COMP1 COMP0 R/W 0 R/W 0 RO 0 RO 0 9 8 7 RO 0 RO 0 RO 0 21 20 19 RO 0 RO 0 RO 0 6 5 4 3 RO 0 RO 0 reserved reserved Type Reset RO 0 SSI0 R/W 0 18 17 16 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 2 1 0 reserved RO 0 RO 0 UART0 RO 0 R/W 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comp 1 Reset Control Reset control for analog comparator 1. 24 COMP0 R/W 0 Analog Comp 0 Reset Control Reset control for analog comparator 0. 23:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Reset Control Reset control for General-Purpose Timer module 2. 17 TIMER1 R/W 0 Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 16 TIMER0 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 15:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Reset Control Reset control for SSI unit 0. 3:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 UART0 R/W 0 UART0 Reset Control Reset control for UART unit 0. April 04, 2010 113 Texas Instruments-Production Data System Control Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 Type Reset 31 30 29 28 27 26 25 24 23 22 reserved EPHY0 reserved EMAC0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 RO 0 RO 0 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved reserved Type Reset 21 RO 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPHY0 R/W 0 PHY0 Reset Control Reset control for Ethernet PHY unit 0. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Reset Control Reset control for Ethernet MAC unit 0. 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 GPIOG R/W 0 Port G Reset Control Reset control for GPIO Port G. 5 GPIOF R/W 0 Port F Reset Control Reset control for GPIO Port F. 4 GPIOE R/W 0 Port E Reset Control Reset control for GPIO Port E. 3 GPIOD R/W 0 Port D Reset Control Reset control for GPIO Port D. 2 GPIOC R/W 0 Port C Reset Control Reset control for GPIO Port C. 1 GPIOB R/W 0 Port B Reset Control Reset control for GPIO Port B. 114 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 0 GPIOA R/W 0 Description Port A Reset Control Reset control for GPIO Port A. April 04, 2010 115 Texas Instruments-Production Data Internal Memory 7 Internal Memory The LM3S6730 microcontroller comes with 64 KB of bit-banded SRAM and 128 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1 on page 116 illustrates the Flash functions. The dashed boxes in the figure indicate registers residing in the System Control module rather than the Flash Control module. Figure 7-1. Flash Block Diagram Flash Control Icode Bus Cortex-M3 FMA FMD FMC FCRIS FCIM FCMISC System Bus Dcode Bus Flash Array Flash Protection Bridge FMPREn FMPPEn Flash Timing USECRL User Registers USER_DBG USER_REG0 USER_REG1 SRAM Array 7.2 Functional Description This section describes the functionality of the SRAM and Flash memories. 7.2.1 SRAM Memory ® The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C 116 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. 7.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also “Serial Flash Loader” on page 417 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 7.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 7.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in two pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 7-1 on page 117. Table 7-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection 0 0 Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. April 04, 2010 117 Texas Instruments-Production Data Internal Memory Table 7-1. Flash Protection Policy Combinations (continued) FMPPEn FMPREn Protection 0 1 Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 1 1 No protection. The block may be written, erased, executed or read. A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using the Flash Memory Control (FMC) register. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 119. 7.2.2.3 Interrupts The Flash memory controller can generate interrupts when the following conditions are observed: ■ Programming Interrupt - signals when a program or erase action is complete. ■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its corresponding FMPPEn bit. The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see page 126) by setting the corresponding MASK bits. If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw Interrupt Status (FCRIS) register (see page 125). Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register (see page 127). 7.3 Flash Memory Initialization and Configuration 7.3.1 Flash Programming ® The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. 7.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 118 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 7.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 7.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. 7.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a write operation. Prior to being committed, the register contents are unaffected by any reset condition except power-on reset, which returns the register contents to the original value. By committing the register values using the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained following power cycling. Once the register contents are committed, the contents are permanent, and they cannot be restored to their factory default values. With the exception of the USER_DBG register, the settings in these registers can be tested before committing them to Flash memory. For the USER_DBG register, the data to be written is loaded into the FMD register before it is committed. The FMD register is read only and does not allow the USER_DBG operation to be tried before committing it to nonvolatile memory. Important: These registers can only have bits changed from 1 to 0 by user programming. Once committed, these registers cannot be restored to their factory default values. In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and USER_DBG registers each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. These five registers can only be committed once whereas the Flash memory protection registers may be committed multiple times. Table 7-2 on page 119 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 7-2. User-Programmable Flash Memory Resident Registers FMA Value Data Source FMPRE0 Register to be Committed 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_REG2 0x8000.0002 USER_REG2 USER_REG3 0x8000.0003 USER_REG3 USER_DBG 0x7510.0000 FMD April 04, 2010 119 Texas Instruments-Production Data Internal Memory 7.4 Register Map Table 7-3 on page 120 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. Table 7-3. Flash Register Map Offset Name Type Reset See page Description Flash Memory Control Registers (Flash Control Offset) 0x000 FMA R/W 0x0000.0000 Flash Memory Address 121 0x004 FMD R/W 0x0000.0000 Flash Memory Data 122 0x008 FMC R/W 0x0000.0000 Flash Memory Control 123 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 125 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 126 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 127 Flash Memory Protection Registers (System Control Offset) 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 130 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 130 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 131 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 131 0x140 USECRL R/W 0x31 USec Reload 129 0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 132 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 133 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 134 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 135 0x208 FMPRE2 R/W 0x0000.0000 Flash Memory Protection Read Enable 2 136 0x20C FMPRE3 R/W 0x0000.0000 Flash Memory Protection Read Enable 3 137 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 138 0x408 FMPPE2 R/W 0x0000.0000 Flash Memory Protection Program Enable 2 139 0x40C FMPPE3 R/W 0x0000.0000 Flash Memory Protection Program Enable 3 140 7.5 Flash Register Descriptions (Flash Control Offset) This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. 120 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 16 OFFSET OFFSET Type Reset Bit/Field Name Type Reset Description 31:17 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16:0 OFFSET R/W 0x0 Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 119 for details on values for this field). April 04, 2010 121 Texas Instruments-Production Data Internal Memory Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DATA Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:0 DATA R/W 0x0 Data Value Data value for write operation. 122 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 121). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 122) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COMT MERASE ERASE WRITE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 WRKEY Type Reset reserved Type Reset Bit/Field Name Type Reset 31:16 WRKEY WO 0x0 Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 15:4 reserved RO 0x0 3 COMT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 2 MERASE R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. April 04, 2010 123 Texas Instruments-Production Data Internal Memory Bit/Field Name Type Reset 1 ERASE R/W 0 Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 0 WRITE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 µs. 124 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PRIS ARIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through the FMC register bits (see page 123). Value Description 1 The programming cycle has completed. 0 The programming cycle has not completed. This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register. 0 ARIS RO 0 Access Raw Interrupt Status Value Description 1 A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. 0 No access has tried to improperly program or erase the Flash memory. This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register. April 04, 2010 125 Texas Instruments-Production Data Internal Memory Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PMASK AMASK RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. Value Description 0 AMASK R/W 0 1 An interrupt is sent to the interrupt controller when the PRIS bit is set. 0 The PRIS interrupt is suppressed and not sent to the interrupt controller. Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. Value Description 1 An interrupt is sent to the interrupt controller when the ARIS bit is set. 0 The ARIS interrupt is suppressed and not sent to the interrupt controller. 126 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PMISC R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 PMISC AMISC R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clears PMISC and also the PRIS bit in the FCRIS register (see page 125). 0 When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. Writing a 1 to this bit clears AMISC and also the ARIS bit in the FCRIS register (see page 125). 0 When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. April 04, 2010 127 Texas Instruments-Production Data Internal Memory 7.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 128 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 USEC RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 USEC R/W 0x31 Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. If the maximum system frequency is being used, USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. April 04, 2010 129 Texas Instruments-Production Data Internal Memory Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.E000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 130 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.E000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 PROG_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. April 04, 2010 131 Texas Instruments-Production Data Internal Memory Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, this register cannot be restored to the factory default value. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset 31 NW R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 1 0 DBG1 DBG0 R/W 1 R/W 0 Description User Debug Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:2 DATA R/W 0x1FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 1 DBG1 R/W 1 Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 132 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once committed, this register cannot be restored to the factory default value. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. April 04, 2010 133 Texas Instruments-Production Data Internal Memory Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once committed, this register cannot be restored to the factory default value. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 134 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. April 04, 2010 135 Texas Instruments-Production Data Internal Memory Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 128 KB of flash. 136 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 128 KB of flash. April 04, 2010 137 Texas Instruments-Production Data Internal Memory Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 138 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 128 KB of flash. April 04, 2010 139 Texas Instruments-Production Data Internal Memory Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 128 KB of flash. 140 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G). The GPIO module supports 23-46 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ 23-46 GPIOs, depending on configuration ■ 5-V-tolerant input/outputs ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Pins configured as digital inputs are Schmitt-triggered. ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 8.1 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-1 on page 142). The LM3S6730 microcontroller contains seven ports and thus seven of these physical GPIO blocks. April 04, 2010 141 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Figure 8-1. GPIO Port Block Diagram Commit Control Mode Control GPIOLOCK GPIOCR GPIOAFSEL DEMUX Alternate Input Alternate Output Pad Input Alternate Output Enable Pad Output MUX Pad Output Enable Digital I/O Pad Package I/O Pin GPIO Output GPIODATA GPIODIR Interrupt MUX GPIO Input Data Control GPIO Output Enable Interrupt Control Pad Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 8.1.1 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 8.1.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 149) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 8.1.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 148) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. 142 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-2 on page 143, where u is data unchanged by the write. Figure 8-2. GPIODATA Write Example ADDR[9:2] 0x098 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 0 0 0xEB 1 1 1 0 1 0 1 1 GPIODATA u u 1 u u 0 1 u 7 6 5 4 3 2 1 0 During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 143. Figure 8-3. GPIODATA Read Example 8.1.2 ADDR[9:2] 0x0C4 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 0 0 GPIODATA 1 0 1 1 1 1 1 0 Returned Value 0 0 1 1 0 0 0 0 7 6 5 4 3 2 1 0 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 150) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 151) ■ GPIO Interrupt Event (GPIOIEV) register (see page 152) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 153). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 154 and page 155). As the name implies, the GPIOMIS register only shows interrupt April 04, 2010 143 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 156). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 8.1.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 157), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 8.1.4 Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 157) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 167) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 168) have been set to 1. 8.1.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable. For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. 8.1.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 145 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-2 on page 145 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. 144 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 8-1. GPIO Pad Configuration Examples a Configuration GPIO Register Bit Value AFSEL DIR ODR DEN DR2R DR4R DR8R ? X X X X ? ? ? ? ? ? X X ? ? ? ? ? ? X X X X 1 ? ? ? ? ? ? 0 1 ? ? ? ? ? ? X 0 1 ? ? ? ? ? ? 0 0 0 0 0 0 X X X X 1 X 0 1 ? ? ? ? ? ? Digital Input (GPIO) 0 0 0 1 Digital Output (GPIO) 0 1 0 1 Open Drain Output (GPIO) 0 1 1 1 Digital Input (Timer CCP) 1 X 0 1 Digital Output (Timer PWM) 1 X 0 Digital Input/Output (SSI) 1 X Digital Input/Output (UART) 1 Analog Input (Comparator) Digital Output (Comparator) PUR PDR ? SLR a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 8-2. GPIO Interrupt Configuration Example Register Desired Interrupt Event Trigger GPIOIS a Pin 2 Bit Value 7 0=edge 6 5 4 3 2 1 0 X X X X X 0 X X X X X X X 0 X X X X X X X 1 X X 0 0 0 0 0 1 0 0 1=level GPIOIBE 0=single edge 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don’t care bit) 8.3 Register Map Table 8-3 on page 146 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ GPIO Port A: 0x4000.4000 April 04, 2010 145 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) ■ ■ ■ ■ ■ ■ GPIO Port B: 0x4000.5000 GPIO Port C: 0x4000.6000 GPIO Port D: 0x4000.7000 GPIO Port E: 0x4002.4000 GPIO Port F: 0x4002.5000 GPIO Port G: 0x4002.6000 Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect, and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 8-3. GPIO Register Map Description See page Offset Name Type Reset 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 148 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 149 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 150 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 151 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 152 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 153 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 154 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 155 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 156 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 157 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 159 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 160 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 161 146 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 8-3. GPIO Register Map (continued) Offset Name Type Reset 0x50C GPIOODR R/W 0x0000.0000 0x510 GPIOPUR R/W - 0x514 GPIOPDR R/W 0x518 GPIOSLR 0x51C Description See page GPIO Open Drain Select 162 GPIO Pull-Up Select 163 0x0000.0000 GPIO Pull-Down Select 164 R/W 0x0000.0000 GPIO Slew Rate Control Select 165 GPIODEN R/W - GPIO Digital Enable 166 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 167 0x524 GPIOCR - - GPIO Commit 168 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 170 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 171 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 172 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 173 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 174 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 175 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 176 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 177 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 178 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 179 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 180 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 181 8.4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. April 04, 2010 147 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 149). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA R/W 0x00 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 142 for examples of reads and writes. 148 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DIR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DIR R/W 0x00 GPIO Data Direction The DIR values are defined as follows: Value Description 0 Pins are inputs. 1 Pins are outputs. April 04, 2010 149 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IS RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IS R/W 0x00 GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 Edge on corresponding pin is detected (edge-sensitive). 1 Level on corresponding pin is detected (level-sensitive). 150 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 150) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 152). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IBE RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IBE R/W 0x00 GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description 0 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 152). 1 Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. April 04, 2010 151 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 150). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IEV RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IEV R/W 0x00 GPIO Interrupt Event The IEV values are defined as follows: Value Description 0 Falling edge or Low levels on corresponding pins trigger interrupts. 1 Rising edge or High levels on corresponding pins trigger interrupts. 152 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IME RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IME R/W 0x00 GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 Corresponding pin interrupt is masked. 1 Corresponding pin interrupt is not masked. April 04, 2010 153 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 153). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 RIS RO 0x00 GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 Corresponding pin interrupt requirements not met. 1 Corresponding pin interrupt has met requirements. 154 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset MIS RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 MIS RO 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 Corresponding GPIO line interrupt not active. 1 Corresponding GPIO line asserting interrupt. April 04, 2010 155 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 W1C 0 W1C 0 W1C 0 W1C 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IC RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IC W1C 0x00 GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 Corresponding interrupt is unaffected. 1 Corresponding interrupt is cleared. 156 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 157) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 167) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 168) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x420 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 AFSEL RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 157 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 7:0 AFSEL R/W - Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). 1 Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 158 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV2 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV2 R/W 0xFF Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. April 04, 2010 159 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV4 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV4 R/W 0x00 Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 160 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV8 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV8 R/W 0x00 Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. April 04, 2010 161 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 166). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ODE RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 ODE R/W 0x00 Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 Open drain configuration is disabled. 1 Open drain configuration is enabled. 162 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 164). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x510 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PUE RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PUE R/W - Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. April 04, 2010 163 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 163). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PDE RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PDE R/W 0x00 Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 164 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 161). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SRL RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 SRL R/W 0x00 Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 Slew rate control disabled. 1 Slew rate control enabled. April 04, 2010 165 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x51C Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - reserved Type Reset reserved Type Reset DEN RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DEN R/W - Digital Enable The DEN values are defined as follows: Value Description 0 Digital functions disabled. 1 Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 166 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 168). Writing 0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 LOCK R/W R/W 0 Reset R/W 0 Description 0x0000.0001 GPIO Lock A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 locked 0x0000.0000 unlocked April 04, 2010 167 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSELregister bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 - - - - - - - - reserved Type Reset reserved Type Reset CR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 168 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 7:0 CR - - Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. April 04, 2010 169 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0] 170 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8] April 04, 2010 171 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16] 172 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24] April 04, 2010 173 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x61 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 174 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. April 04, 2010 175 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 176 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. April 04, 2010 177 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 178 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. April 04, 2010 179 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 180 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID3 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. April 04, 2010 181 Texas Instruments-Production Data General-Purpose Timers 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1, and Timer 2). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). ® The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 39). The General-Purpose Timers provide the following features: ■ Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: – As a single 32-bit timer – As one 32-bit Real-Time Clock (RTC) to event capture – For Pulse Width Modulation (PWM) ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock when using an external 32.768-KHz clock as the input – User-enabled stalling when the controller asserts CPU Halt flag during debug ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – User-enabled stalling when the controller asserts CPU Halt flag during debug ■ 16-bit Input Capture modes – Input edge count capture – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 9.1 Block Diagram Note: ® In Figure 9-1 on page 183, the specific CCP pins available depend on the Stellaris device. See Table 9-1 on page 183 for the available CCPs. 182 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 9-1. GPTM Module Block Diagram 0x0000 (Down Counter Modes) TimerA Control GPTMTAPMR TA Comparator GPTMTAPR Clock / Edge Detect GPTMTAMATCHR Interrupt / Config TimerA Interrupt GPTMCFG GPTMTAILR GPTMAR En GPTMTAMR GPTMCTL GPTMIMR TimerB Interrupt 32 KHz or Even CCP Pin RTC Divider GPTMRIS GPTMMIS TimerB Control GPTMICR GPTMTBPMR GPTMTBR En Clock / Edge Detect GPTMTBPR GPTMTBMATCHR GPTMTBILR Odd CCP Pin TB Comparator GPTMTBMR 0x0000 (Down Counter Modes) System Clock Table 9-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin Timer 0 TimerA CCP0 - TimerB - CCP1 TimerA CCP2 - TimerB - CCP3 TimerA - - TimerB - - Timer 1 Timer 2 9.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 194), the GPTM TimerA Mode (GPTMTAMR) register (see page 195), and the GPTM TimerB Mode (GPTMTBMR) register (see page 197). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. April 04, 2010 183 Texas Instruments-Production Data General-Purpose Timers 9.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 208) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 209). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 212) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 213). 9.2.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 208 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 209 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 216 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 217 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 9.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 195), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 199), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 204), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 206). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 202), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 205). 184 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. 9.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 210) by the controller. The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 9.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 194). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. April 04, 2010 185 Texas Instruments-Production Data General-Purpose Timers The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 9-2. 16-Bit Timer With Prescaler Configurations a Prescale #Clock (T c) Max Time Units 00000000 1 1.3107 mS 00000001 2 2.6214 mS 00000010 3 3.9322 mS ------------ -- -- -- 11111101 254 332.9229 mS 11111110 255 334.2336 mS 11111111 256 335.5443 mS a. Tc is the clock period. 9.2.3.2 16-Bit Input Edge Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Count mode. In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 9-2 on page 187 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. 186 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 9-2. 16-Bit Input Edge Count Mode Example Timer stops, flags asserted Count Timer reload on next cycle Ignored Ignored 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 9.2.3.3 16-Bit Input Edge Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 9-3 on page 188 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). April 04, 2010 187 Texas Instruments-Production Data General-Purpose Timers Figure 9-3. 16-Bit Input Edge Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 9.2.3.4 16-Bit PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-4 on page 189 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. 188 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 9-4. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 9.3 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, and TIMER2 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. April 04, 2010 189 Texas Instruments-Production Data General-Purpose Timers 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 190. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared. 9.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 190 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller In One-Shot mode, the timer stops counting after step 8 on page 190. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 191 through step 9 on page 191. 9.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM April 04, 2010 191 Texas Instruments-Production Data General-Purpose Timers Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 9.4 Register Map Table 9-3 on page 192 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 ■ Timer2: 0x4003.2000 Table 9-3. Timers Register Map Description See page Offset Name Type Reset 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 194 0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 195 0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 197 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 199 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 202 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 204 192 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 9-3. Timers Register Map (continued) Offset Name 0x020 Reset GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 205 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 206 0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM TimerA Interval Load 208 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 209 0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM TimerA Match 210 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 211 0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 212 0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 213 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 214 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 215 0x048 GPTMTAR RO 0xFFFF.FFFF GPTM TimerA 216 0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 217 9.5 Description See page Type Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. April 04, 2010 193 Texas Instruments-Production Data General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 GPTMCFG R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 GPTMCFG R/W 0x0 GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2 Reserved 0x3 Reserved 0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 194 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TAAMS TACMR RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TAMR R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TAAMS R/W 0 GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TACMR R/W 0 To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode April 04, 2010 195 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1:0 TAMR R/W 0x0 Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 196 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TBAMS TBCMR RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TBMR R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TBAMS R/W 0 GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TBCMR R/W 0 To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode April 04, 2010 197 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1:0 TBMR R/W 0x0 Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register’s contents are ignored and GPTMTAMR is used. 198 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 13 12 11 10 9 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TBSTALL TBEN reserved TAPWML reserved RTCEN TASTALL TAEN R/W 0 R/W 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset 15 14 reserved TBPWML RO 0 R/W 0 reserved RO 0 RO 0 TBEVENT R/W 0 R/W 0 TAEVENT R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:15 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 TBPWML R/W 0 GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 13:12 reserved RO 0 11:10 TBEVENT R/W 0x0 0 Output is unaffected. 1 Output is inverted. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges April 04, 2010 199 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 9 TBSTALL R/W 0 Description GPTM Timer B Stall Enable The TBSTALL values are defined as follows: Value Description 0 Timer B continues counting while the processor is halted by the debugger. 1 Timer B freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TBSTALL bit is ignored. 8 TBEN R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 TimerB is disabled. 1 TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 TAPWML R/W 0 GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 RTCEN R/W 0 GPTM RTC Enable The RTCEN values are defined as follows: Value Description 3:2 TAEVENT R/W 0x0 0 RTC counting is disabled. 1 RTC counting is enabled. GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 200 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 1 TASTALL R/W 0 Description GPTM Timer A Stall Enable The TASTALL values are defined as follows: Value Description 0 Timer A continues counting while the processor is halted by the debugger. 1 Timer A freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TASTALL bit is ignored. 0 TAEN R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 TimerA is disabled. 1 TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. April 04, 2010 201 Texas Instruments-Production Data General-Purpose Timers Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 CBEIM CBMIM TBTOIM RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RTCIM CAEIM CAMIM TATOIM RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBEIM R/W 0 GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 9 CBMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 8 TBTOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 7:4 reserved RO 0 0 Interrupt is disabled. 1 Interrupt is enabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 202 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 3 RTCIM R/W 0 Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 2 CAEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 1 CAMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 TATOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. April 04, 2010 203 Texas Instruments-Production Data General-Purpose Timers Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RTCRIS CAERIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 CBERIS RO 0 CBMRIS TBTORIS RO 0 RO 0 reserved CAMRIS TATORIS RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBERIS RO 0 GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 7:4 reserved RO 0x0 3 RTCRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 204 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 CBEMIS CBMMIS TBTOMIS RO 0 RO 0 RO 0 reserved RTCMIS RO 0 CAEMIS CAMMIS TATOMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBEMIS RO 0 GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 9 CBMMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 7:4 reserved RO 0x0 3 RTCMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 2 CAEMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 1 CAMMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. April 04, 2010 205 Texas Instruments-Production Data General-Purpose Timers Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 reserved Type Reset reserved Type Reset RO 0 RO 0 RO 0 CBECINT CBMCINT RO 0 RO 0 W1C 0 W1C 0 reserved TBTOCINT W1C 0 RO 0 RO 0 RO 0 RTCCINT CAECINT CAMCINT RO 0 W1C 0 W1C 0 W1C 0 0 TATOCINT W1C 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBECINT W1C 0 GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 9 CBMCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 8 TBTOCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 7:4 reserved RO 0x0 0 The interrupt is unaffected. 1 The interrupt is cleared. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 206 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 3 RTCCINT W1C 0 Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 2 CAECINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 1 CAMCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking. 0 TATOCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt The TATOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. April 04, 2010 207 Texas Instruments-Production Data General-Purpose Timers Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x028 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAILRH Type Reset TAILRL Type Reset Bit/Field Name Type Reset 31:16 TAILRH R/W 0xFFFF Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 208 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset TBILRL Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBILRL R/W 0xFFFF GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. April 04, 2010 209 Texas Instruments-Production Data General-Purpose Timers Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x030 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAMRH Type Reset TAMRL Type Reset Bit/Field Name Type Reset 31:16 TAMRH R/W 0xFFFF Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 15:0 TAMRL R/W 0xFFFF GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 210 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset TBMRL Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBMRL R/W 0xFFFF GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. April 04, 2010 211 Texas Instruments-Production Data General-Purpose Timers Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TAPSR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TAPSR R/W 0x00 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-2 on page 186 for more details and an example. 212 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TBPSR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TBPSR R/W 0x00 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-2 on page 186 for more details and an example. April 04, 2010 213 Texas Instruments-Production Data General-Purpose Timers Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TAPSMR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TAPSMR R/W 0x00 GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 214 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TBPSMR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TBPSMR R/W 0x00 GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. April 04, 2010 215 Texas Instruments-Production Data General-Purpose Timers Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x048 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 TARH Type Reset TARL Type Reset Bit/Field Name Type Reset 31:16 TARH RO 0xFFFF Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 15:0 TARL RO 0xFFFF GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 216 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved Type Reset TBRL Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBRL RO 0xFFFF GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. April 04, 2010 217 Texas Instruments-Production Data Watchdog Timer 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. ® The Stellaris Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the controller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 218 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 10.1 Block Diagram Figure 10-1. WDT Module Block Diagram WDTLOAD Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS 32-Bit Down Counter WDTMIS 0x00000000 WDTLOCK System Clock WDTTEST Comparator WDTVALUE Identification Registers 10.2 WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. April 04, 2010 219 Texas Instruments-Production Data Watchdog Timer Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 10.4 Register Map Table 10-1 on page 220 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 10-1. Watchdog Timer Register Map Description See page Offset Name Type Reset 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 222 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 223 0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 224 0x00C WDTICR WO - Watchdog Interrupt Clear 225 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 226 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 227 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 228 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 229 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 230 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 231 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 232 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 233 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 234 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 235 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 236 220 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 10-1. Watchdog Timer Register Map (continued) Offset Name 0xFEC Reset WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 237 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 238 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 239 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 240 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 241 10.5 Description See page Type Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. April 04, 2010 221 Texas Instruments-Production Data Watchdog Timer Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 WDTLoad Type Reset WDTLoad Type Reset Bit/Field Name Type 31:0 WDTLoad R/W Reset R/W 1 Description 0xFFFF.FFFF Watchdog Load Value 222 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 WDTValue Type Reset WDTValue Type Reset Bit/Field Name Type 31:0 WDTValue RO Reset RO 1 Description 0xFFFF.FFFF Watchdog Value Current value of the 32-bit down counter. April 04, 2010 223 Texas Instruments-Production Data Watchdog Timer Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 RESEN INTEN R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RESEN R/W 0 Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 INTEN R/W 0 0 Disabled. 1 Enable the Watchdog module reset output. Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description 0 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 1 Interrupt event enabled. Once enabled, all writes are ignored. 224 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WDTIntClr Type Reset WDTIntClr Type Reset Bit/Field Name Type Reset 31:0 WDTIntClr WO - WO - Description Watchdog Interrupt Clear April 04, 2010 225 Texas Instruments-Production Data Watchdog Timer Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 WDTRIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 WDTRIS RO 0 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 226 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 WDTMIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 WDTMIS RO 0 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. April 04, 2010 227 Texas Instruments-Production Data Watchdog Timer Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STALL R/W 0 reserved Bit/Field Name Type Reset Description 31:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 STALL R/W 0 Watchdog Stall Enable ® When set to 1, if the Stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 228 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WDTLock Type Reset WDTLock Type Reset Bit/Field Name Type Reset 31:0 WDTLock R/W 0x0000 R/W 0 Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked April 04, 2010 229 Texas Instruments-Production Data Watchdog Timer Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0] 230 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8] April 04, 2010 231 Texas Instruments-Production Data Watchdog Timer Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16] 232 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24] April 04, 2010 233 Texas Instruments-Production Data Watchdog Timer Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0] 234 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8] April 04, 2010 235 Texas Instruments-Production Data Watchdog Timer Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16] 236 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24] April 04, 2010 237 Texas Instruments-Production Data Watchdog Timer Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0] 238 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8] April 04, 2010 239 Texas Instruments-Production Data Watchdog Timer Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16] 240 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24] April 04, 2010 241 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 11 Universal Asynchronous Receivers/Transmitters (UARTs) ® The Stellaris Universal Asynchronous Receiver/Transmitter (UART) has the following features: ■ Fully programmable 16C550-type UART with IrDA support ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable baud-rate generator allowing speeds up to 3.125 Mbps ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ False-start bit detection ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration 242 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 11.1 Block Diagram Figure 11-1. UART Module Block Diagram System Clock Interrupt Interrupt Control UARTIFLS UARTIM UARTMIS UARTRIS UARTICR Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 11.2 TxFIFO 16 x 8 . . . Baud Rate Generator UARTDR Transmitter (with SIR Transmit Encoder) UnTx UARTIBRD UARTFBRD Control/Status RxFIFO 16 x 8 UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR . . . Receiver (with SIR Receive Decoder) UnRx Functional Description ® Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 261). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 11.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data April 04, 2010 243 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 11-2 on page 244 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 11-2. UART Character Frame UnTX LSB 1 5-8 data bits 0 n Parity bit if enabled Start 11.2.2 1-2 stop bits MSB Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 257) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 258). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 259), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write 244 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 11.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 254) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 243). The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 252). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 11.2.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 256 for more information on IrDA low-power pulse-duration configuration. Figure 11-3 on page 246 shows the UART transmit and receive signals, with and without IrDA modulation. April 04, 2010 245 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Figure 11-3. IrDA Data Modulation Data bits Start bit UnTx 1 0 0 0 1 Stop bit 0 0 1 1 1 UnTx with IrDA 3 16 Bit period Bit period UnRx with IrDA UnRx 0 1 0 Start 1 0 0 1 1 Data bits 0 1 Stop In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal as an alternate function must be configured as the UnRx signal and pulled High. 11.2.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 250). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 259). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 254) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 263). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 11.2.6 Interrupts The UART can generate interrupts when the following conditions are observed: 246 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller ■ Overrun Error ■ Break Error ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 268). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 265) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 267). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 269). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 11.2.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 261). In loopback mode, data transmitted on UnTx is received on the UnRx input. 11.2.8 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 11.3 Initialization and Configuration To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1 register. This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 20 MHz and the desired UART configuration is: ■ 115200 baud rate April 04, 2010 247 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) ■ Data length of 8 bits ■ One stop bit ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 244, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 257) should be set to 10. The value to be loaded into the UARTFBRD register (see page 258) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. 11.4 Register Map Table 11-1 on page 248 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 261) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 11-1. UART Register Map Offset Name Type Reset Description See page 0x000 UARTDR R/W 0x0000.0000 UART Data 250 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 252 0x018 UARTFR RO 0x0000.0090 UART Flag 254 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 256 248 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 11-1. UART Register Map (continued) Name Type Reset 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 257 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 258 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 259 0x030 UARTCTL R/W 0x0000.0300 UART Control 261 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 263 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 265 0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 267 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 268 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 269 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 271 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 272 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 273 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 274 0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 275 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 276 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 277 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 278 0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 279 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 280 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 281 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 282 11.5 Description See page Offset Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. April 04, 2010 249 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 1: UART Data (UARTDR), offset 0x000 Important: Use caution when reading this register. Performing a read may change bit status. This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 OE BE PE FE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DATA Bit/Field Name Type Reset Description 31:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 OE RO 0 UART Overrun Error The OE values are defined as follows: Value Description 10 BE RO 0 0 There has been no data loss due to a FIFO overrun. 1 New data was received when the FIFO was full, resulting in data loss. UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 250 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 9 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 7:0 DATA R/W 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. April 04, 2010 251 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Reads UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 OE BE PE FE RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 OE RO 0 UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 2 BE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 252 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 1 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. Writes UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset DATA WO 0 Bit/Field Name Type Reset Description 31:8 reserved WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA WO 0 Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. April 04, 2010 253 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TXFE RXFF TXFF RXFE BUSY RO 1 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 TXFE RO 1 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 6 RXFF RO 0 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 5 TXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 4 RXFE RO 1 UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 254 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset Description 3 BUSY RO 0 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 255 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ILPDVSR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 ILPDVSR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 256 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 244 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset DIVINT Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0 15:0 DIVINT R/W 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Integer Baud-Rate Divisor April 04, 2010 257 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 244 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DIVFRAC R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor 258 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SPS RO 0 RO 0 RO 0 RO 0 R/W 0 5 WLEN R/W 0 R/W 0 4 3 2 1 0 FEN STP2 EPS PEN BRK R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 SPS R/W 0 UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 6:5 WLEN R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 4 FEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 3 STP2 R/W 0 UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. April 04, 2010 259 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2 EPS R/W 0 Description UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 BRK R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. 260 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. Note: The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register. 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH). 4. Reprogram the control register. 5. Enable the UART. UART Control (UARTCTL) UART0 base: 0x4000.C000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE TXE LBE RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 0 SIRLP SIREN UARTEN RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 RXE R/W 1 UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: 8 TXE R/W 1 To enable reception, the UARTEN bit must also be set. UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. April 04, 2010 261 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 7 LBE R/W 0 Description UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 6:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 SIRLP R/W 0 UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 256 for more information. 1 SIREN R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 0 UARTEN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 262 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RXIFLSEL R/W 1 TXIFLSEL R/W 1 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:3 RXIFLSEL R/W 0x2 UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value Description 0x0 RX FIFO ≥ 1/8 full 0x1 RX FIFO ≥ ¼ full 0x2 RX FIFO ≥ ½ full (default) 0x3 RX FIFO ≥ ¾ full 0x4 RX FIFO ≥ 7/8 full 0x5-0x7 Reserved April 04, 2010 263 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2:0 TXIFLSEL R/W 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO ≤ 1/8 full 0x1 TX FIFO ≤ ¼ full 0x2 TX FIFO ≤ ½ full (default) 0x3 TX FIFO ≤ ¾ full 0x4 TX FIFO ≤ 7/8 full 0x5-0x7 Reserved 264 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 15 14 RO 0 RO 0 RO 0 13 12 11 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 OEIM BEIM PEIM FEIM RTIM TXIM RXIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIM R/W 0 UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 9 BEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 5 TXIM R/W 0 UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. April 04, 2010 265 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 4 RXIM R/W 0 Description UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 266 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OERIS RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BERIS PERIS FERIS RTRIS TXRIS RXRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OERIS RO 0 UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 9 BERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved RO 0xF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 267 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OEMIS RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 268 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OEIC RO 0 RO 0 RO 0 RO 0 W1C 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEIC PEIC FEIC RTIC TXIC RXIC W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIC W1C 0 Overrun Error Interrupt Clear The OEIC values are defined as follows: Value Description 9 BEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Break Error Interrupt Clear The BEIC values are defined as follows: Value Description 8 PEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Parity Error Interrupt Clear The PEIC values are defined as follows: Value Description 7 FEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Framing Error Interrupt Clear The FEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. April 04, 2010 269 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 6 RTIC W1C 0 Description Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 5 TXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 4 RXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Receive Interrupt Clear The RXIC values are defined as follows: Value Description 3:0 reserved RO 0x00 0 No effect on the interrupt. 1 Clears interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 270 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x0000 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. April 04, 2010 271 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x0000 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 272 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x0000 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. April 04, 2010 273 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 PID7 RO 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 274 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 Offset 0xFE0 Type RO, reset 0x0000.0011 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x11 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. April 04, 2010 275 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 276 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. April 04, 2010 277 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 278 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. April 04, 2010 279 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 280 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. April 04, 2010 281 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 282 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 12 Synchronous Serial Interface (SSI) ® The Stellaris Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. ® The Stellaris SSI module has the following features: ■ Master or slave operation ■ Programmable clock bit rate and prescale ■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing 12.1 Block Diagram Figure 12-1. SSI Module Block Diagram Interrupt Interrupt Control SSIIM SSIMIS Control/ Status SSIRIS SSIICR SSICR0 SSICR1 TxFIFO 8 x16 . . . SSITx SSISR SSIRx SSIDR RxFIFO 8 x16 System Clock SSIPCellID0 Identification Registers SSIPeriphID0 SSIPeriphID 4 SSIPCellID1 SSIPeriphID 1 SSIPeriphID 5 SSIPCellID2 SSIPeriphID 2 SSIPeriphID 6 SSIPCellID3 SSIPeriphID 3 SSIPeriphID7 12.2 Clock Prescaler Transmit / Receive Logic SSIClk SSIFss . . . SSICPSR Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with April 04, 2010 283 Texas Instruments-Production Data Synchronous Serial Interface (SSI) internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 12.2.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 302). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 295). The frequency of the output clock SSIClk is defined by: SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) Note: For master mode, the system clock must be at least two times faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 411 to view SSI timing parameters. 12.2.2 FIFO Operation 12.2.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 299), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or a µDMA request when the FIFO is empty. 12.2.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 12.2.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service ■ Receive FIFO service 284 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller ■ Receive FIFO time-out ■ Receive FIFO overrun All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 303). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 305 and page 306, respectively). 12.2.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 12.2.4.1 Texas Instruments Synchronous Serial Frame Format Figure 12-2 on page 286 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. April 04, 2010 285 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 12-3 on page 286 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits 12.2.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. 286 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. 12.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 12-4 on page 287 and Figure 12-5 on page 287. Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB MSB Q 4 to 16 bits SSITx MSB Note: LSB Q is undefined. Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB LSB MSB MSB 4 to16 bits SSITx LSB MSB LSB MSB In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. April 04, 2010 287 Texas Instruments-Production Data Synchronous Serial Interface (SSI) One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 12-6 on page 288, which covers both single and continuous transfers. Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q Q MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. 288 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 12-7 on page 289 and Figure 12-8 on page 289. Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSIRx MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx MSB LSB LSB MSB 4 to 16 bits In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. April 04, 2010 289 Texas Instruments-Production Data Synchronous Serial Interface (SSI) However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 12-9 on page 290, which covers both single and continuous transfers. Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB LSB Q 4 to 16 bits MSB SSITx Note: LSB Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.7 MICROWIRE Frame Format Figure 12-10 on page 291 shows the MICROWIRE frame format, again for a single frame. Figure 12-11 on page 292 shows the same format when back-to-back frames are transmitted. 290 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 12-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx LSB MSB 8-bit control 0 SSIRx MSB LSB 4 to 16 bits output data MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. April 04, 2010 291 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB MSB LSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 12-12 on page 292 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup=(2*tSSIClk) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 12.3 Initialization and Configuration To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 4. Write the SSICR0 register with the following configuration: 292 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 12.4 Register Map Table 12-1 on page 293 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 12-1. SSI Register Map Offset Name Type Reset Description See page 0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 295 0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 297 April 04, 2010 293 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Table 12-1. SSI Register Map (continued) Name Type Reset 0x008 SSIDR R/W 0x0000.0000 SSI Data 299 0x00C SSISR RO 0x0000.0003 SSI Status 300 0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 302 0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 303 0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 305 0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 306 0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 307 0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 308 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 309 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 310 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 311 0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 312 0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 313 0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 314 0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 315 0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 316 0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 317 0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 318 0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 319 12.5 Description See page Offset Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. 294 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 SPH SPO R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset SCR Type Reset FRF R/W 0 DSS Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 SCR R/W 0x0000 SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=FSSIClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 6 SPO R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. April 04, 2010 295 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 5:4 FRF R/W 0x0 Description SSI Frame Format Select The FRF values are defined as follows: Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Instruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved 3:0 DSS R/W 0x00 SSI Data Size Select The DSS values are defined as follows: Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data 296 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SOD MS SSE LBM RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 SOD R/W 0 SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. The SOD values are defined as follows: Value Description 2 MS R/W 0 0 SSI can drive SSITx output in Slave Output mode. 1 SSI must not drive the SSITx output in Slave mode. SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). The MS values are defined as follows: Value Description 0 Device configured as a master. 1 Device configured as a slave. April 04, 2010 297 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 1 SSE R/W 0 Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 SSI operation disabled. 1 SSI operation enabled. Note: 0 LBM R/W 0 This bit must be set to 0 before any control registers are reprogrammed. SSI Loopback Mode Setting this bit enables Loopback Test mode. The LBM values are defined as follows: Value Description 0 Normal serial port operation enabled. 1 Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 298 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 3: SSI Data (SSIDR), offset 0x008 Important: Use caution when reading this register. Performing a read may change bit status. SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DATA R/W 0x0000 SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. April 04, 2010 299 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BSY RFF RNE TNF TFE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 R0 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:5 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 BSY RO 0 SSI Busy Bit The BSY values are defined as follows: Value Description 3 RFF RO 0 0 SSI is idle. 1 SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. SSI Receive FIFO Full The RFF values are defined as follows: Value Description 2 RNE RO 0 0 Receive FIFO is not full. 1 Receive FIFO is full. SSI Receive FIFO Not Empty The RNE values are defined as follows: Value Description 1 TNF RO 1 0 Receive FIFO is empty. 1 Receive FIFO is not empty. SSI Transmit FIFO Not Full The TNF values are defined as follows: Value Description 0 Transmit FIFO is full. 1 Transmit FIFO is not full. 300 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 0 TFE R0 1 Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. April 04, 2010 301 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CPSDVSR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CPSDVSR R/W 0x00 SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. 302 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 TXIM RXIM RTIM RORIM R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask The TXIM values are defined as follows: Value Description 2 RXIM R/W 0 0 TX FIFO half-full or less condition interrupt is masked. 1 TX FIFO half-full or less condition interrupt is not masked. SSI Receive FIFO Interrupt Mask The RXIM values are defined as follows: Value Description 1 RTIM R/W 0 0 RX FIFO half-full or more condition interrupt is masked. 1 RX FIFO half-full or more condition interrupt is not masked. SSI Receive Time-Out Interrupt Mask The RTIM values are defined as follows: Value Description 0 RX FIFO time-out interrupt is masked. 1 RX FIFO time-out interrupt is not masked. April 04, 2010 303 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 0 RORIM R/W 0 Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 RX FIFO overrun interrupt is masked. 1 RX FIFO overrun interrupt is not masked. 304 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXRIS RXRIS RTRIS RORRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. April 04, 2010 305 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXMIS RXMIS RTMIS RORMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXMIS RO 0 SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. 306 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RTIC RORIC RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 RORIC W1C 0 0 No effect on interrupt. 1 Clears interrupt. SSI Receive Overrun Interrupt Clear The RORIC values are defined as follows: Value Description 0 No effect on interrupt. 1 Clears interrupt. April 04, 2010 307 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 308 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 SSI Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. April 04, 2010 309 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 SSI Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 310 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 SSI Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. April 04, 2010 311 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 PID0 RO 0x22 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 312 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. April 04, 2010 313 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 314 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. April 04, 2010 315 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 316 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. April 04, 2010 317 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 318 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. April 04, 2010 319 Texas Instruments-Production Data Ethernet Controller 13 Ethernet Controller ® The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. ® The Stellaris Ethernet Controller module has the following features: ■ Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line – 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler – Full-featured auto-negotiation ■ Multiple operational modes – Full- and half-duplex 100 Mbps – Full- and half-duplex 10 Mbps – Power-saving and power-down modes ■ Highly configurable – Programmable MAC address – LED activity selection – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ■ Physical media manipulation – Automatic MDI/MDI-X cross-over correction – Register-programmable transmit amplitude – Automatic polarity correction and 10BASE-T signal reception 13.1 Block Diagram As shown in Figure 13-1 on page 321, the Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These layers correspond to the OSI model layers 2 and 1. The CPU accesses the Ethernet Controller via the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the PHY layer via an internal Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus. 320 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 13-1. Ethernet Controller ARM Cortex M3 Ethernet Media Controller Physical Access Layer Entity Controller MAC (Layer 2) Magnetics RJ45 PHY (Layer 1) Figure 13-2 on page 321 shows more detail of the internal structure of the Ethernet Controller and how the register set relates to various functions. Figure 13-2. Ethernet Controller Block Diagram Interrupt Interrupt Control Receive Control MACRIS MACIACK MACIM MACRCTL MACNP TXOP Transmit FIFO Data Access Transmit Encoding Pulse Shaping Collision Detect Carrier Sense Receive Decoding Clock Recovery TXON MDIX MACDDATA RXIP Transmit Control MACTCTL Receive FIFO RXIN MACTHR MACTR Media Independent Interface Management Register Set MII Control Individual Address MACIA0 MACIA1 MACMCTL MACMDV MACMTXD MACMRXD MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR16 MR17 MR18 MR19 MR23 MR24 Auto Negotiation XTALPPHY Clock Reference XTALNPHY LED0 LED1 13.2 Functional Description Note: A 12.4-kΩ resistor should be connected between the ERBIAS and ground. The 12.4-kΩ resistor should have a 1% tolerance and should be located in close proximity to the ERBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used. The functional description of the Ethernet Controller is discussed in the following sections. 13.2.1 MAC Operation The following sections decribe the operation of the MAC unit, including an overview of the Ethernet frame format, the MAC layer FIFOs, Ethernet transmission and reception options, and LED indicators. April 04, 2010 321 Texas Instruments-Production Data Ethernet Controller 13.2.1.1 Ethernet Frame Format Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure 13-3 on page 322. Figure 13-3. Ethernet Frame Preamble 7 Bytes SFD Destination Address 1 Byte 6 Bytes Source Address Length/ Type Data FCS 6 Bytes 2 Bytes 46 - 1500 Bytes 4 Bytes The seven fields of the frame are transmitted from left to right. The bits within the frame are transmitted from least to most significant bit. ■ Preamble The Preamble field is used to synchronize with the received frame’s timing. The preamble is 7 octets long. ■ Start Frame Delimiter (SFD) The SFD field follows the preamble pattern and indicates the start of the frame. Its value is 1010.1011. ■ Destination Address (DA) This field specifies destination addresses for which the frame is intended. The LSB (bit 16 of DA oct 1 in the frame, see Table 13-1 on page 323) of the DA determines whether the address is an individual (0), or group/multicast (1) address. ■ Source Address (SA) The source address field identifies the station from which the frame was initiated. ■ Length/Type Field The meaning of this field depends on its numeric value. This field can be interpreted as length or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. The meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified by the IEEE 802.3 standard. However, the Ethernet Controller assumes type interpretation if the value of the Length/Type field is greater than 1500 decimal. The definition of the Type field is specified in the IEEE 802.3 standard. The first of the two octets in this field is most significant. ■ Data The data field is a sequence of octets that is at least 46 in length, up to 1500 in length. Full data transparency is provided so any values can appear in this field. A minimum frame size of 46 octets is required to meet the IEEE standard. If the frame size is too small, the Ethernet Controller automatically appends extra bits (a pad), thus the pad can have a size of 0 to 46 octets. Data padding can be disabled by clearing the PADEN bit in the Ethernet MAC Transmit Control (MACTCTL) register. For the Ethernet Controller, data sent/received can be larger than 1500 bytes without causing a Frame Too Long error. Instead, a FIFO overrun error is reported using the FOV bit in the 322 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Ethernet MAC Raw Interrupt Status(MACRIS) register when the frame received is too large to fit into the Ethernet Controller’s 2K RAM. ■ Frame Check Sequence (FCS) The frame check sequence carries the cyclic redundancy check (CRC) value. The CRC is computed over the destination address, source address, length/type, and data (including pad) fields using the CRC-32 algorithm. The Ethernet Controller computes the FCS value one nibble at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by clearing the CRC bit in the MACTCTL register. For received frames, this field is automatically checked. If the FCS does not pass, the frame is not placed in the RX FIFO, unless the FCS check is disabled by clearing the BADCRC bit in the MACRCTL register. 13.2.1.2 MAC Layer FIFOs The Ethernet Controller is capable of simultaneous transmission and reception. This feature is enabled by setting the DUPLEX bit in the MACTCTL register. For Ethernet frame transmission, a 2 KB transmit FIFO is provided that can be used to store a single frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to 1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload of up to 2032 bytes (as the first 16 bytes in the FIFO are reserved for destination address, source address and length/type information). For Ethernet frame reception, a 2-KB receive FIFO is provided that can be used to store multiple frames, up to a maximum of 31 frames. If a frame is received, and there is insufficient space in the RX FIFO, an overflow error is indicated using the FOV bit in the MACRIS register. For details regarding the TX and RX FIFO layout, refer to Table 13-1 on page 323. Please note the following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions. For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including the Length/Type bytes and the FCS bits. If FCS generation is disabled by clearing the CRC bit in the MACTCTL register, the last word in the TX FIFO must contain the FCS bytes for the frame that has been written to the FIFO. Also note that if the length of the data payload section is not a multiple of 4, the FCS field is not be aligned on a word boundary in the FIFO. However, for the RX FIFO the beginning of the next frame is always on a word boundary. Table 13-1. TX & RX FIFO Organization FIFO Word Read/Write Sequence Word Bit Fields TX FIFO (Write) 1st 7:0 Data Length Least Significant Frame Length Least Byte Significant Byte 15:8 Data Length Most Significant Frame Length Most Significant Byte Byte 23:16 DA oct 1 31:24 DA oct 2 7:0 DA oct 3 15:8 DA oct 4 23:16 DA oct 5 31:24 DA oct 6 2nd April 04, 2010 RX FIFO (Read) 323 Texas Instruments-Production Data Ethernet Controller Table 13-1. TX & RX FIFO Organization (continued) FIFO Word Read/Write Sequence Word Bit Fields 3rd 7:0 SA oct 1 15:8 SA oct 2 23:16 SA oct 3 31:24 SA oct 4 7:0 SA oct 5 15:8 SA oct 6 4th 5th to nth last Note: 13.2.1.3 TX FIFO (Write) RX FIFO (Read) 23:16 Len/Type Most Significant Byte 31:24 Len/Type Least Significant Byte 7:0 data oct n 15:8 data oct n+1 23:16 data oct n+2 31:24 data oct n+3 7:0 FCS 1 15:8 FCS 2 23:16 FCS 3 31:24 FCS 4 If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the correct CRC. If the CRC bit is set, the Ethernet Controller automatically writes the FCS bytes. Ethernet Transmission Options At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation by using the DUPLEX bit in the MACTCTL register. The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing the CRC bit. The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46 bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is set. This feature can be disabled by clearing the PADEN bit. The transmitter must be enabled by setting the TXEN bit in the TCTL register. 13.2.1.4 Ethernet Reception Options The Ethernet Controller RX FIFO should be cleared during software initialization. The receiver should first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL) register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register. The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case, a Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the BADCRC bit in the MACRCTL register. In normal operating mode, the receiver accepts only those frames that have a destination address that matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0) 324 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller and Ethernet MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can also be configured for Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the MACRCTL register. 13.2.2 Internal MII Operation For the MII management interface to function properly, the MDIO signal must be connected through a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents management transactions on this internal MII to function. Note that it is possible for data transmission across the MII to still function since the PHY layer auto-negotiates the link parameters by default. For the MII management interface to function properly, the internal clock must be divided down from the system clock to a frequency no greater than 2.5 MHz. The Ethernet MAC Management Divider (MACMDV) register contains the divider used for scaling down the system clock. See page 344 for more details about the use of this register. 13.2.3 PHY Operation The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external filter is required. 13.2.3.1 Clock Selection The Ethernet Controller has an on-chip crystal oscillator which can also be driven by an external oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground. 13.2.3.2 Auto-Negotiation The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100 Mbps operation over copper wiring. This function is controlled via register settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the auto-negotiation function by clearing the ANEGEN bit. The contents of the Ethernet PHY Management Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller’s link partner during auto-negotiation via fast-link pulse coding. Once auto-negotiation is complete, the DPLX and RATE bits in the Ethernet PHY Management Register 18 - Diagnostic (MR18) register reflect the actual speed and duplex condition. If auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Setting the RANEG bit in the MR0 register also causes auto-negotiation to restart. 13.2.3.3 Polarity Correction The Ethernet Controller is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the Ethernet PHY Management Register 16 - Vendor-Specific (MR16) control this feature. The default is automatic mode, where April 04, 2010 325 Texas Instruments-Production Data Ethernet Controller APOL is clear and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter manual mode, APOL should be set. In manual mode RVSPOL controls the signal polarity. 13.2.3.4 MDI/MDI-X Configuration The Ethernet Controller supports the MDI/MDI-X configuration as defined in IEEE 802.3-2002 specification. The MDI/MDI-X configuration eliminates the need for cross-over cables when connecting to another device, such as a hub. The algorithm is controlled via settings in the Ethernet PHY Management Register 24 - MDI/MIDIX Control (MR24). Refer to page 366 for additional details about these settings. 13.2.3.5 Power Management The PHY has two power-saving modes: ■ Power-Down ■ Receive Power Management Power-down mode is activated by setting the PWRDN bit in the MR0 register. When the PHY is in power-down mode, it consumes minimum power. While in the power-down state, the Ethernet Controller still responds to management transactions. Receive power management (RXCC mode) is activated by setting the RXCC bit in the MR16 register. In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all other receive circuitry are powered down. As soon as a valid signal is detected, all circuits are automatically powered up to resume normal operation. Note that the RXCC mode is not supported during 10BASE-T operation. 13.2.3.6 LED Indicators The Ethernet Controller supports two LED signals that can be used to indicate various states of operation. These signals are mapped to the LED0 and LED1 pins. By default, these pins are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be reconfigured to their alternate function. See “General-Purpose Input/Outputs (GPIOs)” on page 141 for additional details. The function of these pins is programmable via the PHY layer Ethernet PHY Management Register 23 - LED Configuration (MR23). Refer to page 365 for additional details on how to program these LED functions. 13.2.4 Interrupts The Ethernet Controller can generate an interrupt for one or more of the following conditions: ■ A frame has been received into an empty RX FIFO ■ A frame transmission error has occurred ■ A frame has been transmitted successfully ■ A frame has been received with inadequate room in the RX FIFO (overrun) ■ A frame has been received with one or more error conditions (for example, FCS failed) ■ An MII management transaction between the MAC and PHY layers has completed ■ One or more of the following PHY layer conditions occurs: 326 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller – Auto-Negotiate Complete – Remote Fault – Link Status Change – Link Partner Acknowledge – Parallel Detect Fault – Page Received – Receive Error – Jabber Event Detected 13.3 Initialization and Configuration The following sections describe the hardware and software configuration required to set up the Ethernet Controller. 13.3.1 Hardware Configuration Figure 13-4 on page 327 shows the proper method for interfacing the Ethernet Controller to a 10/100BASE-T Ethernet jack. Figure 13-4. Interface to an Ethernet Jack Stellaris Microcontroller PF2/LED1 PF3/LED0 MDIO TXOP 60 59 PF2/LED1 PF3/LED0 +3.3V 10/100BASE-T Ethernet Jack P2 58 R3 +3.3V +3.3V R4 49.9 10K R5 49.9 C2 10pF C3 10pF 43 12 11 R6 330 C4 3 G+ G- 1CT: 1 +3.3V TX+ 1 TX- 2 5 TXON RXIP 0.1UF 46 RX+ 3 4 4 7 40 C5 5 RX- 6 1CT: 1 +3.3V 7 6 8 RXIN 0.1UF 37 +3.3V R8 49.9 R9 49.9 C6 10pF C7 10pF R7 8 +3.3V 2 1 Y- 9 10 NC 330 Y+ GND J3011G21DNL GL GR C13 0.01UF The following isolation transformers have been tested and are known to successfully interface to the Ethernet PHY layer. ■ Isolation Transformers – TDK TLA-6T103 – Bel-Fuse S558-5999-46 – Halo TG22-3506ND – Pulse PE-68515 – Valor ST6118 April 04, 2010 327 Texas Instruments-Production Data Ethernet Controller – YCL 20PMT04 ■ Isolation transformers in low profile packages (0.100 in/2.5 mm or less) – TDK TLA-6T118 – Halo TG110-S050 – PCA EPF8023G ■ Isolation transformers with integrated RJ45 connector – TDK TLA-6T704 – Delta RJS-1A08T089A ■ Isolation transformers with integrated RJ45 connector, LEDs and termination resistors – Pulse J0011D21B/E – Pulse J3011G21DNL 13.3.2 Software Configuration To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the RCGC2 register (see page 106). The following steps can then be used to configure the Ethernet Controller for basic operation. 1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming a 20-MHz system clock, the MACDIV value should be 0x03 or greater. 2. Program the MACIA0 and MACIA1 register for address filtering. 3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a value of 0x16. 4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using a value of 0x18. 5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers. 6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA) register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available for the next transmit frame. 7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP) register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet() API or compare the number of bytes received to the Length field from the frame to determine when the packet has been completely read. 13.4 Ethernet Register Map Table 13-2 on page 329 lists the Ethernet MAC registers. All addresses given are relative to the Ethernet MAC base address of 0x4004.8000. The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of the IEEE 802.3 specification. Table 13-2 on page 329 also lists these MII Management registers. All addresses given are absolute and are written directly to the REGADR field of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15 are defined by the IEEE specification and are common to all PHY layer implementations. The only variance allowed is for features that may or may not be supported by a specific PHY implementation. 328 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendor's PHY implementation. Vendor-specific registers not listed are reserved. Table 13-2. Ethernet Register Map Offset Name Description See page Type Reset R/W1C 0x0000.0000 Ethernet MAC Raw Interrupt Status/Acknowledge 331 Ethernet MAC 0x000 MACRIS/MACIACK 0x004 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 334 0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 335 0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 336 0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 337 0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 339 0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 340 0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 341 0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 343 0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 344 0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 345 0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 346 0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 347 0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 348 MII Management - MR0 R/W 0x3100 Ethernet PHY Management Register 0 – Control 349 - MR1 RO 0x7849 Ethernet PHY Management Register 1 – Status 351 - MR2 RO 0x000E Ethernet PHY Management Register 2 – PHY Identifier 1 353 - MR3 RO 0x7237 Ethernet PHY Management Register 3 – PHY Identifier 2 354 - MR4 R/W 0x01E1 Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement 355 - MR5 RO 0x0000 Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability 357 - MR6 RO 0x0000 Ethernet PHY Management Register 6 – Auto-Negotiation Expansion 358 - MR16 R/W 0x0140 Ethernet PHY Management Register 16 – Vendor-Specific 359 - MR17 R/W 0x0000 Ethernet PHY Management Register 17 – Interrupt Control/Status 361 - MR18 RO 0x0000 Ethernet PHY Management Register 18 – Diagnostic 363 April 04, 2010 329 Texas Instruments-Production Data Ethernet Controller Table 13-2. Ethernet Register Map (continued) See page Offset Name Type Reset Description - MR19 R/W 0x4000 Ethernet PHY Management Register 19 – Transceiver Control 364 - MR23 R/W 0x0010 Ethernet PHY Management Register 23 – LED Configuration 365 - MR24 R/W 0x00C0 Ethernet PHY Management Register 24 –MDI/MDIX Control 366 13.5 Ethernet MAC Register Descriptions The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by address offset. Also see “MII Management Register Descriptions” on page 348. 330 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. On a write, setting any bit clears the corresponding interrupt status bit. Reads Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Base 0x4004.8000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PHYINT MDINT RXER FOV TXEMP TXER RXINT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 PHYINT RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY Interrupt When set, indicates that an enabled interrupt in the PHY layer has occurred. MR17 in the PHY must be read to determine the specific PHY event that triggered this interrupt. 5 MDINT RO 0 MII Transaction Complete When set, indicates that a transaction (read or write) on the MII interface has completed successfully. 4 RXER RO 0 Receive Error This bit indicates that an error was encountered on the receiver. The possible errors that can cause this interrupt bit to be set are: 3 FOV RO 0 ■ A receive error occurs during the reception of a frame (100 Mb/s only). ■ The frame is not an integer number of bytes (dribble bits) due to an alignment error. ■ The CRC of the frame does not pass the FCS check. ■ The length/type field is inconsistent with the frame data size when interpreted as a length field. FIFO Overrun When set, indicates that an overrun was encountered on the receive FIFO. April 04, 2010 331 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 2 TXEMP RO 0 Description Transmit FIFO Empty When set, indicates that the packet was transmitted and that the TX FIFO is empty. 1 TXER RO 0 Transmit Error When set, indicates that an error was encountered on the transmitter. The possible errors that can cause this interrupt bit to be set are: 0 RXINT RO 0 ■ The data length field stored in the TX FIFO exceeds 2032 decimal (buffer length - 16 bytes of header data). The frame is not sent when this error occurs. ■ The retransmission attempts during the backoff process have exceeded the maximum limit of 16 decimal. Packet Received When set, indicates that at least one packet has been received and is stored in the receiver FIFO. Writes Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Base 0x4004.8000 Offset 0x000 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 PHYINT W1C 0 RO 0 RO 0 6 5 4 3 2 1 0 PHYINT MDINT RXER FOV TXEMP TXER RXINT W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear PHY Interrupt Setting this bit clears the PHYINT interrupt in the MACRIS register. 5 MDINT W1C 0 Clear MII Transaction Complete Setting this bit clears the MDINT interrupt in the MACRIS register. 4 RXER W1C 0 Clear Receive Error Setting this bit clears the RXER interrupt in the MACRIS register. 3 FOV W1C 0 Clear FIFO Overrun Setting this bit clears the FOV interrupt in the MACRIS register. 332 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 2 TXEMP W1C 0 Description Clear Transmit FIFO Empty Setting this bit clears the TXEMP interrupt in the MACRIS register. 1 TXER W1C 0 Clear Transmit Error Setting this bit clears the TXER interrupt in the MACRIS register and resets the TX FIFO write pointer. 0 RXINT W1C 0 Clear Packet Received Setting this bit clears the RXINT interrupt in the MACRIS register. April 04, 2010 333 Texas Instruments-Production Data Ethernet Controller Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the interrupt, while setting the bit enables it. Ethernet MAC Interrupt Mask (MACIM) Base 0x4004.8000 Offset 0x004 Type R/W, reset 0x0000.007F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RXERM FOVM TXEMPM TXERM RXINTM RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset reserved Type Reset PHYINTM MDINTM RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 PHYINTM R/W 1 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Mask PHY Interrupt Clearing this bit masks the PHYINT bit in the MACRIS register from being set. 5 MDINTM R/W 1 Mask MII Transaction Complete Clearing this bit masks the MDINT bit in the MACRIS register from being set. 4 RXERM R/W 1 Mask Receive Error Clearing this bit masks the RXER bit in the MACRIS register from being set. 3 FOVM R/W 1 Mask FIFO Overrun Clearing this bit masks the FOV bit in the MACRIS register from being set. 2 TXEMPM R/W 1 Mask Transmit FIFO Empty Clearing this bit masks the TXEMP bit in the MACRIS register from being set. 1 TXERM R/W 1 Mask Transmit Error Clearing this bit masks the TXER bit in the MACRIS register from being set. 0 RXINTM R/W 1 Mask Packet Received Clearing this bit masks the RXINT bit in the MACRIS register from being set. 334 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 This register configures the receiver and controls the types of frames that are received. It is important to note that when the receiver is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO, even if the AMUL bit is not set. Ethernet MAC Receive Control (MACRCTL) Base 0x4004.8000 Offset 0x008 Type R/W, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RSTFIFO BADCRC RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 RSTFIFO R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 2 1 0 PRMS AMUL RXEN R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear Receive FIFO When set, this bit clears the receive FIFO. This should be done when software initialization is performed. It is recommended that the receiver be disabled (RXEN = 0), before a reset is initiated (RSTFIFO = 1). This sequence flushes and resets the RX FIFO. This bit is automatically cleared when read. 3 BADCRC R/W 1 Enable Reject Bad CRC When set, the BADCRC bit enables the rejection of frames with an incorrectly calculated CRC. If a bad CRC is encountered, the RXER bit in the MACRIS register is set and the receiver FIFO is reset. 2 PRMS R/W 0 Enable Promiscuous Mode When set, the PRMS bit enables Promiscuous mode, which accepts all valid frames, regardless of the specified Destination Address. 1 AMUL R/W 0 Enable Multicast Frames When set, the AMUL bit enables the reception of multicast frames. 0 RXEN R/W 0 Enable Receiver When set the RXEN bit enables the Ethernet receiver. When this bit is clear, the receiver is disabled and all frames are ignored. April 04, 2010 335 Texas Instruments-Production Data Ethernet Controller Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C This register configures the transmitter and controls the frames that are transmitted. Ethernet MAC Transmit Control (MACTCTL) Base 0x4004.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 DUPLEX reserved CRC PADEN TXEN RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 DUPLEX R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Duplex Mode When set, this bit enables Duplex mode, allowing simultaneous transmission and reception. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 CRC R/W 0 Enable CRC Generation When set this bit enables the automatic generation of the CRC and its placement at the end of the packet. If this bit is clear, the frames placed in the TX FIFO are sent exactly as they are written into the FIFO. Note that this bit should generally be set. 1 PADEN R/W 0 Enable Packet Padding When set, this bit enables the automatic padding of packets that do not meet the minimum frame size. Note that this bit should generally be set. 0 TXEN R/W 0 Enable Transmitter When set, this bit enables the transmitter. When this bit is clear, the transmitter is disabled. 336 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 5: Ethernet MAC Data (MACDATA), offset 0x010 Important: Use caution when reading this register. Performing a read may change bit status. This register enables software to access the TX and RX FIFOs. Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. The read pointer is then auto incremented to the next RX FIFO location. Reading from the RX FIFO when a frame has not been received or is in the process of being received will return indeterminate data and not increment the read pointer. Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write pointer is the auto incremented to the next TX FIFO location. Writing more data into the TX FIFO than indicated in the length field will result in the data being lost. Writing less data into the TX FIFO than indicated in the length field will result in indeterminate data being appended to the end of the frame to achieve the indicated length. Attempting to write the next frame into the TX FIFO before transmission of the first has completed will result in the data being lost. There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data re-written. Reads Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RXDATA Type Reset RXDATA Type Reset Bit/Field Name Type 31:0 RXDATA RO Reset Description 0x0000.0000 Receive FIFO Data The RXDATA bits represent the next word of data stored in the RX FIFO. April 04, 2010 337 Texas Instruments-Production Data Ethernet Controller Writes Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 TXDATA Type Reset TXDATA Type Reset Bit/Field Name Type 31:0 TXDATA WO Reset Description 0x0000.0000 Transmit FIFO Data The TXDATA bits represent the next word of data to place in the TX FIFO for transmission. 338 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte Individual Address is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 0 (MACIA0) Base 0x4004.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 R/W 0 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 11 10 9 8 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MACOCT4 Type Reset 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 MACOCT3 MACOCT2 Type Reset 19 MACOCT1 R/W 0 Bit/Field Name Type Reset Description 31:24 MACOCT4 R/W 0x00 MAC Address Octet 4 R/W 0 The MACOCT4 bits represent the fourth octet of the MAC address used to uniquely identify the Ethernet Controller. 23:16 MACOCT3 R/W 0x00 MAC Address Octet 3 The MACOCT3 bits represent the third octet of the MAC address used to uniquely identify the Ethernet Controller. 15:8 MACOCT2 R/W 0x00 MAC Address Octet 2 The MACOCT2 bits represent the second octet of the MAC address used to uniquely identify the Ethernet Controller. 7:0 MACOCT1 R/W 0x00 MAC Address Octet 1 The MACOCT1 bits represent the first octet of the MAC address used to uniquely identify the Ethernet Controller. April 04, 2010 339 Texas Instruments-Production Data Ethernet Controller Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 1 (MACIA1) Base 0x4004.8000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset MACOCT6 Type Reset MACOCT5 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:8 MACOCT6 R/W 0x00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC Address Octet 6 The MACOCT6 bits represent the sixth octet of the MAC address used to uniquely identify each Ethernet Controller. 7:0 MACOCT5 R/W 0x00 MAC Address Octet 5 The MACOCT5 bits represent the fifth octet of the MAC address used to uniquely identify the Ethernet Controller. 340 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C In order to increase the transmission rate, it is possible to program the Ethernet Controller to begin transmission of the next frame prior to the completion of the transmission of the current frame. Note: Extreme care must be used when implementing this function. Software must be able to guarantee that the complete frame is able to be stored in the transmission FIFO prior to the completion of the transmission frame. This register enables software to set the threshold level at which the transmission of the frame begins. If the THRESH bits are set to 0x3F, which is the reset value, the early transmission feature is disabled, and transmission does not start until the NEWTX bit is set in the MACTR register. Writing the THRESH bits to any value besides 0x3F enables the early transmission feature. Once the byte count of data in the TX FIFO reaches the value derived from the THRESH bits as shown below, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 causes the transmitter to wait for 36 bytes of data to be written while a value of 0x02 makes the wait equal to 68 bytes of written data. In general, early transmission starts when: Number of Bytes >= 4 (THRESH x 8 + 1) Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register. Transmission of the frame begins and then the number of bytes indicated by the Data Length field is transmitted. Because under-run checking is not performed, if any event, such as an interrupt, delays the filling of the FIFO, the tail pointer may reach and pass the write pointer in the TX FIFO. In this event, indeterminate values are transmitted rather than the end of the frame. Therefore, sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software. If a frame smaller than the threshold level must be sent, the NEWTX bit in the MACTR register must be set with an explicit write. This initiates the transmission of the frame even though the threshold limit has not been reached. If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the transmit frame is aborted, and a transmit error occurs. Note that in this case, the TXER bit in the MACRIS is not set meaning that the CPU receives no indication that a transmit error happened. Ethernet MAC Threshold (MACTHR) Base 0x4004.8000 Offset 0x01C Type R/W, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 THRESH RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 341 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset Description 5:0 THRESH R/W 0x3F Threshold Value The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO exceeds the value represented by the above equation, transmission of the packet begins. 342 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 This register enables software to control the transfer of data to and from the MII Management registers in the Ethernet PHY layer. The address, name, type, reset configuration, and functional description of each of these registers can be found in Table 13-2 on page 329 and in “MII Management Register Descriptions” on page 348. In order to initiate a read transaction from the MII Management registers, the WRITE bit must be cleared during the same cycle that the START bit is set. In order to initiate a write transaction to the MII Management registers, the WRITE bit must be set during the same cycle that the START bit is set. Ethernet MAC Management Control (MACMCTL) Base 0x4004.8000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 reserved WRITE START RO 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset REGADR RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:3 REGADR R/W 0x0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MII Register Address The REGADR bit field represents the MII Management register address for the next MII management interface transaction. Refer to Table 13-2 on page 329 for the PHY register offsets. Note that any address that is not valid in the register map should not be written to and any data read should be ignored. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 WRITE R/W 0 MII Register Transaction Type The WRITE bit represents the operation of the next MII management interface transaction. If WRITE is set, the next operation is a write; if WRITE is clear, the next transaction is a read. 0 START R/W 0 MII Register Transaction Enable The START bit represents the initiation of the next MII management interface transaction. When this bit is set, the MII register located at REGADR is read (WRITE=0) or written (WRITE=1). April 04, 2010 343 Texas Instruments-Production Data Ethernet Controller Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 This register enables software to set the clock divider for the Management Data Clock (MDC). This clock is used to synchronize read and write transactions between the system and the MII Management registers. The frequency of the MDC clock can be calculated from the following formula: The clock divider must be written with a value that ensures that the MDC clock does not exceed a frequency of 2.5 MHz. Ethernet MAC Management Divider (MACMDV) Base 0x4004.8000 Offset 0x024 Type R/W, reset 0x0000.0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DIV RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DIV R/W 0x80 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Divider The DIV bits are used to set the clock divider for the MDC clock used to transmit data between the MAC and PHY layers over the serial MII interface. 344 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C This register holds the next value to be written to the MII Management registers. Ethernet MAC Management Transmit Data (MACMTXD) Base 0x4004.8000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 MDTX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MDTX R/W 0x0000 MII Register Transmit Data The MDTX bits represent the data that will be written in the next MII management transaction. April 04, 2010 345 Texas Instruments-Production Data Ethernet Controller Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 This register holds the last value read from the MII Management registers. Ethernet MAC Management Receive Data (MACMRXD) Base 0x4004.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 MDRX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MDRX R/W 0x0000 MII Register Receive Data The MDRX bits represent the data that was read in the previous MII management transaction. 346 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there are no frames in the RX FIFO, and the RXINT bit is clear. When NPR is any other value, at least one frame is in the RX FIFO, and the RXINT bit in the MACRIS register is set. Note: The FCS bytes are not included in the NPR value. As a result, the NPR value could be zero before the FCS bytes are read from the FIFO. In addition, a new packet could be received before the NPR value reaches zero. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet() API or compare the number of bytes received to the Length field from the frame to determine when the packet has been completely read. Ethernet MAC Number of Packets (MACNP) Base 0x4004.8000 Offset 0x034 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 NPR RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:0 NPR RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Number of Packets in Receive FIFO The NPR bits represent the number of packets stored in the RX FIFO. While the NPR field is greater than 0, the RXINT interrupt in the MACRIS register is set. April 04, 2010 347 Texas Instruments-Production Data Ethernet Controller Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 This register enables software to initiate the transmission of the frame currently located in the TX FIFO. Once the frame has been transmitted from the TX FIFO or a transmission error has been encountered, the NEWTX bit is automatically cleared. Ethernet MAC Transmission Request (MACTR) Base 0x4004.8000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 NEWTX R/W 0 RO 0 NEWTX R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. New Transmission When set, the NEWTX bit initiates an Ethernet transmission once the packet has been placed in the TX FIFO. This bit is cleared once the transmission has been completed. If early transmission is being used (see the MACTHR register), this bit does not need to be set. 13.6 MII Management Register Descriptions The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers. All addresses given are absolute. Addresses not listed are reserved; these addresses should not be written to and any data read should be ignored. Also see “Ethernet MAC Register Descriptions” on page 330. 348 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 15: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 This register enables software to configure the operation of the PHY layer. The default settings of these registers are designed to initialize the Ethernet Controller to a normal operational mode without configuration. Ethernet PHY Management Register 0 – Control (MR0) Base 0x4004.8000 Address 0x00 Type R/W, reset 0x3100 15 RESET Type Reset R/W 0 14 13 12 11 LOOPBK SPEEDSL ANEGEN PWRDN R/W 0 R/W 1 R/W 1 R/W 0 10 9 8 7 ISO RANEG DUPLEX COLT R/W 0 R/W 0 R/W 1 R/W 0 Bit/Field Name Type Reset 15 RESET R/W 0 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 R/W 0 Description Reset Registers When set, this bit resets the PHY layer registers to their default state and reinitializes internal state machines. Once the reset operation has completed, this bit is cleared by hardware. 14 LOOPBK R/W 0 Loopback Mode When set, this bit enables the Loopback mode of operation. The receiver ignores external inputs and receives the data that is transmitted by the transmitter. 13 SPEEDSL R/W 1 Speed Select Value Description 12 ANEGEN R/W 1 1 Enables the 100 Mb/s mode of operation (100BASE-TX). 0 Enables the 10 Mb/s mode of operation (10BASE-T). Auto-Negotiation Enable When set, this bit enables the auto-negotiation process. 11 PWRDN R/W 0 Power Down When set, this bit places the PHY layer into a low-power consuming state. All data on the data inputs is ignored. 10 ISO R/W 0 Isolate When set, this bit isolates the transmit and receive data paths and ignores all data being transmitted and received. 9 RANEG R/W 0 Restart Auto-Negotiation When set, this bit restarts the auto-negotiation process. Once the restart has initiated, this bit is cleared by hardware. April 04, 2010 349 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 8 DUPLEX R/W 1 Description Set Duplex Mode Value Description 7 COLT R/W 0 1 Enables the Full-Duplex mode of operation. This bit can be set by software in a manual configuration process or by the auto-negotiation process. 0 Enables the Half-Duplex mode of operation. Collision Test When set, this bit enables the Collision Test mode of operation. The COLT bit is set after the initiation of a transmission and is cleared once the transmission is halted. 6:0 reserved R/W 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. These bits should always be written as zero. 350 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 16: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 This register enables software to determine the capabilities of the PHY layer and perform its initialization and operation appropriately. Ethernet PHY Management Register 1 – Status (MR1) Base 0x4004.8000 Address 0x01 Type RO, reset 0x7849 Type Reset 15 14 13 12 11 reserved 100X_F 100X_H 10T_F 10T_H 10 RO 0 RO 1 RO 1 RO 1 RO 1 9 8 7 reserved RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 MFPS ANEGC RFAULT ANEGA LINK JAB EXTD RO 1 RO 0 RC 0 RO 1 RO 0 RC 0 RO 1 Bit/Field Name Type Reset Description 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 100X_F RO 1 100BASE-TX Full-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of supporting 100BASE-TX Full-Duplex mode. 13 100X_H RO 1 100BASE-TX Half-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of supporting 100BASE-TX Half-Duplex mode. 12 10T_F RO 1 10BASE-T Full-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of 10BASE-T Full-Duplex mode. 11 10T_H RO 1 10BASE-T Half-Duplex Mode When set, this bit indicates that the Ethernet Controller is capable of supporting 10BASE-T Half-Duplex mode. 10:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 MFPS RO 1 Management Frames with Preamble Suppressed When set, this bit indicates that the Management Interface is capable of receiving management frames with the preamble suppressed. 5 ANEGC RO 0 Auto-Negotiation Complete When set, this bit indicates that the auto-negotiation process has been completed and that the extended registers defined by the auto-negotiation protocol are valid. 4 RFAULT RC 0 Remote Fault When set, this bit indicates that a remote fault condition has been detected. This bit remains set until it is read, even if the condition no longer exists. April 04, 2010 351 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 3 ANEGA RO 1 Description Auto-Negotiation When set, this bit indicates that the Ethernet Controller has the ability to perform auto-negotiation. 2 LINK RO 0 Link Made When set, this bit indicates that a valid link has been established by the Ethernet Controller. 1 JAB RC 0 Jabber Condition When set, this bit indicates that a jabber condition has been detected by the Ethernet Controller. This bit remains set until it is read, even if the jabber condition no longer exists. 0 EXTD RO 1 Extended Capabilities When set, this bit indicates that the Ethernet Controller provides an extended set of capabilities that can be accessed through the extended register set. 352 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 17: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Base 0x4004.8000 Address 0x02 Type RO, reset 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 0 OUI[21:6] Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15:0 OUI[21:6] RO 0x000E RO 0 Description Organizationally Unique Identifier[21:6] This field, along with the OUI[5:0] field in MR3, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. April 04, 2010 353 Texas Instruments-Production Data Ethernet Controller Register 18: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3) Base 0x4004.8000 Address 0x03 Type RO, reset 0x7237 15 14 13 12 11 10 9 8 7 OUI[5:0] Type Reset RO 0 RO 1 RO 1 RO 1 6 5 4 3 2 MN RO 0 RO 0 RO 1 RO 0 RO 0 1 0 RO 1 RO 1 RN RO 0 RO 1 RO 1 Bit/Field Name Type Reset Description 15:10 OUI[5:0] RO 0x1C Organizationally Unique Identifier[5:0] RO 0 RO 1 This field, along with the OUI[21:6] field in MR2, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. 9:4 MN RO 0x23 Model Number The MN field represents the Model Number of the PHY. 3:0 RN RO 0x7 Revision Number The RN field represents the Revision Number of the PHY implementation. 354 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 19: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 This register provides the advertised abilities of the Ethernet Controller used during auto-negotiation. Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to auto-negotiate to an alternate common technology. Writing to this register has no effect until auto-negotiation is re-initiated by setting the RANEG bit in the MR0 register. Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4) Base 0x4004.8000 Address 0x04 Type R/W, reset 0x01E1 Type Reset 15 14 13 NP reserved RF 12 RO 0 RO 0 R/W 0 11 10 9 reserved RO 0 RO 0 RO 0 RO 0 8 7 6 5 A3 A2 A1 A0 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 15 NP RO 0 Next Page 4 3 2 1 0 RO 0 RO 1 S RO 0 RO 0 RO 0 When set, this bit indicates the Ethernet Controller is capable of Next Page exchanges to provide more detailed information on the PHY layer’s capabilities. 14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 RF R/W 0 Remote Fault When set, this bit indicates to the link partner that a Remote Fault condition has been encountered. 12:9 reserved RO 0x0 8 A3 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Technology Ability Field[3] When set, this bit indicates that the Ethernet Controller supports the 100Base-TX full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register. 7 A2 R/W 1 Technology Ability Field[2] When set, this bit indicates that the Ethernet Controller supports the 100Base-TX half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register. 6 A1 R/W 1 Technology Ability Field[1] When set, this bit indicates that the Ethernet Controller supports the 10BASE-T full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register.. April 04, 2010 355 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 5 A0 R/W 1 Description Technology Ability Field[0] When set, this bit indicates that the Ethernet Controller supports the 10BASE-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register.. 4:0 S RO 0x1 Selector Field The S field encodes 32 possible messages for communicating between Ethernet Controllers. This field is hard-coded to 0x01, indicating that ® the Stellaris Ethernet Controller is IEEE 802.3 compliant. 356 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 20: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 This register provides the advertised abilities of the link partner’s Ethernet Controller that are received and stored during auto-negotiation. Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5) Base 0x4004.8000 Address 0x05 Type RO, reset 0x0000 Type Reset 15 14 13 NP ACK RF RO 0 RO 0 RO 0 12 11 10 9 8 7 6 5 4 3 A[7:0] RO 0 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 S RO 0 RO 0 Bit/Field Name Type Reset Description 15 NP RO 0 Next Page RO 0 RO 0 RO 0 RO 0 RO 0 When set, this bit indicates that the link partner’s Ethernet Controller is capable of Next page exchanges to provide more detailed information on the Ethernet Controller’s capabilities. 14 ACK RO 0 Acknowledge When set, this bit indicates that the Ethernet Controller has successfully received the link partner’s advertised abilities during auto-negotiation. 13 RF RO 0 Remote Fault Used as a standard transport mechanism for transmitting simple fault information from the link partner. 12:5 A[7:0] RO 0x00 Technology Ability Field The A[7:0] field encodes individual technologies that are supported by the Ethernet Controller. See the MR4 register for definitions. Note that bits 12:9 describe functions that are not implemented on the ® Stellaris Ethernet Controller. Refer to the IEEE 802.3 standard for definitions. 4:0 S RO 0x00 Selector Field The S field encodes possible messages for communicating between Ethernet Controllers. Value Description 0x00 Reserved 0x01 IEEE Std 802.3 0x02 IEEE Std 802.9 ISLAN-16T 0x03 IEEE Std 802.5 0x04 IEEE Std 1394 0x05–0x1F Reserved April 04, 2010 357 Texas Instruments-Production Data Ethernet Controller Register 21: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 This register enables software to determine the auto-negotiation and next page capabilities of the Ethernet Controller and the link partner after auto-negotiation. Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Base 0x4004.8000 Address 0x06 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 4 3 2 1 0 PDF LPNPA reserved PRX LPANEGA RC 0 RO 0 RO 0 RC 0 RO 0 Bit/Field Name Type Reset Description 15:5 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 PDF RC 0 Parallel Detection Fault When set, this bit indicates that more than one technology has been detected at link up. This bit is cleared when read. 3 LPNPA RO 0 Link Partner is Next Page Able When set, this bit indicates that the link partner is enabled to support next page. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 PRX RC 0 New Page Received When set, this bit indicates that a new page has been received from the link partner and stored. This bit remains set until the register is read. 0 LPANEGA RO 0 Link Partner is Auto-Negotiation Able When set, this bit indicates that the link partner is enabled to support auto-negotiation. 358 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 22: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 This register enables software to configure the operation of vendor-specific modes of the Ethernet Controller. Ethernet PHY Management Register 16 – Vendor-Specific (MR16) Base 0x4004.8000 Address 0x10 Type R/W, reset 0x0140 Type Reset 15 14 13 12 11 10 RPTR INPOL reserved TXHIM SQEI NL10 R/W 0 R/W0 0 RO 0 R/W 0 R/W 0 R/W 0 9 8 7 6 reserved RO 0 Bit/Field Name Type Reset 15 RPTR R/W 0 RO 1 RO 0 RO 1 5 4 APOL RVSPOL R/W 0 R/W 0 3 2 reserved RO 0 RO 0 1 0 PCSBP RXCC R/W 0 R/W 0 Description Repeater Mode When set, this bit enables the repeater mode of operation. In this mode, full-duplex is not allowed and the Carrier Sense signal only responds to receive activity. 14 INPOL R/W0 0 Interrupt Polarity Value Description 1 Sets the polarity of the PHY interrupt to be active High. 0 Sets the polarity of the PHY interrupt to active Low. Important: Because the Media Access Controller expects active Low interrupts from the PHY, this bit must always be written with a 0 to ensure proper operation. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 TXHIM R/W 0 Transmit High Impedance Mode When set, this bit enables the transmitter High Impedance mode. In this mode, the TXOP and TXON transmitter pins are put into a high impedance state. The RXIP and RXIN pins remain fully functional. 11 SQEI R/W 0 SQE Inhibit Testing When set, this bit prohibits 10BASE-T SQE testing. When clear, the SQE testing is performed by generating a collision pulse following the completion of the transmission of a frame. 10 NL10 R/W 0 Natural Loopback Mode When set, this bit enables the 10BASE-T Natural Loopback mode. In this mode, the transmission data received by the Ethernet Controller is looped back onto the receive data path when 10BASE-T mode is enabled. 9:6 reserved RO 0x5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 359 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 5 APOL R/W 0 Description Auto-Polarity Disable When set, this bit disables the Ethernet Controller’s auto-polarity function. If this bit is clear, the Ethernet Controller automatically inverts the received signal due to a wrong polarity connection during auto-negotiation when in 10BASE-T mode. 4 RVSPOL R/W 0 Receive Data Polarity This bit indicates whether the receive data pulses are being inverted. If the APOL bit is 0, then the RVSPOL bit is read-only and indicates whether the auto-polarity circuitry is reversing the polarity. In this case, if RVSPOL is set, it indicates that the receive data is inverted; if RVSPOL is clear, it indicates that the receive data is not inverted. If the APOL bit is 1, then the RVSPOL bit is writable and software can force the receive data to be inverted. Setting RVSPOL to 1 forces the receive data to be inverted; clearing RVSPOL does not invert the receive data. 3:2 reserved RO 0x0 1 PCSBP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PCS Bypass When set, this bit enables the bypass of the PCS and scrambling/descrambling functions in 100BASE-TX mode. This mode is only valid when auto-negotiation is disabled and 100BASE-TX mode is enabled. 0 RXCC R/W 0 Receive Clock Control When set, this bit enables the Receive Clock Control power saving mode if the Ethernet Controller is configured in 100BASE-TX mode. This mode shuts down the receive clock when no data is being received to save power. This mode should not be used when PCSBP is enabled and is automatically disabled when the LOOPBK bit in the MR0 register is set. 360 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 23: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 This register provides the means for controlling and observing the events which trigger a PHY layer interrupt in the MACRIS register. This register can also be used in a polling mode via the Media Independent Interface as a means to observe key events within the PHY layer via one register address. Bits 0 through 7 are status bits which are each set based on an event. These bits are cleared after the register is read. Bits 8 through 15 of this register, when set, enable the corresponding bit in the lower byte to signal a PHY layer interrupt in the MACRIS register. Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17) Base 0x4004.8000 Address 0x11 Type R/W, reset 0x0000 15 JABBER_IE Type Reset R/W 0 14 13 RXER_IE PRX_IE R/W 0 12 11 PDF_IE LPACK_IE R/W 0 R/W 0 R/W 0 10 9 8 7 6 LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT R/W 0 R/W 0 Bit/Field Name Type Reset 15 JABBER_IE R/W 0 R/W 0 RC 0 5 4 3 2 PRX_INT PDF_INT LPACK_INT LSCHG_INT RC 0 RC 0 RC 0 RC 0 RC 0 1 0 RFAULT_INT ANEGCOMP_INT RC 0 RC 0 Description Jabber Interrupt Enable When set, this bit enables system interrupts when a Jabber condition is detected by the Ethernet Controller. 14 RXER_IE R/W 0 Receive Error Interrupt Enable When set, this bit enables system interrupts when a receive error is detected by the Ethernet Controller. 13 PRX_IE R/W 0 Page Received Interrupt Enable When set, this bit enables system interrupts when a new page is received by the Ethernet Controller. 12 PDF_IE R/W 0 Parallel Detection Fault Interrupt Enable When set, this bit enables system interrupts when a Parallel Detection Fault is detected by the Ethernet Controller. 11 LPACK_IE R/W 0 LP Acknowledge Interrupt Enable When set, this bit enables system interrupts when FLP bursts are received with the ACK bit in the MR5 register during auto-negotiation. 10 LSCHG_IE R/W 0 Link Status Change Interrupt Enable When set, this bit enables system interrupts when the link status changes from OK to FAIL. 9 RFAULT_IE R/W 0 Remote Fault Interrupt Enable When set, this bit enables system interrupts when a remote fault condition is signaled by the link partner. 8 ANEGCOMP_IE R/W 0 Auto-Negotiation Complete Interrupt Enable When set, this bit enables system interrupts when the auto-negotiation sequence has completed successfully. April 04, 2010 361 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 7 JABBER_INT RC 0 Description Jabber Event Interrupt When set, this bit indicates that a Jabber event has been detected by the 10BASE-T circuitry. 6 RXER_INT RC 0 Receive Error Interrupt When set, this bit indicates that a receive error has been detected by the Ethernet Controller. 5 PRX_INT RC 0 Page Receive Interrupt When set, this bit indicates that a new page has been received from the link partner during auto-negotiation. 4 PDF_INT RC 0 Parallel Detection Fault Interrupt When set, this bit indicates that a parallel detection fault has been detected by the Ethernet Controller during the auto-negotiation process. 3 LPACK_INT RC 0 LP Acknowledge Interrupt When set, this bit indicates that an FLP burst has been received with the ACK bit set in the MR5 register during auto-negotiation. 2 LSCHG_INT RC 0 Link Status Change Interrupt When set, this bit indicates that the link status has changed from OK to FAIL. 1 RFAULT_INT RC 0 Remote Fault Interrupt When set, this bit indicates that a remote fault condition has been signaled by the link partner. 0 ANEGCOMP_INT RC 0 Auto-Negotiation Complete Interrupt When set, this bit indicates that the auto-negotiation sequence has completed successfully. 362 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 24: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 This register enables software to diagnose the results of the previous auto-negotiation. Ethernet PHY Management Register 18 – Diagnostic (MR18) Base 0x4004.8000 Address 0x12 Type RO, reset 0x0000 15 14 13 reserved Type Reset RO 0 RO 0 12 11 10 9 8 ANEGF DPLX RATE RXSD RX_LOCK RC 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15:13 reserved RO 0x0 12 ANEGF RC 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto-Negotiation Failure When set, this bit indicates that no common technology was found during auto-negotiation and auto-negotiation has failed. This bit remains set until read. 11 DPLX RO 0 Duplex Mode When set, this bit indicates that Full-Duplex was the highest common denominator found during the auto-negotiation process. Otherwise, Half-Duplex was the highest common denominator found. 10 RATE RO 0 Rate When set, this bit indicates that 100BASE-TX was the highest common denominator found during the auto-negotiation process. Otherwise, 10BASE-T was the highest common denominator found. 9 RXSD RO 0 Receive Detection When set, this bit indicates that receive signal detection has occurred (in 100BASE-TX mode) or that Manchester-encoded data has been detected (in 10BASE-T mode). 8 RX_LOCK RO 0 Receive PLL Lock When set, this bit indicates that the Receive PLL has locked onto the receive signal for the selected speed of operation (10BASE-T or 100BASE-TX). 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 363 Texas Instruments-Production Data Ethernet Controller Register 25: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 This register enables software to set the gain of the transmit output to compensate for transformer loss. Ethernet PHY Management Register 19 – Transceiver Control (MR19) Base 0x4004.8000 Address 0x13 Type R/W, reset 0x4000 15 14 13 12 11 10 9 8 7 TXO Type Reset R/W 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved R/W 1 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15:14 TXO R/W 0x1 RO 0 RO 0 Description Transmit Amplitude Selection The TXO field sets the transmit output amplitude to account for transmit transformer insertion loss. Value Description 13:0 reserved RO 0x000 0x0 Gain set for 0.0dB of insertion loss 0x1 Gain set for 0.4dB of insertion loss 0x2 Gain set for 0.8dB of insertion loss 0x3 Gain set for 1.2dB of insertion loss Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 364 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 26: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 This register enables software to select the source that causes the LED1 and LED0 signals to toggle. Ethernet PHY Management Register 23 – LED Configuration (MR23) Base 0x4004.8000 Address 0x17 Type R/W, reset 0x0010 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 5 4 3 LED1[3:0] RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 2 1 0 LED0[3:0] R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 LED1[3:0] R/W 0x1 LED1 Source The LED1 field selects the source that toggles the LED1 signal. Value Description 3:0 LED0[3:0] R/W 0x0 0x0 Link OK 0x1 RX or TX Activity (Default LED1) 0x2 Reserved 0x3 Reserved 0x4 Reserved 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity LED0 Source The LED0 field selects the source that toggles the LED0 signal. Value Description 0x0 Link OK (Default LED0) 0x1 RX or TX Activity 0x2 Reserved 0x3 Reserved 0x4 Reserved 0x5 100BASE-TX mode 0x6 10BASE-T mode 0x7 Full-Duplex 0x8 Link OK & Blink=RX or TX Activity April 04, 2010 365 Texas Instruments-Production Data Ethernet Controller Register 27: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 This register enables software to control the behavior of the MDI/MDIX mux and its switching capabilities. Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24) Base 0x4004.8000 Address 0x18 Type R/W, reset 0x00C0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 7 6 PD_MODE AUTO_SW RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 5 4 MDIX MDIX_CM R/W 0 RO 0 3 2 1 0 MDIX_SD R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 PD_MODE R/W 1 Parallel Detection Mode When set, enables the Parallel Detection mode and allows auto-switching to work when auto-negotiation is not enabled. 6 AUTO_SW R/W 1 Auto-Switching Enable When set, enables Auto-Switching of the MDI/MDIX mux. 5 MDIX R/W 0 Auto-Switching Configuration When set, indicates that the MDI/MDIX mux is in the crossover (MDIX) configuration. When 0, it indicates that the mux is in the pass-through (MDI) configuration. When the AUTO_SW bit is 1, the MDIX bit is read-only. When the AUTO_SW bit is 0, the MDIX bit is read/write and can be configured manually. 4 MDIX_CM RO 0 Auto-Switching Complete When set, indicates that the auto-switching sequence has completed. If 0, it indicates that the sequence has not completed or that auto-switching is disabled. 3:0 MDIX_SD R/W 0x0 Auto-Switching Seed This field provides the initial seed for the switching algorithm. This seed directly affects the number of attempts [5,4] respectively to write bits [3:0]. A 0 sets the seed to 0x5. 366 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 14 Analog Comparators An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. Note: Not all comparators have the option to drive an output pin. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. ® The Stellaris Analog Comparators module has the following features: ■ Two independent integrated analog comparators ■ Configurable for output to drive an output pin or generate an interrupt ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of these voltages – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage 14.1 Block Diagram Figure 14-1. Analog Comparator Module Block Diagram C1- -ve input C1+ +ve input Comparator 1 output C1o +ve input (alternate) ACCTL1 ACSTAT1 interrupt reference input C0- -ve input C0+ +ve input Comparator 0 output C0o +ve input (alternate) ACCTL0 ACSTAT0 interrupt reference input Voltage Ref Interrupt Control ACRIS internal bus ACREFCTL ACMIS ACINTEN interrupt April 04, 2010 367 Texas Instruments-Production Data Analog Comparators 14.2 Functional Description Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module) for the analog input pin be disabled to prevent excessive current draw from the I/O pads. The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. VIN- < VIN+, VOUT = 1 VIN- > VIN+, VOUT = 0 As shown in Figure 14-2 on page 368, the input source for VIN- is an external input. In addition to an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference. Figure 14-2. Structure of Comparator Unit -ve input 0 output CINV 1 IntGen +ve input (alternate) reference input 2 internal bus ACCTL ACSTAT interrupt +ve input A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal reference is configured through one control register (ACREFCTL). Interrupt status and control is configured through three registers (ACMIS, ACRIS, and ACINTEN). Typically, the comparator output is used internally to generate controller interrupts. It may also be used to drive an external pin. Important: The ASRCP bits in the ACCTLn register must be set before using the analog comparators. 14.2.1 Internal Reference Programming The structure of the internal reference is shown in Figure 14-3 on page 369. This is controlled by a single configuration register (ACREFCTL). Table 14-1 on page 369 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally. 368 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 14-3. Comparator Internal Reference Structure 8R AVDD 8R R R R ••• EN 15 14 ••• 1 0 Decoder VREF internal reference RNG Table 14-1. Internal Reference Voltage and ACREFCTL Field Values ACREFCTL Register EN Bit Value Output Reference Voltage Based on VREF Field Value RNG Bit Value EN=0 RNG=X 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. EN=1 RNG=0 Total resistance in ladder is 31 R. The range of internal reference in this mode is 0.85-2.448 V. RNG=1 Total resistance in ladder is 23 R. The range of internal reference for this mode is 0-2.152 V. 14.3 Initialization and Configuration The following example shows how to configure an analog comparator to read back its output value from an internal register. 1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register in the System Control module. 2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input. 3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the value 0x0000.030C. April 04, 2010 369 Texas Instruments-Production Data Analog Comparators 4. Configure comparator 0 to use the internal voltage reference and to not invert the output by writing the ACCTL0 register with the value of 0x0000.040C. 5. Delay for some time. 6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value. Change the level of the signal input on C0- to see the OVAL value change. 14.4 Register Map Table 14-2 on page 370 lists the comparator registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Analog Comparator base address of 0x4003.C000. Table 14-2. Analog Comparators Register Map Name Type Reset 0x000 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 371 0x004 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 372 0x008 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 373 0x010 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 374 0x020 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 375 0x024 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 376 0x040 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 375 0x044 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 376 14.5 Description See page Offset Register Descriptions The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset. 370 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 This register provides a summary of the interrupt status (masked) of the comparators. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x000 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 IN1 R/W1C 0 Comparator 1 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 0 IN0 R/W1C 0 Comparator 0 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. April 04, 2010 371 Texas Instruments-Production Data Analog Comparators Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 This register provides a summary of the interrupt status (raw) of the comparators. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 IN1 RO 0 Comparator 1 Interrupt Status When set, indicates that an interrupt has been generated by comparator 1. 0 IN0 RO 0 Comparator 0 Interrupt Status When set, indicates that an interrupt has been generated by comparator 0. 372 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 This register provides the interrupt enable for the comparators. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 IN1 R/W 0 Comparator 1 Interrupt Enable When set, enables the controller interrupt from the comparator 1 output. 0 IN0 R/W 0 Comparator 0 Interrupt Enable When set, enables the controller interrupt from the comparator 0 output. April 04, 2010 373 Texas Instruments-Production Data Analog Comparators Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 9 8 EN RNG R/W 0 R/W 0 reserved RO 0 RO 0 RO 0 VREF RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:10 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 EN R/W 0 Resistor Ladder Enable The EN bit specifies whether the resistor ladder is powered on. If 0, the resistor ladder is unpowered. If 1, the resistor ladder is connected to the analog VDD. This bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 8 RNG R/W 0 Resistor Ladder Range The RNG bit specifies the range of the resistor ladder. If 0, the resistor ladder has a total resistance of 31 R. If 1, the resistor ladder has a total resistance of 23 R. 7:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 VREF R/W 0x00 Resistor Ladder Voltage Ref The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 14-1 on page 369 for some output reference voltage examples. 374 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 These registers specify the current output value of the comparator. Analog Comparator Status 0 (ACSTAT0) Base 0x4003.C000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 OVAL reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 OVAL RO 0 Comparator Output Value The OVAL bit specifies the current output value of the comparator. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 375 Texas Instruments-Production Data Analog Comparators Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 These registers configure the comparator’s input and output. Analog Comparator Control 0 (ACCTL0) Base 0x4003.C000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 CINV reserved RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset RO 0 ASRCP reserved ISLVAL R/W 0 ISEN R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:9 ASRCP R/W 0x00 Analog Source Positive The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: Value Function 0x0 Pin value 0x1 Pin value of C0+ 0x2 Internal voltage reference 0x3 Reserved 8:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 ISLVAL R/W 0 Interrupt Sense Level Value The ISLVAL bit specifies the sense value of the input that generates an interrupt if in Level Sense mode. If 0, an interrupt is generated if the comparator output is Low. Otherwise, an interrupt is generated if the comparator output is High. 376 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Bit/Field Name Type Reset 3:2 ISEN R/W 0x0 Description Interrupt Sense The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: Value Function 1 CINV R/W 0 0x0 Level sense, see ISLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge Comparator Output Invert The CINV bit conditionally inverts the output of the comparator. If 0, the output of the comparator is unchanged. If 1, the output of the comparator is inverted prior to being processed by hardware. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. April 04, 2010 377 Texas Instruments-Production Data Pin Diagram 15 Pin Diagram The LM3S6730 microcontroller pin diagrams are shown below. Figure 15-1. 100-Pin LQFP Package Pin Diagram 378 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 15-2. 108-Ball BGA Package Pin Diagram (Top View) April 04, 2010 379 Texas Instruments-Production Data Signal Tables 16 Signal Tables The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register. Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7 and PC[3:0]) which default to the JTAG functionality. Table 16-1 on page 380 shows the pin-to-signal-name mapping, including functional characteristics of the signals. Table 16-2 on page 383 lists the signals in alphabetical order by signal name. Table 16-3 on page 387 groups the signals by functionality, except for GPIOs. Table 16-4 on page 389 lists the GPIO pins and their alternate functionality. 16.1 100-Pin LQFP Package Pin Tables Table 16-1. Signals by Pin Number a Pin Number Pin Name Pin Type Buffer Type 1 PE7 I/O TTL Description GPIO port E bit 7. 2 PE6 I/O TTL GPIO port E bit 6. C1o O TTL Analog comparator 1 output. 3 VDDA - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. 4 GNDA - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. 5 PE5 I/O TTL GPIO port E bit 5. 6 PE4 I/O TTL GPIO port E bit 4. 7 LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). 8 VDD - Power Positive supply for I/O and some logic. Ground reference for logic and I/O pins. 9 GND - Power 10 PD0 I/O TTL GPIO port D bit 0. 11 PD1 I/O TTL GPIO port D bit 1. 12 PD2 I/O TTL GPIO port D bit 2. 13 PD3 I/O TTL GPIO port D bit 3. 14 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 15 GND - Power Ground reference for logic and I/O pins. 16 XTALPPHY I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. 17 XTALNPHY O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave unconnected when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. 380 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-1. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type 18 PG1 I/O TTL GPIO port G bit 1. 19 PG0 I/O TTL GPIO port G bit 0. 20 VDD - Power Positive supply for I/O and some logic. 21 GND - Power Ground reference for logic and I/O pins. 22 PC7 I/O TTL GPIO port C bit 7. 23 24 25 26 27 28 29 30 31 Description PC6 I/O TTL GPIO port C bit 6. CCP3 I/O TTL Capture/Compare/PWM 3. PC5 I/O TTL GPIO port C bit 5. C1+ I Analog PC4 I/O TTL GPIO port C bit 4. Analog comparator 1 positive input. PA0 I/O TTL GPIO port A bit 0. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. PA1 I/O TTL GPIO port A bit 1. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. PA2 I/O TTL GPIO port A bit 2. SSI0Clk I/O TTL SSI module 0 clock. PA3 I/O TTL GPIO port A bit 3. SSI0Fss I/O TTL SSI module 0 frame. PA4 I/O TTL GPIO port A bit 4. SSI0Rx I TTL SSI module 0 receive. PA5 I/O TTL GPIO port A bit 5. SSI0Tx O TTL SSI module 0 transmit. 32 VDD - Power Positive supply for I/O and some logic. 33 GND - Power Ground reference for logic and I/O pins. 34 PA6 I/O TTL GPIO port A bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. 35 PA7 I/O TTL GPIO port A bit 7. 36 VCCPHY - Power VCC of the Ethernet PHY. 37 RXIN I Analog RXIN of the Ethernet PHY. 38 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 39 GND - Power Ground reference for logic and I/O pins. 40 RXIP I Analog RXIP of the Ethernet PHY. 41 ERBIAS I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. 42 GNDPHY - Power GND of the Ethernet PHY. 43 TXOP O Analog TXOP of the Ethernet PHY. 44 VDD - Power Positive supply for I/O and some logic. 45 GND - Power Ground reference for logic and I/O pins. 46 TXON O Analog TXON of the Ethernet PHY. 47 PF0 I/O TTL GPIO port F bit 0. April 04, 2010 381 Texas Instruments-Production Data Signal Tables Table 16-1. Signals by Pin Number (continued) Pin Number Pin Name 48 49 a Pin Type Buffer Type Description OSC0 I Analog Main oscillator crystal input or an external clock reference input. OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. 50 NC - - No connect. Leave the pin electrically unconnected/isolated. 51 NC - - No connect. Leave the pin electrically unconnected/isolated. 52 NC - - No connect. Leave the pin electrically unconnected/isolated. 53 NC - - No connect. Leave the pin electrically unconnected/isolated. 54 GND - Power Ground reference for logic and I/O pins. 55 VDD - Power Positive supply for I/O and some logic. 56 VDD - Power Positive supply for I/O and some logic. Ground reference for logic and I/O pins. 57 GND - Power 58 MDIO I/O TTL MDIO of the Ethernet PHY. 59 60 PF3 I/O TTL GPIO port F bit 3. LED0 O TTL Ethernet LED 0. PF2 I/O TTL GPIO port F bit 2. LED1 O TTL Ethernet LED 1. 61 PF1 I/O TTL GPIO port F bit 1. 62 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 63 GND - Power Ground reference for logic and I/O pins. 64 RST I TTL System reset input. 65 CMOD0 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. 66 PB0 I/O TTL GPIO port B bit 0. CCP0 I/O TTL Capture/Compare/PWM 0. PB1 I/O TTL GPIO port B bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. 68 VDD - Power Positive supply for I/O and some logic. 69 GND - Power Ground reference for logic and I/O pins. 70 PB2 I/O TTL GPIO port B bit 2. 71 PB3 I/O TTL GPIO port B bit 3. 72 PE0 I/O TTL GPIO port E bit 0. 73 PE1 I/O TTL GPIO port E bit 1. 74 PE2 I/O TTL GPIO port E bit 2. 75 PE3 I/O TTL GPIO port E bit 3. 76 CMOD1 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. 77 PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. 67 78 382 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-1. Signals by Pin Number (continued) Pin Number 79 80 a Pin Name Pin Type Buffer Type Description PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I/O TTL JTAG TMS and SWDIO. PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. JTAG/SWD CLK. TCK I TTL 81 VDD - Power Positive supply for I/O and some logic. 82 GND - Power Ground reference for logic and I/O pins. 83 VCCPHY - Power VCC of the Ethernet PHY. 84 VCCPHY - Power VCC of the Ethernet PHY. 85 GNDPHY - Power GND of the Ethernet PHY. 86 GNDPHY - Power GND of the Ethernet PHY. 87 GND - Power Ground reference for logic and I/O pins. 88 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 89 PB7 I/O TTL GPIO port B bit 7. TRST I TTL JTAG TRST. PB6 I/O TTL GPIO port B bit 6. C0+ I Analog PB5 I/O TTL C1- I Analog PB4 I/O TTL C0- I Analog Analog comparator 0 negative input. 93 VDD - Power Positive supply for I/O and some logic. 94 GND - Power Ground reference for logic and I/O pins. 95 PD4 I/O TTL GPIO port D bit 4. 96 PD5 I/O TTL GPIO port D bit 5. 97 GNDA - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. 98 VDDA - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. 99 PD6 I/O TTL GPIO port D bit 6. 100 PD7 I/O TTL GPIO port D bit 7. C0o O TTL Analog comparator 0 output. 90 91 92 Analog comparator 0 positive input. GPIO port B bit 5. Analog comparator 1 negative input. GPIO port B bit 4. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-2. Signals by Signal Name a Pin Name Pin Number Pin Type Buffer Type C0+ 90 I Analog Description Analog comparator 0 positive input. April 04, 2010 383 Texas Instruments-Production Data Signal Tables Table 16-2. Signals by Signal Name (continued) Pin Name Pin Number a Pin Type Buffer Type Description C0- 92 I Analog C0o 100 O TTL Analog comparator 0 negative input. C1+ 24 I Analog Analog comparator 1 positive input. C1- 91 I Analog Analog comparator 1 negative input. C1o 2 O TTL Analog comparator 1 output. CCP0 66 I/O TTL Capture/Compare/PWM 0. CCP1 34 I/O TTL Capture/Compare/PWM 1. CCP2 67 I/O TTL Capture/Compare/PWM 2. Analog comparator 0 output. CCP3 23 I/O TTL Capture/Compare/PWM 3. CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. ERBIAS 41 I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. GND 9 15 21 33 39 45 54 57 63 69 82 87 94 - Power Ground reference for logic and I/O pins. GNDA 4 97 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDPHY 42 85 86 - Power GND of the Ethernet PHY. LDO 7 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). LED0 59 O TTL Ethernet LED 0. LED1 60 O TTL Ethernet LED 1. MDIO 58 I/O TTL MDIO of the Ethernet PHY. NC 50 51 52 53 - - OSC0 48 I Analog No connect. Leave the pin electrically unconnected/isolated. Main oscillator crystal input or an external clock reference input. 384 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description OSC1 49 O Analog PA0 26 I/O TTL GPIO port A bit 0. PA1 27 I/O TTL GPIO port A bit 1. PA2 28 I/O TTL GPIO port A bit 2. PA3 29 I/O TTL GPIO port A bit 3. PA4 30 I/O TTL GPIO port A bit 4. PA5 31 I/O TTL GPIO port A bit 5. PA6 34 I/O TTL GPIO port A bit 6. PA7 35 I/O TTL GPIO port A bit 7. PB0 66 I/O TTL GPIO port B bit 0. PB1 67 I/O TTL GPIO port B bit 1. PB2 70 I/O TTL GPIO port B bit 2. PB3 71 I/O TTL GPIO port B bit 3. PB4 92 I/O TTL GPIO port B bit 4. PB5 91 I/O TTL GPIO port B bit 5. PB6 90 I/O TTL GPIO port B bit 6. PB7 89 I/O TTL GPIO port B bit 7. PC0 80 I/O TTL GPIO port C bit 0. PC1 79 I/O TTL GPIO port C bit 1. PC2 78 I/O TTL GPIO port C bit 2. PC3 77 I/O TTL GPIO port C bit 3. PC4 25 I/O TTL GPIO port C bit 4. PC5 24 I/O TTL GPIO port C bit 5. PC6 23 I/O TTL GPIO port C bit 6. PC7 22 I/O TTL GPIO port C bit 7. PD0 10 I/O TTL GPIO port D bit 0. PD1 11 I/O TTL GPIO port D bit 1. PD2 12 I/O TTL GPIO port D bit 2. PD3 13 I/O TTL GPIO port D bit 3. PD4 95 I/O TTL GPIO port D bit 4. PD5 96 I/O TTL GPIO port D bit 5. PD6 99 I/O TTL GPIO port D bit 6. PD7 100 I/O TTL GPIO port D bit 7. PE0 72 I/O TTL GPIO port E bit 0. PE1 73 I/O TTL GPIO port E bit 1. PE2 74 I/O TTL GPIO port E bit 2. PE3 75 I/O TTL GPIO port E bit 3. PE4 6 I/O TTL GPIO port E bit 4. PE5 5 I/O TTL GPIO port E bit 5. PE6 2 I/O TTL GPIO port E bit 6. Main oscillator crystal output. Leave unconnected when using a single-ended clock source. April 04, 2010 385 Texas Instruments-Production Data Signal Tables Table 16-2. Signals by Signal Name (continued) Pin Name a Pin Number Pin Type Buffer Type Description PE7 1 I/O TTL GPIO port E bit 7. PF0 47 I/O TTL GPIO port F bit 0. PF1 61 I/O TTL GPIO port F bit 1. PF2 60 I/O TTL GPIO port F bit 2. PF3 59 I/O TTL GPIO port F bit 3. PG0 19 I/O TTL GPIO port G bit 0. PG1 18 I/O TTL GPIO port G bit 1. RST 64 I TTL System reset input. RXIN 37 I Analog RXIN of the Ethernet PHY. RXIP 40 I Analog RXIP of the Ethernet PHY. SSI0Clk 28 I/O TTL SSI module 0 clock. SSI0Fss 29 I/O TTL SSI module 0 frame. SSI0Rx 30 I TTL SSI module 0 receive. SSI0Tx 31 O TTL SSI module 0 transmit. SWCLK 80 I TTL JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I/O TTL JTAG TMS and SWDIO. TRST 89 I TTL JTAG TRST. TXON 46 O Analog TXON of the Ethernet PHY. TXOP 43 O Analog TXOP of the Ethernet PHY. U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. VCCPHY 36 83 84 - Power VCC of the Ethernet PHY. VDD 8 20 32 44 55 56 68 81 93 - Power Positive supply for I/O and some logic. VDD25 14 38 62 88 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 386 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description VDDA 3 98 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. XTALNPHY 17 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave unconnected when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY 16 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-3. Signals by Function, Except for GPIO Function Analog Comparators Ethernet General-Purpose Timers Pin Name C0+ a Pin Number Pin Type Buffer Type Description 90 I Analog Analog comparator 0 positive input. Analog comparator 0 negative input. C0- 92 I Analog C0o 100 O TTL C1+ 24 I Analog Analog comparator 1 positive input. C1- 91 I Analog Analog comparator 1 negative input. C1o 2 O TTL ERBIAS 41 I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. GNDPHY 42 85 86 - Power GND of the Ethernet PHY. LED0 59 O TTL Ethernet LED 0. LED1 60 O TTL Ethernet LED 1. MDIO 58 I/O TTL MDIO of the Ethernet PHY. RXIN 37 I Analog RXIN of the Ethernet PHY. RXIP 40 I Analog RXIP of the Ethernet PHY. TXON 46 O Analog TXON of the Ethernet PHY. TXOP 43 O Analog TXOP of the Ethernet PHY. VCCPHY 36 83 84 - Power VCC of the Ethernet PHY. XTALNPHY 17 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave unconnected when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY 16 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. CCP0 66 I/O TTL Capture/Compare/PWM 0. CCP1 34 I/O TTL Capture/Compare/PWM 1. CCP2 67 I/O TTL Capture/Compare/PWM 2. CCP3 23 I/O TTL Capture/Compare/PWM 3. Analog comparator 0 output. Analog comparator 1 output. April 04, 2010 387 Texas Instruments-Production Data Signal Tables Table 16-3. Signals by Function, Except for GPIO (continued) Function JTAG/SWD/SWO Power Pin Name Pin Number a Pin Type Buffer Type Description SWCLK 80 I TTL JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I/O TTL JTAG TMS and SWDIO. TRST 89 I TTL JTAG TRST. GND 9 15 21 33 39 45 54 57 63 69 82 87 94 - Power Ground reference for logic and I/O pins. GNDA 4 97 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO 7 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). VDD 8 20 32 44 55 56 68 81 93 - Power Positive supply for I/O and some logic. VDD25 14 38 62 88 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDDA 3 98 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. 388 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-3. Signals by Function, Except for GPIO (continued) Function SSI System Control & Clocks UART Pin Name a Pin Number Pin Type Buffer Type Description SSI0Clk 28 I/O TTL SSI module 0 clock. SSI0Fss 29 I/O TTL SSI module 0 frame. SSI0Rx 30 I TTL SSI module 0 receive. SSI0Tx 31 O TTL SSI module 0 transmit. CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. OSC0 48 I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 64 I TTL System reset input. U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-4. GPIO Pins and Alternate Functions IO Pin Number Multiplexed Function Multiplexed Function PA0 26 U0Rx PA1 27 U0Tx PA2 28 SSI0Clk PA3 29 SSI0Fss PA4 30 SSI0Rx PA5 31 SSI0Tx PA6 34 CCP1 PA7 35 PB0 66 CCP0 PB1 67 CCP2 PB2 70 PB3 71 PB4 92 C0- PB5 91 C1- PB6 90 C0+ PB7 89 TRST PC0 80 TCK SWCLK PC1 79 TMS SWDIO PC2 78 TDI PC3 77 TDO PC4 25 PC5 24 SWO C1+ April 04, 2010 389 Texas Instruments-Production Data Signal Tables Table 16-4. GPIO Pins and Alternate Functions (continued) 16.2 IO Pin Number Multiplexed Function PC6 23 CCP3 PC7 22 PD0 10 PD1 11 PD2 12 PD3 13 PD4 95 PD5 96 PD6 99 PD7 100 PE0 72 PE1 73 PE2 74 PE3 75 PE4 6 PE5 5 PE6 2 PE7 1 PF0 47 PF1 61 PF2 60 LED1 PF3 59 LED0 PG0 19 PG1 18 Multiplexed Function C0o C1o 108-Pin BGA Package Pin Tables Table 16-5. Signals by Pin Number a Pin Number Pin Name Pin Type Buffer Type A1 NC - - No connect. Leave the pin electrically unconnected/isolated. A2 NC - - No connect. Leave the pin electrically unconnected/isolated. A3 NC - - No connect. Leave the pin electrically unconnected/isolated. A4 NC - - No connect. Leave the pin electrically unconnected/isolated. A5 GNDA - Power A6 PB4 I/O TTL C0- I Analog PB6 I/O TTL C0+ I Analog PB7 I/O TTL GPIO port B bit 7. TRST I TTL JTAG TRST. A7 A8 Description The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GPIO port B bit 4. Analog comparator 0 negative input. GPIO port B bit 6. Analog comparator 0 positive input. 390 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-5. Signals by Pin Number (continued) Pin Number A9 A10 a Pin Name Pin Type Buffer Type Description PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. A11 PE0 I/O TTL GPIO port E bit 0. A12 PE3 I/O TTL GPIO port E bit 3. B1 NC - - No connect. Leave the pin electrically unconnected/isolated. B2 NC - - No connect. Leave the pin electrically unconnected/isolated. B3 NC - - No connect. Leave the pin electrically unconnected/isolated. B4 NC - - No connect. Leave the pin electrically unconnected/isolated. B5 GNDA - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. B6 GND - Power Ground reference for logic and I/O pins. B7 PB5 I/O TTL C1- I Analog PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. B8 B9 GPIO port B bit 5. Analog comparator 1 negative input. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I/O TTL JTAG TMS and SWDIO. B10 CMOD1 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. B11 PE2 I/O TTL GPIO port E bit 2. B12 PE1 I/O TTL GPIO port E bit 1. C1 PE7 I/O TTL GPIO port E bit 7. C2 PE6 I/O TTL GPIO port E bit 6. C1o O TTL Analog comparator 1 output. C3 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. C4 GND - Power Ground reference for logic and I/O pins. C5 GND - Power Ground reference for logic and I/O pins. C6 VDDA - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. C7 VDDA - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. C8 GNDPHY - Power GND of the Ethernet PHY. April 04, 2010 391 Texas Instruments-Production Data Signal Tables Table 16-5. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type Description C9 GNDPHY - Power GND of the Ethernet PHY. C10 VCCPHY - Power VCC of the Ethernet PHY. C11 PB2 I/O TTL GPIO port B bit 2. C12 PB3 I/O TTL GPIO port B bit 3. D1 PE4 I/O TTL GPIO port E bit 4. D2 PE5 I/O TTL GPIO port E bit 5. D3 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. D10 VCCPHY - Power VCC of the Ethernet PHY. D11 VCCPHY - Power VCC of the Ethernet PHY. D12 PB1 I/O TTL GPIO port B bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. E1 PD4 I/O TTL GPIO port D bit 4. E2 PD5 I/O TTL GPIO port D bit 5. E3 LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). E10 VDD33 - Power Positive supply for I/O and some logic. E11 CMOD0 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. E12 PB0 I/O TTL GPIO port B bit 0. CCP0 I/O TTL Capture/Compare/PWM 0. PD7 I/O TTL GPIO port D bit 7. C0o O TTL Analog comparator 0 output. F2 PD6 I/O TTL GPIO port D bit 6. F3 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. F10 GND - Power Ground reference for logic and I/O pins. F11 GND - Power Ground reference for logic and I/O pins. F12 GND - Power Ground reference for logic and I/O pins. G1 PD0 I/O TTL GPIO port D bit 0. G2 PD1 I/O TTL GPIO port D bit 1. G3 VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. G10 VDD33 - Power Positive supply for I/O and some logic. G11 VDD33 - Power Positive supply for I/O and some logic. G12 VDD33 - Power Positive supply for I/O and some logic. H1 PD3 I/O TTL GPIO port D bit 3. H2 PD2 I/O TTL GPIO port D bit 2. F1 H3 GND - Power Ground reference for logic and I/O pins. H10 VDD33 - Power Positive supply for I/O and some logic. H11 RST I TTL System reset input. 392 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-5. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type H12 PF1 I/O TTL GPIO port F bit 1. J1 XTALNPHY O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave unconnected when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. J2 XTALPPHY I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. J3 GND - Power Ground reference for logic and I/O pins. J10 GND - Power Ground reference for logic and I/O pins. J11 PF2 I/O TTL GPIO port F bit 2. LED1 O TTL Ethernet LED 1. PF3 I/O TTL GPIO port F bit 3. LED0 O TTL Ethernet LED 0. K1 PG0 I/O TTL GPIO port G bit 0. K2 PG1 I/O TTL GPIO port G bit 1. K3 ERBIAS I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. K4 GNDPHY - Power GND of the Ethernet PHY. K5 GND - Power Ground reference for logic and I/O pins. K6 GND - Power Ground reference for logic and I/O pins. K7 VDD33 - Power Positive supply for I/O and some logic. K8 VDD33 - Power Positive supply for I/O and some logic. J12 Description K9 VDD33 - Power Positive supply for I/O and some logic. K10 GND - Power Ground reference for logic and I/O pins. K11 NC - - No connect. Leave the pin electrically unconnected/isolated. K12 NC - - No connect. Leave the pin electrically unconnected/isolated. L1 PC4 I/O TTL GPIO port C bit 4. L2 PC7 I/O TTL GPIO port C bit 7. L3 PA0 I/O TTL GPIO port A bit 0. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. L4 L5 L6 PA3 I/O TTL GPIO port A bit 3. SSI0Fss I/O TTL SSI module 0 frame. PA4 I/O TTL GPIO port A bit 4. SSI0Rx I TTL SSI module 0 receive. PA6 I/O TTL GPIO port A bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. L7 RXIN I Analog RXIN of the Ethernet PHY. L8 TXON O Analog TXON of the Ethernet PHY. MDIO of the Ethernet PHY. L9 MDIO I/O TTL L10 GND - Power Ground reference for logic and I/O pins. L11 OSC0 I Analog Main oscillator crystal input or an external clock reference input. L12 VDD - Power Positive supply for I/O and some logic. April 04, 2010 393 Texas Instruments-Production Data Signal Tables Table 16-5. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type M1 PC5 I/O TTL C1+ I Analog PC6 I/O TTL GPIO port C bit 6. CCP3 I/O TTL Capture/Compare/PWM 3. PA1 I/O TTL GPIO port A bit 1. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. M2 M3 M4 M5 Buffer Type Description GPIO port C bit 5. Analog comparator 1 positive input. PA2 I/O TTL GPIO port A bit 2. SSI0Clk I/O TTL SSI module 0 clock. PA5 I/O TTL GPIO port A bit 5. SSI0Tx O TTL SSI module 0 transmit. M6 PA7 I/O TTL GPIO port A bit 7. M7 RXIP I Analog RXIP of the Ethernet PHY. M8 TXOP O Analog TXOP of the Ethernet PHY. M9 PF0 I/O TTL GPIO port F bit 0. M10 NC - - M11 OSC1 O Analog No connect. Leave the pin electrically unconnected/isolated. M12 NC - - Main oscillator crystal output. Leave unconnected when using a single-ended clock source. No connect. Leave the pin electrically unconnected/isolated. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-6. Signals by Signal Name a Pin Name Pin Number Pin Type Buffer Type Description C0+ A7 I Analog Analog comparator 0 positive input. C0- A6 I Analog Analog comparator 0 negative input. C0o F1 O TTL C1+ M1 I Analog Analog comparator 1 positive input. C1- B7 I Analog Analog comparator 1 negative input. C1o C2 O TTL Analog comparator 1 output. CCP0 E12 I/O TTL Capture/Compare/PWM 0. CCP1 L6 I/O TTL Capture/Compare/PWM 1. CCP2 D12 I/O TTL Capture/Compare/PWM 2. CCP3 M2 I/O TTL Capture/Compare/PWM 3. CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. ERBIAS K3 I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. Analog comparator 0 output. 394 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-6. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description GND B6 C4 C5 F10 F11 F12 H3 J3 J10 K5 K6 K10 L10 - Power Ground reference for logic and I/O pins. GNDA A5 B5 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GNDPHY C8 C9 K4 - Power GND of the Ethernet PHY. LDO E3 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). LED0 J12 O TTL Ethernet LED 0. LED1 J11 O TTL Ethernet LED 1. MDIO L9 I/O TTL MDIO of the Ethernet PHY. NC A1 A2 A3 A4 B1 B2 B3 B4 K11 K12 M10 M12 - - OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. PA0 L3 I/O TTL GPIO port A bit 0. PA1 M3 I/O TTL GPIO port A bit 1. PA2 M4 I/O TTL GPIO port A bit 2. PA3 L4 I/O TTL GPIO port A bit 3. PA4 L5 I/O TTL GPIO port A bit 4. PA5 M5 I/O TTL GPIO port A bit 5. PA6 L6 I/O TTL GPIO port A bit 6. No connect. Leave the pin electrically unconnected/isolated. April 04, 2010 395 Texas Instruments-Production Data Signal Tables Table 16-6. Signals by Signal Name (continued) Pin Name a Pin Number Pin Type Buffer Type Description PA7 M6 I/O TTL GPIO port A bit 7. PB0 E12 I/O TTL GPIO port B bit 0. PB1 D12 I/O TTL GPIO port B bit 1. PB2 C11 I/O TTL GPIO port B bit 2. PB3 C12 I/O TTL GPIO port B bit 3. PB4 A6 I/O TTL GPIO port B bit 4. PB5 B7 I/O TTL GPIO port B bit 5. PB6 A7 I/O TTL GPIO port B bit 6. PB7 A8 I/O TTL GPIO port B bit 7. PC0 A9 I/O TTL GPIO port C bit 0. PC1 B9 I/O TTL GPIO port C bit 1. PC2 B8 I/O TTL GPIO port C bit 2. PC3 A10 I/O TTL GPIO port C bit 3. PC4 L1 I/O TTL GPIO port C bit 4. PC5 M1 I/O TTL GPIO port C bit 5. PC6 M2 I/O TTL GPIO port C bit 6. PC7 L2 I/O TTL GPIO port C bit 7. PD0 G1 I/O TTL GPIO port D bit 0. PD1 G2 I/O TTL GPIO port D bit 1. PD2 H2 I/O TTL GPIO port D bit 2. PD3 H1 I/O TTL GPIO port D bit 3. PD4 E1 I/O TTL GPIO port D bit 4. PD5 E2 I/O TTL GPIO port D bit 5. PD6 F2 I/O TTL GPIO port D bit 6. PD7 F1 I/O TTL GPIO port D bit 7. PE0 A11 I/O TTL GPIO port E bit 0. PE1 B12 I/O TTL GPIO port E bit 1. PE2 B11 I/O TTL GPIO port E bit 2. PE3 A12 I/O TTL GPIO port E bit 3. PE4 D1 I/O TTL GPIO port E bit 4. PE5 D2 I/O TTL GPIO port E bit 5. PE6 C2 I/O TTL GPIO port E bit 6. PE7 C1 I/O TTL GPIO port E bit 7. PF0 M9 I/O TTL GPIO port F bit 0. PF1 H12 I/O TTL GPIO port F bit 1. PF2 J11 I/O TTL GPIO port F bit 2. PF3 J12 I/O TTL GPIO port F bit 3. PG0 K1 I/O TTL GPIO port G bit 0. PG1 K2 I/O TTL GPIO port G bit 1. RST H11 I TTL System reset input. RXIN L7 I Analog RXIN of the Ethernet PHY. 396 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-6. Signals by Signal Name (continued) Pin Name Pin Number a Pin Type Buffer Type Description RXIP M7 I Analog SSI0Clk M4 I/O TTL RXIP of the Ethernet PHY. SSI module 0 clock. SSI0Fss L4 I/O TTL SSI module 0 frame. SSI0Rx L5 I TTL SSI module 0 receive. SSI0Tx M5 O TTL SSI module 0 transmit. SWCLK A9 I TTL JTAG/SWD CLK. SWDIO B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I/O TTL JTAG TMS and SWDIO. TRST A8 I TTL JTAG TRST. TXON L8 O Analog TXON of the Ethernet PHY. TXOP M8 O Analog TXOP of the Ethernet PHY. U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. VCCPHY C10 D10 D11 - Power VCC of the Ethernet PHY. VDD L12 - Power Positive supply for I/O and some logic. VDD25 C3 D3 F3 G3 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD33 E10 G10 G11 G12 H10 K7 K8 K9 - Power Positive supply for I/O and some logic. VDDA C6 C7 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. XTALNPHY J1 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave unconnected when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY J2 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. April 04, 2010 397 Texas Instruments-Production Data Signal Tables Table 16-7. Signals by Function, Except for GPIO Function Analog Comparators Ethernet General-Purpose Timers JTAG/SWD/SWO Pin Name a Pin Number Pin Type Buffer Type C0+ A7 I Analog Analog comparator 0 positive input. C0- A6 I Analog Analog comparator 0 negative input. C0o F1 O TTL C1+ M1 I Analog Analog comparator 1 positive input. C1- B7 I Analog Analog comparator 1 negative input. C1o C2 O TTL ERBIAS K3 I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. GNDPHY C8 C9 K4 - Power GND of the Ethernet PHY. LED0 J12 O TTL Ethernet LED 0. LED1 J11 O TTL Ethernet LED 1. MDIO L9 I/O TTL MDIO of the Ethernet PHY. RXIN L7 I Analog RXIN of the Ethernet PHY. RXIP M7 I Analog RXIP of the Ethernet PHY. TXON L8 O Analog TXON of the Ethernet PHY. TXOP M8 O Analog TXOP of the Ethernet PHY. VCCPHY C10 D10 D11 - Power VCC of the Ethernet PHY. XTALNPHY J1 O TTL Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave unconnected when using a single-ended 25-MHz clock input connected to the XTALPPHY pin. XTALPPHY J2 I TTL Ethernet PHY XTALP 25-MHz oscillator crystal input or external clock reference input. E12 I/O TTL Capture/Compare/PWM 0. CCP1 L6 I/O TTL Capture/Compare/PWM 1. CCP2 D12 I/O TTL Capture/Compare/PWM 2. CCP3 M2 I/O TTL Capture/Compare/PWM 3. SWCLK A9 I TTL JTAG/SWD CLK. SWDIO B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I/O TTL JTAG TMS and SWDIO. TRST A8 I TTL JTAG TRST. CCP0 Description Analog comparator 0 output. Analog comparator 1 output. 398 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-7. Signals by Function, Except for GPIO (continued) Function Power SSI Pin Name a Pin Number Pin Type Buffer Type Description GND B6 C4 C5 F10 F11 F12 H3 J3 J10 K5 K6 K10 L10 - Power Ground reference for logic and I/O pins. GNDA A5 B5 - Power The ground reference for the analog circuits ( Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO E3 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). VDD L12 - Power Positive supply for I/O and some logic. VDD25 C3 D3 F3 G3 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDD33 E10 G10 G11 G12 H10 K7 K8 K9 - Power Positive supply for I/O and some logic. VDDA C6 C7 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. SSI0Clk M4 I/O TTL SSI module 0 clock. SSI0Fss L4 I/O TTL SSI module 0 frame. SSI0Rx L5 I TTL SSI module 0 receive. SSI0Tx M5 O TTL SSI module 0 transmit. April 04, 2010 399 Texas Instruments-Production Data Signal Tables Table 16-7. Signals by Function, Except for GPIO (continued) Function System Control & Clocks UART Pin Name a Pin Number Pin Type Buffer Type Description CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST H11 I TTL System reset input. U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-8. GPIO Pins and Alternate Functions IO Pin Number Multiplexed Function PA0 L3 U0Rx PA1 M3 U0Tx PA2 M4 SSI0Clk PA3 L4 SSI0Fss PA4 L5 SSI0Rx PA5 M5 SSI0Tx PA6 L6 CCP1 PA7 M6 PB0 E12 CCP0 PB1 D12 CCP2 Multiplexed Function PB2 C11 PB3 C12 PB4 A6 C0- PB5 B7 C1- PB6 A7 C0+ PB7 A8 TRST PC0 A9 TCK SWCLK PC1 B9 TMS SWDIO PC2 B8 TDI PC3 A10 TDO PC4 L1 PC5 M1 C1+ PC6 M2 CCP3 PC7 L2 PD0 G1 PD1 G2 400 SWO April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 16-8. GPIO Pins and Alternate Functions (continued) IO Pin Number PD2 H2 PD3 H1 PD4 E1 PD5 E2 PD6 F2 PD7 F1 PE0 A11 PE1 B12 PE2 B11 PE3 A12 PE4 D1 PE5 D2 PE6 C2 Multiplexed Function Multiplexed Function C0o C1o PE7 C1 PF0 M9 PF1 H12 PF2 J11 LED1 PF3 J12 LED0 PG0 K1 PG1 K2 April 04, 2010 401 Texas Instruments-Production Data Operating Characteristics 17 Operating Characteristics Table 17-1. Temperature Characteristics Characteristic Symbol Value Industrial operating temperature range TA -40 to +85 Unit °C Extended operating temperature range TA -40 to +105 °C Unpowered storage temperature range TS -65 to +150 °C Table 17-2. Thermal Characteristics Characteristic a Thermal resistance (junction to ambient) b Average junction temperature Symbol Value ΘJA 34 Unit TJ TA + (PAVG • ΘJA) °C/W °C a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. a Table 17-3. ESD Absolute Maximum Ratings Parameter Name Min Nom Max Unit VESDHBM - - 2.0 kV VESDCDM - - 1.0 kV VESDMM - - 100 V a. All Stellaris parts are ESD tested following the JEDEC standard. 402 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 18 Electrical Characteristics 18.1 DC Characteristics 18.1.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 18-1. Maximum Ratings Characteristic Symbol a Value Unit Min Max VDD 0 4 V Core supply voltage (VDD25) VDD25 0 3 V Analog supply voltage (VDDA) VDDA 0 4 V VCCPHY 0 4 V VIN -0.3 5.5 V I - 25 mA I/O supply voltage (VDD) Ethernet PHY supply voltage (VCCPHY) Input voltage Maximum current per output pins a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either GND or VDD). 18.1.2 Recommended DC Operating Conditions For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. Table 18-2. Recommended DC Operating Conditions Parameter Parameter Name Min Nom Max Unit VDD I/O supply voltage 3.0 3.3 3.6 V VDD25 Core supply voltage 2.25 2.5 2.75 V VDDA Analog supply voltage 3.0 3.3 3.6 V Ethernet PHY supply voltage 3.0 3.3 3.6 V VCCPHY VIH High-level input voltage 2.0 - 5.0 V VIL Low-level input voltage -0.3 - 1.3 V a VOH High-level output voltage 2.4 - - V VOLa Low-level output voltage - - 0.4 V April 04, 2010 403 Texas Instruments-Production Data Electrical Characteristics Table 18-2. Recommended DC Operating Conditions (continued) Parameter IOH IOL Parameter Name Min Nom Max Unit 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA High-level source current, VOH=2.4 V Low-level sink current, VOL=0.4 V a. VOL and VOH shift to 1.2 V when using high-current GPIOs. 18.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics Table 18-3. LDO Regulator Characteristics Parameter Parameter Name Min Nom Max Unit Programmable internal (logic) power supply output value 2.25 2.5 2.75 V Output voltage accuracy - 2% - % tPON Power-on time - - 100 µs tON Time on - - 200 µs tOFF Time off - - 100 µs VSTEP Step programming incremental voltage - 50 - mV CLDO External filter capacitor size for internal power supply 1.0 - 3.0 µF Min Nom Max Unit VLDOOUT 18.1.4 GPIO Module Characteristics Table 18-4. GPIO Module DC Characteristics Parameter 18.1.5 Parameter Name RGPIOPU GPIO internal pull-up resistor 50 - 110 kΩ RGPIOPD GPIO internal pull-down resistor 55 - 180 kΩ Power Specifications The power measurements specified in the tables that follow are run on the core processor using SRAM with the following specifications (except as noted): ■ VDD = 3.3 V ■ VDD25 = 2.50 V ■ VDDA = 3.3 V ■ VDDPHY = 3.3 V ■ Temperature = 25°C 404 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller ■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator ■ Main oscillator (MOSC) = enabled ■ Internal oscillator (IOSC) = disabled Table 18-5. Detailed Power Specifications Parameter Parameter Name Conditions 3.3 V VDD, VDDA, VDDPHY Nom IDD_RUN Run mode 1 (Flash loop) VDD25 = 2.50 V Max a 2.5 V VDD25 Nom Max Unit 48 pending 108 pendinga mA 5 pendinga 52 pendinga mA 48 pendinga 100 pendinga mA 5 pendinga 45 pendinga mA 5 pendinga 16 pendinga mA 4.6 pendinga 0.21 pendinga mA Code= while(1){} executed in Flash Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (Flash loop) VDD25 = 2.50 V Code= while(1){} executed in Flash Peripherals = All OFF System Clock = 50 MHz (with PLL) Run mode 1 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_SLEEP Sleep mode VDD25 = 2.50 V Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_DEEPSLEEP Deep-Sleep mode LDO = 2.25 V Peripherals = All OFF System Clock = IOSC30KHZ/64 a. Pending characterization completion. 18.1.6 Flash Memory Characteristics Table 18-6. Flash Memory Characteristics Parameter Min Nom Max Unit 10,000 100,000 - cycles Data retention at average operating temperature of 85˚C (industrial) or 105˚C (extended) 10 - - years TPROG Word program time 20 - - µs TERASE Page erase time 20 - - ms PECYC TRET Parameter Name Number of guaranteed program/erase cycles a before failure April 04, 2010 405 Texas Instruments-Production Data Electrical Characteristics Table 18-6. Flash Memory Characteristics (continued) Parameter Parameter Name Min Nom Max Unit TME Mass erase time - - 250 ms a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 18.2 AC Characteristics 18.2.1 Load Conditions Unless otherwise specified, the following conditions are true for all timing measurements. Timing measurements are for 4-mA drive strength. Figure 18-1. Load Conditions CL = 50 pF pin GND 18.2.2 Clocks Table 18-7. Phase Locked Loop (PLL) Characteristics Parameter Parameter Name a fref_crystal Crystal reference referencea Min Nom Max Unit 3.579545 - 8.192 MHz fref_ext External clock 3.579545 - 8.192 MHz fpll PLL frequency - 400 - MHz TREADY PLL lock time - - 0.5 ms b a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register. b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. Table 18-8 on page 406 shows the actual frequency of the PLL based on the crystal frequency used (defined by the XTAL field in the RCC register). Table 18-8. Actual PLL Frequency XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error 0x4 0x5 3.5795 400.904 0.0023% 3.6864 398.1312 0.0047% 0x6 4.0 400 - 0x7 4.096 401.408 0.0035% 0x8 4.9152 398.1312 0.0047% 0x9 5.0 400 - 0xA 5.12 399.36 0.0016% 0xB 6.0 400 - 0xC 6.144 399.36 0.0016% 406 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 18-8. Actual PLL Frequency (continued) XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error 0xD 7.3728 398.1312 0.0047% 0xE 8.0 400 0.0047% 0xF 8.192 398.6773333 0.0033% Table 18-9. Clock Characteristics Parameter Name Min Nom Max Unit fIOSC Parameter Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz fIOSC30KHZ Internal 30 KHz oscillator frequency 15 30 45 KHz fMOSC Main oscillator frequency tMOSC_per Main oscillator period fref_crystal_bypass 1 - 8.192 MHz 125 - 1000 ns Crystal reference using the main oscillator (PLL in BYPASS mode) 1 - 8.192 MHz fref_ext_bypass External clock reference (PLL in BYPASS mode) 0 - 50 MHz fsystem_clock System clock 0 - 50 MHz Table 18-10. Crystal Characteristics Parameter Name Value Frequency Frequency tolerance Aging Oscillation mode 8 6 4 3.5 MHz ±50 ±50 ±50 ±50 ppm ±5 ±5 ±5 ±5 ppm/yr Parallel Parallel Parallel Parallel - ±25 ±25 ±25 ±25 ppm Temperature stability (-40°C to 85°C) 18.2.3 Units Temperature stability (-40°C to 105°C) ±25 ±25 ±25 ±25 ppm Motional capacitance (typ) 27.8 37.0 55.6 63.5 pF Motional inductance (typ) 14.3 19.1 28.6 32.7 mH Equivalent series resistance (max) 120 160 200 220 Ω Shunt capacitance (max) 10 10 10 10 pF Load capacitance (typ) 16 16 16 16 pF Drive level (typ) 100 100 100 100 µW JTAG and Boundary Scan Table 18-11. JTAG Characteristics Parameter No. J1 Parameter Parameter Name Min Nom Max Unit 0 - 10 MHz fTCK TCK operational clock frequency J2 tTCK TCK operational clock period 100 - - ns J3 tTCK_LOW TCK clock Low time - tTCK - ns J4 tTCK_HIGH TCK clock High time - tTCK - ns J5 tTCK_R TCK rise time 0 - 10 ns J6 tTCK_F TCK fall time 0 - 10 ns April 04, 2010 407 Texas Instruments-Production Data Electrical Characteristics Table 18-11. JTAG Characteristics (continued) Parameter No. Parameter Parameter Name Min Nom Max Unit J7 tTMS_SU TMS setup time to TCK rise 20 - - ns J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns J9 tTDI_SU TDI setup time to TCK rise 25 - - ns J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns J11 TCK fall to Data Valid from High-Z - t TDO_ZDV 2-mA drive 23 35 ns 4-mA drive 15 26 ns 8-mA drive 14 25 ns 18 29 ns 21 35 ns 4-mA drive 14 25 ns 8-mA drive 13 24 ns 18 28 ns 9 11 ns 4-mA drive 7 9 ns 8-mA drive 6 8 ns 8-mA drive with slew rate control 7 9 ns 8-mA drive with slew rate control J12 t TDO_DV TCK fall to Data Valid from Data Valid 2-mA drive - 8-mA drive with slew rate control J13 t TDO_DVZ TCK fall to High-Z from Data Valid J14 tTRST J15 tTRST_SU 2-mA drive - TRST assertion time 100 - - ns TRST setup time to TCK rise 10 - - ns Figure 18-2. JTAG Test Clock Input Timing J2 J3 J4 TCK J6 J5 408 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 18-3. JTAG Test Access Port (TAP) Timing TCK J7 TMS TDI J8 J7 TMS Input Valid TMS Input Valid J9 J9 J10 TDI Input Valid J11 TDO J8 J10 TDI Input Valid J12 J13 TDO Output Valid TDO Output Valid Figure 18-4. JTAG TRST Timing TCK J14 J15 TRST 18.2.4 Reset Table 18-12. Reset Characteristics Parameter No. Parameter Parameter Name R1 VTH Reset threshold R2 VBTH Brown-Out threshold R3 TPOR R4 TBOR R5 TIRPOR Internal reset timeout after POR R6 TIRBOR Internal reset timeout after BOR R7 TIRHWR R8 Min Nom Max Unit - 2.0 - V 2.85 2.9 2.95 V Power-On Reset timeout - 10 - ms Brown-Out timeout - 500 - µs 6 - 11 ms 0 - 1 µs Internal reset timeout after hardware reset (RST pin) 0 - 1 ms TIRSWR Internal reset timeout after software-initiated system reset a 2.5 - 20 µs R9 TIRWDR Internal reset timeout after watchdog reseta 2.5 - 20 µs R10 TVDDRISE Supply voltage (VDD) rise time (0V-3.3V) - - 250 µs R11 TMIN Minimum RST pulse width 2 - - µs a a. 20 * t MOSC_per April 04, 2010 409 Texas Instruments-Production Data Electrical Characteristics Figure 18-5. External Reset Timing (RST) RST R7 R11 /Reset (Internal) Figure 18-6. Power-On Reset Timing R1 VDD R3 /POR (Internal) R5 /Reset (Internal) Figure 18-7. Brown-Out Reset Timing R2 VDD R4 /BOR (Internal) R6 /Reset (Internal) Figure 18-8. Software Reset Timing SW Reset R8 /Reset (Internal) 410 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 18-9. Watchdog Reset Timing WDOG Reset (Internal) R9 /Reset (Internal) 18.2.5 Sleep Modes a Table 18-13. Sleep Modes AC Characteristics Parameter No Parameter D1 tWAKE_S D2 tWAKE_PLL_S Parameter Name Min Nom Max Unit Time to wake from interrupt in sleep or deep-sleep mode, not using the PLL - - 7 system clocks Time to wake from interrupt in sleep or deep-sleep mode when using the PLL - - TREADY ms a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode. 18.2.6 General-Purpose I/O (GPIO) Note: All GPIOs are 5 V-tolerant. Table 18-14. GPIO Characteristics Parameter Parameter Name Condition tGPIOR tGPIOF 18.2.7 GPIO Rise Time (from 20% to 80% of VDD) Min Nom Max Unit - 17 26 ns 9 13 ns 2-mA drive 4-mA drive 8-mA drive 6 9 ns 8-mA drive with slew rate control 10 12 ns 17 25 ns 8 12 ns 8-mA drive 6 10 ns 8-mA drive with slew rate control 11 13 ns GPIO Fall Time (from 80% to 20% of VDD) 2-mA drive - 4-mA drive Synchronous Serial Interface (SSI) Table 18-15. SSI Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit S1 tclk_per SSIClk cycle time 2 - 65024 system clocks S2 tclk_high SSIClk high time - 0.5 - t clk_per S3 tclk_low SSIClk low time - 0.5 - t clk_per S4 tclkrf SSIClk rise/fall time - 7.4 26 ns S5 tDMd Data from master valid delay time 0 - 1 system clocks S6 tDMs Data from master setup time 1 - - system clocks S7 tDMh Data from master hold time 2 - - system clocks S8 tDSs Data from slave setup time 1 - - system clocks April 04, 2010 411 Texas Instruments-Production Data Electrical Characteristics Table 18-15. SSI Characteristics (continued) Parameter No. Parameter S9 Parameter Name tDSh Min Nom Max Unit 2 - - system clocks Data from slave hold time Figure 18-10. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S4 S2 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits Figure 18-11. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer S2 S1 SSIClk S3 SSIFss SSITx MSB LSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data 412 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure 18-12. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S4 S2 SSIClk (SPO=0) S3 SSIClk (SPO=1) S6 SSITx (master) S7 MSB S5 SSIRx (slave) S8 LSB S9 MSB LSB SSIFss 18.2.8 Ethernet Controller a Table 18-16. 100BASE-TX Transmitter Characteristics Parameter Name Min Nom Max Unit Peak output amplitude 950 - 1050 mVpk Output amplitude symmetry 98 - 102 % Output overshoot - - 5 % Rise/Fall time 3 - 5 ns Rise/Fall time imbalance - - 500 ps Duty cycle distortion - - - ps Jitter - - 1.4 ns a. Measured at the line side of the transformer. a Table 18-17. 100BASE-TX Transmitter Characteristics (informative) Parameter Name Min Nom Max Unit Return loss 16 - - dB Open-circuit inductance 350 - - µH a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 18-18. 100BASE-TX Receiver Characteristics Parameter Name Min Nom Max Unit Signal detect assertion threshold 600 700 - mVppd Signal detect de-assertion threshold 350 425 - mVppd - 20 - kΩ Differential input resistance April 04, 2010 413 Texas Instruments-Production Data Electrical Characteristics Table 18-18. 100BASE-TX Receiver Characteristics (continued) Parameter Name Min Nom Jitter tolerance (pk-pk) Max Unit 4 - - ns -75 - +75 % Signal detect assertion time - - 1000 µs Signal detect de-assertion time - - 4 µs Unit Baseline wander tracking a Table 18-19. 10BASE-T Transmitter Characteristics Parameter Name Min Nom Max Peak differential output signal 2.2 - 2.8 V Harmonic content 27 - - dB Link pulse width - 100 - ns Start-of-idle pulse width - 300 - ns 350 a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. a Table 18-20. 10BASE-T Transmitter Characteristics (informative) Parameter Name Output return loss Min Nom Max Unit 15 - - dB 29-17log(f/10) - - dB Peak common-mode output voltage - - 50 mV Common-mode rejection - - 100 mV Common-mode rejection jitter - - 1 ns Output impedance balance a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 18-21. 10BASE-T Receiver Characteristics Parameter Name DLL phase acquisition time Min Nom Max Unit - 10 - BT Jitter tolerance (pk-pk) 30 - - ns Input squelched threshold 500 600 700 mVppd Input unsquelched threshold 275 350 425 mVppd Differential input resistance - 20 - kΩ - 10-10 - - 25 - - V Bit error ratio Common-mode rejection a Table 18-22. Isolation Transformers Name Value Condition 1 CT : 1 CT +/- 5% Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz Leakage inductance 0.40 uH (max) @ 1 MHz (min) Turns ratio Inter-winding capacitance DC resistance 25 pF (max) 0.9 Ohm (max) 414 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Table 18-22. Isolation Transformers (continued) Name Insertion loss HIPOT Value Condition 0.4 dB (typ) 0-65 MHz 1500 Vrms a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO) bits in the MR19 register. a Table 18-23. Ethernet Reference Crystal Name Frequency Value Condition 25.00000 MHz Frequency tolerance ±50 PPM Aging ±2 PPM/yr Temperature stability (-40° to 85°) ±5 PPM ±5 PPM Temperature stability (-40° to 105°) Oscillation mode Parallel resonance, fundamental mode Parameters at 25° C ±2° C; Drive level = 0.5 mW Drive level (typ) 50-100 µW Shunt capacitance (max) 10 pF Motional capacitance (min) 10 fF Series resistance (max) 60 Ω Spurious response (max) > 5 dB below main within 500 kHz a. If the internal crystal oscillator is used, select a crystal that meets these specifications. Figure 18-13. External XTLP Oscillator Characteristics Tr Tf Tclkhi Tclklo Tclkper April 04, 2010 415 Texas Instruments-Production Data Electrical Characteristics Table 18-24. External XTLP Oscillator Characteristics Parameter Name Symbol Min Nom Max Unit XTLN Input Low Voltage XTLNILV XTLPf - - 0.8 - - 25.0 - - XTLP Period Tclkper - 40 - - XTLP Duty Cycle XTLPDC 40 - 60 % Rise/Fall Time Tr , Tf - - 4.0 ns Absolute Jitter TJITTER - - 0.1 ns a XTLP Frequency b 40 60 a. IEEE 802.3 frequency tolerance ±50 ppm. b. IEEE 802.3 frequency tolerance ±50 ppm. 18.2.9 Analog Comparator Table 18-25. Analog Comparator Characteristics Parameter Parameter Name Min Nom Max Unit VOS Input offset voltage - ±10 ±25 mV VCM Input common mode voltage range 0 - VDD-1.5 V CMRR Common mode rejection ratio 50 - - dB TRT Response time - - 1 µs TMC Comparator mode change to Output Valid - - 10 µs Table 18-26. Analog Comparator Voltage Reference Characteristics Parameter Parameter Name Min Nom Max Unit - LSB RHR Resolution high range - VDD/31 RLR Resolution low range - VDD/23 - LSB AHR Absolute accuracy high range - - ±1/2 LSB ALR Absolute accuracy low range - - ±1/4 LSB 416 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller A Serial Flash Loader A.1 Serial Flash Loader ® The Stellaris serial flash loader is a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. The serial flash loader uses a simple packet interface to provide synchronous communication with the device. The flash loader runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used. The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both the data format and communication protocol are identical for both serial interfaces. A.2 Interfaces Once communication with the flash loader is established via one of the serial interfaces, that interface is used until the flash loader is reset or new code takes over. For example, once you start communicating using the SSI port, communications with the flash loader via the UART are disabled until the device is reset. A.2.1 UART The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is automatically detected by the flash loader and can be any valid baud rate supported by the host and the device. The auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the ® same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device which is calculated as follows: Max Baud Rate = System Clock Frequency / 16 In order to determine the baud rate, the serial flash loader needs to determine the relationship between its own crystal frequency and the baud rate. This is enough information for the flash loader to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows the host to use any valid baud rate that it wants to communicate with the device. The method used to perform this automatic synchronization relies on the host sending the flash loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the UART to match the host’s baud rate. After the host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has received a synchronization pattern correctly. For example, the time to wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate of 115200, this time is 2*(20/115200) or 0.35 ms. A.2.2 SSI The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications, with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame Formats” on page 285 in the SSI chapter for more information on formats for this transfer protocol. Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running April 04, 2010 417 Texas Instruments-Production Data Serial Flash Loader the flash loader. Since the host device is the master, the SSI on the flash loader device does not need to determine the clock as it is provided directly by the host. A.3 Packet Handling All communications, with the exception of the UART auto-baud, are done via defined packets that are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. A.3.1 Packet Format All packets sent and received from the device use the following byte-packed format. struct { unsigned char ucSize; unsigned char ucCheckSum; unsigned char Data[]; }; A.3.2 ucSize The first byte received holds the total size of the transfer including the size and checksum bytes. ucChecksum This holds a simple checksum of the bytes in the data buffer only. The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3]. Data This is the raw data intended for the device, which is formatted in some form of command interface. There should be ucSize–2 bytes of data provided in this buffer to or from the device. Sending Packets The actual bytes of the packet can be sent individually or all at once; the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. This limitation is discussed further in the section that describes the serial flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA (0x24)” on page 420). Once the packet has been formatted correctly by the host, it should be sent out over the UART or SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly. A.3.3 Receiving Packets The flash loader sends a packet of data in the same format that it receives a packet. The flash loader may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. There is no break in the data after the first non-zero byte is sent from the flash loader. Once the device communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to indicate that the transmission was successful. The appropriate response after sending a NAK to the flash loader is to resend the command that failed and request the data again. If needed, the host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the 418 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller flash loader only accepts the first non-zero data as a valid response. This zero padding is needed by the SSI interface in order to receive data to or from the flash loader. A.4 Commands The next section defines the list of commands that can be sent to the flash loader. The first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. A.4.1 COMMAND_PING (0X20) This command simply accepts the command and sets the global status to success. The format of the packet is as follows: Byte[0] = 0x03; Byte[1] = checksum(Byte[2]); Byte[2] = COMMAND_PING; The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status, the receipt of an ACK can be interpreted as a successful ping to the flash loader. A.4.2 COMMAND_GET_STATUS (0x23) This command returns the status of the last command that was issued. Typically, this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. The command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. The last step is to ACK or NAK the received data so the flash loader knows that the data has been read. Byte[0] = 0x03 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_GET_STATUS A.4.3 COMMAND_DOWNLOAD (0x21) This command is sent to the flash loader to indicate where to store data and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. This command also triggers an erase of the full area to be programmed so this command takes longer than other commands. This results in a longer time to receive the ACK/NAK back from the board. This command should be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size are valid for the device running the flash loader. The format of the packet to send this command is a follows: Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] Byte[7] = = = = = = = = 11 checksum(Bytes[2:10]) COMMAND_DOWNLOAD Program Address [31:24] Program Address [23:16] Program Address [15:8] Program Address [7:0] Program Size [31:24] April 04, 2010 419 Texas Instruments-Production Data Serial Flash Loader Byte[8] = Program Size [23:16] Byte[9] = Program Size [15:8] Byte[10] = Program Size [7:0] A.4.4 COMMAND_SEND_DATA (0x24) This command should only follow a COMMAND_DOWNLOAD command or another COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands automatically increment address and continue programming from the previous location. The caller should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program successfully and not overflow input buffers of the serial interfaces. The command terminates programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK to this command, the flash loader does not increment the current address to allow retransmission of the previous data. Byte[0] = 11 Byte[1] = checksum(Bytes[2:10]) Byte[2] = COMMAND_SEND_DATA Byte[3] = Data[0] Byte[4] = Data[1] Byte[5] = Data[2] Byte[6] = Data[3] Byte[7] = Data[4] Byte[8] = Data[5] Byte[9] = Data[6] Byte[10] = Data[7] A.4.5 COMMAND_RUN (0x22) This command is used to tell the flash loader to execute from the address passed as the parameter in this command. This command consists of a single 32-bit value that is interpreted as the address to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK signal back to the host device before actually executing the code at the given address. This allows the host to know that the command was received successfully and the code is now running. Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] A.4.6 = = = = = = = 7 checksum(Bytes[2:6]) COMMAND_RUN Execute Address[31:24] Execute Address[23:16] Execute Address[15:8] Execute Address[7:0] COMMAND_RESET (0x25) This command is used to tell the flash loader device to reset. This is useful when downloading a new image that overwrote the flash loader and wants to start from a full reset. Unlike the COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set up for the new code. It can also be used to reset the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader. 420 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Byte[0] = 3 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_RESET The flash loader responds with an ACK signal back to the host device before actually executing the software reset to the device running the flash loader. This allows the host to know that the command was received successfully and the part will be reset. April 04, 2010 421 Texas Instruments-Production Data Register Quick Reference B Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 System Control Base 0x400F.E000 DID0, type RO, offset 0x000, reset VER CLASS MAJOR MINOR PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD BORIOR LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 VADJ RIS, type RO, offset 0x050, reset 0x0000.0000 PLLLRIS BORRIS PLLLIM BORIM PLLLMIS BORMIS IMC, type R/W, offset 0x054, reset 0x0000.0000 MISC, type R/W1C, offset 0x058, reset 0x0000.0000 RESC, type R/W, offset 0x05C, reset - SW WDT BOR POR EXT RCC, type R/W, offset 0x060, reset 0x0780.3AD1 ACG PWRDN SYSDIV USESYSDIV BYPASS XTAL OSCSRC IOSCDIS MOSCDIS PLLCFG, type RO, offset 0x064, reset - F R RCC2, type R/W, offset 0x070, reset 0x0780.2810 USERCC2 SYSDIV2 PWRDN2 BYPASS2 OSCSRC2 DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 DSDIVORIDE DSOSCSRC DID1, type RO, offset 0x004, reset VER FAM PARTNO PINCOUNT TEMP PKG ROHS QUAL DC0, type RO, offset 0x008, reset 0x00FF.003F SRAMSZ FLASHSZ DC1, type RO, offset 0x010, reset 0x0000.309F MINSYSDIV MPU PLL WDT SWO SWD JTAG TIMER2 TIMER1 TIMER0 DC2, type RO, offset 0x014, reset 0x0307.0011 COMP1 COMP0 SSI0 UART0 DC3, type RO, offset 0x018, reset 0x8F00.0FC0 32KHZ CCP3 C1O CCP2 CCP1 C1PLUS C1MINUS CCP0 C0O C0PLUS C0MINUS 422 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA TIMER2 TIMER1 TIMER0 DC4, type RO, offset 0x01C, reset 0x5000.007F EPHY0 EMAC0 RCGC0, type R/W, offset 0x100, reset 0x00000040 WDT SCGC0, type R/W, offset 0x110, reset 0x00000040 WDT DCGC0, type R/W, offset 0x120, reset 0x00000040 WDT RCGC1, type R/W, offset 0x104, reset 0x00000000 COMP1 COMP0 SSI0 UART0 SCGC1, type R/W, offset 0x114, reset 0x00000000 COMP1 COMP0 TIMER2 TIMER1 SSI0 TIMER0 UART0 DCGC1, type R/W, offset 0x124, reset 0x00000000 COMP1 COMP0 TIMER2 TIMER1 SSI0 TIMER0 UART0 RCGC2, type R/W, offset 0x108, reset 0x00000000 EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA TIMER2 TIMER1 TIMER0 SCGC2, type R/W, offset 0x118, reset 0x00000000 EPHY0 EMAC0 DCGC2, type R/W, offset 0x128, reset 0x00000000 EPHY0 EMAC0 SRCR0, type R/W, offset 0x040, reset 0x00000000 WDT SRCR1, type R/W, offset 0x044, reset 0x00000000 COMP1 COMP0 SSI0 UART0 SRCR2, type R/W, offset 0x048, reset 0x00000000 EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Internal Memory Flash Memory Control Registers (Flash Control Offset) Base 0x400F.D000 FMA, type R/W, offset 0x000, reset 0x0000.0000 OFFSET OFFSET FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY COMT April 04, 2010 MERASE ERASE WRITE 423 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRIS ARIS PMASK AMASK PMISC AMISC DBG1 DBG0 FCRIS, type RO, offset 0x00C, reset 0x0000.0000 FCIM, type R/W, offset 0x010, reset 0x0000.0000 FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000 Internal Memory Flash Memory Protection Registers (System Control Offset) Base 0x400F.E000 USECRL, type R/W, offset 0x140, reset 0x31 USEC FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE NW DATA DATA USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF NW DATA DATA USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF NW DATA DATA FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE2, type R/W, offset 0x208, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE2, type R/W, offset 0x408, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE 424 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 General-Purpose Input/Outputs (GPIOs) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 DATA GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 DIR GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 IS GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 IBE GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 IEV GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 IME GPIORIS, type RO, offset 0x414, reset 0x0000.0000 RIS GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 MIS GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 IC GPIOAFSEL, type R/W, offset 0x420, reset - AFSEL GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF DRV2 GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 DRV4 GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 DRV8 GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 ODE GPIOPUR, type R/W, offset 0x510, reset - PUE April 04, 2010 425 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 PDE GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 SRL GPIODEN, type R/W, offset 0x51C, reset - DEN GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 LOCK LOCK GPIOCR, type -, offset 0x524, reset - CR GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 PID0 GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 426 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 General-Purpose Timers Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 GPTMCFG GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 TAAMS TACMR TAMR TBAMS TBCMR TBMR GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 TBPWML TBEVENT TBSTALL TBEN TAPWML RTCEN TAEVENT TASTALL TAEN CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS CBEMIS CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF TAILRH TAILRL GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF TBILRL GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF TAMRH TAMRL GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF TBMRL GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 TAPSR GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 TBPSR GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 TAPSMR GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 TBPSMR April 04, 2010 427 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESEN INTEN GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF TARH TARL GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF TBRL Watchdog Timer Base 0x4000.0000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF WDTLoad WDTLoad WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF WDTValue WDTValue WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 WDTICR, type WO, offset 0x00C, reset WDTIntClr WDTIntClr WDTRIS, type RO, offset 0x010, reset 0x0000.0000 WDTRIS WDTMIS, type RO, offset 0x014, reset 0x0000.0000 WDTMIS WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 STALL WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 WDTLock WDTLock WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 PID0 WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 PID1 WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 428 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OE BE PE FE EPS PEN BRK SIRLP SIREN UARTEN WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads) UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes) DATA UARTFR, type RO, offset 0x018, reset 0x0000.0090 TXFE RXFF TXFF RXFE BUSY UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 ILPDVSR UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 DIVINT UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 DIVFRAC UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 SPS WLEN FEN STP2 UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 RXE TXE LBE UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 RXIFLSEL TXIFLSEL UARTIM, type R/W, offset 0x038, reset 0x0000.0000 OEIM BEIM PEIM FEIM RTIM TXIM RXIM OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS UARTRIS, type RO, offset 0x03C, reset 0x0000.000F April 04, 2010 429 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS OEIC BEIC PEIC FEIC RTIC TXIC RXIC SSE LBM UARTMIS, type RO, offset 0x040, reset 0x0000.0000 UARTICR, type W1C, offset 0x044, reset 0x0000.0000 UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 PID0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Synchronous Serial Interface (SSI) SSI0 base: 0x4000.8000 SSICR0, type R/W, offset 0x000, reset 0x0000.0000 SCR SPH SPO FRF DSS SSICR1, type R/W, offset 0x004, reset 0x0000.0000 SOD MS SSIDR, type R/W, offset 0x008, reset 0x0000.0000 DATA 430 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BSY RFF RNE TNF TFE TXIM RXIM RTIM RORIM TXRIS RXRIS RTRIS RORRIS TXMIS RXMIS RTMIS RORMIS RTIC RORIC SSISR, type RO, offset 0x00C, reset 0x0000.0003 SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 CPSDVSR SSIIM, type R/W, offset 0x014, reset 0x0000.0000 SSIRIS, type RO, offset 0x018, reset 0x0000.0008 SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 SSIICR, type W1C, offset 0x020, reset 0x0000.0000 SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 PID0 SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 April 04, 2010 431 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Ethernet Controller Ethernet MAC Base 0x4004.8000 MACRIS/MACIACK, type RO, offset 0x000, reset 0x0000.0000 (Reads) PHYINT MDINT RXER FOV TXEMP TXER RXINT PHYINT MDINT RXER FOV TXEMP TXER RXINT RXERM FOVM TXEMPM TXERM RXINTM PRMS AMUL RXEN CRC PADEN TXEN WRITE START MACRIS/MACIACK, type WO, offset 0x000, reset 0x0000.0000 (Writes) MACIM, type R/W, offset 0x004, reset 0x0000.007F PHYINTM MDINTM MACRCTL, type R/W, offset 0x008, reset 0x0000.0008 RSTFIFO BADCRC MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000 DUPLEX MACDATA, type RO, offset 0x010, reset 0x0000.0000 (Reads) RXDATA RXDATA MACDATA, type WO, offset 0x010, reset 0x0000.0000 (Writes) TXDATA TXDATA MACIA0, type R/W, offset 0x014, reset 0x0000.0000 MACOCT4 MACOCT3 MACOCT2 MACOCT1 MACIA1, type R/W, offset 0x018, reset 0x0000.0000 MACOCT6 MACOCT5 MACTHR, type R/W, offset 0x01C, reset 0x0000.003F THRESH MACMCTL, type R/W, offset 0x020, reset 0x0000.0000 REGADR MACMDV, type R/W, offset 0x024, reset 0x0000.0080 DIV MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000 MDTX MACMRXD, type R/W, offset 0x030, reset 0x0000.0000 MDRX MACNP, type RO, offset 0x034, reset 0x0000.0000 NPR 432 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MACTR, type R/W, offset 0x038, reset 0x0000.0000 NEWTX Ethernet Controller MII Management MR0, type R/W, address 0x00, reset 0x3100 RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT MR1, type RO, address 0x01, reset 0x7849 100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD PRX LPANEGA PCSBP RXCC MR2, type RO, address 0x02, reset 0x000E OUI[21:6] MR3, type RO, address 0x03, reset 0x7237 OUI[5:0] MN RN MR4, type R/W, address 0x04, reset 0x01E1 NP RF A3 A2 A1 A0 S MR5, type RO, address 0x05, reset 0x0000 NP ACK RF A[7:0] S MR6, type RO, address 0x06, reset 0x0000 PDF LPNPA MR16, type R/W, address 0x10, reset 0x0140 RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL MR17, type R/W, address 0x11, reset 0x0000 JABBER_IE RXER_IE PRX_IE PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT MR18, type RO, address 0x12, reset 0x0000 ANEGF DPLX RATE RXSD RX_LOCK MR19, type R/W, address 0x13, reset 0x4000 TXO MR23, type R/W, address 0x17, reset 0x0010 LED1[3:0] LED0[3:0] MR24, type R/W, address 0x18, reset 0x00C0 PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD Analog Comparators Base 0x4003.C000 ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 IN1 IN0 IN1 IN0 IN1 IN0 ACRIS, type RO, offset 0x004, reset 0x0000.0000 ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 EN RNG VREF ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 OVAL ACSTAT1, type RO, offset 0x040, reset 0x0000.0000 OVAL April 04, 2010 433 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 ASRCP ISLVAL ISEN CINV ASRCP ISLVAL ISEN CINV ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 434 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller C Ordering and Contact Information C.1 Ordering Information LM3Snnnn–gppss–rrm Part Number nnn = Sandstorm-class parts nnnn = All other Stellaris® parts Shipping Medium T = Tape-and-reel Omitted = Default shipping (tray or tube) Temperature E = –40°C to +105°C I = –40°C to +85°C Revision Speed 20 = 20 MHz 25 = 25 MHz 50 = 50 MHz 80 = 80 MHz 100 = 100 MHz Package BZ = 108-ball BGA QC = 100-pin LQFP QN = 48-pin LQFP QR = 64-pin LQFP GZ = 48-pin QFN Table C-1. Part Ordering Information C.2 Orderable Part Number Description LM3S6730-IBZ50-A2 Stellaris LM3S6730 Microcontroller Industrial Temperature 108-ball BGA LM3S6730-IBZ50-A2T Stellaris LM3S6730 Microcontroller Industrial Temperature 108-ball BGA Tape-and-reel LM3S6730-EQC50-A2 Stellaris LM3S6730 Microcontroller Extended Temperature 100-pin LQFP LM3S6730-EQC50-A2T Stellaris LM3S6730 Microcontroller Extended Temperature 100-pin LQFP Tape-and-reel LM3S6730-IQC50-A2 Stellaris LM3S6730 Microcontroller Industrial Temperature 100-pin LQFP LM3S6730-IQC50-A2T Stellaris LM3S6730 Microcontroller Industrial Temperature 100-pin LQFP Tape-and-reel ® ® ® ® ® ® Part Markings ® The Stellaris microcontrollers are marked with an identifying number. This code contains the following information: ■ The first line indicates the part number. In the example figure below, this is the LM3S6965. ■ The first seven characters in the second line indicate the temperature, package, speed, and revision. In the example figure below, this is an Industrial temperature (I), 100-pin LQFP package (QC), 50-MHz (50), revision A2 (A2) device. ■ The remaining characters contain internal tracking numbers. April 04, 2010 435 Texas Instruments-Production Data Ordering and Contact Information C.3 Kits ® The Stellaris Family provides the hardware and software tools that engineers need to begin development quickly. ■ Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files ® ■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers before purchase ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor. C.4 Support Information ® For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm. 436 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller D Package Information Figure D-1. 100-Pin LQFP Package Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane. April 04, 2010 437 Texas Instruments-Production Data Package Information Body +2.00 mm Footprint, 1.4 mm package thickness Symbols Leads 100L A Max. 1.60 A1 - 0.05 Min./0.15 Max. A2 ±0.05 1.40 D ±0.20 16.00 D1 ±0.05 14.00 E ±0.20 16.00 E1 ±0.05 14.00 L +0.15/-0.10 0.60 e Basic 0.50 b +0.05 0.22 θ - 0˚-7˚ ddd Max. 0.08 ccc Max. 0.08 JEDEC Reference Drawing MS-026 Variation Designator BED 438 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S6730 Microcontroller Figure D-2. 108-Ball BGA Package April 04, 2010 439 Texas Instruments-Production Data Package Information Note: The following notes apply to the package drawing. Symbols MIN NOM MAX A 1.22 1.36 1.50 A1 0.29 0.34 0.39 A3 0.65 0.70 0.75 c 0.28 0.32 0.36 D 9.85 10.00 10.15 D1 E 8.80 BSC 9.85 E1 b 10.00 8.80 BSC 0.43 0.48 bbb 0.53 .20 ddd .12 e 0.80 BSC f 10.15 - 0.60 M 12 n 108 - REF: JEDEC MO-219F 440 April 04, 2010 Texas Instruments-Production Data IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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