LINER LTC4269-1

LTC4269-1
IEEE 802.3at PD with
Synchronous No-Opto
Flyback Controller
DESCRIPTION
FEATURES
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The LTC®4269-1 is an integrated Powered Device (PD)
controller and switching regulator intended for high
power IEEE 802.3at and 802.3af applications. The
LTC4269-1 is targeted for high efﬁciency, single and
multioutput applications from 10W to 25W. By supporting both 1-event and 2-event classiﬁcations, as deﬁned
by the IEEE, the LTC4269-1 can be used in a wide range
of product conﬁgurations.
25.5W IEEE 802.3at Compliant (Type 2) PD
Integrated State-of-the-Art Synchronous Flyback
Controller
– Isolated Power Supply Efﬁciency >92%
– 88% Efﬁciency Including Diode Bridge and
Hot Swap™ FET
Flexible Integrated Auxiliary Power Support
Superior EMI Performance
Robust 100V 0.7Ω (Typ) Integrated Hot Swap MOSFET
IEEE 802.3at High Power Available Indicator
Integrated Signature Resistor and Programmable
Class Current
Undervoltage, Overvoltage and Thermal Protection
Short-Circuit Protection with Auto-Restart
Programmable Soft-Start and Switching Frequency
Complementary Power Good Indicators
Thermally Enhanced 7mm × 4mm DFN Package
The LTC4269-1 synchronous, current mode, ﬂyback controller generates multiple supply rails in a single conversion
step providing for the highest system efﬁciency while maintaining tight regulation across all outputs. The LTC4269-1
includes Linear Technology’s patented No-Opto feedback
topology to provide full IEEE 802.3 isolation without the
need of an opto-isolator circuit. A true soft-start function
allows graceful ramp-up of all output voltages.
All Linear Technology PD solutions include a shutdown
pin to provide ﬂexible auxiliary power options. The
LTC4269-1 can accommodate adaptor voltages from 18V
to 60V and supports both PoE or aux dominance options.
The LTC4269-1 is available in a space saving 32-pin DFN
package.
APPLICATIONS
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VoIP Phones with Advanced Display Options
Dual-Radio Wireless Access Points
PTZ Security Cameras
RFID Readers
Industrial Controls
TYPICAL APPLICATION
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5841643.
25W High Efﬁciency PD Solution
•
0.18μH
10μH
VIN
•
+
2.2μF
10μF
39k
383k
54V FROM
DATA PAIR
~ +
~ –
54V FROM
SPARE PAIR
~ +
~ –
47μF
+
5V
5A
100μF
•
27.4k
10μF
14k
TO MICRO
CONTROLLER
PWRGD UVLO
VPORTP
3.01k
T2P
VCC
FB
SENSE+
33mΩ
RCLASS
0.1μF
PG
30.9Ω
SENSE–
LTC4269-1
SG
VCMP
SHDN
VPORTN
VNEG SYNC GND OSC
PGDLY
12k
33pF
tON
ENDLY RCMP CCMP
100k
38.3k
2.2nF
1μF
10nF
•
•
1.21k
0.1μF
42691 TA01a
42691fb
1
LTC4269-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Pins with Respect to VPORTN
VPORTP Voltage......................................... –0.3V to 100V
VNEG Voltage ......................................... –0.3V to VPORTP
VNEG Pull-Up Current ..................................................1A
SHDN ....................................................... –0.3V to 100V
RCLASS, Voltage ............................................ –0.3V to 7V
RCLASS Source Current...........................................50mA
PWRGD Voltage (Note 3)
Low Impedance Source ......VNEG –0.3V to VNEG +11V
Sink Current.........................................................5mA
PWRGD, T2P Voltage ............................... –0.3V to 100V
PWRGD, T2P Sink Current .....................................10mA
Pins with Respect to GND
VCC (Note 3)
Low Impedance Source ....................... –0.3V to +18V
Sink Current.......................................................30mA
SENSE–, SENSE+ Voltage ........................ –0.5V to +0.5V
UVLO, SYNC Voltage...................................–0.3V to VCC
FB Current ..............................................................±2mA
VCMP Current .........................................................±1mA
Operating Ambient Temperature Range
LTC4269C-1 ................................................. 0°C to 70°C
LTC4269I-1 ..............................................–40°C to 85°C
SHDN
1
32 VPORTP
T2P
2
31 NC
RCLASS
3
30 PWRGD
NC
4
29 PWRGD
VPORTN
5
28 NC
VPORTN
6
27 VNEG
NC
7
NC
8
SG
9
26 VNEG
33
25 NC
24 PG
VCC 10
23 PGDLY
tON 11
22 RCMP
ENDLY 12
21 CCMP
SYNC 13
20 SENSE+
SFST 14
19 SENSE –
OSC 15
18 UVLO
FB 16
17 VCMP
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 2°C/W
GND, EXPOSED PAD (PIN 33) MUST BE SOLDERED TO A
HEAT SINKING PLANE THAT IS CONNECTED TO VNEG
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4269CDKD-1#PBF
LTC4269CDKD-1#TRPBF
42691
32-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
LTC4269IDKD-1#PBF
LTC4269IDKD-1#TRPBF
42691
32-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
42691fb
2
LTC4269-1
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
60
9.8
21
37.2
V
V
V
V
V
V
Interface Controller (Note 4)
Operating Input Voltage
Signature Range
Classiﬁcation Range
ON Voltage
OFF Voltage
Overvoltage Lockout
At VPORTP (Note 5)
l
l
l
l
1.5
12.5
30.0
71
ON/OFF Hysteresis Window
l
4.1
V
Signature/Class Hysteresis Window
l
1.4
V
State Machine Reset for 2-Event Classiﬁcation
l
2.57
Supply Current at 57V
Measured at VPORTP Pin
Class 0 Current
5.40
V
l
1.35
mA
VPORTP = 17.5V, No RCLASS Resistor
l
0.40
mA
Signature Resistance
1.5V ≤ VPORTP ≤ 9.8V (Note 6)
l
26
kΩ
Invalid Signature Resistance, SHDN Invoked
1.5V ≤ VPORTP ≤ 9.8V, VSHDN = 3V (Note 6)
l
11
kΩ
l
11
kΩ
Reset Threshold
Supply Current
Signature
Invalid Signature Resistance During Mark Event (Notes 6, 7)
23.25
Classiﬁcation
Class Accuracy
10mA < ICLASS < 40mA, 12.5V < VPORTP < 21V
(Notes 8, 9)
l
±3.5
%
Classiﬁcation Stability Time
VPORTP Pin Step to 17.5V, RCLASS = 30.9, ICLASS Within
3.5% of Ideal Value (Notes 8, 9)
l
1
ms
Inrush Current
VPORTP = 54V, VNEG = 3V
l
100
180
mA
Power FET On-Resistance
Tested at 600mA into VNEG, VPORTP = 54V
l
0.7
1.0
Ω
Power FET Leakage Current at VNEG
VPORTP = SHDN = VNEG = 57V
l
1
μA
Normal Operation
60
Digital Interface
SHDN Input High Level Voltage
l
SHDN Input Low Level Voltage
l
3
V
0.45
V
SHDN Input Resistance
VPORTP = 9.8V, SHDN = 9.65V
l
PWRGD, T2P Output Low Voltage
Tested at 1mA, VPORTP = 54V. For T2P, Must Complete
2-Event Classiﬁcation to See Active Low
l
0.15
V
PWRGD, T2P Leakage Current
Pin Voltage Pulled 57V, VPORTP = VPORTN = 0V
l
1
μA
PWRGD Output Low Voltage
Tested at 0.5mA, VPORTP = 52V, VNEG = 48V, Output
Voltage Is with Respect to VNEG
l
0.4
V
PWRGD Clamp Voltage
Tested at 2mA, VNEG = 0V, Voltage with Respect to VNEG
l
16.5
V
PWRGD Leakage Current
VPWRGD = 11V, VNEG = 0V, Voltage with Respect to VNEG
l
1
μA
100
12
kΩ
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LTC4269-1
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PWM Controller (Note 10)
Power Supply
VCC Turn-On Voltage, VCC(ON)
l
14
15.3
16
V
VCC Turn-Off Voltage, VCC(OFF)
●
8
9.7
11
V
6.5
V
VCC Hysteresis
VCC(ON) – VCC(OFF)
●
4
5.6
VCC Shunt Clamp
VUVLO = 0V, IVCC = 15mA
●
19.5
20.5
VCC Supply Current (ICC)
VCMP = Open (Note 11)
●
4
6.4
10
mA
VCC Start-Up Current
VCC = 10V
●
180
400
μA
1.237
1.251
V
Feedback Ampliﬁer
●
Feedback Regulation Voltage (VFB)
Feedback Pin Input Bias Current
RCMP Open
Feedback Ampliﬁer Transconductance
ΔIC = ±10μA
Feedback Ampliﬁer Source or Sink Current
1.220
200
●
700
1000
1400
●
25
55
90
Feedback Ampliﬁer Clamp Voltage
VFB = 0.9V
VFB = 1.4V
Reference Voltage Line Regulation
12V ≤ VCC ≤ 18V
Feedback Ampliﬁer Voltage Gain
VCMP = 1.2V to 1.7V
Soft-Start Charging Current
VSFST = 1.5V
16
20
Soft-Start Discharge Current
VSFST = 1.5V, VUVLO = 0V
0.8
1.3
Control Pin Threshold (VCMP)
Duty Cycle = Min
2.56
0.84
●
0.005
V
nA
μmho
μA
V
V
0.02
1400
%/ V
V/ V
25
μA
mA
1
V
Gate Outputs
PG, SG Output High Level
●
7.4
8
PG, SG Output Low Level
●
0.01
0.05
V
●
1.6
2.3
V
6.6
V
PG, SG Output Shutdown Strength
VUVLO = 0V; IPG, ISG = 20mA
PG Rise Time
CPG = 1nF
11
ns
SG Rise Time
CSG = 1nF
15
ns
PG, SG Fall Time
CPG, CSG = 1nF
10
ns
Current Ampliﬁer
Switch Current Limit at Maximum VCMP
VSENSE+
●
88
ΔVSENSE /ΔVCMP
110
0.07
VSENSE+, VSFST < 1V
●
Switching Frequency (fOSC)
COSC = 100pF
●
Oscillator Capacitor Value (COSC)
(Note 12)
Sense Voltage Overcurrent Fault Voltage
98
mV
V/ V
206
230
mV
100
110
kHz
200
pF
Timing
84
33
Minimum Switch On Time (tON(MIN))
200
ns
Flyback Enable Delay Time (tENDLY)
265
ns
200
ns
PG Turn-On Delay Time (tPGDLY)
Maximum Switch Duty Cycle
●
SYNC Pin Threshold
●
SYNC Pin Input Resistance
85
88
1.53
40
%
2.1
V
kΩ
42691fb
4
LTC4269-1
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Load Compensation
Load Compensation to VSENSE Offset Voltage
VRCMP with VSENSE+ = 0V
1
mV
Feedback Pin Load Compensation Current
VSENSE+ = 20mV, VFB = 1.230V
20
μA
UVLO Function
●
UVLO Pin Threshold (VUVLO)
UVLO Pin Bias Current
VUVLO = 1.2V
VUVLO = 1.3V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: Active high PWRGD internal clamp self-regulates to 14V with
respect to VNEG. VCC has internal 19.5V clamp with respect to GND.
Note 4: All voltages are with respect to VPORTN pin unless otherwise noted.
Note 5: Input voltage speciﬁcations are deﬁned with respect to LTC4269-1
pins and meet IEEE 802.3af/at speciﬁcations when the input diode bridge
is included.
Note 6: Signature resistance is measured via the ΔV/ΔI method with the
minimum ΔV of 1V. The LTC4269-1 signature resistance accounts for the
additional series resistance in the input diode bridge.
1.215
1.240
1.265
V
–0.25
–4.50
0
–3.4
0.25
–2.50
μA
μA
Note 7: An invalid signature after the 1st classiﬁcation event is mandated
by the IEEE802.3at standard. See the Applications Information section.
Note 8: Class accuracy is with respect to the ideal current deﬁned as
1.237/RCLASS and does not include variations in RCLASS resistance.
Note 9: This parameter is assured by design and wafer level testing.
Note 10: VCC = 14V; PG, SG Open; VCMP = 1.5V, VSENSE– = 0V, RCMP = 1k,
RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise speciﬁed. All
voltages are with respect to GND.
Note 11: Supply current does not include gate charge current to the
MOSFETs. See the Applications Information section.
Note 12: Component value range guaranteed by design.
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LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
50
TA = 25°C
VPORTP CURRENT (mA)
VPORTP CURRENT (mA)
TA = 25°C
0.3
0.2
30
CLASS 3
20
CLASS 2
CLASS 1
0.1
10
0
0
CLASS 1 OPERATION
CLASS 4
40
0.4
Input Current vs Input Voltage
11.0
VPORTP CURRENT (mA)
0.5
10.5
85°C
–40°C
10.0
CLASS 0
0
2
4
6
VPORTP VOLTAGE (V)
10
8
0
42691 G01
10
50
20
30
40
VPORTP VOLTAGE (V)
(RISING)
9.5
60
12
14
20
18
16
VPORTP VOLTAGE (V)
22
42691 G03
42691 G02
Signature Resistance
vs Input Voltage
Class Operation vs Time
On-Resistance vs Temperature
28
SIGNATURE RESISTANCE (kΩ)
RESISTANCE = $V = V2 – V1
$I I2 – I1
27 DIODES: HD01
TA = 25°C
IEEE UPPER LIMIT
1.0
RESISTANCE (Ω)
26
LTC4269-1 + 2 DIODES
25
CLASS
CURRENT
10mA/DIV
24
LTC4269-1 ONLY
IEEE LOWER LIMIT
3
4
TIME (10μs/DIV)
9
10
7
5
8
6
VPORTP VOLTAGE (V)
0.2
–50
42691 G05
Active High PWRGD
Output Low Voltage vs Current
1.0
TA = 25°C
Inrush Current vs Input Voltage
TA = 25°C
VPORTP – VNEG = 4V
110
0.2
CURRENT (mA)
PWRGD (V)
0.4
0.6
0.4
0.2
2
6
4
CURRENT (mA)
8
10
42691 G07
100
115
0.8
0
75
0
25
50
–25
JUNCTION TEMPERATURE (°C)
42691 G06
0.6
0
0.6
42691 G04
PWRGD, T2P Output Low Voltage
vs Current
0.8
0.8
0.4
23
22
V1: 1
V2: 2
VPWRGD – VPORTN (V)
VT2P – VPORTN (V)
TA = 25°C
VPORTP
VOLTAGE
10V/DIV
105
100
95
90
0
0
0.5
1
1.5
CURRENT (mA)
2
42691 G08
85
40
55
45
50
VPORTP VOLTAGE (V)
60
42691 G09
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LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
VCC(ON) and VCC(OFF)
vs Temperature
VCC Start-Up Current
vs Temperature
16
VCC Current vs Temperature
10
300
VCC(ON)
15
9
250
14
8
IVCC (μA)
VCC (V)
12
11
IVCC (mA)
200
13
150
7
6
STATIC PART CURRENT
100
VCC(OFF)
5
10
50
9
8
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
4
0
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
42691 G10
108
100
98
96
94
210
200
195
90
–50
180
–50 –25
125
98
92
0
50
75
25
TEMPERATURE (°C)
42691 G13
100
90
–50
125
1.240
1.235
1.234
1.233
1.232
1.03
250
1.02
200
VFB RESET (V)
FEEDBACK PIN INPUT BIAS (nA)
VFB (V)
1.236
150
100
125
42691 G16
1.01
1.00
0.99
0.98
50
0.97
1.231
100
125
1.04
RCMP OPEN
1.239
100
VFB Reset vs Temperature
300
1.237
50
25
0
75
TEMPERATURE (°C)
42691 G15
Feedback Pin Input Bias
vs Temperature
1.238
–25
42691 G14
VFB vs Temperature
50
25
0
75
TEMPERATURE (°C)
100
94
185
100
102
96
190
92
–25
COSC = 100pF
104
205
fOSC (kHz)
SENSE VOLTAGE (mV)
SENSE VOLTAGE (mV)
110
106
102
1.230
–50
125
Oscillator Frequency
vs Temperature
SENSE = VSENSE+
–
215 WITH VSENSE = 0V
104
50
25
0
75
TEMPERATURE (°C)
100
42691 G12
220
FB = 1.1V
SENSE = VSENSE+
WITH VSENSE– = 0V
–25
125
SENSE Fault Voltage
vs Temperature
110
106
100
VCC = 14V
3
50
–50 –25
25
75
0
TEMPERATURE (°C)
42691 G11
SENSE Voltage vs Temperature
108
DYNAMIC CURRENT CPG = 1nF,
CSG = 1nF, fOSC = 100kHz
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
42691 G17
0.96
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
42691 G18
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LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Ampliﬁer Source and
Sink Current vs Temperature
70
70
25°C
10
–10
1050
SINK
CURRENT
VFB = 1.4V
60
IVCMP (μA)
IVCMP (μA)
65
–40°C
30
1100
SOURCE CURRENT
VFB = 1.1V
125°C
50
Feedback Ampliﬁer gm
vs Temperature
gm (μmho)
Feedback Ampliﬁer Output
Current vs VFB
1000
55
50
–30
950
45
–50
–70
0.9
1
1.1
1.2
VFB (V)
1.3
40
–50
1.5
1.4
50
25
75
0
TEMPERATURE (°C)
–25
100
42691 G19
–25
75
0
25
50
TEMPERATURE (°C)
100
125
42691 G21
42691 G20
Feedback Ampliﬁer Voltage Gain
vs Temperature
1700
900
–50
125
IUVLO Hysteresis vs Temperature
UVLO vs Temperature
3.7
1.250
1650
1600
3.6
1.245
1550
1500
3.5
AV (V/V)
UVLO (V)
1450
1400
1350
1300
IUVLO (μA)
1.240
1.235
3.4
3.3
1.230
3.2
1250
1200
1.225
3.1
1150
1100
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
1.220
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
42691 G22
80
22
70
21
60
20
50
VCC Clamp Voltage
vs Temperature
21.5
TA = 25°C
20.5
FALL TIME
30
17
20
16
10
ICC = 10mA
21.0
40
18
125
VCC (V)
TIME (ns)
SFST CHARGE CURRENT (μA)
23
100
42691 G24
PG, SG Rise and Fall Times
vs Load Capacitance
19
50
25
75
0
TEMPERATURE (°C)
42691 G23
Soft-Start Charge Current
vs Temperature
15
–50 –25
3.0
–50 –25
125
20.0
RISE TIME
19.5
0
0
50
75
25
TEMPERATURE (°C)
100
125
42691 G25
0
1
2
3 4 5 6 7
CAPACITANCE (nF)
8
9
10
42691 G26
19.0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
42691 G27
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LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum PG On-Time
vs Temperature
325
300
RtON(MIN) = 158k
330
250
305
200
310
tPGDLY (ns)
tON(MIN) (ns)
RENDLY = 90k
RPGDLY = 27.4k
320
300
290
285
tENDLY (ns)
340
Enable Delay Time
vs Temperature
PG Delay Time vs Temperature
150
RPGDLY = 16.9k
100
265
245
280
260
–50 –25
225
50
270
75
50
25
TEMPERATURE (°C)
0
100
125
0
–50
–25
25
0
75
50
TEMPERATURE (°C)
42691 G28
100
125
42691 G29
205
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
42691 G30
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4269-1
operation and corrupt the signature resistance. If unused,
tie SHDN to VPORTN.
T2P (Pin 2): Type 2 PSE Indicator, Open-Drain. Low impedance indicates the presence of a Type 2 PSE.
RCLASS (Pin 3): Class Select Input. Connect a resistor
between RCLASS and VPORTN to set the classiﬁcation load
current (see Table 2).
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
VPORTN (Pins 5, 6): Input Voltage, Negative Rail. Pin 5 and
Pin 6 must be electrically tied together at the package.
SG (Pin 9): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchronous rectiﬁer. Large dynamic currents may ﬂow during
voltage transitions. See the Applications Information
section for details.
VCC (Pin 10): Supply Voltage Pin. Bypass this pin to
GND with a 4.7μF, or more, capacitor. This pin has a 19.5V
clamp to ground. VCC has an undervoltage lockout function that turns the part on when VCC is approximately
15.3V and off at 9.7V. In a conventional trickle-charge
bootstrapped conﬁguration, the VCC supply current
increases signiﬁcantly during turn-on causing a benign
relaxation oscillation action on the VCC pin if the part does
not start normally.
tON (Pin 11): Pin for external programming resistor to
set the minimum time that the primary switch is on for
each cycle. Minimum turn-on facilitates the isolated feedback method. See the Applications Information section
for details.
ENDLY (Pin 12): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback ampliﬁer for a ﬁxed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for ﬂyback voltage sensing.
See the Applications Information section for details.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to
discharge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See the Applications Information section for details.
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (CSFST) to GND, controls the ramp-up of peak
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
42691fb
9
LTC4269-1
PIN FUNCTIONS
the VCMP voltage and thus limits peak current until softstart is complete. The ramp time is approximately 70ms
per μF of capacitance. Leave SFST open if not using the
soft-start function.
OSC (Pin 15): Oscillator. This pin, in conjunction with an
external capacitor (COSC) to GND, deﬁnes the controller
oscillator frequency. The frequency is approximately
100kHz • 100/COSC (pF).
FB (Pin 16): Feedback Ampliﬁer Input. Feedback is usually
sensed via a third winding and enabled during the ﬂyback
period. This pin also sinks additional current to compensate
for load current variation as set by the RCMP pin. Keep the
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
VCMP (Pin 17): Frequency Compensation Control. VCMP
is used for frequency compensation of the switcher control loop. It is the output of the feedback ampliﬁer and
the input to the current comparator. Switcher frequency
compensation components are placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback ampliﬁer output is enabled
during the synchronous switch on time.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
from VPORTP to this pin sets an undervoltage lockout based
upon VPORTP level (not VCC). When the UVLO pin is below
its threshold, the gate drives are disabled, but the part
draws its normal quiescent current from VCC. The VCC
undervoltage lockout supersedes this function, so VCC
must be great enough to start the part.
The bias current on this pin has hysteresis such that the
bias current is sourced when UVLO threshold is exceeded.
This introduces a hysteresis at the pin equivalent to the bias
current change times the impedance of the upper divider
resistor. The user can control the amount of hysteresis
by adjusting the impedance of the divider. Tie the UVLO
pin to VCC if not using this function. See the Applications
Information section for details. This pin is used for the
UVLO function of the switching regulator. The PD interface
section has an internal UVLO.
SENSE –,
SENSE+
(Pins 19, 20): Current Sense Inputs.
These pins are used to measure primary-side switch current through an external sense resistor. Peak primary-side
current is used in the converter control loop. Make Kelvin
connections to the sense resistor RSENSE to reduce noise
problems. SENSE – connects to the GND side. At maximum
current (VCMP at its maximum voltage) SENSE pins have
100mV threshold. The signal is blanked (ignored) during
the minimum turn-on time.
CCMP (Pin 21): Load Compensation Capacitive Control.
Connect a capacitor from CCMP to GND in order to reduce
the effects of parasitic resistances in the feedback sensing
path. A 0.1μF ceramic capacitor sufﬁces for most applications. Short this pin to GND when load compensation is
not needed.
RCMP (Pin 22): Load Compensation Resistive Control.
Connect a resistor from RCMP to GND in order to compensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See the Applications
Information section for details.
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (RPGDLY) to set delay from
synchronous gate turn-off to primary gate turn-on. See
the Applications Information section for details.
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary-side MOSFET switch. Large dynamic currents ﬂow during voltage transitions. See the Applications
Information section for details.
VNEG (Pins 26, 27): System Negative Rail. Connects VNEG
to VPORTN through an internal power MOSFET. Pin 26 and
Pin 27 must be electrically tied together at the package.
PWRGD (Pin 29): Power Good Output, Open-Collector.
High impedence signals power-up completion. PWRGD
is referenced to VNEG and features a 14V clamp.
PWRGD (Pin 30): Complementary Power Good Output,
Open-Drain. Low impedance signals power-up completion.
PWRGD is referenced to VPORTN.
VPORTP (Pin 32): Positive Power Input. Tie to the input
port power through the input diode bridge.
Exposed Pad (Pin 33): Ground. This is the negative rail
connection for both signal ground and gate driver grounds
of the ﬂyback controller. This pin should be connected to
VNEG.
42691fb
10
LTC4269-1
BLOCK DIAGRAM
CLASSIFICATION
CURRENT LOAD
SHDN
1
VPORTP
+
1.237V
16k
T2P
2
32
25k
–
RCLASS
3
NC
31
PWRGD
30
CONTROL
CIRCUITS
PWRGD
4 NC
29
VPORTN
5
14V
VNEG
VPORTN
6
VNEG
BOLD LINE INDICATES
HIGH CURRENT PATH
7 NC
27
26
8 NC
VCC
CLAMPS
20V
+
+
FB
1.3
–
1.237V
REFERENCE
(VFB)
–
INTERNAL
REGULATOR
VCMP
+
3V
S
Q
R
Q
–
UVLO
+
–
UVLO
17
COLLAPSE DETECT
+
18
16
ERROR AMP
CURRENT
COMPARATOR
IUVLO
SFST
1V
14
OVERCURRENT
FAULT
–
–
15.3V
0.7
–
VCC UVLO
+
10
TSD
SENSE–
19
–
CURRENT
SENSE AMP
+
+
CURRENT TRIP
SENSE+
SLOPE COMPENSATION
15
13
11
23
12
OSC
OSCILLATOR
RCMPF
50k
CCMP
ENABLE
SET
+
SYNC
ENDLY
21
–
LOAD
COMPENSATION
tON
PGDLY
20
LOGIC
BLOCK
RCMP
TO FB
22
VCC
PGATE
GATE DRIVE
PG
24
SGATE
+
25 NC
–
3V
VCC
28 NC
GATE DRIVE
SG
GND
(EXPOSED PAD)
9
33
42691 BD
42691fb
11
LTC4269-1
APPLICATIONS INFORMATION
OVERVIEW
50
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
VPORTP (V)
40
30
ON
OFF
20
10
CLASSIFICATION
DETECTION V2
DETECTION V1
VPORTP – VNEG (V)
50
The IEE802.3at standard establishes a higher power
allocation for Power over Ethernet while maintaining
backwards compatibility with the existing IEEE 802.3af
systems. Power sourcing equipment (PSE) and powered
devices are distinguished as Type 1 complying with the
IEEE 802.3af/IEEE 802.3at power levels, or Type 2 complying with the IEEE 802.3at power levels. The maximum
available power of a Type 2 PD is 25.5W.
dV = INRUSH
dt
C1
40
30
OFF
ON
OFF
20
T = RLOAD C1
10
TIME
VPORTP – PWRGD (V)
TIME
The IEEE 802.3at standard also establishes a new method
of acquiring power classiﬁcation from a PD and communicating the presence of a Type 2 PSE. A Type 2 PSE has the
option of acquiring PD power classiﬁcation by performing
2-event classiﬁcation (layer 1) or by communicating with
the PD over the data line (layer 2). In turn, a Type 2 PD
must be able to recognize both layers of communications
and identify a Type 2 PSE.
–10
POWER
BAD
–20
PWRGD
TRACKS
VPORTP
–30
–40
POWER
GOOD
PWRGD – VNEG (V)
–50
POWER
BAD
PWRGD
TRACKS
VPORTP
PWRGD TRACKS
VPORTN
20
POWER
BAD
10
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
The LTC4269-1 is speciﬁcally designed to support the
front end of a PD that must operate under the IEEE 802.3at
standard. In particular, the LTC4269-1 provides the T2P
indicator bit which recognizes 2-event classiﬁcation.
This indicator bit may be used to alert the LTC4269-1
output load that a Type 2 PSE is present. With an internal
signature resistor, classiﬁcation circuitry, inrush control,
and thermal shutdown, the LTC4269-1 is a complete PD
Interface solution capable of supporting in the next generation PD applications.
LOAD, ILOAD
PD CURRENT
INRUSH
CLASSIFICATION
DETECTION I2
TIME
DETECTION I1
I1 =
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
I2 =
25kΩ
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
INRUSH = 100mA
V
ILOAD = PORTP
RLOAD
MODES OF OPERATION
The LTC4269-1 has several modes of operation depending on the input voltage applied between the VPORTP and
VPORTN pins. Figure 1 presents an illustration of voltage
and current waveforms the LTC4269-1 may encounter with
the various modes of operation summarized in Table 1.
TIME
LTC4269-1
IIN
PSE
RCLASS VPORTP
PWRGD
RCLASS
RLOAD
C1
PWRGD
VPORTN
VNEG
42691 F01
Figure 1. VNEG, PWRGD, PWRGD and PD
Current as a Function of Input Voltage
42691fb
12
LTC4269-1
APPLICATIONS INFORMATION
The input diode bridge introduces a voltage drop that
affects the range for each mode of operation. The
LTC4269-1 compensates for these voltage drops so that a
PD built with the LTC4269-1 meets the IEEE 802.3af/IEEE
802.3at-established voltage ranges. Note the Electrical
Characteristics are referenced with respect to the
LTC4269- 1 package pins.
Table 1. LTC4269-1 Modes of Operation as a Function
of Input Voltage
VPORTP–VPORTN (V)
LTC4269-1 MODES OF OPERATION
0V to 1.4V
Inactive (Reset After 1st Classiﬁcation Event)
1.5V to 9.8V
(5.4V to 9.8V)
25k Signature Resistor Detection Before 1st
Classiﬁcation Event (Mark, 11k Signature
Corrupt After 1st Classiﬁcation Event)
12.5V to ON/OFF*
Classiﬁcation Load Current Active
ON/OFF* to 60V
Inrush and Power Applied To PD Load
>71V
Overvoltage Lockout,
Classiﬁcation and Hot Swap Are Disabled
DETECTION
During detection, the PSE looks for a 25k signature resistor which identiﬁes the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltages V1 and V2 and the corresponding PD current. The
PSE calculates the signature resistance using the ΔV/ΔI
measurement technique.
*ON/OFF includes hysteresis. Rising input threshold, 37.2V Max.
Falling input threshold, 30V Min.
These modes satisfy the requirements deﬁned in the
IEEE 802.3af/IEEE 802.3at speciﬁcation.
INPUT DIODE BRIDGE
In the IEEE 802.3af/IEEE 802.3at standard, the modes of
operation reference the input voltage at the PD’s RJ45
connector. Since the PD must handle power received in
either polarity from either the data or the spare pair, input
diode bridges BR1 and BR2 are connected between the
RJ45 connector and the LTC4269-1 (Figure 2).
RJ45
1
2
3
TX+
T1
BR1
TX–
RX+
–
POWERED 6 RX
DEVICE
(PD)
SPARE+
INPUT
4
5
The LTC4269-1 presents its precision, temperature-compensated 25k resistor between the VPORTP and VPORTN
pins, alerting the PSE that a PD is present and requests
power to be applied. The LTC4269-1 signature resistor
also compensates for the additional series resistance
introduced by the input diode bridge. Thus a PD built
with the LTC4269-1 conforms to the IEEE 802.3af/IEEE
802.3at speciﬁcations.
TO PHY
VPORTP
BR2
0.1μF
100V D3
LTC4269-1
VPORTN
7
42691 F02
8
SPARE–
Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs
42691fb
13
LTC4269-1
APPLICATIONS INFORMATION
SIGNATURE CORRUPT OPTION
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4269-1 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/IEEE 802.3at speciﬁcation, and alerts the PSE not to apply power. Invoking
the SHDN pin also ceases operation for classiﬁcation and
disconnects the LTC4269-1 load from the PD input. If this
feature is not used, connect SHDN to VPORTN.
LTC4269-1
TO
PSE
VPORTP
16k
25k SIGNATURE
RESISTOR
SHDN
VPORTN
42691 F03
SIGNATURE DISABLE
Figure 3. 25k Signature Resistor with Disable
CLASSIFICATION
Classiﬁcation provides a method for more efﬁcient power
allocation by allowing the PSE to identify a PD power classiﬁcation. Class 0 is included in the IEEE speciﬁcation for
PDs that do not support classiﬁcation. Class 1-3 partitions
PDs into three distinct power ranges. Class 4 includes the
new power range under IEEE802.3at (see Table 2).
During classiﬁcation probing, the PSE presents a ﬁxed
voltage between 15.5V and 20.5V to the PD (Figure 1).
The LTC4269-1 asserts a load current representing the
PD power classiﬁcation. The classiﬁcation load current
is programmed with a resistor RCLASS that is chosen
from Table 2.
Table 2. Summary of Power Classiﬁcations and LTC4269-1
RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
NOMINAL
CLASSIFICATION
LOAD CURRENT
(mA)
LTC4269-1
RCLASS
RESISTOR
(Ω, 1%)
0
Type 1
0.44 to 12.95
< 0.4
Open
1
Type 1
0.44 to 3.84
10.5
124
2
Type 1
3.84 to 6.49
18.5
69.8
3
Type 1
6.49 to 12.95
28
45.3
4
Type 2
12.95 to 25.5
40
30.9
2-EVENT CLASSIFICATION AND THE T2P PIN
A Type 2 PSE may declare the availability of high power
by performing a 2-event classiﬁcation (layer 1) or by
communicating over the high speed data line (layer 2). A
Type 2 PD must recognize both layers of communication.
Since layer 2 communication takes place directly between
the PSE and the LTC4269-1 load, the LTC4269-1 concerns
itself only with recognizing 2-event classiﬁcation.
In 2-event classiﬁcation, a Type 2 PSE probes for power
classiﬁcation twice. Figure 4 presents an example of a
2-event classiﬁcation. The 1st classiﬁcation event occurs
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4269-1 presents a class 4 load current. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
The PSE repeats this sequence, signaling the 2nd Classiﬁcation and 2nd mark event occurrence. This alerts the
LTC4269-1 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4269-1 charges
up the reservoir capacitor C1 with a controlled inrush current. When C1 is fully charged, and the LTC4269-1 declares
power good, the T2P pin presents an active low signal, or
low impedance output with respect to VPORTN . The T2P
output becomes inactive when the LTC4269-1 input voltage
falls below undervoltage lockout threshold.
42691fb
14
LTC4269-1
APPLICATIONS INFORMATION
SIGNATURE CORRUPT DURING MARK
50
VPORTP (V)
40
30
1st CLASS
2nd CLASS
ON
OFF
20
10
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
PD CURRENT
INRUSH
LOAD, ILOAD
1st CLASS
2nd CLASS
40mA
TIME
DETECTION V1
DETECTION V2
VPORTP – VNEG (V)
50
40
PD STABILITY DURING CLASSIFICATION
1st MARK 2nd MARK
dV = INRUSH
dt
C1
30
OFF
ON
OFF
20
T = RLOAD C1
10
TIME
VPORTP – T2P (V)
–10
–20
–30
TRACKS
VPORTN
–50
INRUSH = 100mA
RCLASS = 30.9Ω
V
ILOAD = PORTN
RLOAD
LTC4269-1
IIN
PSE
RLOAD
RCLASS VPORTP
RCLASS
T2P
VPORTN
C1
VNEG
Figure 4. VNEG, T2P and PD Current
as a Result of 2-Event Classiﬁcation
Classiﬁcation presents a challenging stability problem due
to the wide range of possible classiﬁcation load current.
The onset of the classiﬁcation load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classiﬁcation with the
onset and removal of the classiﬁcation load current.
The LTC4269-1 prevents this oscillation by introducing a
voltage hysteresis window between the detection and classiﬁcation ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classiﬁcation load current, thus providing a trouble-free
transition between detection and classiﬁcation modes.
TIME
–40
As a member of the IEEE 802.3at working group, Linear
Technology noted that it is possible for a Type 2 PD to
receive a false indication of a 2-event classiﬁcation if a PSE
port is pre-charged to a voltage above the detection voltage
range before the ﬁrst detection cycle. The IEEE working
group modiﬁed the standard to prevent this possibility by
requiring a Type 2 PD to corrupt the signature resistance
during the mark event, alerting the PSE not to apply power.
The LTC4269-1 conforms to this standard by corrupting
the signature resistance. This also discharges the port
before the PSE begins the next detection cycle.
42691 F04
The LTC4269-1 also maintains a positive I-V slope throughout the classiﬁcation range up to the on-voltage. In the
event a PSE overshoots beyond the classiﬁcation voltage
range, the available load current aids in returning the PD
back into the classiﬁcation voltage range. (The PD input
may otherwise be “trapped” by a reverse-biased diode
bridge and the voltage held by the 0.1μF capacitor).
INRUSH CURRENT
Once the PSE detects and optionally classiﬁes the PD,
the PSE then applies powers on the PD. When the
LTC4269-1 input voltage rises above the on-voltage
threshold, LTC4269-1 connects VNEG to VPORTN through
the internal power MOSFET.
42691fb
15
LTC4269-1
APPLICATIONS INFORMATION
To control the power-on surge currents in the system, the
LTC4269-1 provides a ﬁxed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
The LTC4269-1 keeps the PD inrush current below the
PSE current limit to provide a well controlled power-up
characteristic that is independent of the PSE behavior.
This ensures a PD using the LTC4269-1 interoperability
with any PSE.
TURN-ON/ TURN-OFF THRESHOLD
The IEEE 802.3af/at speciﬁcation for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This speciﬁcation provides an adequate
voltage to begin PD operation, and to discontinue PD operation when the input voltage is too low. In addition, this
speciﬁcation allows PD designs to incorporate an ON/OFF
hysteresis window to prevent start-up oscillations.
The LTC4269-1 features an ON/OFF hysteresis window (see
Figure 5) that conforms with the IEEE 802.3af/at speciﬁcation and accommodates the voltage drop in the cable and
input diode bridge at the onset of the inrush current.
does not fall below the OFF threshold. When the LTC4269-1
input voltage falls below the OFF threshold, the PD load
is disconnected, and classiﬁcation mode resumes. C1
discharges through the LTC4269-1 circuitry.
COMPLEMENTARY POWER GOOD
When LTC4269-1 fully charges the load capacitor (C1),
power good is declared and the LTC4269-1 load can safely
begin operation. The LTC4269-1 provides complementary
power good signals that remain active during normal operation and are de-asserted when the input voltage falls
below the OFF threshold, when the input voltage exceeds
the overvoltage lockout (OVLO) threshold, or in the event
of a thermal shutdown (see Figure 6).
The PWRGD pin features an open collector output referenced to VNEG which can interface directly with the UVLO
pin. When power good is declared and active, the PWRGD
pin is high impedance with respect to VNEG. An internal
14V clamp limits the PWRGD pin voltage. Connecting the
PWRGD pin to the UVLO prevents the DC/DC converter
LTC4269-1
Once C1 is fully charged, the LTC4269-1 turns on is internal
MOSFET and passes power to the PD load. The LTC4269-1
continues to power the PD load as long as the input voltage
LTC4269-1
TO
PSE
VPORTP
+
C1
5μF
MIN
PD
LOAD
ON/OFF AND
OVERVOLTAGE
LOCKOUT
CIRCUIT
VPORTN
30 PWRGD
OVLO
ON/OFF
TSD
CONTROL
CIRCUIT
29 PWRGD
VPORTN 5
27 VNEG
VPORTN 6
26 VNEG
BOLD LINE INDICATES HIGH CURRENT PATH
VNEG
VPORTP – VPORTN
LTC4269-1
VOLTAGE
POWER MOSFET
0V TO ON*
OFF
>ON*
ON
<OFF*
OFF
>OVLO
OFF
*INCLUDES ON/OFF HYSTERESIS
ON THRESHOLD 36.1V
OFF THRESHOLD 30.7V
OVLO THRESHOLD 71.0V
42691 F05
CURRENT-LIMITED
TURN ON
Figure 5. LTC4269-1 ON/OFF and Overvoltage Lockout
INRUSH COMPLETE
ON < VPORTP < OVLO
AND NOT IN THERMAL SHUTDOWN
POWER
NOT
GOOD
POWER
GOOD
VPORTP < OFF
VPORTP > OVLO
OR THERMAL SHUTDOWN
42691 F06
Figure 6. LTC4269-1 Power Good Functional and State Diagram
42691fb
16
LTC4269-1
APPLICATIONS INFORMATION
from commencing operation before the PD interface
completely charges the reservoir capacitor, C1.
The active low PWRGD pin connects to an internal, opendrain MOSFET referenced to VPORTN and may be used as an
indicator bit when power good is declared and active. The
PWRGD pin is low impedance with respect to VPORTN.
PWRGD PIN WHEN SHDN IS INVOKED
In PD applications where an auxiliary power supply invokes
the SHDN feature, the PWRGD pin becomes high impedance. This prevents the PWRGD pin that is connected to
the UVLO pin from interfering with the DC/DC converter
operations when powered by an auxiliary power supply.
OVERVOLTAGE LOCKOUT
The LTC4269-1 includes an overvoltage lockout (OVLO)
feature (Figure 6) which protects the LTC4269-1 and its
load from an overvoltage event. If the input voltage exceeds the OVLO threshold, the LTC4269-1 discontinues
PD operation. Normal operations resume when the input
voltage falls below the OVLO threshold and when C1 is
charged up.
THERMAL PROTECTION
The IEEE 802.3af/at speciﬁcation requires a PD to withstand
any applied voltage from 0V to 57V indeﬁnitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
During classiﬁcation, excessive heating may occur if the
PSE exceeds the 75ms probing time limit. At turn-on, when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
The LTC4269-1 includes a thermal protection feature
which protects the LTC4269-1 from excessive heating.
If the LTC4269-1 junction temperature exceeds the overtemperature threshold, the LTC4269-1 discontinues PD
operations and power good becomes inactive. Normal
operation resumes when the junction temperature falls
below the overtemperature threshold and when C1 is
charged up.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
isolation transformer must also include a center tap on
the RJ45 connector side (see Figure 7).
The increased current levels in a Type 2 PD over a Type 1
increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
provide correct impedance matching and to avoid radiated
and conducted emissions. Transformer vendors such as
Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
Table 4. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
Halo Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
PCA Electronics
16799 Schoenborn Street
North Hills, CA 91343
Tel: 818-892-0761
www.pca.com
Pulse Engineering
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
Tyco Electronics
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
42691fb
17
LTC4269-1
APPLICATIONS INFORMATION
Input Diode Bridge
Figure 2 shows how two diode bridges are typically connected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4269-1 supports the use of either silicon or
Schottky input diode bridges. However, there are trade-offs
in the choice of diode bridges.
An input diode bridge must be rated above the maximum
current the PD application will encounter at the temperature the PD will operate. Diode bridge vendors typically
call out the operating current at room temperature, but
derate the maximum current with increasing temperature.
Consult the diode bridge vendors for the operating current
derating curve.
A silicon diode bridge can consume over 4% of the available
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
A Schottky bridge may not be suitable for some high
temperature PD application. The leakage current has a
voltage dependency that can reduce the perceived signature
resistance. In addition, the IEEE 802.3af/at speciﬁcation
mandates the leakage back-feeding through the unused
RJ45
1
2
3
6
4
TX+
8
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drastically derated. The larger package may not be acceptable in some space-limited environments.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This conﬁguration extends the maximum
operating current while maintaining a smaller package
proﬁle. Figure 7 shows how to reconnect the two diode
bridges. Consult the diode bridge vendors for the derating
curve when only one of four diodes is in operation.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1μF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement.
14 T1 1
TX–
RX+
RX–
12
3
13
10
2
5
11
4
9
6
BR1
HD01
TO PHY
COILCRAFT
ETHI - 230LD
SPARE+
5
7
bridge cannot generate more than 2.8V across a 100k
resistor when a PD is powered with 57V.
SPARE –
VPORTP
BR2
HD01
C14
0.1μF
100V
D3
SMAJ58A
TVS
LTC4269-1
C1
VPORTN VNEG
42691 F07
Figure 7. PD Front-End with Isolation Transformer, Diode Bridges,
Capacitors, and a Transient Voltage Suppressor (TVS).
42691fb
18
LTC4269-1
APPLICATIONS INFORMATION
Transient Voltage Suppressor
T2P Interface
The LTC4269-1 speciﬁes an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4269-1, install a transient voltage suppressor (D3)
between the input diode bridge and the LTC4269-1 as
shown in Figure 7.
When a 2-event classiﬁcation sequence successfully
completes, the LTC4269-1 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-1 load,
or to leave the pin unconnected.
Classiﬁcation Resistor (RCLASS)
The RCLASS resistor sets the classiﬁcation load current,
corresponding to the PD power classiﬁcation. Select the
value of RCLASS from Table 2 and connect the resistor
between the RCLASS and VPORTN pins as shown in Figure
4, or ﬂoat the RCLASS pin if the classiﬁcation load current is not required. The resistor tolerance must be 1%
or better to avoid degrading the overall accuracy of the
classiﬁcation circuit.
Figure 8 shows two interface options using the T2P
pin and the opto-isolator. The T2P pin is active low and
connects to an opto-isolator to communicate across the
DC/DC converter isolation barrier. The pull-up resistor RP
is sized according to the requirements of the opto-isolator operating current, the pull-down capability of the T2P
pin, and the choice of V+. V+ for example can come from
the PoE supply rail (which the LTC4269-1 VPORTP is tied
to), or from the voltage source that supplies power to
the DC/DC converter. Option 1 has the advantage of not
drawing power unless T2P is declared active.
Load Capacitor
The IEEE 802.3af/at speciﬁcation requires that the PD
maintains a minimum load capacitance of 5μF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store signiﬁcant energy when fully
charged. The PD design must ensure that this energy is not
inadvertently dissipated in the LTC4269-1. For example,
if the VPORTP pin shorts to VPORTN while the capacitor
is charged, current will ﬂow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
VPORTP
TO
PSE
V+
RP
LTC4269-1
TO PD LOAD
–54V
VPORTN
T2P
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
V+
VPORTP
LTC4269-1
T2P
TO
PSE
RP
TO PD LOAD
–54V
VPORTN
VNEG
42691 F08
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
Figure 8. T2P Interface Examples
42691fb
19
LTC4269-1
APPLICATIONS INFORMATION
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to VPORTN. If unused, connect
SHDN directly to VPORTN.
provides a seamless transition from PoE to auxiliary power
when auxiliary power is applied, however, the removal of
auxiliary power to PoE power is not seamless.
Auxiliary Power Source
Contact Linear Technology applications support for detail
information on implementing a custom auxiliary power
supply.
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
Auxiliary power can be injected into an LTC4269-1-based
PD at the input of the LTC4269-1 VPORTN , at VNEG, or even
the power supply output. In addition, some PD application
may desire auxiliary supply dominance or may be conﬁgured for PoE dominance. Furthermore, PD applications
may also opt for a seamless transition — that is, without
power disruption — between PoE and auxiliary power.
The most common auxiliary power option injects power at
VNEG. Figure 9 presents an example of this application. In
this example, the auxiliary port injects 48V onto the line via
diode D1. The components surrounding the SHDN pin are
selected so that the LTC4269-1 does not disconnect power
to the output until the auxiliary supply exceeds 36V.
This conﬁguration is an auxiliary-dominant conﬁguration.
That is, the auxiliary power source supplies the power even
if PoE power is already present. This conﬁguration also
RJ45
1
TX+
3
6
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically draw
at least 10mA and also have an AC impedance less than
26.25k in parallel with 0.05μF. If one of these conditions
is not met, the PSE may disconnect power to the PD.
T1
+
–
2
Under the IEEE 802.3at standard, a PD must operate
under 12.95W in accordance with IEEE 802.3at standard
until it recognizes a Type 2 PSE. Initializing PD operation
in 12.95W mode eliminates interoperability issue in case
a Type 2 PD connects to a Type 1 PSE. Once the PD recognizes a Type 2 PSE, the IEEE 802.3at standard requires
the PD to wait 80ms in 12.95W operation before 25.5W
operation can commence.
TX
RX+
TO PHY
TVS
0.1μF
100V
C1
BR1
–
RX–
36V
VPORTP
100k
4
SPARE
+
+
5
7
8
BR2
SPARE–
SHDN
GND
10k
–
ISOLATED
WALL
TRANSFORMER
LTC4269-1
10k
VPORTN VNEG
+
D1
–
42691 F09
Figure 9. Auxiliary Power Dominant PD Interface Example
42691fb
20
LTC4269-1
APPLICATIONS INFORMATION
SWITCHING REGULATOR OVERVIEW
The LTC4269-1 includes a current mode converter designed
speciﬁcally for use in an isolated ﬂyback topology employing
synchronous rectiﬁcation. The LTC4269-1 operation is
similar to traditional current mode switchers. The major
difference is that output voltage feedback is derived via
sensing the output voltage through the transformer. This
precludes the need of an opto-isolator in isolated designs,
thus greatly improving dynamic response and reliability.
The LTC4269-1 has a unique feedback ampliﬁer that
samples a transformer winding voltage during the ﬂyback
period and uses that voltage to control output voltage.
The internal blocks are similar to many current mode
controllers. The differences lie in the feedback ampliﬁer and
load compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
ﬂyback control. For more information on the basics of
current mode switcher/controllers and isolated ﬂyback
converters see Application Note 19.
Feedback Ampliﬁer—Pseudo DC Theory
For the following discussion, refer to the simpliﬁed
Switching Regulator Feedback Ampliﬁer diagram (Figure
10A). When the primary-side MOSFET switch MP turns off,
its drain voltage rises above the VPORTP rail. Flyback occurs
when the primary MOSFET is off and the synchronous
secondary MOSFET is on. During ﬂyback the voltage on
nondriven transformer pins is determined by the secondary
voltage. The amplitude of this ﬂyback pulse, as seen on
the third winding, is given as:
VFLBK =
(
VOUT +ISEC • ESR + RDS(ON)
NSF
)
RDS(ON) = on-resistance of the synchronous MOSFET MS
ISEC = transformer secondary current
ESR = impedance of secondary circuit capacitor, winding
and traces
NSF = transformer effective secondary-to-ﬂyback winding
turns ratio (i.e., NS/NFLBK)
The ﬂyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
ampliﬁer compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
ampliﬁer whose output is connected to VCMP only during
a period in the ﬂyback time. An external capacitor on
the VCMP pin integrates the net feedback amp current to
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference VFB because of the high gain in
the overall loop. The relationship between VFLBK and VFB
is expressed as:
VFLBK =
R1+ R2
• VFB
R2
Combining this with the previous VFLBK expression yields
an expression for VOUT in terms of the internal reference,
programming resistors and secondary resistances:
(
⎞
⎛ R1+ R2
VOUT = ⎜
• VFB • NSF ⎟ −ISEC • ESR + RDS(ON)
⎠
⎝ R2
)
The effect of nonzero secondary output impedance is
discussed in further detail (see Load Compensation
Theory). The practical aspects of applying this equation for
VOUT are found in subsequent sections of the Applications
Information.
Feedback Ampliﬁer Dynamic Theory
So far, this has been a pseudo-DC treatment of ﬂyback
feedback ampliﬁer operation. But the ﬂyback signal is a
pulse, not a DC level. Provision is made to turn on the
ﬂyback ampliﬁer only when the ﬂyback pulse is present,
using the enable signal as shown in the timing diagram
(Figure 10b).
Minimum Output Switch On Time (tON(MIN))
The LTC4269-1 affects output voltage regulation via
ﬂyback pulse action. If the output switch is not turned on,
there is no ﬂyback pulse and output voltage information
is not available. This causes irregular loop response and
start-up/latchup problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
feedback is blanked each cycle for tON(MIN). If the output load
is less than that developed under these conditions, forced
continuous operation normally occurs. See subsequent
discussions in the Applications Information section for
further details.
42691fb
21
LTC4269-1
APPLICATIONS INFORMATION
T1
VFLBK
FLYBACK
LTC4269-1 FEEDBACK AMP
R1
16
FB
–
1V
VFB
1.237V
R2
•
VCMP
17
+
CVCMP
VIN
•
PRIMARY
SECONDARY
+
•
+
COUT
ISOLATED
OUTPUT
MP
–
COLLAPSE
DETECT
MS
R
ENABLE
S
Q
42691 F10a
Figure 10a. LTC4269-1 Switching Regulator Feedback Ampliﬁer
PRIMARY-SIDE
MOSFET DRAIN
VOLTAGE
VFLBK
0.8 • VFLBK
VIN
PG VOLTAGE
SG VOLTAGE
42691 F10b
tON(MIN)
MIN ENABLE
ENABLE
DELAY
PG DELAY
FEEDBACK
AMPLIFIER
ENABLED
Figure 10b. LTC4269-1 Switching Regulator Timing Diagram
42691fb
22
LTC4269-1
APPLICATIONS INFORMATION
Enable Delay Time (ENDLY)
Load Compensation Theory
The ﬂyback pulse appears when the primary-side switch
shuts off. However, it takes a ﬁnite time until the transformer
primary-side voltage waveform represents the output
voltage. This is partly due to rise time on the primaryside MOSFET drain node, but, more importantly, is due
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
output voltage. Some time is also required for internal
settling of the feedback ampliﬁer circuitry. In order to
maintain immunity to these phenomena, a ﬁxed delay is
introduced between the switch turn-off command and the
enabling of the feedback ampliﬁer. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufﬁciently settled by the end of the enable delay period,
regulation error may result. See the subsequent sections
for further details.
The LTC4269-1 uses the flyback pulse to obtain
information about the isolated output voltage. An error
source is caused by transformer secondary current ﬂow
through the synchronous MOSFET RDS(ON) and real life
nonzero impedances of the transformer secondary and
output capacitor. This was represented previously by the
expression, ISEC • (ESR + RDS(ON)). However, it is generally
more useful to convert this expression to effective output
impedance. Because the secondary current only ﬂows
during the off portion of the duty cycle (DC), the effective
output impedance equals the lumped secondary impedance
divided by off time DC.
Collapse Detect
where:
Once the feedback ampliﬁer is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the ﬂyback
voltage (FB) to a ﬁxed reference, nominally 80% of VFB.
When the ﬂyback waveform drops below this level, the
feedback ampliﬁer is disabled.
Minimum Enable Time
The feedback ampliﬁer, once enabled, stays on for a ﬁxed
minimum time period, termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low, e.g., during start-up. The minimum
enable time period ensures that the VCMP node is able to
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback ampliﬁer is enabled during only a portion of
the cycle time. This can vary from the ﬁxed minimum enable
time described to a maximum of roughly the off switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and VCMP node slew rate.
Since the off-time duty cycle is equal to 1 – DC, then:
RS(OUT) =
ESR + RDS(ON)
1− DC
RS(OUT) = effective supply output impedance
DC = duty cycle
RDS(ON) and ESR are as deﬁned previously
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases, the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 11 shows the block diagram of the load
compensation function. Switch current is converted to a
voltage by the external sense resistor, averaged and lowpass
ﬁltered by the internal 50k resistor RCMPF and the external
capacitor on CCMP. This voltage is impressed across the
external RCMP resistor by op amp A1 and transistor Q3
producing a current at the collector of Q3 that is subtracted
from the FB node. This effectively increases the voltage
required at the top of the R1/R2 feedback divider to achieve
equilibrium.
The average primary-side switch current increases to
maintain output voltage regulation as output loading
increases. The increase in average current increases RCMP
resistor current which affects a corresponding increase
42691fb
23
LTC4269-1
APPLICATIONS INFORMATION
in sensed output voltage, compensating for the IR drops.
Assuming relatively ﬁxed power supply efﬁciency, Eff,
power balance gives:
K1•
POUT = Eff • PIN
VOUT • IOUT = Eff • VIN • IIN
Average primary-side current is expressed in terms of
output current as follows:
IIN = K1•IOUT
where:
ESR + RDS(ON)
RSENSE
• R1• NSF =
RCMP
1− DC
Solving for RCMP gives:
RCMP = K1•
RSENSE • (1− DC)
• R1• NSF
ESR + RDS(ON)
The practical aspects of applying this equation to determine
an appropriate value for the RCMP resistor are discussed
subsequently in the Applications Information section.
V
K1= OUT
VIN • Eff
So, the effective change in VOUT target is:
ΔVOUT = K1•
Nominal output impedance cancellation is obtained by
equating this expression with RS(OUT):
Transformer Design
RSENSE
• R1• NSF • ΔIOUT
RCMP
Transformer design/speciﬁcation is the most critical part of
a successful application of the LTC4269-1. The following
sections provide basic information about designing the
transformer and potential trade-offs. If you need help, the
LTC Applications group is available to assist in the choice
and/or design of the transformer.
thus:
ΔVOUT
R
= K1• SENSE • R1• NSF
ΔIOUT
RCMP
where:
Turns Ratios
K1 = dimensionless variable related to VIN, VOUT and efﬁciency, as previously explained
The design of the transformer starts with determining
duty cycle (DC). DC impacts the current and voltage stress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
RSENSE = external sense resistor
VFLBK
R1
FB
Q1 Q2
16
LOAD
COMP I
•
•
MP
+
Q3
A1
–
22 RCMP
VOUT 1− DC
•
VIN
DC
VFB
VIN
R2
N IDEAL =
•
RCMPF
+
50k SENSE
20
21 CCMP
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
RSENSE
42691 F11
Figure 11. Load Compensation Diagram
Avoid extreme duty cycles, as they generally increase current stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
N IDEAL =
5 1− 0.5 1
•
=
48 0.5
9.6
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio.
42691fb
24
LTC4269-1
APPLICATIONS INFORMATION
Note the use of the external feedback resistive divider
ratio to set output voltage provides the user additional
freedom in selecting a suitable transformer turns ratio.
Turns ratios that are the simple ratios of small integers;
e.g., 1:1, 2:1, 3:2 help facilitate transformer construction
and improve performance.
When building a supply with multiple outputs derived
through a multiple winding transformer, lower duty cycle
can improve cross regulation by keeping the synchronous
rectiﬁer on longer, and thus, keep secondary windings
coupled longer. For a multiple output transformer, the turns
ratio between output windings is critical and affects the
accuracy of the voltages. The ratio between two output
voltages is set with the formula VOUT2 = VOUT1 • N21 where
N21 is the turns ratio between the two windings. Also
keep the secondary MOSFET RDS(ON) small to improve
cross regulation.
The feedback winding usually provides both the feedback
voltage and power for the LTC4269-1. Set the turns ratio
between the output and feedback winding to provide a
rectiﬁed voltage that under worst-case conditions is greater
than the 11V maximum VCC turn-off voltage.
NSF >
VOUT
11+ VF
where:
VF = Diode Forward Voltage
For our example: NSF >
We will choose
5
1
=
11+ 0.7 2.34
1
3
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary-side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
ﬂyback voltage may break down the MOSFET switch if it
has too low a BVDSS rating.
One solution to reducing this spike is to use a clamp circuit
to suppress the voltage excursion. However, suppressing
the voltage extends the ﬂyback pulse width. If the ﬂyback
pulse extends beyond the enable delay time, output
voltage regulation is affected. The feedback system has a
deliberately limited input range, roughly ±50mV referred
to the FB node. This rejects higher voltage leakage spikes
because once a leakage spike is several volts in amplitude,
a further increase in amplitude has little effect on the
feedback system. Therefore, it is advisable to arrange the
clamp circuit to clamp at as high a voltage as possible,
observing MOSFET breakdown, such that leakage spike
duration is as short as possible. Application Note 19
provides a good reference on clamp design.
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a clamp, but
exhibit little to no regulation error due to leakage spike
behavior. Inductances from several percent up to, perhaps,
ten percent, cause increasing regulation error.
Avoid double digit percentage leakage inductances. There
is a potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leakage
spike becomes such a large portion of the ﬂyback waveform
that the processing circuitry is fooled into thinking that the
leakage spike itself is the real ﬂyback signal!
It then reverts to a potentially stable state whereby the
top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This typically reduces the output voltage
abruptly to a fraction, roughly one-third to two-thirds of
its correct value.
Once load current is reduced sufﬁciently, the system snaps
back to normal operation. When using transformers with
considerable leakage inductance, exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This is usually evident
by simultaneously viewing the primary-side MOSFET drain
voltage to observe ﬁrsthand the leakage spike behavior.
42691fb
25
LTC4269-1
APPLICATIONS INFORMATION
A ﬁnal note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I = V/R
behavior—is the most apt to be bistable. Capacitive loads
that exhibit I = V2/R behavior are less susceptible.
Ripple current and percentage ripple is largest at minimum
duty cycle; in other words, at the highest input voltage.
LP is calculated from the following equation.
LP
2
2
VIN(MAX) • DCMIN )
VIN(MAX) • DCMIN ) • Eff
(
(
=
=
fOSC • XMAX • PIN
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the ﬂyback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior, this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
Winding Resistance Effects
Primary or secondary winding resistance acts to reduce
overall efﬁciency (POUT/PIN). Secondary winding resistance
increases effective output impedance, degrading load regulation. Load compensation can mitigate this to some extent
but a good design keeps parasitic resistances low.
Biﬁlar Winding
A biﬁlar, or similar winding, is a good way to minimize
troublesome leakage inductances. Biﬁlar windings also
improve coupling coefﬁcients, and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so is not always practical.
Primary Inductance
The transformer primary inductance, LP, is selected
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value. As a general
rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to
0.4). Higher values of ripple will increase conduction losses,
while lower values will require larger cores.
fOSC • XMAX • POUT
where:
fOSC is the oscillator frequency
DCMIN is the DC at maximum input voltage
XMAX is ripple current ratio at maximum input voltage
Using common high power PoE values, a 48V (41V < VIN
< 57V) to 5V/5.3A converter with 90% efﬁciency, POUT=
26.5W and PIN = 29.5W. Using X = 0.4 N = 1/8 and fOSC
= 200kHz:
DCMIN =
1+
LP =
1
=
N • VIN(MAX)
VOUT
(57V • 0.412)2
200kHz • 0.4 • 26.5W
1
= 41.2%
1 57
1+ •
8 5
= 260µH
Optimization might show that a more efﬁcient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at trade-offs.
Transformer Core Selection
Once LP is known, the type of transformer is selected. High
efﬁciency converters use ferrite cores to minimize core
loss. Actual core loss is independent of core size for a ﬁxed
inductance, but decreases as inductance increases. Since
increased inductance is accomplished through more turns
of wire, copper losses increase. Thus, transformer design
balances core and copper losses. Remember that increased
winding resistance will degrade cross regulation and
increase the amount of load compensation required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
when the peak design current is exceeded. This results
42691fb
26
LTC4269-1
APPLICATIONS INFORMATION
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
at minimum VIN:
PIN
⎛ X
⎞
• ⎜ 1+ MIN ⎟
VIN(MIN) • DCMAX ⎝
2 ⎠
IPK =
1+
XMIN
1
=
N • VIN(MIN )
VOUT
1
= 49.4%
1 41
1+ •
8 5
2
VIN(MIN) • DCMAX )
(
=
=
fOSC • LP • PIN
( 41• 49.4%)2
200kHz • 260µH • 29.5W
= 0.267
Using the example numbers leads to:
IPK =
29.5W ⎛ 0.267 ⎞
• ⎜ 1+
⎟ = 1.65A
41• 0.494 ⎝
2 ⎠
Multiple Outputs
One advantage that the ﬂyback topology offers is that
additional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the ﬂyback winding signal is a combination of
activity on all the secondary windings. Thus load regulation
is affected by each winding’s load. Take care to minimize
cross regulation effects.
Setting Feedback Resistive Divider
The expression for VOUT developed in the Operation section
is rearranged to yield the following expression for the
feedback resistors:
(
⎛ 5 + 5.3 • 0.008 ⎞
R1= 3.32k ⎜
− 1⎟ = 37.28k
⎝ 1.237 • 1/ 3
⎠
choose 37.4k.
now :
DCMAX =
Continuing the example, if ESR + RDS(ON) = 8mΩ, R2 =
3.32k, then:
)
⎛ ⎡V
⎤ ⎞
OUT +ISEC • ESR + RDS(ON) ⎦
⎣
⎜
R1= R2
− 1⎟
VFB • NSF
⎜⎝
⎟⎠
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
Current Sense Resistor Considerations
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane connected
with wide and short traces keeps stray resistance and
inductance low.
The dual sense pins allow for a full Kelvin connection. Make
sure that SENSE+ and SENSE– are isolated and connect
close to the sense resistor.
Peak current occurs at 100mV of sense voltage VSENSE. So
the nominal sense resistor is VSENSE/IPK. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010Ω Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
Size RSENSE using worst-case conditions, minimum LP,
VSENSE and maximum VIN. Continuing the example, let us
assume that our worst-case conditions yield an IPK of 40%
above nominal, so IPK = 2.3A. If there is a 10% tolerance
on RSENSE and minimum VSENSE = 88mV, then RSENSE •
110% = 88mV/2.3A and nominal RSENSE = 35mΩ. Round
to the nearest available lower value, 33mΩ.
42691fb
27
LTC4269-1
APPLICATIONS INFORMATION
Selecting the Load Compensation Resistor
The expression for RCMP was derived in the Operation
section as:
RCMP = K1•
RSENSE • (1− DC)
• R1• NSF
ESR + RDS(ON)
Continuing the example:
⎛ V
⎞
5
K1= ⎜ OUT ⎟ =
= 0.116
⎝ VIN • Eff ⎠ 48 • 90%
DC=
1+
1
=
N•VIN(NOM)
VOUT
1
= 45.5%
1 48
1+ •
8 5
If ESR + RDS(ON) = 8mΩ
RCMP = 0.116 •
33mΩ • (1− 0.455)
1
• 37.4kΩ •
8mΩ
3
= 3.25k
This value for RCMP is a good starting point, but empirical
methods are required for producing the best results.
This is because several of the required input variables
are difﬁcult to estimate precisely. For instance, the ESR
term above includes that of the transformer secondary,
but its effective ESR value depends on high frequency
behavior, not simply DC winding resistance. Similarly, K1
appears as a simple ratio of VIN to VOUT times efﬁciency,
but theoretically estimating efﬁciency is not a simple
calculation.
4. Compute:
RCMP = K1•
5. Verify this result by connecting a resistor of this value
from the RCMP pin to ground.
6. Disconnect the ground short to CCMP and connect a 0.1μF
ﬁlter capacitor to ground. Measure the output impedance RS(OUT) = ΔVOUT/ΔIOUT with the new compensation
in place. RS(OUT) should have decreased signiﬁcantly.
Fine tuning is accomplished experimentally by slightly
altering RCMP. A revised estimate for RCMP is:
⎛ RS(OUT)CMP ⎞
RCMP
′ = RCMP • ⎜ 1+
RS(OUT) ⎟⎠
⎝
where R′CMP is the new value for the load compensation
resistor. RS(OUT)CMP is the output impedance with RCMP
in place and RS(OUT) is the output impedance with no
load compensation (from step 2).
Setting Frequency
The switching frequency of the LTC4269-1 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 12 shows the nominal relationship between
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
300
1. Build a prototype of the desired supply including the
actual secondary components.
200
fOSC (kHz)
The suggested empirical method is as follows:
2. Temporarily ground the CCMP pin to disable the load
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line.
RSENSE
• R1• NSF
RS(OUT)
100
ΔVOUT/ΔIOUT = RS(OUT) .
3. Calculate a value for the K1 constant based on VIN, VOUT
and the measured efﬁciency.
50
30
100
COSC (pF)
200
42691 F12
Figure 12. fOSC vs OSC Capacitor Values
42691fb
28
LTC4269-1
APPLICATIONS INFORMATION
trace length and area to minimize stray capacitance and
potential noise pick-up.
You can synchronize the oscillator frequency to an
external frequency. This is done with a signal on the SYNC
pin. Set the LTC4269-1 frequency 10% slower than the
desired external frequency using the OSC pin capacitor,
then use a pulse on the SYNC pin of amplitude greater
than 2V and with the desired frequency. The rising edge
of the SYNC signal initiates an OSC capacitor discharge
forcing primary MOSFET off (PG voltage goes low). If
the oscillator frequency is much different from the sync
frequency, problems may occur with slope compensation
and system stability. Also, keep the sync pulse width
greater than 500ns.
Selecting Timing Resistors
There are three internal “one-shot” times that are
programmed by external application resistors: minimum
on-time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated ﬂyback control
technique, and their functions are previously outlined in
the Theory of Operation section. The following information
should help in selecting and/or optimizing these timing
values.
Minimum Output Switch On-Time (tON(MIN))
Minimum on-time is the programmable period during which
current limit is blanked (ignored) after the turn-on of the
primary-side switch. This improves regulator performance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
both the gate/source charging current and the discharge
of drain capacitance. The isolated ﬂyback sensing requires
a pulse to sense the output. Minimum on-time ensures
that the output switch is always on a minimum time and
that there is always a signal to close the loop.
The tON(MIN) resistor is set with the following equation
R tON(MIN) (kΩ ) =
tON(MIN) (ns ) − 104
1.063
Keep RtON(MIN) greater than 70k. A good starting value
is 160k.
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback ampliﬁer. As discussed earlier,
this delay allows the feedback ampliﬁer to ignore the
leakage inductance voltage spike on the primary side.
The worst-case leakage spike pulse width is at maximum
load conditions. So, set the enable delay time at these
conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondaryside controller might cause discontinuous operation at
light loads. Under such conditions, the amount of energy
stored in the transformer is small. The ﬂyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the ﬂyback waveform at light loads.
Even though the LTC4269-1 has a robust gate drive, the gate
transition time slows with very large MOSFETs. Increase
delay time as required when using such MOSFETs.
The enable delay resistor is set with the following
equation:
RENDLY (kΩ ) =
tENDLY (ns) − 30
2.616
Keep RENDLY greater than 40k. A good starting point is
56k.
The LTC4269-1 does not employ cycle skipping at light
loads. Therefore, minimum on-time along with synchronous rectiﬁcation sets the switch over to forced continuous
mode operation.
42691fb
29
LTC4269-1
APPLICATIONS INFORMATION
Primary Gate Delay Time (PGDLY)
Switcher’s UVLO Pin Function
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
between the primary-side switch and secondary-side synchronous switch(es) and the subsequent current spike in
the transformer. This spike will cause additional component
stress and a loss in regulator efﬁciency.
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on VIN. The gate drivers are disabled when
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The primary gate delay resistor is set with the following
equation:
RPGDLY (kΩ ) =
tPGDLY (ns) + 47
9.01
A good starting point is 15k.
Soft-Start Function
The LTC4269-1 contains an optional soft-start function that
is enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the VCMP pin from exceeding that on the SFST
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20μA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when VCC is too low (undervoltage lockout),
current sense voltage is greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the VCMP node voltage is also pulled low
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
The bias current on this pin depends on the pin voltage and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 13, the voltage hysteresis at VIN is
equal to the change in bias current times RA. The design
procedure is to select the desired VIN referred voltage
hysteresis, VUVHYS. Then:
RA =
VUVHYS
IUVLO
where:
IUVLO = IUVLOL – IUVLOH is approximately 3.4μA
RB is then selected with the desired turn-on voltage:
RB =
RA
⎛ VIN(ON) ⎞
– 1⎟
⎜⎝ V
⎠
UVLO
VIN
The time it takes to fully charge soft-start is:
• 1.4V
C
t SS = SFST
= 70kΩ • CSFST (µF )
20µA
IUVLO
VIN
IUVLO
RA1
VIN
RA2
RA
RB
UVLO
LTC4969-1
RA
RB
UVLO
LTC4969-1
CUVLO
UVLO
RB
42691 F13
(13a) UV Turning On
(13b) UV Turning Off
(13c) UV Filtering
Figure 13. UVLO Pin Function and Recommended Filtering
42691fb
30
LTC4269-1
APPLICATIONS INFORMATION
If we wanted a VIN-referred trip point of 36V, with 1.8V
(5%) of hysteresis (on at 36V, off at 34.2V):
1.8V
= 529k, use 523k
3.4µA
523k
= 18.5k, use 18.7k
RB =
⎛ 36V
⎞
– 1⎟
⎜⎝
1.23V ⎠
RA =
If CTR is undersized, VCC reaches the VCC turn-off threshold
before stabilization and the LTC4269-1 turns off. The VCC
node then begins to charge back up via RTR to the turn-on
threshold, where the part again turns on. Depending upon
the circuit, this may result in either several on-off cycles
before proper operation is reached, or permanent relaxation
oscillation at the VCC node.
VIN
Even with good board layout, board noise may cause
problems with UVLO. You can ﬁlter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 13c shows an alternate method of ﬁltering by splitting the RA resistor with the capacitor. The split should put
more of the resistance on the UVLO side.
RTR
•
VIN
+
•
CTR
IVCC
•
VCC
LTC4269-1
PG
GND
Converter Start-Up
The standard topology for the LTC4269-1 utilizes a third
transformer winding on the primary side that provides
both feedback information and local VCC power for the
LTC4269-1 (see Figure 14). This power bootstrapping
improves converter efﬁciency but is not inherently selfstarting. Start-up is affected with an external “trickle charge”
resistor and the LTC4269-1’s internal VCC undervoltage
lockout circuit. The VCC undervoltage lockout has wide
hysteresis to facilitate start-up.
In operation, the trickle charge resistor, RTR, is connected
to VIN and supplies a small current, typically on the order
of 1mA to charge CTR. Initially the LTC4269-1 is off and
draws only its start-up current. When CTR reaches the VCC
turn-on threshold voltage the LTC4269-1 turns on abruptly
and draws its normal supply current.
Switching action commences and the converter begins to
deliver power to the output. Initially the output voltage is
low and the ﬂyback voltage is also low, so CTR supplies
most of the LTC4269-1 current (only a fraction comes
from RTR.) VCC voltage continues to drop until, after
some time (typically tens of milliseconds) the output
voltage approaches its desired value. The ﬂyback winding
then provides the LTC4269-1 supply current and the VCC
voltage stabilizes.
VCC(ON) THRESHOLD
VVCC
IVCC
0
VPG
42691 F14
Figure 14. Typical Power Bootstrapping
RTR is selected to yield a worst-case minimum charging
current greater than the maximum rated LTC4269-1 start-up
current, and a worst-case maximum charging current less
than the minimum rated LTC4269-1 supply current.
R TR(MAX) <
VIN(MIN) − VCC(ON _ MAX)
ICC(ST _ MAX)
and
R TR(MIN) >
VIN(MAX) − VCC(ON _ MIN)
ICC(MIN)
Make CTR large enough to avoid the relaxation oscillatory
behavior described above. This is complicated to determine theoretically as it depends on the particulars of the
secondary circuit and load behavior. Empirical testing is
recommended. Note that the use of the optional soft-start
function lengthens the power-up timing and requires a
correspondingly larger value for CTR.
42691fb
31
LTC4269-1
APPLICATIONS INFORMATION
The LTC4269-1 has an internal clamp on VCC of approximately 19.5V. This provides some protection for the part
in the event that the switcher is off (UVLO low) and the
VCC node is pulled high. If RTR is sized correctly, the part
should never attain this clamp voltage.
Control Loop Compensation
Loop frequency compensation is performed by connecting a capacitor network from the output of the feedback
ampliﬁer (VCMP pin) to ground as shown in Figure 15.
Because of the sampling behavior of the feedback ampliﬁer,
compensation is different from traditional current mode
controllers. Normally only CVCMP is required. RVCMP can
be used to add a zero, but the phase margin improvement
traditionally offered by this extra resistor is usually already
accomplished by the nonzero secondary circuit impedance.
CVCMP2 can be used to add an additional high frequency
pole and is usually sized at 0.1 times CVCMP.
Slope Compensation
The LTC4269-1 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the DC is greater than 50%. In some switching
regulators, slope compensation reduces the maximum peak
current at higher duty cycles. The LTC4269-1 eliminates
this problem by having circuitry that compensates for
the slope compensation so that maximum current sense
voltage is constant across all duty cycles.
Minimum Load Considerations
At light loads, the LTC4269-1 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
tON(MIN) resistor. If this produces more power than the
load requires, power will ﬂow back into the primary during the off period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efﬁciency is reduced.
VCMP
17
CVCMP2
RVCMP
CVCMP
42691 F15
Figure 15. VCMP Compensation Network
In further contrast to traditional current mode switchers,
VCMP pin ripple is generally not an issue with the LTC4269-1.
The dynamic nature of the clamped feedback ampliﬁer
forms an effective track/hold type response, whereby the
VCMP voltage changes during the ﬂyback pulse, but is then
held during the subsequent switch-on portion of the next
cycle. This action naturally holds the VCMP voltage stable
during the current comparator sense action (current mode
switching).
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
Maximum Load Considerations
The current mode control uses the VCMP node voltage
and ampliﬁed sense resistor voltage as inputs to the
current comparator. When the ampliﬁed sense voltage
exceeds the VCMP node voltage, the primary-side switch
is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
VCMP reaches its 2.56V clamp. At clamp, the primary-side
MOSFET will turn off at the rated 100mV VSENSE level. This
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across RSENSE to exceed the max 100mV rating
because of the minimum switch on time blanking. If the
voltage on VSENSE exceeds 205mV after the minimum
turn-on time, the SFST capacitor is discharged, causing
the discharge of the VCMP capacitor. This then reduces
the peak current on the next cycle and will reduce overall
stress in the primary switch.
42691fb
32
LTC4269-1
APPLICATIONS INFORMATION
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhibited
by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is
DCMIN = tON(MIN) • fOSC <
(
ISC • RSEC + RDS(ON)
VIN • NSP
)
where:
tON(MIN) is the primary-side switch minimum on-time
ISC is the short-circuit output current
NSP is the secondary-to-primary turns ratio (NSEC/NPRI)
(other variables as previously deﬁned)
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
Output Voltage Error Sources
The LTC4269-1’s feedback sensing introduces additional
minor sources of errors. The following is a summary list:
• The internal bandgap voltage reference sets the reference
voltage for the feedback ampliﬁer. The speciﬁcations
detail its variation.
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
• The transformer secondary current ﬂows through the
impedances of the winding resistance, synchronous
MOSFET RDS(ON) and output capacitor ESR. The DC
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s off-time. So, divide the load current by
(1 – DC).
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LTC4269-1 load compensation circuitry
(see Load Compensation). If multiple output windings are
used, the ﬂyback winding will have a signal that represents
an amalgamation of all these windings impedances. Take
care that you examine worst-case loading conditions when
tweaking the voltages.
Power MOSFET Selection
The power MOSFETs are selected primarily on the criteria of
on-resistance RDS(ON), input capacitance, drain-to-source
breakdown voltage (BVDSS), maximum gate voltage (VGS)
and maximum drain current (ID(MAX)).
For the primary-side power MOSFET, the peak current is:
PIN
⎛ X
⎞
IPK(PRI) =
• ⎜ 1+ MIN ⎟
VIN(MIN) • DCMAX ⎝
2 ⎠
where XMIN is peak-to-peak current ratio as deﬁned
earlier.
For each secondary-side power MOSFET, the peak current is:
IOUT
⎛ X
⎞
IPK(SEC) =
• ⎜ 1+ MIN ⎟
⎝
1− DCMAX
2 ⎠
Select a primary-side power MOSFET with a BVDSS
greater than:
VOUT(MAX)
L
BVDSS ≥IPK LKG + VIN(MAX) +
CP
NSP
where NSP reﬂects the turns ratio of that secondary-to
primary winding. LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from
the drain capacitance (COSS) of the primary-side power
MOSFET). A clamp may be added to reduce the leakage
inductance as discussed.
42691fb
33
LTC4269-1
APPLICATIONS INFORMATION
For each secondary-side power MOSFET, the BVDSS should
be greater than:
PD(PRI) =IRMS(PRI)2 • RDS(ON) (1+ δ ) +
BVDSS ≥ VOUT + VIN(MAX) • NSP
Choose the primary-side MOSFET RDS(ON) at the nominal
gate drive voltage (7.5V). The secondary-side MOSFET gate
drive voltage depends on the gate drive method.
Primary-side power MOSFET RMS current is given by:
IRMS(PRI) =
PIN
VIN(MIN) DCMAX
VIN(MAX) •
PIN(MAX)
DCMIN
• RDR •
CMILLER
•f
VGATE(MAX) − VTH OSC
where:
RDR is the gate driver resistance (≈10Ω)
VTH is the MOSFET gate threshold voltage
For each secondary-side power MOSFET RMS current is
given by:
IRMS(SEC) =
With CMILLER determined, calculate the primary-side power
MOSFET power dissipation:
IOUT
1− DCMAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high VDS, a
transition power loss term is included for accuracy. CMILLER
is the most critical parameter in determining the transition
loss, but is not directly speciﬁed on the data sheets.
CMILLER is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 16).
fOSC is the operating frequency
VGATE(MAX) = 7.5V for this part
(1 + δ) is generally given for a MOSFET in the form of a
normalized RDS(ON) vs temperature curve. If you don’t
have a curve, use δ = 0.005/°C • ΔT for low voltage
MOSFETs.
The secondary-side power MOSFETs typically operate
at substantially lower VDS, so you can neglect transition
losses. The dissipation is calculated using:
PDIS(SEC) = IRMS(SEC)2 • RDS(ON)(1 + δ)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
TJ = TA + PDIS • θJA
MILLER EFFECT
VGS
a
where TA is the ambient temperature and θJA is the MOSFET
junction to ambient thermal resistance.
b
QA
QB
GATE CHARGE (QG)
42691 F16
Figure 16. Gate Charge Curve
The ﬂat portion of the curve is the result of the Miller (gate
to-drain) capacitance as the drain voltage drops. The Miller
capacitance is computed as:
CMILLER =
QB − Q A
VDS
The curve is done for a given VDS. The Miller capacitance
for different VDS voltages are estimated by multiplying the
computed CMILLER by the ratio of the application VDS to
the curve speciﬁed VDS.
Once you have TJ iterate your calculations recomputing
δ and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efﬁciency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer efﬁciency.
42691fb
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LTC4269-1
APPLICATIONS INFORMATION
The LTC4269-1 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
maximum VGS of 10V and larger.
IRMS(SEC) =IOUT
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchronous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary, as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate drivers
and secondary-side synchronous controllers available
that provide the buffer function as well as additional
features.
Capacitor Selection
In a ﬂyback converter, the input and output current ﬂows
in pulses, placing severe demands on the input and output
ﬁlter capacitors. The input and output ﬁlter capacitors
are selected based on RMS current ratings and ripple
voltage.
Select an input capacitor with a ripple current rating
greater than:
IRMS(PRI) =
PIN
1− DCMAX
DCMAX
VIN(MIN)
Continuing the example:
IRMS(PRI) =
29.5W
41V
capacitor should have an RMS current rating greater
than:
1− 49.4%
= 0.728A
49.4%
Keep input capacitor series resistance (ESR) and inductance
(ESL) small, as they affect electromagnetic interference
suppression. In some instances, high ESR can also
produce stability problems because ﬂyback converters
exhibit a negative input resistance characteristic. Refer
to Application Note 19 for more information.
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
DCMAX
1− DCMAX
Continuing the example:
IRMS(SEC) = 5.3A
49.4%
= 5.24A
1− 49.4%
This is calculated for each output in a multiple winding
application.
ESR and ESL along with bulk capacitance directly affect the
output voltage ripple. The waveforms for a typical ﬂyback
converter are illustrated in Figure 17.
IPRI
PRIMARY
CURRENT
IPRI
N
SECONDARY
CURRENT
RINGING
DUE TO ESL
ΔVCOUT
OUTPUT VOLTAGE
RIPPLE WAVEFORM
ΔVESR
42691 F17
Figure 17. Typical Flyback Converter Waveforms
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity, we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESRCOUT ≤ 1% •
VOUT • (1− DCMAX )
IOUT
42691fb
35
LTC4269-1
APPLICATIONS INFORMATION
The other 1% is due to the bulk C component, so use:
COUT ≥
IOUT
1% • VOUT • fOSC
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisﬁes the required bulk C.
Continuing our example, the output capacitor needs:
5V • (1− 49.4%)
= 4mΩ
5.3A
5.3A
COUT ≥
= 600µF
1% • 5 • 200kHz
ESRCOUT ≤ 1% •
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
One way to reduce cost and improve output ripple is to use a
simple LC ﬁlter. Figure 18 shows an example of the ﬁlter.
L1, 0.1μH
FROM
SECONDARY
WINDING
+
C1
47μF
s3
+
VOUT
COUT
470μF
COUT2
1μF
RLOAD
42691 F18
Figure 18.
The design of the ﬁlter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a COUT 1/4 the size of the nonﬁlter
solution. Make C1 1/4 of COUT to make the second ﬁlter
pole independent of COUT. C1 may be best implemented
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1μH ﬁlter inductor is sufﬁcient. Add a small ceramic
capacitor (COUT2) for high frequency noise on VOUT. For
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
Circuit simulation is a way to optimize output capacitance
and ﬁlters, just make sure to include the component
parasitic. LTC SwitcherCADTM is a terriﬁc free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
signiﬁcantly impact ripple. Refer to the PC Board Layout
section for more details.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4269-1 is speciﬁed to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily VPORTN and VPORTP)
can routinely see peak voltages in excess of 10kV. To
protect the LTC4269-1, it is highly recommended that the
SMAJ58A unidirectional 58V transient voltage suppressor
be installed between the diode bridge and the LTC4269-1
(D3 in Figure 2).
ISOLATION
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4269-1 or support circuitry
other than the RJ-45 port.
LAYOUT CONSIDERATIONS FOR THE LTC4269-1
The LTC4269-1’s PD front end is relatively immune to
layout problems. Excessive parasitic capacitance on the
RCLASS pin should be avoided. Include a PCB heat sink
to which the exposed pad on the bottom of the package
can be soldered. This heat sink should be electrically
connected to GND. For optimum thermal performance,
make the heat sink as large as possible. Voltages in a
PD can be as large as 57V for PoE applications, so high
voltage layout techniques should be employed. The SHDN
SwitcherCAD is a trademark of Linear Technology Corporation.
42691fb
36
LTC4269-1
APPLICATIONS INFORMATION
pin should be separated from other high voltage pins, like
VPORTP, VNEG, to avoid the possibility of leakage currents
shutting down the LTC4269-1. If not used, tie SHDN to
VPORTN. The load capacitor connected between VPORTP and
VNEG of the LTC4269-1 can store signiﬁcant energy when
fully charged. The design of a PD must ensure that this
energy is not inadvertently dissipated in the LTC4269-1.
The polarity-protection diodes prevent an accidental short
on the cable from causing damage. However if, VPORTN
is shorted to VPORTP inside the PD while capacitor C1
is charged, current will ﬂow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
Keep electric ﬁeld radiation low by minimizing the length
and area of traces (keep stray capacitances low). The drain
of the primary-side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes.
Check that the maximum BVDSS ratings of the MOSFETs
are not exceeded due to inductive ringing. This is done by
viewing the MOSFET node voltages with an oscilloscope. If
it is breaking down, either choose a higher voltage device,
add a snubber or specify an avalanche-rated MOSFET.
Place the small-signal components away from high frequency switching nodes. This allows the use of a pseudo-Kelvin
connection for the signal ground, where high di/dt gate
driver currents ﬂow out of the IC ground pin in one direction
(to the bottom plate of the VCC decoupling capacitor) and
small-signal currents ﬂow in the other direction.
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LTC4269-1
directly to the ground terminal of the VCC decoupling
capacitor, the bottom terminal of the current sense resistor
and the ground terminal of the input capacitor, using a
ground plane with multiple vias. Place the VCC capacitor
immediately adjacent to the VCC and GND pins on the IC
package. This capacitor carries high di/dt MOSFET gate
drive currents. Use a low ESR ceramic capacitor.
Keep the trace from the feedback divider tap to the FB pin
short to preclude inadvertent pick-up.
For applications with multiple switching power converters
connected to the same input supply, make sure that the
input ﬁlter capacitor for the LTC4269-1 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple which could
interfere with the LTC4269-1 operation. A few inches of PC
trace or wire (L ≅ 100nH) between the CIN of the LTC4269-1
and the actual source VIN, is sufﬁcient to prevent current
sharing problems.
Take care in PCB layout to keep the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. This reduces the parasitic inductance and
also minimizes magnetic ﬁeld radiation. Figure 19 outlines
the critical paths.
T1
VCC
VIN
CVCC
•
•
GATE
TURN-ON
VCC
•
+
PG
MP
CVIN
OUT
GATE
TURN-OFF
RSENSE
+
+
CR
VCC
VCC
Q4
T2
•
COUT
GATE
TURN-ON
MS
•
SG
Q3
GATE
TURN-OFF
42691 F19
Figure 19. Layout Critical High Current Paths
42691fb
37
38
54V FROM
SPARE PAIR
54V FROM
DATA PAIR
–
48V
AUX IN
+
B1100
s8
10k
107k
BSS63LT
36V
CMDZ
5258B
10k
0.1μF
100V
SMAJ58A
VPORTP
BAS21
S2B
30.9Ω
10μF
100V
4.7μH
15k
PGDLY
+
0.1μF
150k
OSC
R9
20k
VCC
ENDLY
2.1k
RCMP
LTC4269-1
22μF
16V
2.2μF
100V
SYNC
100k
tON
TO ISOLATED
SIDE VIA OPTO
T2P
RCLASS VPORTN VNEG
SHDN
UVLO
20k
1%
330k
1%
+
33pF
FB
680pF
SG
SENSE–
SENSE+
PG
1000pF
100V
10Ω
GND VCMP
0.1μF
3.01k
1%
29.4k
1%
CCMP
0.033μF
SFST
91Ω
BAS21
25W High Efﬁciency Triple Output PD Supply
10k
•
•
2200pF
42691 TA02
10k
15Ω
47μF
s2
0.33μH
47μF
0.33μH
1μF
47Ω
10Ω
10Ω
FMMT618
B0540W
220pF
1500pF
BAT54
FMMT718
Si4362DY
•
Si4488DY
•
Si4470EY
•
4700pF
PA0184
3300pF
0.1μF
330Ω
15mΩ
1%
Si4488DY
•
•
PA1558NL
+
+
100μF
3.3V
3A
12V
0.25A
22μF
s2
100μF
5V
2A
LTC4269-1
TYPICAL APPLICATIONS
42691fb
LTC4269-1
TYPICAL APPLICATIONS
PoE-Based 5V, 5A Power Supply
0.18μH
T1
•
+
+
–
47μF
•
VPORTP
5V
5A
C1
100μF
10μH
48V AUXILLIARY
POWER
+
B1100 s 8 PLCS
•
39k
2.2μF
10μF
150Ω
107k
36V
PDZ36B
54V FROM
DATA PAIR
10k
BSS63LT1
22pF
+
BAS21
1μF
10μF
27.4k
383k
5.1Ω
20Ω
FDS8880
S1B
BAS21
14.0k
1.5nF
3.01k
FDS2582
UVLO
PWRGD
FB
VCC
2.2nF
2kV
PG
SENSE+
VPORTP
33mΩ
SHDN
SMAJ58A
54V FROM
SPARE PAIR
0.1μF
100V
RCLASS
SENSE–
LTC4269-1
30.9Ω
MMBT3906
MMBT3904
SG
24k
100Ω
VPORTN
VNEG SYNC
T1: PCA ELECTRONICS, EPC3409G-LF
OR
PULSE, PA2369NL
T2: PULSE, PE-68386NL
C1: PSLB20J107M(45)
15Ω
1μF
GND
OSC
PGDLY
33pF
tON
T2
0.1μF
100k
12k
2.2nF
VCMP
ENDLY RCMP CCMP
38.3k
1.2k
10k
•
•
BAT54
1nF
10k
3.3nF
42691 TA03a
Efﬁciency
92
90
5.25
42VPORT
88
5.20
5.15
50VPORT
86
EFFICIENCY (%)
EFFICIENCY (%)
Regulation
84
82
80
78
50VPORT
42VPORT
5.05
5.00
57VPORT
4.95
4.90
76
74
5.10
4.85
57VPORT
72
0.5 1.0
4.80
4.75
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT CURRENT (A)
42691 TA03b
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT CURRENT (A)
42691 TA03c
42691fb
39
LTC4269-1
TYPICAL APPLICATIONS
PoE-Based 12V, 2A Power Supply
T1
•
0.33μH
VPORTP
+
–
+
10μH
48V AUXILLIARY
POWER
+
2.2μF
10μF
B1100 s 8 PLCS
36V
PDZ36B
10k
BSS63LT1
47pF
+
BAS21
1μF
22μF
29.4k
383k
15Ω
20Ω
BAS21
C1
47μF
150Ω
107k
54V FROM
DATA PAIR
10μF
•
•
20k
12V
2A
FDS3572
S1B
14.0k
470pF
3.01k
FDS2582
UVLO
PWRGD
FB
2.2nF
2kV
PG
VCC
SENSE+
VPORTP
33mΩ
SHDN
SMAJ58A
54V FROM
SPARE PAIR
0.1μF
100V
RCLASS
SENSE–
LTC4269-1
30.9Ω
MMBT3906
MMBT3904
SG
24k
100Ω
VPORTN
VNEG SYNC
15Ω
1μF
GND
OSC
PGDLY
tON
2.2nF
VCMP
ENDLY RCMP CCMP
T2
T1: PCA ELECTRONICS, EPC3410G-LF
OR
PULSE, PA2467NL
T2: PULSE, PE-68386NL
C1: PSLDIC476MH
33pF
0.1μF
100k
12k
38.3k
2.2k
10k
•
•
BAT54
1nF
10k
4.7nF
42691 TA04a
Efﬁciency
93
12.5
91
12.4
87
85
12.3
57VIN
42VIN
12.2
48VIN
VOUT (V)
89
EFFICIENCY (%)
Regulation
83
81
42VIN
12.0
57VIN
11.9
79
11.8
77
11.7
75
11.6
73
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
11.5
42691 TA04b
50VIN
12.1
0.2 0.38 0.56 0.74 0.92 1.1 1.3 1.5 1.6 1.8
LOAD CURRENT (A)
2
42691 TA04c
42691fb
40
LTC4269-1
TYPICAL APPLICATIONS
PoE-Based 3.3V, 7A Power Supply
0.18μH
T1
•
+
+
–
47μF
•
VPORTP
3.3V
7A
C1
100μF
10μH
48V AUXILLIARY
POWER
+
B1100 s 8 PLCS
•
20k
2.2μF
10μF
150Ω
107k
36V
PDZ36B
54V FROM
DATA PAIR
10k
BSS63LT1
22pF
+
BAS21
1μF
22μF
B0540W
29.4k
383k
5.1Ω
20Ω
FDS8670
S1B
BAS21
14.0k
2.2nF
3.01k
FDS2582
UVLO
PWRGD
FB
VCC
SENSE+
VPORTP
33mΩ
SHDN
SMAJ58A
54V FROM
SPARE PAIR
0.1μF
100V
47Ω
2.2nF
2kV
PG
RCLASS
SENSE–
LTC4269-1
30.9Ω
MMBT3906
MMBT3904
1μF
16V
SG
24k
100Ω
VPORTN
VNEG SYNC
15Ω
1μF
GND
OSC
PGDLY
tON
2.2nF
VCMP
ENDLY RCMP CCMP
T2
T1: PCA ELECTRONICS, EPC3408G-LF
OR
PULSE, PA2466NL
T2: PULSE, PE-68386NL
C1: PSLB20J107M(25)
33pF
0.1μF
100k
12k
38.3k
1k
5.1k
•
•
BAT54
2.2nF
10k
6.8nF
42691 TA05a
Efﬁciency
Regulation
91
3.45
37VIN
3.42
89
3.39
88
3.36
87
48VIN
VOUT (V)
EFFICIENCY (%)
90
86
85
84
57VIN
3.33
50VIN
42VIN
3.30
3.27
57VIN
3.24
83
3.21
82
3.18
81
0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0
LOAD CURRENT (A)
3.15
0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0
LOAD CURRENT (A)
42691 TA05b
42691 TA05c
42691fb
41
LTC4269-1
PACKAGE DESCRIPTION
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev A)
0.70 ± 0.05
4.50 ± 0.05
6.43 ±0.05
2.65 ±0.05
3.10 ± 0.05
PACKAGE
OUTLINE
0.20 ± 0.05
0.40 BSC
6.00 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
17
R = 0.115
TYP
32
R = 0.05
TYP
0.40 ± 0.10
6.43 ±0.10
4.00 ±0.10
2.65 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
16
0.75 ±0.05
0.40 BSC
1
6.00 REF
BOTTOM VIEW—EXPOSED PAD
0.200 REF
0.20 ± 0.05
(DKD32) QFN 0707 REV A
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
42691fb
42
LTC4269-1
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
04/10
Connected PWRGD Pin to UVLO Pin in Typical Application Circuit Drawings
Added Text Clarifying Connecting PWRGD Pin to UVLO Pin in Complementary Power Good Section of the
Applications Information Section
1, 39-41
16, 17
42691fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
43
LTC4269-1
RELATED PARTS
PART NUMBER
®
LT 1952
DESCRIPTION
COMMENTS
Single Switch Synchronous Forward Counter
Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current
TM
LTC3803-3
Current Mode Flyback DC/DC Controller in ThinSOT
300kHz Constant-Frequency, Adjustable Slope Compensation, Optimized
for High Input Voltage Applications
LTC3805
Adjustable Frequency Current Mode Flyback Controller
Slope Comp, Overcurrent Protect, Internal/External Clock
LTC3825
Isolated No-Opto Synchronous Flyback Controller with
Wide Input Supply Range
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Accurate Regulation without Trim, Synchronous for High Efﬁciency
LTC4257-1
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classiﬁcation, Dual
Current Limit
LTC4258
Quad IEEE 802.3af Power over Ethernet Controller
DC Disconnect Only, IEEE-Compliant PD Detection and Classiﬁcation,
Autonomous Operation or I2C Control
LTC4259A-1
Quad IEEE 802.3af Power over Ethernet Controller
AC or DC Disconnect, IEEE-Compliant PD Detection and Classiﬁcation,
Autonomous Operation or I2C Control
LTC4263
Single IEEE 802.3af Power over Ethernet Controller
AC or DC Disconnect, IEEE-Compliant PD Detection and Classiﬁcation,
Autonomous Operation
LTC4263-1
High Power Single PSE Controller
Internal Switch, Autonomous Operation, 30W
LTC4264
High Power PD Interface Controller with 750mA
Current Limit
750mA Internal Switch, Programmable Classiﬁcation Current to 75mA.
Precision Dual Current Limit with Disable.
LTC4265
IEEE 802.3at High Power PD Interface Controller with
2-Event Classiﬁcation
2-Event Classiﬁcation Recognition, 100mA Inrush Current, Single-Class
Programming Resistor, Full Compliance to 802.3at
LTC4266
IEEE 802.3at Quad PSE Controller
Supports IEEE 802.3at Type 1 and Type 2 PDs, 0.34Ω Channel Resistance,
Advanced Power Management, High Reliability 4-Point PD Detection,
Legacy Capacitance Detect
LTC4267-1
IEEE 802.3af PD Interface with an Integrated
Switching Regulator
100V 400mA Internal Switch, Programmable Classiﬁcation, 200kHz
Constant-Frequency PWM, Optimized for IEEE-Compliant PD System
LTC4267-3
IEEE 802.3af PD Interface with an Integrated
Switching Regulator
100V 400mA Internal Switch, Programmable Classiﬁcation, 300kHz
Constant-Frequency PWM, Optimized for IEEE-Compliant PD System
LTC4268-1
High Power PD with Synchronous No-Opto Flyback
Controller
IEEE 802.3af Compliant, 750mA Hot Swap FET, 92% Power Supply
Efﬁciency, Flexible Aux Support, Superior EMI
LTC4269-2
IEEE 802.3af/IEEE 802.3at PD with Synchronous
Forward Controller
2-Event Classiﬁcation Recognition, 94% Power Supply Efﬁciency, Flexible
Aux Support, Superior EMI, 100kHz to 500kHz
ThinSOT is a trademark of Linear Technology Corporation.
42691fb
44 Linear Technology Corporation
LT 0410 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009

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