VT82887 VIA Technologies, Inc. Real Time Clock determined by the logic level presented on AD6 during the address portion of an access cycle. An external crystal and battery are the only components required to maintain time-ofday and memory status in the absence of power. A complete description of operating conditions, electrical characteristics, bus timing and pin descriptions follows. FEATURES • Drop-in replacement for IBM AT computer clock/calendar. • Pin configuration closely matches the DS12887 • Totally nonvolatile with over 10 years of operation in the absence of power PIN ASSIGNMENT VT82887 24 PIN DIP · Self-contained subsystem includes lithium, quartz and support circuitry GND 1 24 VCC NC 2 23 SQW NC 3 22 NC AD0 4 21 RCLR# • 12- or 24-hour clock with AM and PM in 12hour mode AD1 5 20 NC • Daylight Savings Time option AD2 6 19 IRQ# • Intel bus timing AD3 7 18 RESET# • Multiplex bus for pin efficiency AD4 8 17 RD# • Interfaced with software as 128 RAM locations AD5 9 16 NC AD6 10 15 WR# AD7 11 14 AS GND 12 13 CS# • Counts seconds, minutes, hours, days, day of the week, date, month and year with leap year compensation • Binary or BCD representation of time, calendar and alarm - 14 bytes of clock and control registers - 114 bytes of general purpose RAM • Programmable square wave output signal • Bus-compatible interrupt signals (IRQ#) • Three interrupts are separately softwaremaskable and testable PIN DESCRIPTION AD0-AD7 NC CS# AS WR# RD# RESET# IRQ# SQW VCC GND RCLR# - Times-of-day alarm once/second to once/day - Periodic rates from 122 µs to 500 ms - End of clock update cycle DESCRIPTION The VT82887 Real Time Clock is designed to be a direct replacement for the DS12887. The VT82887 is identical in form, fit and function to the DS12887. It has 114 bytes of general purpose RAM. Access to this RAM space is OPERATION 1 - Multiplexed Address/Data Bus - No Connection - Chip Select - Address Strobe - Write Strobe - Read Strobe - Reset Input - Interrupt Request Output - Square Wave Output - +5 Volt Supply - Ground - RAM Clear VT82887 VIA Technologies, Inc. Real Time Clock The block diagram in Figure 1 shows the pin connections with the major internal functions of the VT82887. The following paragraphs describe the function of each pin. FIGURE 1: BLOCK DIAGRAM VT82887 system to stabilize after power is applied. When VCC falls below 4.25 volts, the chip select input is internally forced to an inactive level regardless of the value of CS# at the input pin. The VT82887 is, therefore, writeprotected. When VCC falls below the level of POWER-DOWN/POWER-UP CONSIDERATIONS The Real Time Clock function will continue to operate and all of the RAM, time, calendar and alarm memory locations remain 8 OSC 64 64 CS# VCC VBAT POWER SWITCH AND WRITE PROTECT PERIODIC INTERUPT SQUARE WAVE SELECTOR VCC PWGD SQUARE WAVE OUT SQW CS# IRQ# REGISTERS A,B,C,D RESET# RD# AS AD0AD7 CLOCK, CALENDAR AND ALARM RAM CLOCK/ CALENDAR UPDATE WR# DOUBLE BUFFERED BUS INTERFACE BCD/ BINARY INCREMENT USER RAM 114 BYTES RCLR# VBAT, the external VCC supply is switched off and the external VBAT lithium energy source supplies power to the Real Time Clock and the RAM memory. nonvolatile regardless of the level of the VCC input. When VCC is applied to the VT82887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 100 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A). This time period allows the 2 VT82887 VIA Technologies, Inc. Real Time Clock the Real Time Clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts typical. SIGNAL DESCRIPTIONS VCC − DC power is provided to the device on this pin. VCC is the +5 volt input. When 5 volts are applied within normal limits, the device is fully accessible and data can be written and read. When VCC is below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are switched over to the internal lithium energy source. The timekeeping function maintains an accuracy of ± 1 minute per month at 25°C regardless of the voltage input on the V CC pin. RCLR# − The RCLR# pin is used to clear (set to logic 1) all 114 bytes of general purpose RAM but does not affect the RAM associated with the real time clock. In order to clear the RAM, RCLR# must be forced to an input logic of 0 (-0.3 to +0.8 volts) during battery back-up mode when VCC is not applied. The RCLR# function is designed to be used via human interface (shorting to ground manually or by switch) and not to be driven with external buffers. This pin is internally pulled up. SQW (Square Wave Output) − The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of TABLE 1: PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY SELECT BITS REGISTER A tPI PERIODIC SQW OUTPUT RS3 RS2 RS1 RS0 INTERRUPT RATE FREQUENCY 0 0 0 0 None None 0 0 0 1 3.90625 ms 256 Hz 0 0 1 0 7.8125 ms 128 Hz 0 0 1 1 122.070 µs 8.192 kHz 0 1 0 0 244.141 µs 4.096 kHz 0 1 0 1 488.281 µs 2.048 kHz 0 1 1 0 976.5625 µs 1.024 kHz 0 1 1 1 1.953125 ms 512 Hz 1 0 0 0 3.90625 ms 256 Hz 1 0 0 1 7.8125 ms 128 Hz 1 0 1 0 15.625 ms 64 Hz 1 0 1 1 31.25 ms 32 Hz 1 1 0 0 62.5 ms 16 Hz 1 1 0 1 125 ms 8 Hz 1 1 1 0 250 ms 4 Hz 1 1 1 1 500 ms 2 Hz paths. The addresses are present during the first portion of the bus cycle and the same pins and cycle paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of AD0-AD7 (Multiplexed Bidirectional Address/Data Bus) − Multiplexed buses save pins because address information and data information time share the same signal 3 VT82887 VIA Technologies, Inc. Real Time Clock the VT82887 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS which the VT82887 uses to latch the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the RD# or WR# pulses. In a read cycle the VT82887 outputs 8 bits of data during the latter portion of the RD# pulse. The read cycle is terminated and the bus returns to a high impedance state as RD# transitions high as in Intel timing. When no interrupt conditions are present, the IRQ# level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ# bus. The IRQ# bus is an open drain output and requires an external pull-up resistor. RESET# (Reset Input) − The RESET# pin has no effect on the clock, calendar, or RAM. On power-up the RESET# pin can be held low for a time in order to allow the power supply to stabilize. The amount of time that RESET# is held low is dependent on the application. However, if RESET# is used on power-up, the time RESET# is low should exceed 200 ms to make sure that the internal timer that controls the VT82887 on power-up has timed out. When RESET# is low and VCC is above 4.25 volts, the following occurs: AS (Address Strobe Input) − A positive going address strobe pulse serves to demultiplex the bus. The falling edge of AS causes the address to be latched within the VT82887. RD# (Read Strobe) − The low active RD# pin identifies the time period when the VT82887 drives the bus with read data. The RD# signal is the same definition as the Output Enable (OE#) signal on a typical memory. A. Periodic Interrupt Enable (PIE) bit is cleared to zero. WR# (Write Strobe) − The low active WR# pin is used to indicate a write cycle. The data on the bus AD0-AD7 at the rising edge of WR# will be written into VT82887. C. Update Ended Interrupt Flag (UF) bit is cleared to zero. CS# (Chip Select Input) − The Chip Select signal must be asserted low for a bus cycle in order that the VT82887 can be accessed. CS# must be kept in the active state during RD# and WR#. Bus cycles which take place without asserting CS# will latch addresses but no access will occur. When VCC is below 4.25 volts, the VT82887 internally inhibits access cycles by internally disabling the CS# input. This action protects both the real time clock data and RAM data during power outages. E. Periodic Interrupt Flag (PF) bit is cleared to zero. I. Square Wave Output Enable (SQWE) bit is cleared to zero. IRQ# (Interrupt Request Output) − The IRQ# pin is an active low output of the VT82887 that can be used as an interrupt input to a processor. The IRQ# output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ# pin the processor program normally reads the C register. The RESET# pin also clears pending interrupts. J. Update Ended Interrupt Enable (UIE) is cleared to zero. B. Alarm Interrupt Enable (AIE) bit is cleared to zero. D. Interrupt Request Status Flag (IRQF) bit is cleared to zero. F. The device is not accessible RESET# is returned high. until G. Alarm Interrupt Flag (AF) bit is cleared to zero. H. IRQ# pin is in the high impedance state. In a typical application RESET# can be connected to VCC. This connection will allow the VT82887 to go in and out of power fail without affecting any of the control registers. ADDRESS MAP The address map of the VT82887 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that 4 VT82887 VIA Technologies, Inc. Real Time Clock contain the RTC time, calendar and alarm data, and four bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 2. Bit 7 of Register A is read-only. 3. The high order bit of the seconds byte is read-only. The contents of four registers (A, B, C and D) are described in the “Register” section. 1. Registers C and D are read-only. FIGURE 2: ADDRESS MAP VT82887 BCD), the data mode bit (DM) of Register B must be set to the appropriate logic level. All ten time, calendar and alarm bytes must use the same data mode. The SET bit in Register B should be cleared after time, calendar or alarm have been written to allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the ten time, calendar and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before Binary or BCD Input 0 00 14 Bytes Clock and Control Status Registers 13 OD 14 0E 114 Bytes Storage Registers 127 7F writing the internal time, calendar and alarm registers, the SET bit in Register B should be written to a logic one to prevent updates from occurring while access is being attempted. In addition to writing the ten time, calendar and alarm registers in a selected format (binary or 0 SECONDS 00 1 SECONDS ALARM 01 2 MINUTES 02 3 MINUTES ALARM 03 4 HOURS 04 5 HOURS ALARM 05 6 DAY OF THE WEEK 06 7 DAY OF THE MONTH 07 8 MONTH 08 9 YEAR 09 10 REGISTER A 0A 11 REGISTER B 0B 12 REGISTER C 0C 13 REGISTER D 0D ten data bytes. Table 2 shows the binary and BCD formats of the ten time, calendar and alarm locations. The 24-12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte 5 VT82887 VIA Technologies, Inc. Real Time Clock represents PM when it is a logic one. Once per second the ten bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later in this text. at the specified time each day if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of the three alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three alarm bytes create an interrupt every second. The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes and seconds alarm locations, the alarm interrupt is initiated TABLE 2: TIME. CALENDAR AND ALARM DATA MODES ADDRESS DECIMAL RANGE LOCATION FUNCTION RANGE BINARY DATA MODE BCD DATA MODE 0 Seconds 0-59 00-3B 00-59 1 Seconds Alarm 0-59 00-3B 00-59 2 Minutes 0-59 00-3B 00-59 3 Minutes Alarm 0-59 00-3B 00-59 4 Hours-12-hr Mode 1-12 01-0C AM, 81-8C PM 01-12AM,81-92PM Hours-24-hr Mode 0-23 00-17 00-23 Hours Alarm-12-hr 1-12 01-0C AM, 81-8C PM 01-12AM,81-92PM Hours Alarm-24-hr 0-23 00-17 00-23 6 Day of the Week Sunday = 1 1-7 01-07 01-07 7 Date of the Month 1-31 01-1F 01-31 8 Month 1-12 01-0C 01-12 9 Year 0-99 00-63 00-99 5 The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic interrupt can be selected for rates from 500 ms to 122 µs. The update-ended interrupt can be used to indicate to the program that an update cycle is complete. Each of these independent NONVOLATILE RAM The 114 general purpose nonvolatile RAM bytes are not dedicated to any special function within the VT82887. They can be used by the processor program as nonvolatile memory and are fully available during the update cycle. INTERRUPTS 6 VT82887 VIA Technologies, Inc. Real Time Clock interrupt conditions is described in greater detail in other sections of this text. one or more interrupts have been initiated by the VT82887. The act of reading Register C clears all active flag bits and the IRQF bit. The processor program can select which interrupts, if any, are going to be used. Three bits in Register B enable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when the event occurs. A zero in an interrupt-enable bit prohibits the IRQ# pin from being asserted from the interrupt condition. If an interrupt flag is already set when the interrupt is enabled, IRQ# is immediately set at an active level, although the interrupt initiating the event may have occurred much earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. OSCILLATOR CONTROL BITS The VT82887’s internal oscillator can be turned on and off as required. A pattern of 010 in bits 4 through 6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of 11X will turn the oscillator on, but hold the countdown chain of the oscillator in reset. All other combinations of bits 4 through 6 keep the oscillator off. SQUARE WAVE OUTPUT SELECTION Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of Figure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the SQW pin. The RS0-RS3 bits in Register A establish the square wave output frequency. These frequencies are listed in Table 1. The SQW frequency selection shares its 1-of-15 selector with the periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on and off under program control with the square wave enable bit (SQWE). When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag bits are set independent of the state of the corresponding enable bit in Register B. The flag bit can be used in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which software can interrogate as necessary. When the flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read; however, care should be taken when using the flag bits as they are cleared each time Register C is read. Double latching is included with Register C so that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared when read and new interrupts which are pending during the read cycle are held until the cycle is completed. One, two, or three bits can be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost. PERIODIC INTERRUPT SELECTION The periodic interrupt will cause the IRQ# pin to go to an active state from once every 500 ms to once every 122 µs. This function is separate from the alarm interrupt which can be output from once per second to once per day. The periodic interrupt rate is select using the same Register A bits which selected the square wave frequency (see Table 1). Changing the Register A bits affects both the square wave frequency and the periodic interrupt output. However, each function has a separate enable bit in Register B. The SQWE bit controls the square wave output. Similarly the periodic interrupt is enabled by the PIE bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create output intervals, or await the next needed software function. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the IRQ# pin is asserted low. IRQ# is asserted as long as at least one of three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a one whenever the IRQ# pin is being driven low. Determination that the RTC initiated an interrupt is accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that UPDATE CYCLE 7 VT82887 VIA Technologies, Inc. Real Time Clock The VT82887 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar and alarm bytes is frozen and will not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer. This feature allows time to maintain accuracy independent of reading or writing the time, calendar and alarm buffers and also guarantees that time and calendar information is consistent. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three positions. should be cleared before leaving the interrupt routine. A second method uses the update-inprogress bit (UIP) in Register A to determine if the update cycle is in progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs 244 µs later. If a low is read on the UIP bit, the user has at least 244 µs before the time/calendar data will be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 µs. The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts that occur at a rate of greater than tBUC allow valid time and date information to be reached at each occurrence of the periodic interrupt. The reads should be complete within 1 (t P1/2 + tBUC) to ensure that data is not read during the update cycle. There are three methods that can handle access of the real time clock that avoid any possibility of accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read valid time and date information. If this interrupt is used, the IRQF bit in Register C FIGURE 3: UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP 1 sec UIP tUC (tPI)/2 (tPI)/2 tPI tBUC PF UF UIP REGISTERS The VT82887 has four control registers which are accessible at all times, even during the update cycle. DV1 DV0 RS3 RS2 RS1 RS0 UIP The Update in Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is one, the update transfer will soon occur. When UIP is a zero, the update transfer will not occur for at least 244 µs. The time, calendar and alarm information in RAM is fully available for access when the UIP bit is zero. REGISTER A MSB DV2 LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8 VT82887 VIA Technologies, Inc. Real Time Clock The UIP bit is read only and is not affected by RESET#. Writing the SET bit in Register B to a one inhibits any update transfer and clears the UIP status bit. read/write bit that is not modified by RESET# or internal functions of the VT82887. PIE The Periodic Interrupt Enable PIE bit is a read/write bit which allows the Periodic Interrupt Flag (PF) bit in Register C to drive the IRQ# pin low. When the PIE bit is set to one, periodic interrupts are generated by driving the IRQ# pin low at a rate specified by the RS3-RS0 bits of Register A. A zero in the PIE bit blocks the IRQ# output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal VT82887 functions, but is cleared to zero on RESET#. DV0, DV1, DV2 These three bits are used to turn the oscillator on or off and to reset the countdown chain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC to keep time. A pattern of 11X will enable the oscillator but hold the countdown chain in reset. The next update will occur at 500 ms after a pattern of 010 is written to DV0, DV1 and DV2. RS3, RS2, RS1, RS0 AIE These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following: The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to one, permits the Alarm Flag (AF) bit in Register C to assert IRQ#. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is set to zero, the AF bit does not initiate the IRQ# signal. The RESET# pin clears AIE to zero. The internal functions of the VT82887 do not affect the AIE bit. 1. Enable the interrupt with the PIE bit; 2. Enable the SQW output pin with the SQWE bit; 3. Enable both at the same time and the same rate; UIE 4. Enable neither. The Update Ended Interrupt Enable (UIE) bit is a read/write that enables the Update End Flag (UF) bit in Register C to assert IRQ#. The RESET# pin going low or the SET bit going high clears UIE bit. Table 1 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the RS bits. These four read/write bits are not affected by RESET#. REGISTER B SQWE MSB LSB When the Square Wave Enable (SQWE) bit is set to a one, a square wave signal at the frequency set by the rate-selection bits RS3 through RS0 is driven out on the SQW pin. When the SQWE bit is set to zero, the SQW pin is held low; the state of SQWE is cleared by the RESET# pin. SQWE is a read/write bit. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SET PIE AIE UIE SQW E DM 24/12 DSE SET When the SET bit is a zero, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a one, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initialization. SET is a DM The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is not modified by internal 9 VT82887 VIA Technologies, Inc. Real Time Clock functions or RESET#. A one in DM signifies binary data while a zero in DM specifies Binary Coded Decimal (BCD) data. the periodic rate. PF is set to a one independent of the state of the PIE bit. When both PF and PIE are ones, the IRQ# signal is active and will set the IRQF bit. The PF bit is cleared by a RESET# or a software read of Register C. 24/12 The 24/12 control bit establishes the format of the hours byte. A one indicates the 24-hour mode and a zero indicates the 12-hour mode. This bit is read/write and is not affected by internal functions or RESET#. AF A one in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time. If the AIE bit is also a one, the IRQ# pin will go low and a one will appear in the IRQF pin. UF is cleared by reading Register C or a RESET#. DSE The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when DSE is set to one. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October when the time reaches 1:59:59 AM it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a zero. This bit is not affected by internal functions or RESET#. UF The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to one, the one in UF causes the IRQF bit to be a one which will assert the IRQ# pin. UF is cleared by reading Register C or a RESET#. REGISTER C BIT 0 THROUGH BIT 3 MSB These are unused bits of the status Register C. These bits always read zero and cannot be written. LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IRQF PF AF UF 0 0 0 0 IRQF The Interrupt Request Flag (IRQF) bit is set to a one when one or more of the following are true: PF = AF = UF = UIE = 1 PIE AIE = = REGISTER D MSB 1 1 LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VRT That is, IRQF = PF • PIE + AF • AIE + UF • UIE. 0 0 0 0 0 0 0 VRT This bit is not writeable and should always be one when read. If a zero is ever present, an exhausted external lithium energy source is indicated and both the contents of the RTC data and RAM data are questionable. This bit is unaffected by RESET#. Any time the IRQF bit is one, the IRQ# pin is driven low. All flag bits are cleared after Register C is read by the program or when the RESET# pin is low. PF BIT 6 THROUGH BIT 0 The Periodic Interrupt Flag (PF) is a read-only bit which is set to a one when an edge is detected on the selected tap of the divider chain. The RS3 through RS0 bits establish The remaining bits of Register D are not usable. They cannot be written and, when read, they will always read zero. ABSOLUTE MAXIMUM RATINGS* 10 VT82887 VIA Technologies, Inc. Real Time Clock VOLTAGE ON ANY PIN RELATIVE TO GROUND -0.3V TO +7.0V OPERATING TEMPERATURE 0°C TO 70°C STORAGE TEMPERATURE -40°C TO +70°C SOLDERING TEMPERATURE 260°C FOR 10 SECONDS *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0°C TO 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage VCC 4.5 5.0 5.5 V 1 Input Logic 1 VIH 2.2 VCC+0.3 V 1 Input Logic 0 VIL -0.3 +0.8 V 1 DC ELECTRICAL CHARACTERISTICS (0°C TO 70°C, VCC = 4.5 TO 5.5V) PARAMETER Power Supply Current SYMBOL MIN ICC1 TYP MAX UNITS NOTES 5 10 mA 2 Input Leakage IIL -1.0 +1.0 µA 3 I/O Leakage ILO -1.0 +1.0 µA 4 Input Current IMOT -1.0 +500 µA 3 Output @ 2.4V IOH -1.0 mA 1,5 Output @ 0.4V IOL 4.0 mA 1 Write Protect Voltage VTP 4.0 4.25 4.5 V SYMBOL MIN TYP MAX UNITS CIN 5 pF COUT 7 pF CAPACITANCE (tA = 25°C) PARAMETER Input Capacitance Output Capacitance NOTES AC ELECTRICAL CHARACTERISTICS (0°C TO 70°C, VCC = 4.5V TO 5.5V) PARAMETER SYMBOL MIN tCYC 385 Pulse Width, DS/E Low or RD/WR# High PW EL 150 ns Pulse Width, DS/E High or RD/WR# Low PW EH 125 ns Input Rise and Fall Time tR, tF Cycle Time TYP MAX UNITS DC ns 30 11 ns NOTES VT82887 VIA Technologies, Inc. Real Time Clock Chip Select Setup Time before WR#, or RD# tCS 20 ns Chip Select Hold Time tCH 0 ns Read Data Hold Time tDHR 10 Write Data Hold Time tDHW 0 Muxed Address Valid Time to AS Fall tASL 30 ns Muxed Address Hold Time tAHL 10 ns Delay Time RD# to AS Rise tASD 25 ns Pulse Width AS High PW ASH 60 ns Delay Time, AS to RD# Rise tASED 40 ns Output Data Delay Time from RD# tDDR 20 DataSetup Time tDSW 100 ns Reset Pulse Width tRWL 5 µs IRQ# Release from RD# tIRDS 2 µs IRQ# Release from RESET# tIRR 2 µs Delay Time before Update tBUC 80 120 244 ns ns 5 µs Cycle Periodic Interrupt Time tPI See Table 1 Interval Time of Update Cycle tUC 1708 µs 5. Measured with a load as shown in Figure 4. NOTES 1. All voltages are referenced to ground. 2. All outputs are open. 3. Applies to the AD0-AD7 pins, the IRQ# pin and the SQW pin when each is in the high impedence state. 4. The IRQ# pin is open drain. FIGURE 4: OUTPUT LOAD 12 VT82887 VIA Technologies, Inc. Real Time Clock +5 VOLTS 1.1 KΩ D.U.T. 50 pF 680Ω VT82887 BUS TIMING FOR WRITE CYCLE 13 VT82887 VIA Technologies, Inc. Real Time Clock tCYC AS PW ASH tASD RD# tASD tASED PW EH WR# PW EL tCS t CH CS# tAHL tASL tDSW AD0-AD7 VT82887 BUS TIMING FOR READ CYCLE 14 tDHW VT82887 VIA Technologies, Inc. Real Time Clock tCYC AS PW ASH tASD tASED PW EH RD# PW EL tASD WR# tCS tDDR t CH CS# tAHL tDHR tASL AD0-AD7 VT82887 IRQ RELEASE DELAY TIMING 15 VT82887 VIA Technologies, Inc. Real Time Clock RD# t RWL RESET# IRQ# tRDS tIRR POWER DOWN/POWER UP TIMING VCC 4.5V 3.2V tF tR tPD tREC CS# CURRENT SUPPLIED FROM EXTERNAL LITHIUM ENERGY CELL DATA RETENTION tDR POWER DOWN/POWER UP TIMING 16 VT82887 VIA Technologies, Inc. PARAMETER Real Time Clock SYMBOL MIN tPD 0 µs VCC slew from 4.5V to 0V (CS# at VIH) tF 300 µs VCC slew from 0V to 4.5V (CS# at VIH) tR 100 µs CS# at VIH after Power-Up tREC 20 SYMBOL MIN tDR 10 CS# at VIH before Power-Down TYP MAX UNITS 200 ms MAX UNITS NOTES (tA = 25°C) PARAMETER Expected Data Retention NOTE The real time clock will keep time to an accuracy of ±1 minute per month during data retention time for the period of tDR. WARNING Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. 17 TYP years NOTES