CY7C1378C 9-Mbit (256K x 32) Pipelined SRAM with NoBL™ Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT® devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 256K x 32 common I/O architecture • Single 3.3V power supply (VDD) • Fast clock-to-output times — 2.8 ns (for 250-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Asynchronous Output Enable (OE) • Available in JEDEC-standard lead-free 100-Pin TQFP package • Burst Capability—linear or interleaved burst order • “ZZ” Sleep mode option The CY7C1378C is a 3.3V, 256K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1378C is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.8 ns (250-MHz device) Write operations are controlled by the four Byte Write Select (BW[A:D]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Logic Block Diagram-CY7C1378C (256K x 32) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD BWA BWB BWC BWD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 ZZ E O U T P U T D A T A S T E E R I N G INPUT REGISTER 0 B U F F E R S DQs E E READ LOGIC SLEEP CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05687 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 14, 2006 CY7C1378C Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time (tCO) 2.8 3.2 3.5 ns Maximum Operating Current (IDD) 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA VDD VSS CLK WE CEN OE ADV/LD 92 91 90 89 88 87 86 85 A CE3 93 A BWA 94 81 BWB 95 82 BWC 96 83 BWD 97 NC CE2 98 A A CE1 99 A 1 80 NC 2 79 DQB DQC 3 78 DQB VDDQ 4 77 VDDQ VSS 5 76 VSS DQC 6 75 DQB DQC 7 74 DQB DQC 8 73 DQB DQC 9 72 DQB VSSQ 10 71 VSS VDDQ 11 70 VDDQ DQC 12 69 DQB DQC 13 68 DQB NC 14 67 VSS VDD 15 66 NC NC 16 65 VSS 17 64 VDD ZZ DQD 18 63 DQA DQD 19 62 DQA VDDQ 20 61 VDDQ VSSQ 21 60 VSS DQD 22 59 DQA DQD 23 58 DQA DQD 24 57 DQA DQD 25 56 DQA VSS 26 55 VSS VDDQ 27 54 VDDQ DQD 28 53 DQA DQD 29 52 DQA NC 30 51 NC Document #: 38-05687 Rev. *F 42 43 44 45 46 47 48 49 50 NC A A A A A A A NC 41 38 A0 NC 37 A1 VDD 36 A 40 35 39 34 A NC 33 VSS 32 CY7C1378C A MODE 31 BYTE D NC DQC A BYTE C 100 100-Pin TQFP Pinout 84 Pin Configuration BYTE B BYTE A Page 2 of 13 CY7C1378C Pin Definitions Name TQFP I/O Description A0, A1, A 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 InputAddress Inputs used to select one of the 256K address locations. Synchronous Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BW[A:D] 93, 94, 95, 96 InputByte Write Inputs, active LOW. Qualified with WE to conduct Writes to the Synchronous SRAM. Sampled on the rising edge of CLK. WE 88 InputWrite Enable Input, active LOW. Sampled on the rising edge of CLK if CEN Synchronous is active LOW. This signal must be asserted LOW to initiate a Write sequence. ADV/LD 85 InputAdvance/Load Input. Used to advance the on-chip address counter or load Synchronous a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK 89 CE1 98 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used Synchronous in conjunction with CE2 and CE3 to select/deselect the device. CE2 97 InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used Synchronous in conjunction with CE1 and CE3 to select/deselect the device. CE3 92 InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used Synchronous in conjunction with CE1 and CE2 to select/deselect the device. OE 86 InputOutput Enable, asynchronous input, active LOW. Combined with the Asynchronous synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN 87 InputClock Enable Input, active LOW. When asserted LOW the Clock signal is Synchronous recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ 64 InputZZ “sleep” Input. This active HIGH input places the device in a non-time Asynchronous critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data Synchronous register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a Write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. MODE 31 VDD 15,41,65,91 VDDQ 4, 11, 20, 27, 54, 61, 70, 77 I/O Power Supply VSS 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 Ground Document #: 38-05687 Rev. *F Input-Clock Input Strap pin Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power Supply Power supply inputs to the core of the device. Power supply for the I/O circuitry. Ground for the device. Page 3 of 13 CY7C1378C Pin Definitions (continued) Name NC TQFP I/O Description 1, 14, 16 30, 38, 39, 42, 43, 51, 66, 80, 84 - No Connects. Not internally connected to the die. NC (18M, 36M, 72M, 144M, 288M, 576M, 1G) These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M, 288M, 576M, and 1G densities. Functional Overview The CY7C1378C is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.8 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BW[A:D] can be used to conduct Byte Write operations. Burst Read Accesses The CY7C1378C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQP[A:D]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus, provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the Chip Enable signals, its output will tri-state following the next clock rise. Document #: 38-05687 Rev. *F On the next clock rise the data presented to DQs (or a subset for Byte Write operations, see Write Cycle Description table for details) inputs is latched into the device and the Write is complete. The data written during the Write operation is controlled by BW[A:D] signals. The CY7C1378C provides Byte Write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW[A:D]) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1378C is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated during the data portion of a Write cycle, regardless of the state of OE. Page 4 of 13 CY7C1378C Interleaved Burst Address Table (MODE = Floating or VDD) Burst Write Accesses The CY7C1378C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW[A:D] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8] Address Used CE ZZ Deselect Cycle None H Continue Deselect Cycle None X External Operation ADV/LD WE BWx OE CEN CLK DQ L L X X X L L-H Tri-State L H X X X L L-H Tri-State L L L H X L L L-H Data Out (Q) Next X L H X X L L L-H Data Out (Q) External L L L H X H L L-H Tri-State Next X L H X X H L L-H Tri-State External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State Current X L X X X X H L-H - None X H X X X X X X Tri-State Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) IGNORE CLOCK EDGE (Stall) SLEEP MODE Notes: 2. X = “Don't Care.” H = HIGH, L = LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details. 3. Write is defined by BW[A:D], and WE. See Write Cycle Descriptions table. 4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = Three-state when OE is inactive or when the device is deselected, and DQs = data when OE is active. Document #: 38-05687 Rev. *F Page 5 of 13 CY7C1378C Write Cycle Description[2, 3] Function WE BWD BWC BWB BWA Read H X X X X Write − No bytes written L H H H H Write Byte A − (DQA) L H H H L Write Byte B − (DQB) L H H L H Write Bytes A, B L H H L L Write Byte C − (DQC) L H L H H Write Bytes C,A L H L H L Write Bytes C, B L H L L H Write Bytes C, B, A L H L L L Write Byte D − (DQD) L L H H H Write Bytes D, A L L H H L Write Bytes D, B L L H L H Write Bytes D, B, A L L H L L Write Bytes D, C L L L H H Write Bytes D, C, A L L L H L Write Bytes D, C, B L L L L H Write All Bytes L L L L L ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ sleep mode standby current ZZ > VDD − 0.2V tZZS Device operation to ZZ ZZ > VDD − 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ Active to sleep current This parameter is sampled tRZZI ZZ inactive to exit sleep current This parameter is sampled Document #: 38-05687 Rev. *F Min. Max. Unit 50 mA 2tCYC ns 2tCYC ns 2tCYC 0 ns ns Page 6 of 13 CY7C1378C DC Input Voltage ........................................−0.5V to VDD + 0.5V Maximum Rating (Above which the useful life may be impaired. For User guide-lines not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied.................................................. −55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V Supply Voltage on VDDQ Relative to GND .......−0.5V to +VDD Range Ambient Temperature (TA) VDD/VDDQ DC Voltage Applied to Outputs in Tri-State ................................................−0.5V to VDDQ + 0.5V Commercial 0°C to +70°C 3.3V −5%/+10% Industrial –40°C to +85°C Electrical Characteristics Over the Operating Range [9, 10] Parameter Description Test Conditions VDD Power Supply Voltage VDDQ I/O Supply Voltage for 3.3V I/O VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA Min. Max. Unit 3.135 3.6 V 3.135 VDD V 2.4 V 0.4 V VIH Input HIGH Voltage[9] for 3.3V I/O 2.0 VDD + 0.3V V VIL Input LOW Voltage[9] for 3.3V I/O –0.3 0.8 V IX Input Leakage Current except ZZ and MODE GND ≤ VI ≤ VDDQ −5 5 µA Input Current of MODE Input = VSS −30 Input = VDD Input Current of ZZ −5 Input = VSS Input = VDD IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current ISB1 VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC µA 5 µA 30 −5 µA µA 5 µA 4-ns cycle, 250 MHz 250 mA 5-ns cycle, 200 MHz 220 mA 6-ns cycle, 166 MHz 180 mA Automatic CE Power-Down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 130 mA 5-ns cycle, 200 MHz 120 mA 6-ns cycle, 166 MHz 110 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs VDD = Max, Device Deselected, VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f=0 All speeds 40 mA ISB3 Automatic CE Power-Down Current—CMOS Inputs VDD = Max, Device Deselected, or 4-ns cycle, 250 MHz VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5-ns cycle, 200 MHz f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 120 mA 110 mA 100 mA Automatic CE Power-Down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 40 mA ISB4 All Speeds Notes: 9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2). 10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05687 Rev. *F Page 7 of 13 CY7C1378C Capacitance[11] Parameter Test Conditions 100 TQFP Max. TA = 25°C, f = 1 MHz, VDD = 3.3V, VDDQ = 3.3V 5 pF 5 pF 5 pF Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Unit Thermal Resistance[11] Parameter ΘJA ΘJC Description Test Conditions Thermal Resistance Test conditions follow standard test methods and (Junction to Ambient) procedures for measuring thermal impedance, per Thermal Resistance EIA/JESD51 100 TQFP Package Unit 29.41 °C/W 6.13 °C/W (Junction to Case) AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDD OUTPUT RL = 50Ω Z0 = 50Ω 10% GND 5 pF VL = 1.5V (a) INCLUDING JIG AND SCOPE 90% 10% 90% R = 351Ω (b) ≤ 1 ns ≤ 1 ns (c) Note: 11. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05687 Rev. *F Page 8 of 13 CY7C1378C Switching Characteristics Over the Operating Range [12, 13, 14, 15, 16] –250 Parameter tPOWER Description VDD (typical) to the First Access Min. [13] –200 Max. Min. –166 Max. Min. Max. Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5.0 6.0 ns tCH Clock HIGH 1.8 2.0 2.4 ns tCL Clock LOW 1.8 2.0 2.4 ns Output Times tCO Data Output Valid after CLK Rise tDOH Data Output Hold after CLK Rise 2.8 1.25 tCLZ [14, 15, 16] Clock to Low-Z 1.25 tCHZ Clock to High-Z[14, 15, 16] 1.25 tOEV OE LOW to Output Valid tOELZ tOEHZ OE LOW to Output Low-Z[14, 15, 16] OE HIGH to Output High-Z[14, 15, 16] 3.2 1.5 1.5 1.5 2.8 1.5 2.8 0 3.5 1.5 3.2 0 2.8 ns 1.5 3.2 ns 3.5 ns 3.5 ns 0 3.2 ns ns 3.5 ns Set-up Times tAS Address Set-up before CLK Rise 1.4 1.5 1.5 ns tALS ADV/LD Set-up before CLK Rise 1.4 1.5 1.5 ns tWES GW, BW[A:D] Set-up before CLK Rise 1.4 1.5 1.5 ns tCENS CEN Set-up before CLK Rise 1.4 1.5 1.5 ns tDS Data Input Set-up before CLK Rise 1.4 1.5 1.5 ns tCES Chip Enable Set-up before CLK Rise 1.4 1.5 1.5 ns tAH Address Hold after CLK Rise 0.4 0.5 0.5 ns tALH ADV/LD Hold after CLK Rise 0.4 0.5 0.5 ns tWEH GW, BW[A:D] Hold after CLK Rise 0.4 0.5 0.5 ns Hold Times tCENH CEN Hold after CLK Rise 0.4 0.5 0.5 ns tDH Data Input Hold after CLK Rise 0.4 0.5 0.5 ns tCEH Chip Enable Hold after CLK Rise 0.4 0.5 0.5 ns Notes: 12. Test conditions shown in (a), (b) and (c) of AC Test Loads. 13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated. 14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve Three-state prior to Low-Z under the same system conditions. 16. This parameter is sampled and not 100% tested. Document #: 38-05687 Rev. *F Page 9 of 13 CY7C1378C Switching Waveforms Read/Write Timing[17, 18, 19] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BW[A:D] A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes: 17. For this waveform ZZ is tied LOW. 18. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 19. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document #: 38-05687 Rev. *F Page 10 of 13 CY7C1378C Switching Waveforms (continued) NOP, STALL, and Deselect Cycle[17, 18, 20] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW[A:D] ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) DON’T CARE WRITE D(A4) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[21, 22] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 20. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 21. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device. 22. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05687 Rev. *F Page 11 of 13 CY7C1378C Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 166 Package Diagram Ordering Code CY7C1378C-166AXC Operating Range Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1378C-166AXI 200 Industrial CY7C1378C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1378C-200AXI 250 Industrial CY7C1378C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1378C-250AXI Industrial Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL A ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05687 Rev. *F Page 12 of 13 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1378C Document History Page Document Title: CY7C1378C 9-Mbit (256K x 32) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05687 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 286269 See ECN PCI New data sheet *A 323636 See ECN PCI Changed frequency of 225 MHz to 250 MHz Corrected Maximum CMOS Standby Current in Selection Guide from 30 mA 35 mA Added tCYC of 4.0 ns for 250 MHz Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to 29.41 and 6.13 °C/W respectively Added Industrial Operating Range Replaced Snooze with Sleep in the ZZ Mode Electrical Characteristics and Cycle Description Truth Table Added 3 chip enable for AX package in the ordering information table *B 332879 See ECN PCI Shaded 250 MHz speed bin in the AC/DC Table and Selection Guide Added Address Expansion pins in the Pin Definition Table Modified VOL, VOH test conditions Corrected VDDQ from (2.5V – 5% to VDD) to (3.3V – 5% to 3.465) on page# 8 Updated Ordering Information Table *C 346396 See ECN PCI Corrected (VDD/VDDQ) range in Operating Range Table from (3.3V – 5% to 3.465) to (3.3V −5%/+10%) *D 377095 See ECN PCI Changed ISB2 from 35 to 40 mA Modified test condition in note# 10 from VDDQ < VDD to VDDQ < VDD *E 408725 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed three state to tri-state Converted from Preliminary to Final Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Updated the ordering information *F 501828 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Updated the Ordering Information table. Document #: 38-05687 Rev. *F Page 13 of 13