CYPRESS CY7C1911BV18

CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
18-Mbit QDR™-II SRAM 4-Word
Burst Architecture
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
Features
Functional Description
■
Separate independent read and write data ports
❐ Supports concurrent transactions
■
300 MHz clock for high bandwidth
■
4-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and
CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common IO devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR-II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are provided with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1311BV18), 9-bit words (CY7C1911BV18), 18-bit
words (CY7C1313BV18), or 36-bit words (CY7C1315BV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K and C and C), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Configurations
CY7C1311BV18 – 2M x 8
CY7C1911BV18 – 2M x 9
CY7C1313BV18 – 1M x 18
CY7C1315BV18 – 512K x 36
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
300
278
250
200
167
MHz
x8
765
720
665
560
495
mA
x9
800
730
675
570
490
x18
840
760
705
590
505
x36
985
910
830
675
570
Maximum Operating Frequency
Maximum Operating Current
Cypress Semiconductor Corporation
Document Number: 38-05620 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 02, 2011
[+] Feedback
CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Logic Block Diagram (CY7C1311BV18)
DOFF
Address
Register
Read Add. Decode
Write
Reg
512K x 8 Array
K
CLK
Gen.
Write
Reg
512K x 8 Array
K
Write
Reg
512K x 8 Array
Address
Register
Write
Reg
512K x 8 Array
A(18:0)
19
8
Write Add. Decode
D[7:0]
19
A(18:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
32
VREF
WPS
NWS[1:0]
16
Control
Logic
Reg.
16
Reg.
CQ
Reg. 8
8
8
8
8
Q[7:0]
Logic Block Diagram (CY7C1911BV18)
DOFF
Address
Register
Read Add. Decode
Write
Reg
512K x 9 Array
K
CLK
Gen.
Write
Reg
512K x 9 Array
K
Write
Reg
512K x 9 Array
Address
Register
Write
Reg
512K x 9 Array
A(18:0)
19
9
Write Add. Decode
D[8:0]
Control
Logic
Read Data Reg.
19
A(18:0)
RPS
C
C
CQ
36
VREF
WPS
BWS[0]
18
Control
Logic
Document Number: 38-05620 Rev. *F
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q[8:0]
Page 2 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Logic Block Diagram (CY7C1313BV18)
DOFF
Address
Register
Read Add. Decode
Write
Reg
256K x 18 Array
K
CLK
Gen.
Write
Reg
256K x 18 Array
K
Write
Reg
256K x 18 Array
Address
Register
Write
Reg
256K x 18 Array
A(17:0)
18
18
Write Add. Decode
D[17:0]
Control
Logic
18
A(17:0)
RPS
C
Read Data Reg.
C
CQ
72
VREF
WPS
BWS[1:0]
36
Control
Logic
Reg.
36
Reg.
CQ
Reg. 18
18
18
18
18
Q[17:0]
Logic Block Diagram (CY7C1315BV18)
DOFF
Address
Register
Read Add. Decode
Write
Reg
128K x 36 Array
K
CLK
Gen.
Write
Reg
128K x 36 Array
K
Write
Reg
128K x 36 Array
Address
Register
Write
Reg
128K x 36 Array
A(16:0)
17
36
Write Add. Decode
D[35:0]
Control
Logic
Read Data Reg.
17
A(16:0)
RPS
C
C
CQ
144
VREF
WPS
BWS[3:0]
72
Control
Logic
Document Number: 38-05620 Rev. *F
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q[35:0]
Page 3 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Contents
Pin Configuration ............................................................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Single Clock Mode ...................................................... 9
Concurrent Transactions ........................................... 10
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
DLL ............................................................................ 10
Application Example ...................................................... 11
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port—Test Clock ................................... 14
Test Mode Select (TMS) ........................................... 14
Test Data-In (TDI) ..................................................... 14
Test Data-Out (TDO) ................................................. 14
Performing a TAP Reset ........................................... 14
TAP Registers ........................................................... 14
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 16
TAP Controller Block Diagram ...................................... 17
Document Number: 38-05620 Rev. *F
TAP Electrical Characteristics ...................................... 17
TAP AC Switching Characteristics ............................... 18
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in QDR-II SRAM ........................... 21
Power Up Sequence ................................................. 21
DLL Constraints ........................................................ 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................ 22
Electrical Characteristics .............................................. 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 24
Thermal Resistance ....................................................... 24
Switching Characteristics ............................................. 25
Switching Waveforms .................................................... 27
Ordering Information ..................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagram ........................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC Solutions ......................................................... 32
Page 4 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Pin Configuration
The pin configuration for CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 follow. [1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1311BV18 (2M x 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NWS1
K
NC/144M
RPS
A
NC/36M
CQ
B
NC
NC
NC
A
NC/288M
K
NWS0
A
NC
NC
Q3
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1911BV18 (2M x 9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NC
K
NC/144M
RPS
A
NC/36M
CQ
B
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
Q4
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D4
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q2
D2
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D1
N
NC
D8
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q8
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 38-05620 Rev. *F
Page 5 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Pin Configuration
(continued)
The pin configuration for CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 follow. [1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1313BV18 (1M x 18)
1
2
3
NC/144M NC/36M
4
5
6
7
8
9
10
11
WPS
BWS1
K
NC/288M
RPS
A
NC/72M
CQ
A
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
NC
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
9
10
CY7C1315BV18 (512K x 36)
1
2
4
5
6
7
8
WPS
BWS2
K
BWS1
RPS
D18
A
BWS3
K
BWS0
A
D17
Q17
Q8
Q28
D19
VSS
A
NC
A
VSS
D16
Q7
D8
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
A
CQ
B
Q27
Q18
C
D27
D
E
F
3
NC/288M NC/72M
Document Number: 38-05620 Rev. *F
11
NC/36M NC/144M
CQ
Page 6 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous CY7C1311BV18  D[7:0]
CY7C1911BV18  D[8:0]
CY7C1313BV18  D[17:0]
CY7C1315BV18  D[35:0]
WPS
InputWrite Port Select  Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
NWS0,
NWS1
InputNibble Write Select 0, 1  Active LOW (CY7C1311BV18 Only). Sampled on the rising edge of the K
Synchronous and K clocks during write operations. Used to select which nibble is written into the device during the
current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2, and 3  Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1911BV18 BWS0 controls D[8:0]
CY7C1313BV18  BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315BV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2M x 8 (4 arrays each of 512K x 8) for CY7C1311BV18, 2M x 9 (4 arrays each of 512K x 9) for
CY7C1911BV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313BV18 and 512K x 36 (4 arrays each
of 128K x 36) for CY7C1315BV18. Therefore, only 19 address inputs are needed to access the entire
memory array of CY7C1311BV18 and CY7C1911BV18, 18 address inputs for CY7C1313BV18 and 17
address inputs for CY7C1315BV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
OutputData Output Signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1311BV18  Q[7:0]
CY7C1911BV18  Q[8:0]
CY7C1313BV18  Q[17:0]
CY7C1315BV18  Q[35:0]
RPS
InputRead Port Select  Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of four sequential transfers.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 11 for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 11 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
Document Number: 38-05620 Rev. *F
Page 7 of 32
[+] Feedback
CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Pin Definitions
Pin Name
(continued)
IO
Pin Description
CQ
Echo Clock
CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 25.
CQ
Echo Clock
CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 25.
ZQ
Input
Output Impedance Matching input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off  Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off differs from those listed in this data sheet.
TDO
Output
TDO for JTAG.
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
InputReference
VDD
Supply
Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
VSS
VDDQ
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 38-05620 Rev. *F
Page 8 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Functional Overview
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18,
CY7C1315BV18 are synchronous pipelined Burst SRAMs with a
read port and a write port. The read port is dedicated to read
operations and the write port is dedicated to write operations.
Data flows into the SRAM through the write port and flows out
through the read port. These devices multiplex the address
inputs to minimize the number of address pins required. By
having separate read and write ports, the QDR-II completely
eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1311BV18, four 9-bit data transfers in the case of
CY7C1911BV18, four 18-bit data transfers in the case of
CY7C1313BV18, and four 36-bit data transfers in the case of
CY7C1315BV18 in two clock cycles.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input timing is referenced from the rising
edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single
clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1313BV18 is described in the following sections. The
same basic descriptions apply to CY7C1311BV18,
CY7C1911BV18, and CY7C1315BV18.
Read Operations
The CY7C1313BV18 is organized internally as four arrays of
256K x 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the read
address register. Following the next K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data is
valid 0.45 ns from the rising edge of the output clock (C or C, or
K or K when in single clock mode). To maintain the internal logic,
each read access must be allowed to complete. Each read
access consists of four 18-bit data words and takes two clock
cycles to complete. Therefore, read accesses to the device
cannot be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second read request. Read
accesses can be initiated on every other K clock rise. Doing so
Document Number: 38-05620 Rev. *F
pipelines the data flow such that data is transferred out of the
device on every rising edge of the output clocks (C and C, or K
and K when in single clock mode).
When the read port is deselected, the CY7C1311BV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive output clock (C). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
in the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the positive input clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1311BV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Single Clock Mode
The CY7C1311BV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power on. This function is a strap option and not
alterable during device operation.
Page 9 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Concurrent Transactions
Programmable Impedance
The read and write ports on the CY7C1311BV18 operate
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address location.
This includes forwarding data from a write cycle that was initiated
on the previous K clock rise.
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Read accesses and write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports were deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations cannot be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
cannot be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in
alternating read or write operations being initiated, with the first
access being a read.
Depth Expansion
The CY7C1311BV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Document Number: 38-05620 Rev. *F
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the QDR-II. In single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in the
Switching Characteristics on page 25.
DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the DLL is locked after 1024
cycles of stable clock. The DLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock to the
desired frequency. The DLL automatically locks 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note AN5062, DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+.
Page 10 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Application Example
Figure 1 shows four QDR-II used in an application.
Figure 1. Application Example
SRAM #1
R
P
S
#
Vt
D
A
R
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
C C# K K#
R = 250ohms
SRAM #4
R
P
S
#
D
A
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
R
W
P
S
#
B
W
S
#
ZQ R = 250ohms
CQ/CQ#
Q
C C# K K#
Vt
Vt
Delayed K
Delayed K#
R
R = 50ohms Vt = Vddq/2
Truth Table
The truth table for CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
[8]
[9]
DQ
DQ
DQ
DQ
Write Cycle:
Load address on the rising
edge of K; write data on
two consecutive K and K
rising edges.
L-H
H
Read Cycle:
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
L-H
L [9]
X
Q(A) at C(t + 1) Q(A + 1) at C(t + 2) Q(A + 2) at C(t + 2) Q(A + 3) at C(t + 3)
NOP: No Operation
L-H
H
H
D=X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
Stopped
X
X
Previous State
Previous State
Previous State
Previous State
Standby: Clock Stopped
L
D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Document Number: 38-05620 Rev. *F
Page 11 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Write Cycle Descriptions
The write cycle description table for CY7C1311BV18 and CY7C1313BV18 follows. [2, 10]
BWS0/ BWS1/
K
K
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
NWS0
NWS1
L
Comments
During the data portion of a write sequence
CY7C1311BV18 both nibbles (D[7:0]) are written into the device.
CY7C1313BV18 both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence
CY7C1311BV18 both nibbles (D[7:0]) are written into the device.
CY7C1313BV18 both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence
CY7C1311BV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1313BV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence
CY7C1311BV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1313BV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence
CY7C1311BV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1313BV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence
CY7C1311BV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1313BV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1911BV18 follows. [2, 10]
BWS0
K
K
Comments
L
L–H
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L–H
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
Note
10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 38-05620 Rev. *F
Page 12 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Write Cycle Descriptions
The write cycle description table for CY7C1315BV18 follows. [2, 10]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
Document Number: 38-05620 Rev. *F
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Page 13 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-1900. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively
be connected to VDD through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 16. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 17. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 20 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 19).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 19.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
TAP Registers
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
IDCODE
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
The IDCODE instruction loads a vendor-specific, 32-bit code into
Document Number: 38-05620 Rev. *F
Page 14 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
Document Number: 38-05620 Rev. *F
BYPASS
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set HIGH to enable
the output when the device is powered up, and also when the
TAP controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 15 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [11]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
1
0
PAUSE-DR
0
0
0
1
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05620 Rev. *F
Page 16 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
106
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range [12, 13, 14]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH =2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH =100 A
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 A
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND  VI  VDD
V
–0.3
0.35VDD
V
–5
5
A
Notes
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
13. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5V (Pulse width less than tCYC/2).
14. All Voltage referenced to Ground.
Document Number: 38-05620 Rev. *F
Page 17 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
TAP AC Switching Characteristics
Over the Operating Range [15, 16]
Parameter
Description
Min
Max
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
50
ns
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [16]
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
1.8V
50
0.9V
TDO
0V
Z0 = 50
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 38-05620 Rev. *F
Page 18 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Identification Register Definitions
Instruction Field
Value
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
000
000
000
000
Revision Number
(31:29)
Description
Version number.
Cypress Device ID 11010011011000101 11010011011001101 11010011011010101 11010011011100101 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
00000110100
00000110100
1
1
1
1
ID Register
Presence (0)
Allows unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do not use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do not use: This instruction is reserved for future use.
RESERVED
110
Do not use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 38-05620 Rev. *F
Page 19 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
27
11H
54
7B
81
3G
1
6P
28
10G
55
6B
82
2G
2
6N
29
9G
56
6A
83
1J
3
7P
30
11F
57
5B
84
2J
4
7N
31
11G
58
5A
85
3K
5
7R
32
9F
59
4A
86
3J
6
8R
33
10F
60
5C
87
2K
7
8P
34
11E
61
4B
88
1K
8
9R
35
10E
62
3A
89
2L
9
11P
36
10D
63
1H
90
3L
10
10P
37
9E
64
1A
91
1M
11
10N
38
10C
65
2B
92
1L
12
9P
39
11D
66
3B
93
3N
13
10M
40
9C
67
1C
94
3M
14
11N
41
9D
68
1B
95
1N
15
9M
42
11B
69
3D
96
2M
16
9N
43
11C
70
3C
97
3P
17
11L
44
9B
71
1D
98
2N
18
11M
45
10B
72
2C
99
2P
19
9L
46
11A
73
3E
100
1P
20
10L
47
Internal
74
2D
101
3R
21
11K
48
9A
75
2E
102
4R
22
10K
49
8B
76
1E
103
4P
23
9J
50
7C
77
2F
104
5P
24
9K
51
6C
78
3F
105
5N
25
10J
52
8A
79
1G
106
5R
26
11J
53
7A
80
1F
Document Number: 38-05620 Rev. *F
Page 20 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Power Up Sequence in QDR-II SRAM
DLL Constraints
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The DLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Power Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (all other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
■
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
~
~
Figure 3. Power Up Waveforms
K
K
~
~
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document Number: 38-05620 Rev. *F
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix High (or tie to VDDQ)
Page 21 of 32
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CY7C1313BV18, CY7C1315BV18
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with Power Applied –55 C to +125 C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch up Current.................................................... > 200 mA
Operating Range
Ambient
Temperature (TA)
Range
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
Commercial
0 C to +70 C
DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.3V
Industrial
–40°C to +85°C
DC Input Voltage
[13]
VDD [17]
VDDQ [17]
1.8 ± 0.1V 1.4V to VDD
.............................. –0.5V to VDD + 0.3V
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [14]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
IO Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 18
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 19
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH =0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.3
V
VIL
Input LOW Voltage
–0.3
VREF – 0.1
V
IX
Input Leakage Current
GND  VI  VDDQ
5
5
A
IOZ
Output Leakage Current
GND  VI  VDDQ, Output Disabled
5
5
A
VREF
Input Reference Voltage
IDD [21]
VDD Operating Supply
[20]
Typical Value = 0.75V
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
0.68
300 MHz
278 MHz
250 MHz
0.95
V
(x8)
0.75
765
mA
(x9)
800
(x18)
840
(x36)
985
(x8)
720
(x9)
730
(x18)
760
(x36)
910
(x8)
665
(x9)
675
(x18)
705
(x36)
830
mA
mA
Notes
17. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
18. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
19. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
20. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
21. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 38-05620 Rev. *F
Page 22 of 32
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CY7C1313BV18, CY7C1315BV18
Electrical Characteristics
(continued)
DC Electrical Characteristics
Over the Operating Range [14]
Parameter
IDD
[21]
Description
VDD Operating Supply
Test Conditions
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
200 MHz
167 MHz
ISB1
Automatic Power Down
Current
Max VDD,
Both Ports Deselected,
VIN  VIH or VIN  VIL
f = fMAX = 1/tCYC,
Inputs Static
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Min
Typ
Max
Unit
(x8)
560
mA
(x9)
570
(x18)
590
(x36)
675
(x8)
495
(x9)
490
(x18)
505
(x36)
570
(x8)
290
(x9)
300
(x18)
325
(x36)
385
(x8)
260
(x9)
265
(x18)
300
(x36)
355
(x8)
250
(x9)
250
(x18)
290
(x36)
325
(x8)
230
(x9)
230
(x18)
250
(x36)
270
(x8)
220
(x9)
220
(x18)
230
(x36)
250
mA
mA
mA
mA
mA
mA
AC Electrical Characteristics
Over the Operating Range [13]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
–
V
VIL
Input LOW Voltage
–
–
VREF – 0.2
V
Document Number: 38-05620 Rev. *F
Page 23 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
5
pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7
pF
165 FBGA
Package
Unit
18.7
°C/W
4.5
°C/W
TA = 25C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
Figure 4. AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50
Device
Under
Test
ZQ
RL = 50
VREF = 0.75V
R = 50
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
RQ =
250
(a)
0.75V
INCLUDING
JIG AND
SCOPE
5 pF
[22]
0.25V
Slew Rate = 2 V/ns
RQ =
250
(b)
Note
22. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document Number: 38-05620 Rev. *F
Page 24 of 32
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Switching Characteristics
Over the Operating Range [22, 23]
Cypress Consortium
Parameter Parameter
Description
VDD(Typical) to the First Access [24]
tPOWER
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Min Max Min Max Min Max Min Max Min Max
1
1
1
1
1
Unit
ms
tCYC
tKHKH
K Clock and C Clock Cycle Time
3.3
8.4
3.6
8.4
4.0
8.4
5.0
8.4
6.0
8.4
ns
tKH
tKHKL
Input Clock (K/K; C/C) HIGH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
tKL
tKLKH
Input Clock (K/K; C/C) LOW
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise and C 1.49
to C Rise (rising edge to rising edge)
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
0
1.45
0
1.55
0
1.8
0
2.2
0
2.7
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSC
tIVKH
Control Setup to K Clock Rise
(RPS, WPS)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to
Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tSD [25]
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tKHAX
Address Hold after K Clock Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHC
tKHIX
Control Hold after K Clock Rise
(RPS, WPS)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after 0.3
Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Notes
23. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
24. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
25. For D2 data signal on CY7C1911BV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz, and 300 MHz frequencies.
Document Number: 38-05620 Rev. *F
Page 25 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Switching Characteristics
(continued)
Over the Operating Range [22, 23]
Cypress Consortium
Parameter Parameter
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Min Max Min Max Min Max Min Max Min Max
Unit
Output Times
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
0.40
ns
tCO
tCHQV
C/C Clock Rise (or K/K in single
clock mode) to Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C –0.45
Clock Rise (Active to Active)
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock
Rise
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
tCHZ
tCHQZ
Clock (C/C) Rise to High-Z
(Active to High-Z) [26, 27]
tCLZ
tCHQX1
Clock (C/C) Rise to Low-Z [26, 27]
0.27
0.27
0.30
0.35
–0.27
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
ns
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
–
0.20
–
0.20
–
0.20
–
0.20
–
0.20
ns
–
1024
–
1024
–
1024
–
1024
–
Cycles
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
tKC Reset
tKC Reset
K Static to DLL Reset
30
30
30
30
30
ns
Notes
26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms on page 24. Transition is measured ± 100 mV from steady-state voltage.
27. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 38-05620 Rev. *F
Page 26 of 32
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CY7C1313BV18, CY7C1315BV18
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence [28, 29, 30]
NOP
1
WRITE
3
READ
2
READ
4
NOP
6
WRITE
5
7
K
t KH
t
tKL
t KHKH
CYC
K
RPS
t SC
tHC
t SC
t HC
WPS
A0
A
tSA
A1
A3
A2
t HD
t HA
t
t SD
SD
D
D10
D11
Q00
Q
t KHCH
t KHCH
t HD
D13
D12
Q01
Q02
tCO
Q03
D30
D31
Q20
D33
D32
Q22
Q21
Q23
t CHZ
tCQDOH
t CLZ
t DOH
t CQD
C
t CYC
t KHKH
t KH
t KL
C
t CCQO
t CQOH
CQ
t CQOH
t CCQO
CQ
DON’T CARE
UNDEFINED
Notes
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
29. Outputs are disabled (High-Z) one clock cycle after a NOP.
30. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
Document Number: 38-05620 Rev. *F
Page 27 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Ordering Code
Package
Diagram
Package Type
Operating
Range
250
CY7C1315BV18-250BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free Commercial
200
CY7C1315BV18-200BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free Commercial
CY7C1315BV18-200BZI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1315BV18-200BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Industrial
Ordering Code Definitions
CY 7C 1315 B V18 - XXX XXX X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type: XXX = BZX or BZ
BZX = 165-ball FPBGA (Pb-free)
BZ = 165-ball FPBGA
Frequency Range: XXX = 250 MHz or 200 MHz
Voltage: 1.8 V
Die Revision: 90 nm
Part Identifier
Marketing Code : 7C = SRAM
Company ID: CY = Cypress
Document Number: 38-05620 Rev. *F
Page 28 of 32
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CY7C1313BV18, CY7C1315BV18
Package Diagram
Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
51-85180 *C
Document Number: 38-05620 Rev. *F
Page 29 of 32
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CY7C1313BV18, CY7C1315BV18
Document History Page
Document Title: CY7C1311BV18/CY7C1911BV18/CY7C1313BV18/CY7C1315BV18, 18-Mbit QDR™-II SRAM 4-Word Burst
Architecture
Document Number: 38-05620
Rev. ECN No. Submission
Date
Orig. of
Change
Description of Change
**
252474
See ECN
SYT
New data sheet
*A
325581
See ECN
SYT
Removed CY7C1911BV18 from the title
Included 300-MHz Speed Bin
Added Industrial Temperature Grade
Replaced TBDs for IDD and ISB1 specs
Replaced the TBDs on the Thermal Characteristics Table to JA = 28.51C/W and JC
= 5.91C/W
Replaced TBDs in the Capacitance Table for the 165 FBGA Package
Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D
(13 x 15 x 1.4 mm)
Added Lead-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per availability
*B
413997
See ECN
NXR
Converted from Preliminary to Final
Added CY7C1911BV18 to the title
Added 278-MHz speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North
First Street” to “198 Champion Court”
Changed C/C Description in the features section
Added power-up sequence details and waveforms
Added foot notes# 17, 18, 19 on page# 19
Changed the description of IX from Input Load Current to Input Leakage Current on
page# 20
Modified the IDD and ISB values
Modified test condition in Footnote # 22 on page# 20 from VDDQ < VDD to
VDDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*C
472384
See ECN
NXR
Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD
to Alternately, this pin can be connected directly to VDDQ
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH
from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching
Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied from –10 C
to +85 C to –55 C to +125 C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table
Document Number: 38-05620 Rev. *F
Page 30 of 32
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Document History Page
Document Title: CY7C1311BV18/CY7C1911BV18/CY7C1313BV18/CY7C1315BV18, 18-Mbit QDR™-II SRAM 4-Word Burst
Architecture
Document Number: 38-05620
Rev. ECN No. Submission
Date
*D
2511674
06/03/08
Orig. of
Change
Description of Change
VKN/PYRS Updated Logic Block diagrams
Updated IDD/ISB specs
Added footnote# 21 related to IDD
Updated power up sequence waveform and its description
Changed DLL minimum operating frequency from 80 MHz to 120 MHz
Changed JA spec from 28.51 to 18.7
Changed JC spec from 5.91 to 4.5
Changed tCYC maximum spec to 8.4 ns for all speed bins
Modified footnotes 23 and 30
*E
2898958
03/25/10
NJY
Removed inactive parts from the ordering information table. Updated package diagram.
*F
3160393
02/02/2011
NJY
Updated Ordering Information and added Ordering Code Definitions.
Document Number: 38-05620 Rev. *F
Page 31 of 32
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CY7C1313BV18, CY7C1315BV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05620 Rev. *F
Revised February 02, 2011
Page 32 of 32
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung. All product and company names mentioned in this document are
the trademarks of their respective holders.
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