LINER LTC3810IG-TR

LTC3810
100V Current Mode
Synchronous Switching
Regulator Controller
DESCRIPTION
FEATURES
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The LTC3810 is a synchronous step-down switching
regulator controller that can directly step-down voltages
from up to 100V, making it ideal for telecom and automotive applications. The LTC3810 uses a constant on-time
valley current control architecture to deliver very low duty
cycles with accurate cycle-by-cycle current limit, without
requiring a sense resistor.
High Voltage Operation: Up to 100V
Large 1Ω Gate Drivers
No Current Sense Resistor Required
Dual N-Channel MOSFET Synchronous Drive
Extremely Fast Transient Response
±0.5% 0.8V Voltage Reference
Programmable Output Voltage Tracking/Soft-Start
Generates 10V Driver Supply from Input Supply
Synchronizable to External Clock
Selectable Pulse Skip Mode Operation
Power Good Output Voltage Monitor
Adjustable On-Time/Frequency: tON(MIN) < 100ns
Adjustable Cycle-by-Cycle Current Limit
Programmable Undervoltage Lockout
Output Overvoltage Protection
28-Pin SSOP Package
A precise internal reference provides 0.5% DC accuracy. A
high bandwidth (25MHz) error ampliﬁer provides very fast
line and load transient response. Large 1Ω gate drivers
allow the LTC3810 to drive multiple MOSFETs for higher
current applications. The operating frequency is selected
by an external resistor and is compensated for variations
in VIN and can also be synchronized to an external clock
for switching-noise sensitive applications. A shutdown pin
allows the LTC3810 to be turned off, reducing the supply
current to 240μA.
APPLICATIONS
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Integrated bias control generates gate drive power from the
input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23
MOSFET. When in regulation, power is derived from the
output for higher efﬁciency.
48V Telecom and Base Station Power Supplies
Networking Equipment, Servers
Automotive and Industrial Control Systems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.
TYPICAL APPLICATION
High Efﬁciency High Voltage Step-Down Converter
ION
CSS
1000pF
95
LTC3810
MODE/SYNC
SHDN
M1
Si7456DP
TG
0.1μF
200k
VOUT
12V/6A
SW
DRVCC
INTVCC
SENSE–
BGRTN
VIN = 75V
90
85
RFB1
14k
D1
MBR1100
+
M2
Si7456DP
BG
SGND
L1
10μH
EXTVCC
SENSE+
ITH
VFB
47pF
VIN = 50V
VIN = 25V
BOOST
SS/TRACK
5pF
100
CIN
22μF
M3
ZXMN10A07F
NDRV
PGOOD
VRNG
+
100k
EFFICIENCY (%)
RON
261k
Efﬁciency vs Load Current
VIN
15V TO 100V
COUT
270μF
80
0
1
2
3
LOAD (A)
4
5
6
3810 TA01b
1μF
RFB2
1k
3810 TA01
3810fb
1
LTC3810
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Supply Voltages
INTVCC, DRVCC ...................................... –0.3V to 14V
(DRVCC - BGRTN), (BOOST - SW) ......... –0.3V to 14V
BOOST ................................................ –0.3V to 114V
BGRTN ....................................................... –5V to 0V
EXTVCC .................................................. –0.3V to 15V
(NDRV - INTVCC) Voltage ........................... –0.3V to 10V
SW, SENSE+ Voltage ................................... –1V to 100V
ION Voltage ............................................... –0.3V to 100V
SS/TRACK Voltage ....................................... –0.3V to 5V
PGOOD Voltage ............................................ –0.3V to 7V
VRNG, VON, MODE/SYNC, SHDN,
UVIN Voltages........................................ –0.3V to 14V
PLL/LPF, FB Voltages................................. –0.3V to 2.7V
TG, BG, INTVCC, EXTVCC RMS Currents .................50mA
Operating Temperature Range (Note 2)
LTC3810E............................................. –40°C to 85°C
LTC3810I............................................ –40°C to 125°C
Junction Temperature (Notes 3, 7)........................ 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
TOP VIEW
ION
1
28 BOOST
NC
2
27 TG
NC
3
26 SW
VON
4
25 SENSE+
VRNG
5
24 NC
PGOOD
6
23 NC
MODE/SYNC
7
22 NC
ITH
8
21 SENSE–
VFB
9
20 BGRTN
PLL/LPF 10
19 BG
SS/TRACK 11
18 DRVCC
SGND 12
17 INTVCC
SHDN 13
16 EXTVCC
UVIN 14
15 NDRV
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3810EG#PBF
LTC3810EG#TRPBF
LTC3810EG
28-Lead Plastic SSOP
–40°C to 85°C
LTC3810IG#PBF
LTC3810IG#TRPBF
LTC3810IG
28-Lead Plastic SSOP
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3810EG
LTC3810EG#TR
LTC3810EG
28-Lead Plastic SSOP
–40°C to 85°C
LTC3810IG
LTC3810IG#TR
LTC3810IG
28-Lead Plastic SSOP
–40°C to 125°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV
= 10V, VMODE/SYNC = VSENSE+ = VSENSE – = VBGRTN = VSW =0V, unless otherwise speciﬁed.
SYMBOL
Main Control Loop
INTVCC
IQ
PARAMETER
CONDITIONS
INTVCC Supply Voltage
INTVCC Supply Current
INTVCC Shutdown Current
SHDN > 1.5V, INTVCC = 9.5V (Notes 4, 5)
SHDN = 0V
MIN
l
TYP
MAX
UNITS
3
240
14
6
600
V
mA
μA
6.35
3810fb
2
LTC3810
ELECTRICAL CHARACTERISTICS
The l denotes speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV
= 10V, VMODE/SYNC = VSENSE+ = VSENSE – = VBGRTN = VSW = 0V, unless otherwise speciﬁed.
SYMBOL
IBOOST
PARAMETER
BOOST Supply Current
VFB
Feedback Voltage
ΔVFB,LINE
VSENSE(MAX)
Feedback Voltage Line Regulation
VSENSE(MIN)
Minimum Current Sense Threshold
IVFB
AVOL(EA)
fU
Feedback Current
Error Ampliﬁer DC Open Loop Gain
Error Amp Unity-Gain Crossover
Frequency
MODE/SYNC Threshold
MODE/SYNC Current
Shutdown Threshold
SHDN Pin Input Current
VIN Undervoltage Lockout
VMODE/SYNC
IMODE/SYNC
VSHDN
ISHDN
VVINUV
VVCCUV
Maximum Current Sense Threshold
INTVCC Undervoltage Lockout
Linear Regulator Mode
External Supply Mode
Trickle-Charge Mode
Oscillator and Phase-Locked Loop
On-Time
tON
tON(MIN)
tOFF(MIN)
tON(PLL)
IPLL/LPF
Minimum On-Time
Minimum Off-Time
tON Modulation Range by PLL
Down Modulation
Up Modulation
Phase Detector Output Current
Sinking Capability
Sourcing Capability
CONDITIONS
SHDN > 1.5V (Note 5)
SHDN = 0V
(Note 4)
0°C to 85°C
–40°C to 85°C
–40°C to 125°C (I-Grade)
7V < INTVCC < 14V (Note 4)
MIN
l
l
l
0.796
0.794
0.792
0.792
l
VRNG = 2V, VFB = 0.76V
VRNG = 0V, VFB = 0.76V
VRNG = INTVCC, VFB = 0.76V
VRNG = 2V, VFB = 0.84V
VRNG = 0V, VFB = 0.84V
VRNG = INTVCC, VFB = 0.84V
VFB = 0.8V
256
70
170
65
(Note 6)
VMODE/SYNC Rising
MODE/SYNC = 10V
0.75
1.2
TYP
270
0
0.800
0.800
0.800
0.800
0.002
MAX
400
5
0.804
0.806
0.806
0.808
0.02
320
95
215
–300
–85
–200
20
100
25
384
120
260
0.8
0
1.5
0
0.88
0.80
0.10
0.85
1
2
1
0.92
0.82
0.12
V
μA
V
μA
V
V
V
150
UNITS
μA
μA
V
V
V
V
%/V
mV
mV
mV
mV
mV
mV
nA
dB
MHz
VIN Rising
VIN Falling
Hysteresis
l
l
0.86
0.78
0.07
INTVCC Rising, INDRV = 100μA
INTVCC Rising, NDRV = INTVCC = EXTVCC
INTVCC Rising, NDRV = INTVCC, EXTVCC = 0
INTVCC Falling
l
l
l
6.05
6.05
11.7
6.2
6.2
12
5.7
6.35
6.35
12.3
V
V
V
V
1.55
515
1.85
605
250
2.15
695
100
350
μs
ns
ns
ns
3.6
1.2
5
1.8
μs
μs
ION = 100μA
ION = 300μA
ION = 2000μA
ION = 100μA, VPLL/LPF = 0.6V
ION = 100μA, VPLL/LPF = 1.8V
2.2
0.6
fPLLIN < fSW
fPLLIN > fSW
Driver
IBG,PEAK
RBG,SINK
BG Driver Peak Source Current
BG Driver Pull-Down RDS(ON)
VBG = 0V
ITG,PEAK
RTG,SINK
TG Driver Peak Source Current
TG Driver Pull-Down RDS(ON)
VTG – VSW = 0V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
VFB Rising
VFB Falling
VFB Returning
15
–25
1.5
1.5
μA
μA
2
1
1.5
2
1
Ω
A
A
1.5
Ω
10
–10
1.5
12.5
–12.5
3
%
%
%
PGOOD Output
ΔVFBOV
ΔVFB,HYST
7.5
–7.5
3810fb
3
LTC3810
ELECTRICAL CHARACTERISTICS
The l denotes speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C, INTVCC = DRVCC = VBOOST = VON = VRNG = SHDN = UVIN = VEXTVCC = VNDRV
= 10V, VMODE/SYNC = VSENSE+ = VSENSE– = VBGRTN = VSW = 0V, unless otherwise speciﬁed.
SYMBOL
VPGOOD
IPGOOD
PG Delay
Tracking
ISS/TRACK
VFB,TRACK
VCC Regulators
VEXTVCC
VINTVCC,1
ΔVEXTVCC,1
ΔVLOADREG,1
VINTVCC,2
ΔVLOADREG,2
INDRV
INDRVTO
VCCSR
ICCSR
PARAMETER
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
CONDITIONS
IPGOOD = 5mA
VPGOOD = 5V
VFB Falling
MIN
TYP
0.3
0
120
MAX
0.6
2
SS/TRACK Source Current
Feedback Voltage at Tracking
VSS/TRACK > 0.5V
VTRACK = 0V, ITH = 1.2V (Note 4)
VTRACK = 0.5V, ITH = 1.2V (Note 4)
0.7
1.4
–0.018
0.5
2.5
0.52
μA
V
V
6.7
0.3
10
170
0.5
10.6
250
V
V
V
mV
0.48
UNITS
V
μA
μs
EXTVCC Switchover Voltage
EXTVCC Rising
EXTVCC Hysteresis
INTVCC Voltage from EXTVCC
VEXTVCC – VINTVCC at Dropout
10.5V < VEXTVCC < 15V
ICC = 20mA, VEXTVCC = 9.1V
INTVCC Load Regulation from EXTVCC
ICC = 0mA to 20mA, VEXTVCC = 12V
INTVCC Voltage from NDRV Regulator
INTVCC Load Regulation from NDRV
Linear Regulator in Operation
ICC = 0mA to 20mA, VEXTVCC = 0
9.4
10
0.01
10.6
V
%
Current into NDRV Pin
Linear Regulator Timeout Enable
Threshold
Maximum Supply Voltage
Maximum Current into NDRV/INTVCC
VNDRV – VINTVCC = 3V
20
210
40
270
60
350
μA
μA
l
Maximum VIN
MOSFET Gate Drive
INTVCC UV+
INTVCC
UV–
0.01
Trickle Charger Shunt Regulator
Trickle Charger Shunt Regulator,
INTVCC ≤ 16.7V (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3810E is guaranteed to meet performance speciﬁcations
from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3810I is guaranteed to meet
perfomance speciﬁcations over the full –40°C to 125°C operating
temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3810: TJ = TA + (PD • 100°C/W)
PARAMETER
6.4
0.1
9.4
LTC3810
15
10
%
V
mA
Note 4: The LTC3810 is tested in a feedback loop that servos VFB to the
reference voltage with the ITH pin forced to a voltage between 1V and 2V.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(QG • fOSC).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the speciﬁed maximum operating junction
temperature may impair device reliability.
Note 8: ICC is the sum of current into NDRV and INTVCC.
LTC3810-5
LTC3812-5
100V
60V
60V
6.35V to 14V
4.5V to 14V
4.5V to 14V
6.2V
4.2V
4.2V
6V
4V
4V
3810fb
4
LTC3810
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient Response
Short-Circuit/
Fault Timeout Operation
Start-Up
INTVCC
5V/DIV
VOUT
100mV/
DIV
VOUT
10V/DIV
INTVCC
VOUT
5V/DIV
SS/TRACK
4V/DIV
VIN
50V/DIV
IOUT
5A/DIV
IL
5A/DIV
IL
5A/DIV
3810 G01
50μs/DIV
VIN = 48V
0A TO 5A LOAD STEP
FRONT PAGE CIRCUIT
3810 G02
VIN = 48V
500μs/DIV
ILOAD = 1A
MODE/SYNC = 0V
FRONT PAGE CIRCUIT
Short-Circuit/
Foldback Operation
Tracking
VOUT
5V/DIV
VFB
0.5V/
DIV
3810 G04
200μs/DIV
VIN = 48V
FRONT PAGE CIRCUIT
VFB
ITH
0.5V/DIV
IL
2A/DIV
Efﬁciency vs Load Current
Efﬁciency vs Input Voltage
Frequency vs Input Voltage
100
280
IOUT = 5A
95
IOUT = 0.5A
80
VIN = 12V
10
20
50
40
30
60
INPUT VOLTAGE (V)
70
80
3810 G07
VIN = 60V
270
90
85
80
VOUT = 5V
Si7850 MOSFETs
MODE/SYNC = INTVCC
f = 250kHz
75
f = 250kHz
FRONT PAGE CIRCUIT
VIN = 36V
FREQUENCY (kHz)
EFFICIENCY (%)
90
70
3810 G06
VIN = 48V
20μs/DIV
IOUT = 100mA
MODE/SYNC = INTVCC
FRONT PAGE CIRCUIT
3810 G05
VIN = 48V
500μs/DIV
ILOAD = 1A
MODE/SYNC = 0V
FRONT PAGE CIRCUIT
100
EFFICIENCY (%)
SS/TRACK
VOUT
100mV/
DIV
SS/TRACK
0.5V/DIV
VFB
0.5V/DIV
IL
5A/DIV
IL
5A/DIV
3810 G03
Pulse Skip Mode Operation
VOUT
5V/DIV
70
VIN = 48V
10ms/DIV
RSHORT = 0.1Ω
FRONT PAGE CIRCUIT
0
1
5
2
3
4
LOAD CURRENT (A)
6
IOUT = 0A
260
IOUT = 5A
250
240
7
3810 G08
230
MODE/SYNC = 0V
FRONT PAGE CIRCUIT
10
20
50
40
30
60
INPUT VOLTAGE (V)
70
80
3810 G09
3810fb
5
LTC3810
TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
Frequency vs Load Current
350
400
300
300
On-Time vs ION Current
10000
VON = INTVCC
FORCED
CONTINUOUS
250
200
150
PULSE SKIP
100
50
1.4V
200
1V
0.7V
0.5V
100
0
–100
100
–200
–300
FRONT PAGE CIRCUIT
1
0
2
3
4
–400
5
0
1
1.5
2
ITH VOLTAGE (V)
0.5
LOAD CURRENT (A)
3810 G10
ION = 300μA
600
ON-TIME (ns)
ON-TIME (ns)
500
300
ION = 300μA
640
620
600
200
580
100
560
–50 –25
0
0.5
2
1.5
1
VON VOLTAGE (V)
2.5
3
50
25
75
0
TEMPERATURE (°C)
Maximum Current Sense
Threshold vs VRNG Voltage
100
1.5
125
2
VRNG VOLTAGE (V)
3810 G16
VRNG = INTVCC
200
150
100
50
0
0.2
0
0.4
0.6
0.8
VFB (V)
38125 G15
230
Feedback Reference Voltage
vs Temperature
0.803
VRNG = INTVCC
0.802
220
REFERENCE VOLTAGE (V)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
200
1
100
250
Maximum Current Sense
Threshold vs Temperature
300
0
0.5
3810 G12
3810 G14
3810 G13
400
10000
Current Limit Foldback
660
400
100
1000
ION CURRENT (μA)
10
On-Time vs Temperature
680
0
10
3
3810 G11
On-Time vs VON Voltage
700
2.5
MAXIMUM CURRENT SENSE THRESHOLD (mV)
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
1000
ON-TIME (ns)
CURRENT SENSE THRESHOLD (mV)
FREQUENCY (kHz)
VRNG = 2V
210
200
190
180
–50
0.801
0.800
0.799
0.798
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3810 G17
0.797
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3810 G18
3810fb
6
LTC3810
TYPICAL PERFORMANCE CHARACTERISTICS
Driver Peak Source Current
vs Temperature
2.5
Driver Pull-Down RDS(ON)
vs Temperature
1.50
VBOOST = VINTVCC = 10V
Driver Peak Source Current
vs Supply Voltage
3.0
VBOOST = VINTVCC = 10V
PEAK SOURCE CURRENT (A)
1.00
2.0
RDS(ON) (Ω)
PEAK SOURCE CURRENT (A)
1.25
0.75
0.50
1.5
0.25
1
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
2.0
1.5
1.0
0.5
0
–50 –25
125
2.5
50
25
75
0
TEMPERATURE (°C)
100
0
125
5
6
8 9 10 11 12 13 14 15
7
DRVCC/BOOST VOLTAGE (V)
3810 G20
3810 G19
3810 G21
EXTVCC LDO Resistance at
Dropout vs Temperature
Driver Pull-Down RDS(ON)
vs Supply Voltage
INTVCC Current vs Temperature
4
14
1.1
12
0.8
INTVCC CURRENT (mA)
RESISTANCE (Ω)
0.9
10
8
6
4
0.7
3
2
1
2
6
7
9 10 11 12 13
8
DRVCC/BOOST VOLTAGE (V)
14
15
0
–50 –25
75
50
25
TEMPERATURE (°C)
100
0
125
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
3810 G23
3810 G22
INTVCC Shutdown Current
vs Temperature
100
125
3810 G24
INTVCC Current vs INTVCC Voltage
400
4.0
3.5
300
INTVCC CURRENT (mA)
0.6
INTVCC CURRENT (μA)
RDS(ON) (Ω)
1.0
200
100
3.0
2.5
2.0
1.5
1.0
0.5
0
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
3810 G25
0
0
2
8
6
10
4
INTVCC VOLTAGE (V)
12
14
3810 G26
3810fb
7
LTC3810
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Shutdown Current
vs INTVCC Voltage
SS/TRACK Pull-Up Current
vs Temperature
3
300
SS/TRACK CURRENT (μA)
INTVCC CURRENT (μA)
250
200
150
100
2
1
50
0
–50 –25
0
0
2
8
6
10
4
INTVCC VOLTAGE (V)
12
14
50
25
75
0
TEMPERATURE (°C)
125
3810 G28
3810 G27
ITH Voltage
vs Load Current
Shutdown Threshold
vs Temperature
2.2
3.0
2.0
SHUTDOWN THRESHOLD (V)
2.5
ITH VOLTAGE (V)
100
2.0
1.5
1.0
0.5
0
1
4
3
5
2
LOAD CURRENT (A)
1.6
1.4
1.2
1.0
0.8
VRNG = 0V
FRONT PAGE CIRCUIT
0
1.8
6
7
3810 G29
0.6
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
3810 G30
3810fb
8
LTC3810
PIN FUNCTIONS
ION (Pin 1): On-Time Current Input. Tie a resistor from VIN
to this pin to set the one-shot timer current and thereby
set the switching frequency.
VON (Pin 4): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output voltage
or an external resistive divider from the output makes the
on-time proportional to VOUT. The comparator defaults to
0.7V when the pin is grounded and defaults to 2.4V when
the pin is connected to INTVCC. Tie this pin to INTVCC in
high VOUT applications to use a lower RON value.
VRNG (Pin 5): Sense Voltage Limit Set. The voltage at this
pin sets the nominal sense voltage at maximum output
current and can be set from 0.5V to 2V by a resistive
divider from INTVCC. The nominal sense voltage defaults
to 95mV when this pin is tied to ground, and 215mV when
tied to INTVCC.
PGOOD (Pin 6): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not between ±10% of the regulation point. The output
voltage must be out of regulation for at least 120μs before
the power good output is pulled to ground.
MODE/SYNC (Pin 7): Pulse Skip Mode Enable/Sync Pin.
This multifunction pin provides pulse skip mode enable/
disable control and an external clock input to the phase
detector. Pulling this pin below 0.8V or to an external
logic-level synchronization signal disables pulse skip mode
operation and forces continuous operation. Pulling this
pin above 0.8V enables pulse skip mode operation. For a
clock input, the phase-locked loop will force the rising top
gate signal to be synchronized with the rising edge of the
clock signal.This pin can also be connected to a feedback
resistor divider from a secondary winding on the inductor
to regulate a second output voltage.
ITH (Pin 8): Error Ampliﬁer Compensation Point and Current Control Threshold. The current comparator threshold
increases with control voltage. The voltage ranges from
0V to 2.6V with 1.2V corresponding to zero sense voltage
(zero current).
VFB (Pin 9): Feedback Input. Connect VFB through a resistor
divider network to VOUT to set the output voltage.
PLL/LPF (Pin 10): The phase-locked loop’s lowpass ﬁlter
is tied to this pin. The voltage at this pin defaults to 1.2V
when the IC is not synchronized with an external clock at
the MODE/SYNC pin.
SS/TRACK (Pin 11): Soft-Start/Tracking Input. For softstart, a capacitor to ground at this pin sets the ramp rate of
the output voltage (approximately 0.6s/μF). For coincident
or ratiometric tracking, connect this pin to a resistive divider
between the voltage to be tracked and ground.
SGND (Pin 12): Signal Ground. All small-signal components should connect to this ground and eventually connect
to PGND at one point.
SHDN (Pin 13): Shutdown Pin. Pulling this pin below 1.5V
will shut down the LTC3810, turn off both of the external
MOSFET switches and reduce the quiescent supply current to 240μA.
UVIN (Pin 14): UVLO Input. This pin is input to the internal
UVLO and is compared to an internal 0.8V reference. An
external resistor divider is connected to this pin and the
input supply to program the undervoltage lockout voltage.
When UVIN is less than 0.8V, the LTC3810 is shut down.
NDRV (Pin 15): Drive Output for External Pass Device of
the Linear Regulator for INTVCC. Connect to the gate of
an external NMOS pass device and a pull-up resistor to
the input voltage VIN.
EXTVCC (Pin 16): External Driver Supply Voltage. When
this voltage exceeds 6.7V, an internal switch connects
this pin to INTVCC through an LDO and turns off the external MOSFET connected to NDRV, so that controller and
gate drive are drawn from EXTVCC.
INTVCC (Pin 17): Main Supply Pin. All internal circuits
except the output drivers are powered from this pin.
INTVCC should be bypassed to ground (Pin 10) with at
least a 0.1μF capacitor in close proximity to the LTC3810.
DRVCC (Pin 18): Driver Supply Pin. DRVCC supplies power
to the BG output driver. This pin is normally connected to
INTVCC. DRVCC should be bypassed to BGRTN (Pin 20)
with a low ESR (X5R or better) 1μF capacitor in close
proximity to the LTC3810.
3810fb
9
LTC3810
PIN FUNCTIONS
BG (Pin 19): Bottom Gate Drive. The BG pin drives the
gate of the bottom N-channel synchronous switch MOSFET.
This pin swings from BGRTN to DRVCC.
BGRTN (Pin 20): Bottom Gate Return. This pin connects to
the source of the pull-down MOSFET in the BG driver and
is normally connected to ground. Connecting a negative
supply to this pin allows the synchronous MOSFET ’s gate
to be pulled below ground to help prevent false turn-on
during high dV/dt transitions on the SW node. See the
Applications Information section for more details.
SENSE+, SENSE– (Pin 25, Pin 21): Current Sense Comparator Input. The (+) input to the current comparator is
normally connected to SW unless using a sense resistor.
The (–) input is used to accurately kelvin sense the bottom
side of the sense resistor or MOSFET.
SW (Pin 26): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground
to VIN.
TG (Pin 27): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true ﬂoating drive to the top MOSFET.
BOOST (Pin 28): Top Gate Driver Supply. The BOOST pin
supplies power to the ﬂoating TG driver. BOOST should
be bypassed to SW with a low ESR (X5R or better) 0.1μF
capacitor. An additional fast recovery Schottky diode from
DRVCC to the BOOST pin will create a complete ﬂoating
charge-pumped supply at BOOST.
3810fb
10
LTC3810
FUNCTIONAL DIAGRAM
EXTVCC NDRV INTVCC
INTVCC
0.8V
REF
5V
REG
VIN
INTVCC
MODE
LOGIC
10V
+
NDRV
M3
15
VIN
RUV1
–
12V
UVIN
–
–
14
INTVCC
INTVCC
UV
VIN UV
RUV2
200μA
OFF
6.2V
+
17
EXTVCC
+
16
+
0.8V
+
F
MODE/SYNC
270μA
–
7
10V
+
ON
1.4μA
PLL-SYNC
10
–
+
–
PLL/LPF
+
VON
4
–
100nA
RON
VIN
ION
tON =
1
VVON
(76pF)
IION
R
S
20k
+
6.7V
TG
FCNT
CB
M1
27
SW
26
+
ICMP
SENSE+
SWITCH
LOGIC
IREV
L1
VOUT
25
DRVCC
–
–
CIN
28
ON
Q
+
BOOST
TIMEOUT
LOGIC
DRV OFF
VIN
DB
18
SHDN
BG
OV
×
CVCC
19
M2
BGRTN
+
20
COUT
SENSE–
1.4V
21
OVERTEMP
SENSE
VRNG
PGOOD
ITH’
5
6
FOLDBACK
RFB1
FB
ITH
0.7V
+
4V
8
RC
–
2.6V
VFB
9
CC1
FAULT
EA
+
RUN
SHDN –
– + +
CC2
0.72V
UV
0.8V
+
RFB2
SGND
12
OV
–
0.88V
1.5V
SS/TRACK
11
SHDN
13
3810 FD
3810fb
11
LTC3810
OPERATION
Main Control Loop
The LTC3810 is a current mode controller for DC/DC stepdown converters. In normal operation, the top MOSFET
is turned on for a ﬁxed interval determined by a one-shot
timer (OST). When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator
ICMP trips, restarting the one-shot timer and initiating the
next cycle. Inductor current is determined by sensing the
voltage between the SENSE– and SENSE+ pins using a
sense resistor or the bottom MOSFET on-resistance. The
voltage on the ITH pin sets the comparator threshold corresponding to the inductor valley current. The fast 25MHz
error ampliﬁer EA adjusts this voltage by comparing the
feedback signal VFB to the internal 0.8V reference voltage. If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The ITH voltage
then rises until the average inductor current again matches
the load current.
The operating frequency is determined implicitly by the top
MOSFET on-time and the duty cycle required to maintain
regulation. The one-shot timer generates an on time that is
proportional to the ideal duty cycle, thus holding frequency
approximately constant with changes in VIN. The nominal
frequency can be adjusted with an external resistor RON.
For applications with stringent constant frequency requirements, the LTC3810 can be synchronized with an
external clock. By programming the nominal frequency
the same as the external clock frequency, the LTC3810
behaves as a constant frequency part against the load and
supply variations.
Pulling the SHDN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
Pulse Skip Mode
The LTC3810 can operate in one of two modes selectable
with the MODE/SYNC pin—pulse skip mode or forced
continuous mode (see Figure 1). Pulse skip mode is selected when increased efﬁciency at light loads is desired
(see Figure 2). In this mode, the bottom MOSFET is turned
off when inductor current reverses to minimize efﬁciency
loss due to reverse current ﬂow and gate charge switching.
At low load currents, ITH will drop below the zero current
level (1.2V) shutting off both switches. Both switches will
remain off with the output capacitor supplying the load
current until the ITH voltage rises above the zero current
level to initiate another cycle. In this mode, frequency is
proportional to load current at light loads.
Pulse skip mode operation is disabled by comparator F
when the MODE/SYNC pin is brought below 0.8V, forcing
continuous synchronous operation. Forced continuous
mode is less efﬁcient due to resistive losses, but has the
advantage of better transient response at low currents,
approximately constant frequency operation, and the ability
to maintain regulation when sinking current.
100
90 VIN = 75V
FORCED CONTINUOUS
0A
0A
80
EFFICIENCY (%)
DECREASING
LOAD CURRENT
PULSE SKIP MODE
VIN = 25V
VIN = 25V
70
60
VIN = 75V
50
40
30
0A
0A
20
PULSE SKIP MODE
FORCED CONTINUOUS
10
0A
3810 F01
0A
0
0.01
0.1
1
10
LOAD (A)
3810 F02
Figure 1. Comparison of Inductor Current Waveforms
for Pulse Skip Mode and Forced Continuous Operation
Figure 2. Efﬁciency in Pulse Skip Mode
and Forced Continuous Mode
3810fb
12
LTC3810
OPERATION
Fault Monitoring/Protection
Constant on-time current mode architecture provides accurate cycle-by-cycle current limit protection—a feature
that is very important for protecting the high voltage power
supply from output short circuits. The cycle-by-cycle current monitor guarantees that the inductor current will never
exceed the value programmed on the VRNG pin.
Foldback current limiting provides further protection if the
output is shorted to ground. As VFB drops, the buffered
current threshold voltage ITHB is pulled down and clamped
to 1V. This reduces the inductor valley current level to
one-sixth of its maximum value as VFB approaches 0V.
Foldback current limiting is disabled at start-up.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point after the
internal 120μs power bad mask timer expires. Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
The LTC3810 provides two undervoltage lockout comparators—one for the INTVCC/DRVCC supply and one for
the input supply VIN. The INTVCC UV threshold is 6.2V to
guarantee that the MOSFETs have sufﬁcient gate drive voltage before turning on. The VIN UV threshold (UVIN pin) is
0.8V with 10% hysteresis which allows programming the
VIN threshold with the appropriate resistor divider connected to VIN. If either comparator inputs are under the
UV threshold, the LTC3810 is shut down and the drivers
are turned off.
skip mode operation, where it is possible that the bottom
MOSFET will be off for an extended period of time, an
internal timeout guarantees that the bottom MOSFET is
turned on at least once every 25μs for one on-time period
to refresh the bootstrap capacitor.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-through.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Miller capacitance, even when the bottom driver is holding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-through between the top side and bottom
side MOSFETs can occur. To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V supply is used on BGRTN, the switch node dV/dt could pull
the gate up 2V before the VGS of the bottom MOSFET has
more than 0V across it.
VIN
DRVCC
LTC3810
DRVCC
+
DB
CIN
BOOST
TG
CB
M1
L
SW
VOUT
+
BG
COUT
M2
BGRTN
3810 F03
0V TO –5V
Figure 3. Floating TG Driver Supply and Negative BG Return
Strong Gate Drivers
The LTC3810 contains very low impedance drivers capable
of supplying amps of current to slew large MOSFET gates
quickly. This minimizes transition losses and allows paralleling MOSFETs for higher current applications. A 100V
ﬂoating high side driver drives the top side MOSFET and
a low side driver drives the bottom side MOSFET (see
Figure 3). The bottom side driver is supplied directly
from the DRVCC pin. The top MOSFET drivers are biased
from ﬂoating bootstrap capacitor, CB, which normally is
recharged during each off cycle through an external diode
from DRVCC when the top MOSFET turns off. In pulse
IC/Driver Supply Power
The LTC3810’s internal control circuitry and top and bottom
MOSFET drivers operate from a supply voltage (INTVCC,
DRVCC pins) in the range of 6.2V to 14V. The LTC3810
has two integrated linear regulator controllers to easily
generate this IC/driver supply from either the high voltage
input or from the output voltage. For best efﬁciency the
supply is derived from the input voltage during start-up
and then derived from the lower voltage output as soon
as the output is higher than 6.7V. Alternatively, the supply
can be derived from the input continuously if the output
3810fb
13
LTC3810
OPERATION
is < 6.7V or an external supply in the appropriate range
can be used. The LTC3810 will automatically detect which
mode is being used and operate properly.
The four possible operating modes for generating this
supply are summarized as follows (see Figure 4):
1. LTC3810 generates a 10V start-up supply from a small
external SOT23 N-channel MOSFET acting as linear
regulator with drain connected to VIN and gate controlled
by the LTC3810’s internal linear regulator controller
through the NDRV pin. As soon as the output voltage
reaches 6.7V, the 10V IC/driver supply is derived from
the output through an internal low dropout regulator to
optimize efﬁciency. If the output is lost due to a short,
the LTC3810 goes through repeated low duty cycle
soft-start cycles (with the drivers shut off in between)
to attempt to bring up the output without burning up
the SOT23 MOSFET. This scheme eliminates the long
start-up times associated with a conventional trickle
charger by using an external MOSFET to quickly charge
the IC/driver supply capacitors (CINTVCC, CDRVCC).
start-up. The MOSFET is sized for proper dissipation and
the driver shutdown/restart for VOUT < 6.7V is disabled.
This scheme is less efﬁcient but may be necessary if
VOUT < 6.7V and a boost network is not desired.
3. Trickle charge mode provides an even simpler approach
by eliminating the external MOSFET. The IC/driver supply capacitors are charged through a single high valued
resistor connected to the input supply. When the INTVCC
voltage reaches the turn-on threshold of 12V (automatically raised from 6.7V to provide extra headroom for
start-up), the drivers turn on and begin charging up the
output capacitor. When the output reaches 6.7V, IC/driver
power is derived from the output. In trickle-charge mode,
the supply capacitors must have sufﬁcient capacitance
such that they are not discharged below the 6V INTVCC
UV threshold before the output is high enough to take
over or else the power supply will not start.
4. Low voltage supply available. The simplest approach is if
a low voltage supply (between 6.2V and 14V) is available
and connected directly to the IC/driver supply pins.
2. Similar to (1) except that the external MOSFET is used
for continuous IC/driver power instead of just for
Mode 1: MOSFET for Start-Up Only
Mode 2: MOSFET for Continuous Use
VIN
VIN
I > 270μA
I < 270μA
NDRV
NDRV
INTVCC
+
10V
LTC3810
INTVCC
+
10V
LTC3810
VOUT (>6.7V)
EXTVCC
Mode 3: Trickle Charge Mode
VIN
EXTVCC
Mode 4: External Supply
NDRV
INTVCC
NDRV
+
LTC3810
EXTVCC
10V
INTVCC
LTC3810
VOUT
EXTVCC
+
+
–
6.2V to
14V
3810 F04
Figure 4. Operating Modes for IC/Driver Supply
3810fb
14
LTC3810
APPLICATIONS INFORMATION
The basic LTC3810 application circuit is shown on the ﬁrst
page of this data sheet. External component selection is
primarily determined by the maximum input voltage and
load current and begins with the selection of the sense
resistance and power MOSFET switches. The LTC3810
uses either a sense resistor or the on-resistance of the
synchronous power MOSFET for determining the inductor
current. The desired amount of ripple current and operating
frequency largely determines the inductor value. Next, CIN
is selected for its ability to handle the large RMS current
into the converter and COUT is chosen with low enough
ESR to meet the output voltage ripple and transient
speciﬁcation. Finally, loop compensation components
are selected to meet the required transient/phase margin
speciﬁcations.
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage across a sense resistance that appears between the
SENSE– and SENSE+ pins. The maximum sense voltage
is set by the voltage applied to the VRNG pin and is equal
to approximately:
VSENSE(MAX) = 0.173VRNG – 0.026
The current mode control loop will not allow the inductor
current valleys to exceed VSENSE(MAX)/RSENSE. In practice, one should allow some margin for variations in the
LTC3810 and external component values and a good guide
for selecting the sense resistance is:
RSENSE =
VSENSE(MAX)
1.3 •IOUT(MAX)
the sense resistor. Using a sense resistor provides a well
deﬁned current limit, but adds cost and reduces efﬁciency.
Alternatively, one can eliminate the sense resistor and use
the bottom MOSFET as the current sense element by simply
connecting the SENSE+ pin to the lower MOSFET drain
and SENSE – pin to the MOSFET source. This improves
efﬁciency, but one must carefully choose the MOSFET
on-resistance, as discussed below.
Power MOSFET Selection
The LTC3810 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage BVDSS,
threshold voltage V(GS)TH, on-resistance RDS(ON), input
capacitance and maximum current IDS(MAX).
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically speciﬁed with
a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
RDS(ON)(MAX) =
RSENSE
T
The ρT term is a normalization factor (unity at 25°C)
accounting for the signiﬁcant variation in on-resistance
with temperature (see Figure 5) and typically varies
from 0.4%/°C to 1.0%/°C depending on the particular
MOSFET used.
Connecting the SENSE+ and SENSE– Pins
The LTC3810 can be used with or without a sense resistor. When using a sense resistor, place it between the
source of the bottom MOSFET, M2, and PGND. Connect
the SENSE+ and SENSE– pins to the top and bottom of
ρT NORMALIZED ON-RESISTANCE
2.0
An external resistive divider from INTVCC can be used
to set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 60mV to 320mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 95mV
or 215mV, respectively.
1.5
1.0
0.5
0
–50
50
100
0
JUNCTION TEMPERATURE (°C)
150
3810 F05
Figure 5. RDS(ON) vs Temperature
3810fb
15
LTC3810
APPLICATIONS INFORMATION
The most important parameter in high voltage applications
is breakdown voltage BVDSS. Both the top and bottom
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source during its off-time and must be chosen with the appropriate
breakdown speciﬁcation. Since most MOSFETs in the 60V
to 100V range have higher thresholds (typically VGS(MIN)
≥ 6V), the LTC3810 is designed to be used with a 6.2V to
14V gate drive supply (DRVCC pin).
For maximum efﬁciency, on-resistance RDS(ON) and input
capacitance should be minimized. Low RDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combination of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 6).
VIN
VGS
MILLER EFFECT
a
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
+V
DS
–
–
3810 F06
Figure 6. Gate Charge Characteristic
The curve is generated by forcing a constant input current into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The ﬂat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is ﬂat) is speciﬁed for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying by the ratio of the application VDS to the curve
speciﬁed VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
VDS voltage speciﬁed. CMILLER is the most important selection criteria for determining the transition loss term in
the top MOSFET but is not directly speciﬁed on MOSFET
data sheets. CRSS and COS are speciﬁed sometimes but
deﬁnitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
MainSwitchDutyCycle =
VOUT
VIN
SynchronousSwitchDutyCycle =
VIN – VOUT
VIN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
VOUT
2
IMAX ) (T )RDS(ON) +
(
VIN
I
VIN2 MAX (RDR )(CMILLER ) •
2
1 1
+
(f)
VCC – VTH(IL) VTH(IL) V –V
PBOT = IN OUT (IMAX )2(T )RDS(0N)
VIN
PTOP =
where ρT is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
in drain potential in the particular application. VTH(IL) is
the data sheet speciﬁed typical gate threshold voltage
speciﬁed in the power MOSFET data sheet at the speciﬁed
drain current. CMILLER is the calculated capacitance using
the gate charge curve from the MOSFET data sheet and
the technique described above.
Both MOSFETs have I2R losses while the topside N-channel
equation incudes an additional term for transition losses,
which peak at the highest input voltage. For high input
voltage low duty cycle applications that are typical for the
LTC3810, transition losses are the dominate loss term and
therefore using higher RDS(ON) device with lower CMILLER
usually provides the highest efﬁciency. The synchronous
MOSFET losses are greatest at high input voltage when
the top switch duty factor is low or during a short circuit
when the synchronous switch is on close to 100% of
3810fb
16
LTC3810
APPLICATIONS INFORMATION
the period. Since there is no transition loss term in the
synchronous MOSFET, optimal efﬁciency is obtained by
minimizing RDS(ON)— by using larger MOSFETs or paralleling multiple MOSFETs.
Multiple MOSFETs can be used in parallel to lower
RDS(ON) and meet the current and thermal requirements
if desired. The LTC3810 contains large low impedance
drivers capable of driving large gate capacitances without
signiﬁcantly slowing transition times. In fact, when driving MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (10Ω or less) to reduce noise and EMI caused
by the fast transitions.
Operating Frequency
The choice of operating frequency is a tradeoff between
efﬁciency and component size. Low frequency operation
improves efﬁciency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3810 applications is determined implicitly by the one-shot timer that controls
the on-time, tON, of the top MOSFET switch. The on-time
is set by the current out of the ION pin and the voltage at
the VON pin according to:
tON =
VVON
(76pF)
IION
Tying a resistor RON from VIN to the ION pin yields an
on-time inversely proportional to VIN. For a step-down
converter, this results in approximately constant frequency
operation as the input supply varies:
f=
VOUT
[H ]
VVON • RON(76pF) Z
To hold frequency constant during output voltage changes,
tie the VON pin to VOUT or to a resistive divider from VOUT
when VOUT > 2.4V. The VON pin has internal clamps that
limit its input to the one-shot timer. If the pin is tied below
0.7V, the input to the one-shot is clamped at 0.7V. Similarly,
if the pin is tied above 2.4V, the input is clamped at 2.4V.
In high VOUT applications, tie VON to INTVCC. Figures 7a
and 7b show how RON relates to switching frequency for
several common output voltages.
Changes in the load current magnitude will cause frequency
shift. Parasitic resistance in the MOSFET switches and
inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current
increases. By lengthening the on-time slightly as current
increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from
the ITH pin to the VON pin and VOUT. The values required
will depend on the parasitic resistances in the speciﬁc
1000
1000
VOUT = 3.3V
VOUT = 1.5V
VOUT = 2.5V
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
VOUT = 5V
VOUT = 12V
VOUT = 5V
VOUT = 3.3V
100
100
10
100
RON (kΩ)
1000
3810 F07a
Figure 7a. Switching Frequency vs RON (VON = 0V)
10
100
RON (kΩ)
1000
3810 F07b
Figure 7b. Switching Frequency vs RON (VON = INTVCC)
3810fb
17
LTC3810
APPLICATIONS INFORMATION
application. A good starting point is to feed about 25%
of the voltage change at the ITH pin to the VON pin as
shown in Figure 8. Place capacitance on the VON pin to
ﬁlter out the ITH variations at the switching frequency.
VON
CVON
0.01μF
RVON2
30k
100k
LTC3810
ITH
3810 F08
Figure 8. Correcting Frequency Shift with Load Current Changes
Minimum Off-Time and Dropout Operation
The minimum off-time, tOFF(MIN), is the smallest amount
of time that the LTC3810 is capable of turning on the bottom MOSFET, tripping the current comparator and turning
the MOSFET back off. This time is generally about 250ns.
The minimum off-time limit imposes a maximum duty
cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle
is reached, due to a dropping input voltage for example,
then the output will drop out of regulation. The minimum
input voltage to avoid dropout is:
VIN(MIN) = VOUT
tON + tOFF(MIN)
tON
A plot of maximum duty cycle vs frequency is shown in
Figure 9.
2.0
SWITCHING FREQUENCY (MHz)
Given the desired input and output voltages, the inductor value and operating frequency determine the ripple
current:
V V IL = OUT 1 OUT VIN f L RVON1
200k
INTVCC
10V
Inductor Selection
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efﬁciency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efﬁciency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a speciﬁed maximum, the inductance
should be chosen according to:
V
VOUT OUT
1
L=
f IL(MAX) VIN(MAX) Once the value for L is known, the type of inductor must
be selected. High efﬁciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ® cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
Coilcraft and Toko.
1.5
DROPOUT
REGION
Schottky Diode D1 Selection
1.0
0.5
0
0
0.25
0.50
0.75
DUTY CYCLE (VOUT/VIN)
1.0
3810 F09
Figure 9. Maximum Switching Frequency vs Duty Cycle
The Schottky diode D1 shown in the front page schematic
conducts during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diode of the bottom MOSFET from turning on and
storing charge during the dead time, which can cause a
modest (about 1%) efﬁciency loss. The diode can be rated
for about one half to one ﬁfth of the full load current since
it is on for only a fraction of the duty cycle. In order for the
3810fb
18
LTC3810
APPLICATIONS INFORMATION
diode to be effective, the inductance between it and the
bottom MOSFET must be as small as possible, mandating
that these components be placed adjacently. The diode can
be omitted if the efﬁciency loss is tolerable.
Input Capacitor Selection
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT/VIN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
1/2
VOUT VIN
ICIN(RMS) IO(MAX)
– 1
V V
IN
OUT
This formula has a maximum at VIN = 2VOUT, where IRMS =
IO(MAX)/2. This simple worst-case condition is commonly
used for design because even signiﬁcant deviations do not
offer much relief. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be placed in parallel to meet size or height requirements
in the design.
Because tantalum and OS-CON capacitors are not available
in voltages above 30V, ceramics or aluminum electrolytics
must be used for regulators with input supplies above 30V.
Ceramic capacitors have the advantage of very low ESR
and can handle high RMS current, but ceramics with high
voltage ratings (> 50V) are not available with more than
a few microfarads of capacitance. Furthermore, ceramics have high voltage coefﬁcients which means that the
capacitance values decrease even more when used at the
rated voltage. X5R and X7R type ceramics are recommended for their lower voltage and temperature coefﬁcients. Another consideration when using ceramics is
their high Q which, if not properly damped, may result in
excessive voltage stress on the power MOSFETs. Aluminum electrolytics have much higher bulk capacitance, but
they have higher ESR and lower RMS current ratings.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low ESR
and RMS current. If the RMS current cannot be handled
by the aluminum capacitors alone, when used together,
the percentage of RMS current that will be supplied by the
aluminum capacitor is reduced to approximately:
1
% IRMS,ALUM • 100%
2
1+ (8fCRESR )
where RESR is the ESR of the aluminum capacitor and C
is the overall capacitance of the ceramic capacitors. Using
an aluminum electrolytic with a ceramic also helps damp
the high Q of the ceramic, minimizing ringing.
Output Capacitor Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(ΔVOUT) is approximately equal to:
1 VOUT IL ESR +
8fCOUT Since ΔIL increases with input voltage, the output ripple
is highest at maximum input voltage. ESR also has a
signiﬁcant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of COUT until the feedback loop in the LTC3810 can
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisﬁed the
capacitance is adequate for ﬁltering and has the required
RMS current rating.
Manufacturers such as Nichicon, Nippon Chemi-Con
and Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semiconductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electrolytic at a somewhat higher price. An additional ceramic
capacitor in parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special
polymer and aluminum electrolytic capacitors are available
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
3810fb
19
LTC3810
APPLICATIONS INFORMATION
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX, TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have signiﬁcantly higher ESR, but
can be used in cost-driven applications providing that
consideration is given to ripple current ratings and longterm reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs.
Output Voltage
The LTC3810 output voltage is set by a resistor divider
according to the following formula:
R VOUT = 0.8V 1+ FB1 RFB2 The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error ampliﬁer. The internal reference has a guaranteed
tolerance of < 1%. Tolerance of the feedback resistors
will add additional error to the output voltage. 0.1% to
1% resistors are recommended.
Input Voltage Undervoltage Lockout
A resistor divider connected from the input supply to the
UVIN pin (see Functional Diagram) is used to program the
input supply undervoltage lockout thresholds. When the
rising voltage at UVIN reaches 0.88V, the LTC3810 turns
on, and when the falling voltage at UVIN drops below 0.8V,
the LTC3810 is shut down—providing 10% hysteresis.
The input voltage UVLO thresholds are set by the resistor
divider according to the following formulas:
R VIN,FALLING = 0.8V • 1+ UV1 RUV2 and
R VIN,RISING = 0.88V • 1+ UV1 RUV2 If input supply undervoltage lockout is not needed, it can
be disabled by connecting UVIN to INTVCC .
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. This capacitor is charged through diode DB from
DRVCC when the switch node is low. When the top MOSFET
turns on, the switch node rises to VIN and the BOOST pin
rises to approximately VIN + INTVCC. The boost capacitor
needs to store about 100 times the gate charge required
by the top MOSFET. In most applications 0.1μF to 0.47μF,
X5R or X7R dielectric capacitor is adequate.
The reverse breakdown of the external diode, DB, must
be greater than VIN(MAX). Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse
current to ﬂow at full reverse voltage. If the reverse current times reverse voltage exceeds the maximum allowable power dissipation, the diode may be damaged. For
best results, use an ultrafast recovery diode such as the
MMDL770T1.
Bottom MOSFET Driver Return Supply (BGRTN)
The bottom gate driver, BG, switches from DRVCC to
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,
the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will occur. By using a negative supply on BGRTN, the BG can be
pulled below ground when turning the bottom MOSFET off.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
that the maximum voltage difference between DRVCC and
BGRTN is 14V. If, for example, VBGRTN = –2V, the maximum
voltage on DRVCC pin is now 12V instead of 14V.
IC/MOSFET Driver Supplies (INTVCC and DRVCC)
The LTC3810 drivers are supplied from the DRVCC and
BOOST pins (see Figure 3), which have an absolute maximum voltage of 14V. Since the main supply voltage, VIN
3810fb
20
LTC3810
APPLICATIONS INFORMATION
is typically much higher than 14V a separate supply for
the IC power (INTVCC) and driver power (DRVCC) must
be used. The LTC3810 has integrated bias supply control
circuitry that allows the IC/driver supply to be easily
generated from VIN and/or VOUT with minimal external
components. There are four ways to do this as shown in
the simpliﬁed schematics of Figure 4 and explained in the
following sections.
from overheating. Soft-start cycles are then attempted at
low duty cycle intervals to try to bring the output back up
(see Figure 10). This fault timeout operation is enabled
by choosing the choosing RNDRV such that the resistor
current INDRV is greater than 270μA by using the following formulas:
Using the Linear Regulator for INTVCC/DRVCC Supply
where
ICC = (f) QG(TOP) + QG(BOTTOM) + 3mA
In Mode 1, a small external SOT23 MOSFET, controlled by
the NDRV pin, is used to generate a 10V start-up supply
from VIN. The small SOT23 package can be used because
the NMOS is on continuously only during the brief start-up
period. As soon as the output voltage reaches 6.7V, the
LTC3810 turns off the external NMOS and the LTC3810
regulates the 10V supply from the EXTVCC pin (connected
to VOUT or a VOUT derived boost network) through an
internal low dropout regulator. For this mode to work
properly, EXTVCC must be in the range 6.7V < EXTVCC <
15V. If VOUT < 6.7V, a charge pump or extra winding can
be used to raise EXTVCC to the proper voltage, or alternatively, Mode 2 should be used as explained later in this
section. If VOUT is shorted or otherwise goes below the
minimum 6.5V threshold, the MOSFET connected to VIN
is turned back on to maintain the 10V supply. However if
the output cannot be brought up within a timeout period,
the drivers are turned off to prevent the SOT23 MOSFET
FAULT TIMEOUT
ENABLED
SS/TRACK
RNDRV PMOSFET(MAX) / ICC VTH
270μA
(
)
and VTH is the threshold voltage of the MOSFET.
The value of R NDRV also affects the V IN(MIN) as
follows:
VIN(MIN) = VINTVCC(MIN) + (40μA) RNDRV +VT
(1)
where VINTVCC(MIN) is normally 6V for driving 60V to 100V
MOSFETs. If minimum VIN is not low enough, consider
reducing RNDRV and/or using a darlington NPN instead of
an NMOS to reduce VT to ~1.4V.
When using RNDRV equal to the computed value, the
LTC3810 will enable the low duty cycle soft-start retries
only when the desired maximum power dissipation,
PMOSFET(MAX), in the MOSFET is exceeded and leave the
drivers on continuously otherwise. The shutoff/restart
times are a function of the TRACK/SS capacitor value.
DRIVER OFF THRESHOLD
DRIVER POWER
FROM VOUT
DRIVER POWER
FROM VIN
ISS/TRACK = 1.4MA (SOURCE)
DRIVER POWER
FROM VIN
START-UP
ISS/TRACK = 0.1MA (SINK)
EXTVCC UV THRESHOLD
VOUT
SHORT-CIRCUIT EVENT
START-UP INTO SHORT-CIRCUIT
TG/BG
3810 F10
Figure 10. Fault Timeout Operation
3810fb
21
LTC3810
APPLICATIONS INFORMATION
The external NMOS for the linear regulator should be a
standard 3V threshold type (i.e., not a logic level threshold).
The rate of charge of INTVCC from 0V to 10V is controlled
by the LTC3810 to be approximately 75μs regardless of
the size of the capacitor connected to the INTVCC pin. The
charging current for this capacitor is approximately:
10V
IC = 75μs
CINTVCC
The safe operating area (SOA) for the external NMOS
should be chosen so that capacitor charging does not
damage the NMOS. Excessive values of capacitor are
unnecessary and should be avoided. Typically values in
the 1μF to 10μF work well.
One more design requirement for this mode is the minimum
soft-start capacitor value. The fault timeout is enabled
when SS/TRACK voltage is greater than 4V. This gives the
power supply time to bring the output up before it starts
the timeout sequence. To prevent timeout sequence from
starting prematurely during start-up, a minimum CSS value
is necessary to ensure that VSS/TRACK < 4V until VEXTVCC
> 6.7V. To ensure this, choose:
CSS > COUT • (2.3 × 10–6)/IOUT(MAX)
Mode 2 should be used if VOUT is outside of the 6.7V <
EXTVCC < 15V operating range and the extra complexity
of a charge pump or extra inductor winding is not wanted
to boost this voltage above 6.7V. In this mode, EXTVCC is
grounded and the NMOS is chosen to handle the worstcase power dissipation:
(
) (
)
PMOSFET = VIN(MAX) ( f ) QG(TOP) + QG(BOTTOM) + 3mA To operate properly, the fault timeout operation must be
disabled by choosing
If the required RNDRV value results in an unacceptable
value for VIN(MIN) (see Equation 1), fault timeout operation
can also be disabled by connecting a 500k to 2M resistor
from the SS/TRACK pin to INTVCC.
Using Trickle Charge Mode
Trickle charge mode is selected by shorting NDRV and
INTVCC and connecting EXTVCC to VOUT. Trickle charge
mode has the advantage of not requiring an external
MOSFET but takes longer to start up due to slow charge
up of CINTVCC and CDRVCC through RPULLUP (tDELAY = 0.77
• RPULLUP • CDRVCC) and usually requires larger INTVCC/
DRVCC capacitor values to hold up the supply voltage during start-up. Once the INTVCC/DRVCC voltage reaches the
trickle charge UV threshold of 12V, the drivers will turn on
and start discharging CINTVCC/CDRVCC at a rate determined
by the driver current IG. In order to ensure proper startup, CINTVCC/CDRVCC must be chosen large enough so that
the EXTVCC voltage reaches the switchover threshold of
6.7V before CINTVCC/CDRVCC discharges below the falling
UV threshold of 6V. This is ensured if:
CINTVCC + CDRVCC >IG •
5.5 • 105 • CSS COUT
or
L arger of
IMAX
VOUT(REG) where IG is the gate drive current = (f)(QG(TOP) + QG(BOTTOM))
and IMAX is the maximum inductor current selected by
VRNG.
For RPULLUP , the value should fall in the following range
to ensure proper start-up:
Min RPULLUP > (VIN(MAX)–14V)/ICCSR
Max RPULLUP < (VIN(MIN)–12V)/IQ,SHUTDOWN
RNDRV > (VIN(MAX) – 10V – VTH)/270μA
3810fb
22
LTC3810
APPLICATIONS INFORMATION
Using an External Supply Connected to the INTVCC/
DRVCC Pins
If an external supply is available between 6.2V and 14V,
the supply can be connected directly to the INTVCC/DRVCC
pins. In this mode, INTVCC, EXTVCC and NDRV must be
shorted together.
INTVCC/DRVCC Supply and the EXTVCC Connection
The LTC3810 contains an internal low dropout regulator to
produce the 10V INTVCC/DRVCC supply from the EXTVCC
pin voltage. This regulator turns on when the EXTVCC pin
is above 6.7V and remains on until EXTVCC drops below
6.4V. This allows the IC/MOSFET power to be derived from
the output or an output derived boost network during
normal operation and from the external NMOS from VIN
during start-up or short-circuit. Using the EXTVCC pin in
this way results in signiﬁcant efﬁciency gains compared
to what would be possible when deriving this power
continuously from the typically much higher VIN voltage.
The EXTVCC connection also allows the power supply to
be conﬁgured in trickle charge mode in which it starts up
with a high valued “bleed” resistor connected from VIN
to INTVCC to charge up the INTVCC capacitor. As soon as
the output rises above 6.7V the internal EXTVCC regulator
takes over before the INTVCC capacitor discharges below
the UV threshold. When the EXTVCC regulator is active,
the EXTVCC pin can supply up to 50mA RMS. Do not apply more than 15V to the EXTVCC pin. The following list
summarizes the possible connections for EXTVCC:
1. EXTVCC grounded. This connection will require INTVCC
to be powered continuously from an external NMOS
from VIN resulting in an efﬁciency penalty as high as
10% at high input voltages.
2. EXTVCC connected directly to VOUT. This is the normal
connection for 6.7V < VOUT < 15V and provides the
highest efﬁciency. The power supply will start up using
an external NMOS or a bleed resistor until the output
supply is available.
3. EXTVCC connected to an output-derived boost network.
If VOUT < 6.7V. The low voltage output can be boosted
using a charge pump or ﬂyback winding to greater
than 6.7V.
4. EXTVCC connected to INTVCC. This is the required
connection for EXTVCC if INTVCC is connected to an
external supply where the external supply is 6.2V <
VEXT < 15V.
Applications using large MOSFETs with a high input voltage and high frequency of operation may result in a large
EXTVCC pin current. Therefore, it is good design practice
to verify that the maximum junction temperature rating
and RMS current rating are within the maximum limits.
Typically, most of the EXTVCC current consists of the
MOSFET gates current. In continuous mode operation,
this EXTVCC current is:
(
)
IEXTVCC = f QG(TOP) + QG(BOTTOM) + 3mA < 50mA
The junction temperature can be estimated from the
equations given in Note 2 of the Electrical Characteristics
as follows:
TJ = TA + IEXTVCC • (VEXTVCC – VINTVCC)(100°C/W)
< 125°C
If absolute maximum ratings are exceeded, consider
using an external supply connected directly to the
INTVCC pin.
3810fb
23
LTC3810
APPLICATIONS INFORMATION
C2
IN
C1
R2
R1
FB
–6dB/OCT
GAIN
–6dB/OCT
–
OUT
RB
0
FREQ
+
VREF
–90
–180
PHASE
–270
–360
3810 F11
Figure 11. Type 2 Schematic and Transfer Function
IN
C2
C3
R1
R3
FB
R2
C1
–6dB/OCT
–
GAIN
OUT
RB
VREF
PHASE (DEG)
So far, the AC response of the loop is pretty well out of the
user’s control. The modulator is a fundamental piece of
the LTC3810 design and the external output capacitor is
usually chosen based on the regulation and load current
requirements without considering the AC loop response.
The feedback ampliﬁer, on the other hand, gives us a
handle with which to adjust the AC response. The goal is
to have 180° phase shift at DC (so the loop regulates), and
something less than 360° phase shift (preferably about
300°) at the point that the loop gain falls to 0dB, i.e., the
crossover frequency, with as much gain as possible at
frequencies below the crossover frequency. Since the
modulator/output ﬁlter is a ﬁrst order system with maximum of 90° phase shift (at frequencies below fSW/4) and
the feedback ampliﬁer adds another 90° of phase shift,
some phase boost is required at the crossover frequency
to achieve good phase margin. If the ESR zero is below the
The two types of compensation networks, “Type 2” and
“Type 3” are shown in Figures 11 and 12. When component values are chosen properly, these networks provide
a “phase bump” at the crossover frequency. Type 2 uses
a single pole-zero pair to provide up to about 60° of phase
boost while Type 3 uses two poles and two zeros to provide
up to 150° of phase boost.
PHASE (DEG)
In a typical LTC3810 circuit, the feedback loop consists
of the modulator, the output ﬁlter and load, and the
feedback ampliﬁer with its compensation network. All of
these components affect loop behavior and must be accounted for in the loop compensation. The modulator and
output ﬁlter consists of the internal current comparator,
the output MOSFET drivers and the external MOSFETs,
inductor and output capacitor. Current mode control
eliminates the effect of the inductor by moving it to the
inner loop, reducing it to a ﬁrst order system. From a
feedback loop point of view, it looks like a linear voltage
controlled current source from ITH to VOUT and has a gain
equal to (IMAXROUT)/1.2V. It has fairly benign AC behavior
at typical loop compensation frequencies with signiﬁcant
phase shift appearing at half the switching frequency. The
external output capacitor and load cause a ﬁrst order roll
off at the output at the ROUTCOUT pole frequency, with
the attendant 90° phase shift. This roll off is what ﬁlters
the PWM waveform, resulting in the desired DC output
voltage. The output capacitor also contributes a zero at
the COUTRESR frequency which adds back the 90° phase
and cancels the ﬁrst order roll off.
GAIN (dB)
Feedback Loop Types
crossover frequency, this zero may provide enough phase
boost to achieve the desired phase margin and the only
requirement of the compensation will be to guarantee that
the gain is below zero at frequencies above fSW/4. If the
ESR zero is above the crossover frequency, the feedback
ampliﬁer will probably be required to provide phase boost.
For most LTC3810 applications, Type 2 compensation will
provide enough phase boost; however some applications
where high bandwidth is required with low ESR ceramics
and lots of bulk capacitance, Type 3 compensation may
be necessary to provide additional phase boost.
GAIN (dB)
FEEDBACK LOOP/COMPENSATION
+6dB/OCT
–6dB/OCT
0
FREQ
+
–90
PHASE
–180
–270
–360
3810 F12
Figure 12. Type 3 Schematic and Transfer Function
3810fb
24
LTC3810
APPLICATIONS INFORMATION
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or Type 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable performance with similar power components, but can be way off if
even one major power component is changed signiﬁcantly.
Applications that require optimized transient response will
require recalculation of the compensation values speciﬁcally for the circuit in question. The underlying mathematics
are complex, but the component values can be calculated
in a straightforward manner if we know the gain and phase
of the modulator at the crossover frequency.
Modulator gain and phase can be obtained in one of
three ways: measured directly from a breadboard, or if
the appropriate parasitic values are known, simulated or
generated from the modulator transfer function. Measurement will give more accurate results, but simulation
or transfer function can often get close enough to give
a working system. To measure the modulator gain and
phase directly, wire up a breadboard with an LTC3810
and the actual MOSFETs, inductor and input and output
capacitors that the ﬁnal design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close
to the LTC3810, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
ampliﬁer with a 0.1μF feedback capacitor from ITH to FB
and a 10k to 100k resistor from VOUT to FB. Choose the
bias resistor (RB) as required to set the desired output
voltage. Disconnect RB from ground and connect it to
a signal generator or to the source output of a network
analyzer to inject a test signal into the loop. Measure the
gain and phase from the ITH pin to the output node at the
positive terminal of the output capacitor. Make sure the
analyzer’s input is AC coupled so that the DC voltages
present at both the ITH and VOUT nodes don’t corrupt the
measurements or damage the analyzer.
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor
and MOSFET values into the following SPICE deck and
generate an AC plot of VOUT / VITH with gain in dB and
phase in degrees. Refer to your SPICE manual for details
of how to generate this plot.
*3810 modulator gain/phase
*2006 Linear Technology
*this file simulates a simplified model of
*the LTC3810 for generating a v(out)/v(ith)
*bode plot
.param rdson=.0135 ;MOSFET rdson
.param Vrng=2
;use 1.4 for INTVCC and
0.7
.param
.param
.param
for ground
vsnsmax={0.173*Vrng-0.026}
Imax={vsnsmax/rdson}
DL=4
;inductor ripple current
*inductor current
gl out 0 value={(v(ith)-1.2)*Imax/1.2+DL/2}
*output cap
cout out out2 270u ;capacitor value
resr out2 0 0.018 ;capacitor ESR
*load
Rout out 0 2 ; load resistor
vstim ith 0 0 ac 1 ;ac stimulus
.ac dec 100 100 10meg
.probe
.end
Mathematical software such as MATHCAD or MATLAB
can also be used to generate plots using the following
transfer function of the modulator:
VSENSE(MAX) 1+ s • R
ESR • COUT • R
H(s) = •
L (2)
1.2 • RDS(ON) 1+ s • RL • COUT s = j2f
3810fb
25
LTC3810
APPLICATIONS INFORMATION
Finally, choose a convenient resistor value for R1 (10k
is usually a good value). Now calculate the remaining
values:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
TYPE 2 Loop:
BOOST
K = tan + 45°
2
1
C2 =
2 • f • G • K • R1
(
)
C1= C2 K 2 1
K
2 • f • C1
V (R1)
RB = REF
VOUT VREF
R2 =
GAIN (dB)
0
0
PHASE
–90
–180
FREQUENCY (Hz)
3810 F13
Figure 13. Transfer Function of Buck Modulator
BOOST = – (PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
GAIN
PHASE (DEG)
With the gain/phase plot in hand, a loop crossover frequency can be chosen. Usually the curves look something
like Figure 13. Choose the crossover frequency about 25%
of the switching frequency for maximum bandwidth. Although it may be tempting to go beyond fSW/4, remember
that signiﬁcant phase shift occurs at half the switching
frequency that isn’t modeled in the above H(s) equation
and PSPICE code. Note the gain (GAIN, in dB) and phase
(PHASE, in degrees) at this point. The desired feedback
ampliﬁer gain will be –GAIN to make the loop gain at 0dB
at this frequency. Now calculate the needed phase boost,
assuming 60° as a target phase margin:
TYPE 3 Loop:
BOOST
K = tan2 + 45°
4
1
C2 =
2 • f • G • R1
C1= C2 (K 1)
K
2 • f • C1
R1
R3 =
K1
1
C3 =
2f K • R3
V (R1)
RB = REF
VOUT VREF
R2 =
SPICE or mathematical software can be used to generate
the gain/phase plots for the compensated power supply to
do a sanity check on the component values before trying
them out on the actual hardware. For software, use the
following transfer function:
T(s) = A(s)H(s)
3810fb
26
LTC3810
APPLICATIONS INFORMATION
where H(s) was given in Equation 2 and A(s) depends on
compensation circuit used:
Pulse Skip Mode Operation and MODE/SYNC Pin
The MODE/SYNC pin determines whether the bottom
MOSFET remains on when current reverses in the inductor.
Tying this pin above its 0.8V threshold enables pulse skip
mode operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which current
reverses and discontinuous operation begins depends on
the amplitude of the inductor ripple current and will vary
with changes in VIN. Tying the MODE/SYNC pin below the
0.8V threshold forces continuous synchronous operation,
allowing current to reverse at light loads and maintaining high frequency operation. To prevent forcing current
back into the main power supply, potentially boosting the
input supply to a dangerous voltage level, forced continuous mode of operation is disabled when the TRACK/SS
voltage is below the reference voltage during soft-start
or tracking. During these two periods, the PGOOD signal
is forced low.
Type 2:
A (s) =
1+ s • R3 • C2
C2 • C3 s • RFB1 • (C2 + C3) • 1+ s • R3 •
C2 + C3 Type 3:
A (s) =
1
•
s • R1• (C2 + C3)
(1+ s • (R1+ R3) • C3) • (1+ s • R2 • C1)
C1• C2 (1+ s • R3 • C3) • 1+ s • R2 • C1+
C2 For SPICE, replace VSTIM line in the previous PSPICE
code with following code and generate a gain/phase plot
of V(out)/V(outin):
In addition to providing a logic input to force continuous operation, the MODE/SYNC pin provides a mean to
maintain a ﬂyback winding output when the primary is
operating in pulse skip mode. The secondary output VOUT2
is normally set as shown in Figure 14 by the turns ratio
N of the transformer. However, if the controller goes into
pulse skip mode and halts switching due to a light primary
load current, then VOUT2 will droop. An external resistor
divider from VOUT2 to the MODE/SYNC pin sets a minimum
rfb1 outin vfb 52.5k
rfb2 vfb 0 10k
eithx ithx 0 laplace {0.8-v(vfb)} =
{1/(1+s/1000)}
eith ith 0 value={limit(1e6*v(ithx),0,2.4)}
cc1 ith vfb 4p
cc2 ith x1 8p
rc x1 vfb 210k
rf outin x2 11k ;delete this line for Type 2
cf x2 vfb 120p ;delete this line for Type 2
vstim out outin dc=0 ac=1m
+
VIN
CIN
VIN
1N4148
TG
•
SW
R4
FCB
VOUT2
COUT2
1μF
VOUT1
+
LTC3810
T1
1:N
•
+
COUT
3810 F14
R3
BG
SGND
PGND
Figure 14. Secondary Output Loop
3810fb
27
LTC3810
APPLICATIONS INFORMATION
voltage VOUT2(MIN) below which continuous operation is
forced until VOUT2 has risen above its minimum.
R4 VOUT2(MIN) = 0.8V 1+ R3 Table 1.
MODE/SYNC PIN
CONDITION
DC Voltage: 0V to 0.75V
Forced Continuous
Current Reversal Enabled
DC Voltage: ≥ 0.85V
Pulse Skip Mode Operation
No Current Reversal
Feedback Resistors
Regulating a Secondary Winding
Ext. Clock OV to ≥ 2V
Forced Continuous
Current Reversal Enabled
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
To further limit current in the event of a short-circuit to
ground, the LTC3810 includes foldback current limiting.
If the output falls by more than 60%, then the maximum
sense voltage is progressively lowered to about one tenth
of its full value.
Be aware also that when the fault timeout is enabled for
the external NMOS regulator, an over current limit may
cause the output to fall below the minimum 6.5V UV
threshold. This condition will cause a linear regulator
timeout/restart sequence as described in the Linear Regulator Timeout section if this condition persists.
Fault Conditions: Current Limit and Foldback
Soft-Start and Tracking
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3810, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
The LTC3810 has the ability to either soft-start by itself with
a capacitor or track the output of another supply. When
the device is conﬁgured to soft-start by itself, a capacitor
should be connected to the TRACK/SS pin. The LTC3810 is
put in a low quiescent current shutdown state (IQ ~240μA)
if the SHDN pin voltage is below 1.5V. The TRACK/SS
pin is actively pulled to ground in this shutdown state.
Once the SHDN pin voltage is above 1.5V, the LTC3810 is
powered up. A soft-start current of 1.4μA then starts to
charge the soft-start capacitor CSS. Note that soft-start
is achieved not by limiting the maximum output current
of the controller but by controlling the ramp rate of the
output voltage. Current foldback is disabled during this
soft-start phase. During the soft-start phase, the LTC3810
is ramping the reference voltage until it reaches 0.8V. The
force continuous mode is also disabled and PGOOD signal
is forced low during this phase. The total soft-start time
can be calculated as:
ILIMIT =
VSNS(MAX)
RDS(ON)
1
+ IL
T 2
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for RDS(ON), but not a minimum.
A reasonable assumption is that the minimum RDS(ON)
tSOFTSTART = 0.8 • CSS/1.4μA
When the device is conﬁgured to track another supply,
the feedback voltage of the other supply is duplicated
by a resistor divider and applied to the TRACK/SS pin.
Therefore, the voltage ramp rate on this pin is determined
by the ramp rate of the other supply output voltage.
3810fb
28
LTC3810
APPLICATIONS INFORMATION
Output Voltage Tracking
To implement the coincident tracking in Figure 15a, connect an additional resistive divider to VOUT1 and connect its
midpoint to the TRACK/SS pin of the slave IC. The ratio of
this divider should be selected the same as that of the slave
IC’s feedback divider shown in Figure 16. In this tracking
mode, VOUT1 must be set higher than VOUT2. To implement
the ratiometric tracking, the ratio of the divider should be
exactly the same as the master IC’s feedback divider. Note
that the internal soft-start current will introduce a small
The LTC3810 allows the user to program how its output
ramps up by means of the TRACK/SS pin. Through this
pin, the output can be set up to either coincidentally or
ratiometrically track with another supply’s output, as shown
in Figure 15. In the following discussions, VOUT1 refers
to the master LTC3810’s output and VOUT2 refers to the
slave LTC3810’s output.
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
VOUT2
3810 F15
TIME
TIME
(15a) Coincident Tracking
(15b) Ratiometric Tracking
Figure 15. Two Different Modes of Output Voltage Tracking
VOUT1
VOUT1
VOUT2
R3
R1
R3
TO
VFB1
PIN
TO
TRACK/SS2
PIN
R4
VOUT2
R1
TO
TRACK/SS2
PIN
TO
VFB2
PIN
R2
R4
R3
TO
VFB1
PIN
R2
TO
VFB2
PIN
R4
3810 F16
(16a) Coincident Tracking Setup
(16b) Ratiometric Tracking Setup
Figure 16. Setup for Coincident and Ratiometric Tracking
I
I
+
D1
D2
EA2
TRACK/SS2
0.8V
VFB2
–
D3
3810 F17
Figure 17. Equivalent Input Circuit of Error Ampliﬁer
3810fb
29
LTC3810
APPLICATIONS INFORMATION
error on the tracking voltage depending on the absolute
values of the tracking resistive divider.
By selecting different resistors, the LTC3810 can achieve
different modes of tracking including the two in Figure 15.
So which mode should be programmed? While either
mode in Figure 15 satisﬁes most practical applications,
there do exist some tradeoffs. The ratiometric mode saves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
help of Figure 17. At the input stage of the slave IC’s error
ampliﬁer, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode is
used to match the shifted common mode voltage. The top
two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.8V at steady state and effectively turns off D1.
D2 and D3 will therefore conduct the same current and
offer tight matching between VFB2 and the internal precision 0.8V reference. In the ratiometric mode, however,
TRACK/SS equals 0.8V at steady state. D1 will divert part
of the bias current to make VFB2 slightly lower than 0.8V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a ﬁnite amount
of output voltage deviation. Furthermore, when the master
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well. For better output regulation, use the coincident
tracking mode instead of ratiometric.
The internal oscillator locks to the external clock after
the second clock transition is received. When external
synchronization is detected, LTC3810 will operate in
forced continuous mode. If an external clock transition
is not detected for three successive periods, the internal
oscillator will revert to the frequency programmed by the
RON resistor.
During the start-up phase, phase-locked loop function is
disabled. When LTC3810 is not in synchronization mode,
PLL/LPF pin voltage is set to around 1.215V. Frequency
synchronization is accomplished by changing the internal on-time current according to the voltage on the
PLL/LPF pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the external and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, ΔfH,
is equal to the capture range, ΔfC:
ΔfH = ΔfC = ±0.3 fO
The output of the phase detector is a complementary pair of
current sources charging or discharging the external ﬁlter
network on the PLL/LPF pin. A simpliﬁed block diagram
is shown in Figure 18.
RLP
2.4V
Phase-Locked Loop and Frequency Synchronization
The LTC3810 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency fO. The center frequency is the operating
frequency discussed in the Operating Frequency section.
The LTC3810 incorporates a pulse detection circuit that
will detect a clock on the MODE/SYNC pin. In turn, it will
turn on the phase-locked loop function. The pulse width of
the clock has to be greater than 400ns and the amplitude
of the clock should be greater than 2V.
CLP
PLL/LPF
MODE/SYNC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
3810 F18
Figure 18. Phase-Locked Loop Block Diagram
If the external frequency (fMODE/SYNC) is greater than the
oscillator frequency fO, current is sourced continuously,
pulling up the PLL/LPF pin. When the external frequency
3810fb
30
LTC3810
APPLICATIONS INFORMATION
is less than fO, current is sunk continuously, pulling down
the PLL/LPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLL/LPF
pin is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating
point the phase comparator output is open and the ﬁlter
capacitor CLP holds the voltage. The LTC3810 MODE/SYNC
pin must be driven from a low impedance source such as
a logic gate located close to the pin.
The loop ﬁlter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The ﬁlter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10kΩ and CLP is 0.01μF
to 0.1μF.
Pin Clearance/Creepage Considerations
The LTC3810 is available in the G28 package which
has 0.0106" spacing between adjacent pins. To
maximize PC board trace clearance between high voltage pins, the LTC3810 has three unconnected pins
between all adjacent high voltage and low voltage
pins, providing 4(0.0106") = 0.042" clearance which
will be sufﬁcient for most applications up to 100V.
For more information, refer to the printed circuit board
design standards described in IPC-2221 (www.ipc.org).
Efﬁciency Considerations
The percent efﬁciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efﬁciency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3810 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efﬁciency to drop at high output currents. In continuous
mode the average output current ﬂows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then
the resistance of one MOSFET can simply be summed
with the resistances of L and the board traces to obtain
the DC I2R loss. For example, if RDS(ON) = 0.01Ω and
RL = 0.005Ω, the loss will range from 15mW to 1.5W
as the output current varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
input voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is signiﬁcant
at input voltages above 20V and can be estimated from
the second term of the PMAIN equation found in the Power
MOSFET Selection section. When transition losses are
signiﬁcant, efﬁciency can be improved by lowering the
frequency and/or using a top MOSFET(s) with lower
CRSS at the expense of higher RDS(ON).
3. INTVCC/DRVCC current. This is the sum of the MOSFET
driver and control currents. Control current is typically
about 3mA and driver current can be calculated by: IGATE
= f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT) are
the gate charges of the top and bottom MOSFETs. This
loss is proportional to the supply voltage that INTVCC/
DRVCC is derived from, i.e., VIN for the external NMOS
linear regulator, VOUT for the internal EXTVCC regulator, or VEXT when an external supply is connected to
INTVCC/DRVCC.
4. CIN loss. The input capacitor has the difﬁcult job of ﬁltering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss
and sufﬁcient capacitance to prevent the RMS current
from causing additional upstream losses in fuses or
batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss. When
making adjustments to improve efﬁciency, the input current is the best indicator of changes in efﬁciency. If you
make a change and the input current decreases, then the
efﬁciency has increased. If there is no change in input
current, then there is no change in efﬁciency.
3810fb
31
LTC3810
APPLICATIONS INFORMATION
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem.
Design Example
As a design example, take a supply with the following
speciﬁcations: VIN = 36V to 72V (48V nominal), VOUT =
12V ±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate the
timing resistor with VON = INTVCC:
RON =
12V
= 263k
2.4V • 250kHz • 76pF
and choose the inductor for about 40% ripple current at
the maximum VIN:
12V
12V L=
1
= 10μH
250kHz • 0.4 • 10A 72V With a 10μH inductor, ripple current will vary from 3.2A
to 4A (32% to 40%) over the input supply range.
Next, choose the bottom MOSFET switch. Since the drain
of the MOSFET will see the full supply voltage 72V(max)
plus any ringing, choose an 80V MOSFET to provide a
margin of safety. The Si7852DP has:
BVDSS = 80V
RDS(ON) = 16.5mΩ(max)/13.5mΩ(nom),
δ = 0.007/°C,
CMILLER = (18.5nC – 7nC)/40V = 288pF,
VGS(MILLER) = 4.7V,
θJA= 20°C/W.
This yields a nominal sense voltage of:
VSNS(NOM) = 10A • 1.3 • 0.0135Ω = 176mV
To guarantee proper current limit at worst-case conditions,
increase nominal VSNS by at least 50% to 320mV (by tying
VRNG to 2V). To check if the current limit is acceptable at
VSNS = 320mV, assume a junction temperature of about
80°C above a 70°C ambient (ρ150°C = 2):
ILIMIT 320mV
1
+ • 4A = 11.7A
2 • 0.0165 2
and double-check the assumed TJ in the MOSFET:
72V 12V
PBOT =
• 11.7A 2 • 2 • 0.0165 = 3.8W
72V
TJ = 70°C + 3.8W • 20°C/W = 146°C
Verify that the Si7852DP is also a good choice for the top
MOSFET by checking its power dissipation at current limit
and maximum input voltage, assuming a junction temperature of 50°C above a 70°C ambient (ρ120°C = 1.7):
12V
• 11.7A 2 (1.7 • 0.0165 )
72V
11.7A
+ 72V 2 •
• 2 • 288pF
2
1
1 •
+
• 250kHz
10V 4.7V 4.7V = 0.64W + 1.75W = 2.39W
PMAIN =
TJ = 70°C + 2.39W • 20°C/W = 118°C
The junction temperature will be signiﬁcantly less at
nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in
this circuit.
Since VOUT > 6.7V, the INTVCC/DRVCC voltage can be
generated from VOUT with the internal LDO by connecting
VOUT to the EXTVCC pin. A small SOT23 MOSFET such as
the ZXMN10A07F can be used for the pass device if fault
timeout is enabled. Choose RNDRV to guarantee that fault
timeout is enabled when power dissipation of M3 exceeds
0.4W (max for 70°C ambient). Calculate power dissipation
at VIN(MIN) = 36V:
ICC = 250kHz • 2 • 34nC + 3mA = 20mA
PM3 = (36V – 10V)(0.02A) = 0.52W
3810fb
32
LTC3810
APPLICATIONS INFORMATION
Since power dissipation at VIN(MIN) = 36V already exceeds
0.4W, calculate RNDRV(MAX) such that fault timeout is
always enabled:
RNDRV 36V 10V – 3.5V
= 83.3k
270μA
So, choose RNDRV = 80.6k.
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
ΔVOUT(RIPPLE) = ΔIL(MAX) • ESR = 4A • 0.018Ω
= 72mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔVOUT(STEP) = ΔILOAD • ESR = 10A • 0.018Ω
= 180mV
An optional 10μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 19.
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3810.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and VOUT to maintain good voltage
ﬁltering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (VIN, VOUT, GND or to any other DC rail in your
system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller.
• Segregate the signal and power grounds. All smallsignal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and SGND pins.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
• Connect the bottom driver decoupling capacitor CDRVCC
closely to the DRVCC and BGRTN pins.
3810fb
33
LTC3810
APPLICATIONS INFORMATION
RNDRV
80.6k
RON
261k
CON
100pF
1
20k
4
80.6k
0.01μF
10k
CSS
1000pF
RUV1
470k
11
BOOST
VON
27
TG
26
SW
25
SENSE+
RUV2
12k
CC2
47pF
RFB2
1k
CB 0.1μF
RC
200k
M1
Si7852DP
L1
10μH
CDRVCC
0.1μF
19
BG
18
DRVCC
17
INTVCC
16
EXTVCC
15
NDRV
VOUT
12V
10A
COUT1
270μF
16V
M2
Si7852DP
D1
B1100
CVCC
1μF
SGND
CC1
5pF
PGND
SENSE– 21
20
BGRTN
SS/TRACK
CIN2
1μF
100V
28
ION
12
SGND
13
SHDN
14
UVIN
SHDN
M3
ZXMN10A07F
DB
BAS19
LTC3810
5 V
RNG
6
PGOOD
7
MODE/SYNC
8
ITH
9
VFB
10
PLL/LPF
PGOOD
250kHz
CLOCK
VIN
36V TO 72V
CIN1
68μF
100V
COUT2
10μF
16V
PGND
RFB1
14k
3810 F19
Figure 19. 36V to 72V Input Voltage to 12V/10A Synchronized at 250kHz
TYPICAL APPLICATIONS
7V to 80V Input Voltage to 5V/5A with IC Power from 12V Supply
and All Ceramic Output Capacitors
RON
110k
12V
CON
100pF
1
BOOST
TG
4
VON
5
VRNG
6
PGOOD
7
MODE/SYNC
8
ITH
9
VFB
10
PLL/LPF
PGOOD
RUV1
470k
CSS
1000pF
11
SS/TRACK
12
SGND
13
SHDN
14
UVIN
SHDN
RUV2
61.9k
CC2
200pF
RFB2
1.89k
RC
100k
SGND
CC1
5pF
CIN2
1μF
100V
DB
BAS19
LTC3810
ION
VIN
7V TO 80V
CIN1
68μF
100V
PGND
28
27
CB 0.1μF
26
SW
25
SENSE+
SENSE–
BGRTN
M1
Si7852DP
L1
4.7μH
21
VOUT
5V
5A
20
19
BG
18
DRVCC
17
INTVCC
16
EXTVCC
15
NDRV
CDRVCC
0.1μF
COUT
47μF
6.3V
s3
M2
Si7852DP
D1
B1100
CVCC
1μF
PGND
RFB1
10k
3810 TA04
3810fb
34
LTC3810
TYPICAL APPLICATIONS
15V to 80V Input Voltage to 3.3V/5A with Fault Timeout,
Pulse Skip and VIN UV Disabled
RNDRV
274k
RON
71.5k
M3
ZVN4210G
CON
100pF
1
BOOST
TG
4
5
6
7
8
9
10
PGOOD
CSS
1000pF
PGOOD
MODE/SYNC
ITH
VFB
PLL/LPF
SS/TRACK
12
SGND
13
SHDN
14
UVIN
SHDN
CC2
47pF
RC
200k
RFB2
1.89k
27
CB
0.1μF
M1
Si7852DP
VOUT
3.3V
5A
SENSE
20
BGRTN
DRVCC
19
18
CDRVCC
0.1μF
COUT1
270μF
6.3V
M2
Si7852DP
17
INTVCC
16
EXTVCC
15
NDRV
D1
B1100
CVCC
1μF
SGND
CC1
5pF
L1
4.7μH
– 21
BG
11
PGND
28
26
SW
25
SENSE+
VON
VRNG
CIN2
1μF
100V
DB
BAS19
LTC3810
ION
VIN
15V TO 80V
CIN1
68μF
100V
COUT2
10μF
6.3V
PGND
RFB1
10k
3810 TA05
PACKAGE DESCRIPTION
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
0.42 ±0.03
7.40 – 8.20
(.291 – .323)
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
G28 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3810fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3810
TYPICAL APPLICATION
15V to 100V Input Voltage to 12V/5A with Trickle Charger Start-Up
RNDRV
100k
RON
261k
CON
100pF
BOOST
ION
28
27
4
VON
5
VRNG
6
PGOOD
7
MODE/SYNC
8 I
TH
9 V
FB
10
PLL/LPF
PGOOD
RUV1
470k
CSS
1000pF
11
SS/TRACK
TG
26
SW
+ 25
SENSE
CC2
47pF
RFB2
1k
RC
200k
CC1
5pF
M1
Si7456DP
L1
10μH
SENSE– 21
20
BGRTN
19
BG
DRVCC 18
17
INTV
CDRVCC
0.1μF
EXTVCC 16
15
NDRV
SGND
RUV2
28k
PGND
CB
0.1μF
VOUT
12V
5A
COUT1
270μF
16V
M2
Si7456DP
CC
12
SGND
13
SHDN
14
UVIN
SHDN
CIN2
1μF
100V
DB
BAS19
LTC3810
1
VIN
15V TO 100V
CIN1
68μF
100V
CVCC2
22μF
CVCC1
1μF
D1
B1100
COUT2
10μF
16V
PGND
RFB1
14k
3810 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT®1074HV/LT1076HV
Monolithic 5A/2A Step-Down DC/DC Converters
VIN Up to 60V, TO-220 and DD Packages
LTC1735
Synchronous Step-Down DC/DC Controller
3.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, Current Mode, IOUT ≤ 20A
LTC1778
No RSENSE™ Synchronous DC/DC Controller
4V ≤ VIN ≤ 36V, Fast Transient Response, Current Mode, IOUT ≤ 20A
LT3010
50mA, 3V to 80V Linear Regulator
1.275V ≤ VOUT ≤ 60V, No Protection Diode Required, 8-Lead MSOP
LT3430/LT3431
Monolithic 3A, 200kHz/500kHz Step-Down Regulator
5.5V ≤ VIN ≤ 60V, 0.1Ω Saturation Switch, 16-Pin SSOP
LT3433
Monolithic Step-Up/Step-Down DC/DC Converter
4V ≤ VIN ≤ 60V, 500mA Switch, Automatic Step-Up/Step-Down,
LTC3703
100V Synchronous DC/DC Controller
VIN Up to 100V, 9.3V to 15V Gate Drive Supply
LT3800
High Voltage Synchronous Regulator Controller
VIN Up to 60V, IOUT ≤ 20A, Current Mode, Onboard Bias Regulator,
Burst Mode Operation, 16-Lead TSSOP FE Package
LTC3810-5
No RSENSE Current Mode Controller
VIN Up to 60V, IOUT ≤ 20A, Large 1Ω Gate Drivers
LTC3812-5
No RSENSE Current Mode Controller
VIN Up to 60V, IOUT ≤ 20A, Large 1Ω Gate Drivers
LT3824
High Voltage Step-Down Controller
VIN Up to 60V, P-Channel Top MOSFET, IOUT ≤ 5A, MSOP-10 Package
LT3844
High Voltage Current Mode Controller with
Programmable Operating Frequency
VIN Up to 60V, IOUT ≤ 5A, Onboard Bias Regulator, Burst Mode
Operation, Sync Capability, 16-Lead TSSOP FE Package
LT3845
High Voltage Synchronous Regulator Controller with
Adjustable Operating Frequency
VIN Up to 60V, IOUT ≤ 20A, Onboard Regulator, Burst Mode Operation,
16-Lead TSSOP Package
Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.
3810fb
36
Linear Technology Corporation
LT 0408 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007

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