MURATA SI5317-EVB

Si 5 3 1 7 - EVB
Si5317 E VALUATION B OARD U SER ’ S G U I D E
Description
Features
The Si5317-EVB User’s Guide provides a complete and
simple evaluation of the functions, features, and
performance of the Si5317.

The Si5317 is a pin-controlled 1:1 jitter-attenuating
clock for high-performance applications.
The Si5317 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate jitter attenuation in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The DSPLL loop bandwidth is user
programmable, providing jitter performance optimization
at the application level.
Rev. 0.1 5/10




No software required. Simple jumpers for device
configuration
Fully powered from either a single USB port or an
external power supply
Selectable external reference clock or on-board
crystal
Status LEDs
Header to connect to external test equipment for
automated testing
Copyright © 2010 by Silicon Laboratories
Si5317-EVB
Si5317-EVB
1. Functional Block Diagram
A functional block diagram of the EVB is shown in Figure 1. The Si5317-EVB provides alarm and status outputs,
programmable output clock signal format (LVPECL, LVDS, CML, CMOS), selectable loop bandwidths, and ultra
low jitter.
The Si5317 accepts a single clock input ranging from 1 MHz to 710 MHz and generates two equal frequency clock
outputs ranging from 1 to 710 MHz. The clock frequency range and loop bandwidth are selectable from a simple
look-up table. The Si5317-EVB has a differential clock input that is AC terminated to 50  and then AC-coupled to
the Si5317. The two clock outputs are AC-coupled. The XA-XB reference is usually a 114.285 MHz crystal; but
there are provisions for an external XA-XB reference (either differential or single-ended). The device status are
available on a ribbon header and LEDs. Control pins are strapped using jumper headers for device configuration
and various board options. The board can be powered using either external power supplies or from a PC's USB
port. Refer to the Si5317 data sheet for technical details of the device.
Term*
XA
XB
CKOUT1+
Term*
CKOUT1-
CKIN+
Term*
CKIN-
CKOUT2+
Term*
CKOUT2-
Si5317
Header
USB
+ Regulator
Status/
Control
FRQTBL
FRQSEL[3:0]
BWSEL[1:0]
RATE[1:0]
INC
DEC
LOS
LOL
RST_B
SFOUT[1:0]
DBL2_BY
Figure 1. Si5317 EVB Block Diagram
2
DUT Power
3.3V
GND
Control
2x15
JUMPER
HEADER
VDD
Rev. 0.1
2x5
JUMPER
HEADER
L
E
D
Si5317-EVB
2. Si5317-EVB Input and Output Clocks
2.1. Input Clocks
The Si5317-EVB has a differential clock input that is ac terminated and ac coupled before being presented to the
Si5317. If the input clock frequencies are low (below 10 MHz), there are extra considerations that should be taken
into account. The Si5317 has a maximum clock input rise time specification of 11 ns that must be met (see CKNtrf
in the Si5317 data sheet). Also, if the input clock is LVCMOS, it might be advantageous to replace the input
coupling capacitors (C7, C12, C16. and C18) with 0  resistors. When using LVCMOS inputs, the user should
consider removing the ac termination and using source series termination located at the driving source.
Regardless of the input format, if the clock inputs are not approximately 50% duty cycle, it is highly recommended
to avoid ac coupling. For input clocks that are far off of 50% duty cycle, the average value of the signal that passes
through the coupling capacitor will be significantly off of the midpoint between the maximum and minimum value of
the clock signal, resulting in a mismatch with the common mode input threshold voltage (see Vicm, in the Si5317
data sheet).
2.2. XA-XB Reference
To achieve a very low jitter generation and for stability during holdover, the Si5317 requires a stable, low jitter
reference at its XA-XB pins. To that end, the EVB is configured with a 114.285 MHz third overtone crystal
connected between pins 6 and 7 of the Si5317. However, the Si5317-EVB is also capable of using an external XAXB reference oscillator, either differential or single-ended. For details concerning the allowed XA-XB reference
frequencies and their RATE settings, see the Si5317 data sheet. J1 and J2 are the SMA connectors with ac
termination. AC coupling is also provided that needs to be installed at C6 and C8. Table 1 explains the component
changes that are needed to implement an external XA-XB reference oscillator.
Table 1. XA-XB Reference Connections
Mode
Xtal
Ext Ref
Ext Ref In+
NC
J1
Ext Ref In-
NC
J2
NOPOP
install
install
NOPOP
RATE0(See note 4)
M
H
RATE1(See note 4)
M
M
C6, C8
R8
Notes:
1. Xtal is 114.285 MHz.
2. NC - no connect.
3. NOPOP - do not install.
4. J12 jumper, see Table 3.
5. C6 on bottom of the board.
Rev. 0.1
3
Si5317-EVB
2.3. Output Clock
The clock outputs are AC-coupled and are available on SMAs J5, J7, J9 and J11. For LVCMOS outputs, it might be
desirable to replace the AC coupling capacitors (C9,C14,C17, and C20) with 0  resistors. Also, if greater drive
strength is desired for an LVCMOS output, R6 and R10 can be installed.
2.4. Pin Configuration
J12 is the large jumper header in the center left of the board that implements the jumper plugs that configure the
pins of the Si5317. Each pin can be strapped to become either H, M, or L. The H level is achieved by installing a
jumper plug between the appropriate middle row pin and its VDD row pin. L is achieved by installing a jumper plug
between the appropriate middle row pin and its GND row pin. M is achieved by installing no jumper plug.
2.5. Evaluation Board Power
The EVB can be powered from two possible sources: USB or external supplies. A 3.3 V supply is required to run
the LEDs because of their rather large forward drop. The Si5317 power supply can be separated from the 3.3 V
supply so that the Si5317 can be evaluated at a voltage other than 3.3 V. It is important to note that when the USB
supply is being used, the EVB uses the USB port only for power and that the resulting power supply is strictly 3.3 V.
Here are the instructions for the various possibilities:
2.5.1. External Power Supplies
Install a jumper between J16.1 and J16.2 (labeled EXT).
There should be no USB connection.
If the Si5317 is not being operated at 3.3 V, two supplies should be connected to J14. Connect the 3.3 V supply to
J14.1 and J14.2 (labeled 3.3 V and GND). Connect the SI5317 power supply between J14.2 and J14.3 (labeled
GND and DUT).
If the Si5317 is to be operated at 3.3 V, J15 (labeled ONE PWR) can be installed, requiring only one external
supply. Connect 3.3 V power between J14.2 and J14.3 (labeled GND and DUT).
2.5.2. USB Power
Install a jumper between J16.2 and J16.3 (labeled USB).
Install a jumper at J15 (labeled ONE PWR).
With a USB cable, plug the EVB into a powered USB port.
2.5.3. USB 3.3V Power, External Si5317 Power
Install a jumper between J16.2 and J16.3 (labeled USB).
No jumper at J15 (labeled ONE PWR).
Connect the Si5317 power supply between J14.2 and J14.3 (labeled GND and DUT).
4
Rev. 0.1
Si5317-EVB
3. Connectors and LEDs
3.1. LEDs
Table 2. LED Descriptions
LED
Label
Significance
D1
CS_CA
Not used
D2
LOS2
Not used
D3
LOS1
ON = no valid clock input
D4
LOL
ON = Si5317 is not locked
D5
DUT_PWR
D6
3.3V
ON = Si5317 power is present
ON = 3.3 V power is present
3.2. Jumpers, Headers, and Connectors
Refer to Figure 2 to locate the items described in this section.
J12
C8, R8
Si5317
J16
J15
J13
J14
Figure 2. EVB Jumper Locations
Rev. 0.1
5
Si5317-EVB
Table 3. Configuration Header, J12
J12
Pin
J12.1
not used
J12.2
SFOUT0
J12.3
SFOUT1
J12.4
FRQSEL0
J12.5
FRQSEL1
J12.6
FRQSEL2
J12.7
FRQSEL3
J12.8
FRQTBL
J12.9
BWSEL0
J12.10
BSWEL1
J12.11
DBL2_BY
J12.12
not used
J12.13
RATE0
J12.14
RATE1
Table 4. Status Indication Header, J13
6
J13
Signal
J13.1
INC
J13.3
DEC
J13.5
LOS
J13.7
Not used
J13.9
Not used
J13.11
LOL
J13.13
RST_B
Rev. 0.1
Rev. 0.1
mper
ugs
CKIN2-
CKIN2+
J6
SMA_EDGE
1
J8
SMA_EDGE
1
1C
2C
3C
4C
5C
6C
7C
8C
9C
10C
11C
12C
13C
14C
J12
14A
14B
13A
13B
12A
12B
11A
11B
10A
10B
9A
9B
8A
8B
7A
7B
6A
6B
5A
5B
4A
4B
3A
3B
2A
2B
1A
1B
J10
SMA_EDGE
1
TP2
1
2
14x3_M_HDR_THRU
option list
CKIN1-
J4
SMA_EDGE
1
3
3
3
CKIN1+
2
2
2
2
2
2
Ext Ref In -
3
J2
SMA_EDGE
1
3
J1
SMA_EDGE
1
R7
SFOUT0
SFOUT1
10
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
FRQTBL
BWSEL0
BWSEL1
DBL2_BY
AUTOSEL
RATE0
DUT_PWR
0 ohm
49.9 R11
100N C18
100N C16
49.9 R9
49.9
RATE1
R14
R5
100N C12
100N C7
49.9
C1
10NF
R13
C19
10NF
10NF
C15
C13
10NF
C3
10NF
49.9
R3
X1
4
3
R8
0 ohm
R15
10k
DUT_PWR
49.9
R4
C2
10NF
TP1
1
2
9
1
36
24
25
26
27
2
22
23
14
C11
100N
C10
100N
C4
100N
FILT_DUT_PWR
RST
NC
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
FRQTBL
BWSEL0
BWSEL1
DBL2_BY
AUTOSEL
U1
1
2
1
LOL
CS_CA
LOS1
LOS2
SFOUT0
SFOUT1
INC
DEC
CKOUT2+
CKOUT2-
CKOUT1+
CKOUT1-
Si5315/17
Rate1
Rate0
CKIN_2+
CKIN_2-
CKIN1+
CKIN1-
XA
XB
C5
1UF
R2
0 ohm
Figure 3. Si5317-EVB
R12
0 ohm
NOPOP
15
11
12
13
16
17
6
7
see option list
C8
10NF
NOPOP
see option list
114.285 MHz
2 GND
1
C6
10NF
NOPOP
NOPOP
100
R1
to power plane
8
31
37
3
VDD1
VDD2
VDD3
C14
100N
J7
SMA_EDGE
1
J9
SMA_EDGE
1
J11
SMA_EDGE
1
18
21
3
4
33
1
3
5
7
9
11
13
J13
2
4
6
8
10
12
14
INC
DEC
LOS1
LOS2
CS_CA
LOL
RST_B
CKOUT2-
CKOUT2+
CKOUT1-
CKOUT1+
14_M_Header
INC
DEC
LOS1
LOS2
CS_CA
LOL
RST_B
C20
100N
J5
SMA_EDGE
1
30
R10
0 ohm
NOPOP
100N
C17
optionally
install for
CMOS outputs
R6
0 ohm
NOPOP
100N
C9
to measure DUT supply
Status,
Control
2
DUT_PWR
20
19
35
34
28
29
J3
NOPOP
Ferrite
L1
3
3
3
3
5
10
32
GND1
GND2
GND3
2
2
2
2
Ext Ref In +
LOL
CS_CA
LOS1
LOS2
see option l
Si5317-EVB
4. Schematic
7
*
*
*
1
2
3
Phoenix_3_screw
3.3V
GND
DUT_PWR
J14
1
2
LOL
LOS1
LOS2
CS_CA
C25
1UF
PHOENIX_3P3V
install jumper
to run DUT
from 3.3V
RAW_3P3V
J15
Single
3.3V supply
1
+
C21
220UF
C22
1UF
1
2
BSS138
Q2
Ferrite
1
R20
10k
1
Power Source
Selection
BSS138
Q5
BSS138
Q4
BSS138
Q3
1
L2
1
DUT_PWR
BSS138
Q1
C24
220UF
+
150
150
1
2
3
4
#4
H1
8
7
6
5
Grn
2
C
C
Grn
2
Red
1 C
Red
1 C
Red
1 C
Yel
2 C
A
1
1
2
2
D6
D5
A
A
D4
A
D3
2
D1
1
A
D2
A
1
1
#4
H3
#4
H4
3.3V
DUT_PWR
LOL
LOS1
LOS2
CS_CA
V
Gnd
D+
USB
D-
J17
4
1
VBUS
see option list
3
2
USB power
Figure 4. LED and Power/USB
R150x4
R19
R18
R17
LED_PWR
#4
H2
1
mounting holes
USB_3P3V
1
select 3.3V from either
USB or from J14
0 ohm R16
V3P3
J16
1
2
3
EVB
main
power
3
S2
DUT_PWR
3
2
6
S1
DUT_PWR
3
2
3
2
3
2
Rev. 0.1
2
5
+
C23
33UF
+
VIN
VOUT
NC1
U2
FAN1540B
C26
33UF
3
2
1
PAD
8
7
DUT Power
NC2
NC3
GND
4
5
6
ground
pins
1
J26
J25
J24
1
J23
1
J22
J21
J20
J19
J18
1
1
1
1
1
1
Si5317-EVB
Si5317-EVB
5. Bill of Materials
Item
Qty
Reference
Part
Mfr
MfrPartNum
1
6
C1,C2,C3,
C13,C15,
C19
10NF
Venkel
C0603X7R160103KNE
603
2
11
C4,C7,C9,
C10,C11,
C12,C14,
100N
Venkel
C0603X7R160104KNE
603
603
BOM
Digikey
Footprint
C16,C17,
C18,C20
3
3
C5,C22,C25
1UF
Venkel
C0603X7R6R3105KNE
5
2
C21,C24
220UF
Kemet
T494B227M004A
T
6
2
C23,C26
33UF
Venkel
TA006TCM336M
BR
7
1
D1
Yel
Panasonic
LN1471YTR
P11125CT
-ND
LED_gull
8
3
D2,D3,D4
Red
Lumex
LN1271RAL
P493CTND
LED_gull
9
2
D5,D6
Grn
Panasonic
LN1371G
P491CTND
LED_gull
11
10
J1,J2,J4,J5,
J6,J7,J8,J9,
SMA_
EDGE
Johnson
142-0701-801
J502-ND
SMA_EDGE_p062
399-46311-ND
SM_C_3528_21
3528
J10,J11
13
1
J12
14x3_M_H
DR_THRU
any
two and one row
side by side
15
1
J14
Phoenix_3
_screw
Phoenix
MKDSN 1.5/35.08
16
1
J15
Jmpr_2pin
17
1
J16
Jmpr_3pin
18
1
J17
USB
19
4
J19,J20,J24,
J26
Jmpr_1pin
20
2
L1,L2
Ferrite
Venkel
FBC1206-471H
21
5
Q1,Q2,Q3,
Q4,Q5
BSS138
On Semi
BSS138LT1G
20x3_M_HDR_THRU
277-1248- Phoenix3pinM_p2pitch
ND
3pin_p1pitch
FCI
61729-0010BLF
609-1039ND
USB_typeB
1pin_p1pitch
Rev. 0.1
1206
BSS138L
T10SCTND
SOT23
9
Si5317-EVB
Item
Qty
Reference
Part
Mfr
MfrPartNum
23
4
R2,R8,R13,
R16
0 ohm
Venkel
CR0603-16W000T
603
24
6
R3,R4,R5,
R7,R9,R11
49.9
Venkel
CR0603-16W49R9FT
603
26
1
R14
10
Venkel
CR0603-16W10R0FT
603
27
2
R15,R20
10k
Venkel
CR603-16W1002FT
603
28
2
R17,R18
150
Venkel
CR0603-16W1500FT
603
29
1
R19
R150x4
Panasonic
EXB-38V151JV
31
1
U1
Si5317
Silicon
Labs
Si5317A-C-GM
32
1
U2
FAN1540B
Fairchild
FAN1540BPMX
33
1
X1
114.285
MHz
TXC
7MA1400014
34
3
standoff
SPC Tech
2397
35
3
spacer
Richco
NSS-4-4-01
4
2
C6,C8
10NF
Venkel
C0603X7R160103KNE
12
1
J3
Jmpr_2pin
22
1
R1
100
Venkel
CR0603-16W1000FT
NOPOP
603
25
3
R6,R10,R12
0
Venkel
CR0603-16W000T
NOPOP
603
30
2
TP1,TP2
test_points
14
1
J13
14_M_
Header
19
9
J18,J21,J22,
J23,J25
Jmpr_1pin
10
BOM
Digikey
Y9151CTND
Footprint
1206x4
QFN-36
FAN1540
BMPXCTND
MLP6
xtal 3.2 x 2.5
NOPOP
603
NOPOP
NOPOP
3M
N2514-6002RB
NOPOP MHC14K- 14pinMdualHeader_p1
ND
pitch
NOPOP
Rev. 0.1
1pin_p1pitch
Si5317-EVB
6. Layout
Figure 5. Silkscreen Top
Rev. 0.1
11
Si5317-EVB
Figure 6. Layer 1
12
Rev. 0.1
Si5317-EVB
Figure 7. Layer 2—Ground Plane
Rev. 0.1
13
Si5317-EVB
Figure 8. Layer 3
14
Rev. 0.1
Si5317-EVB
Figure 9. Layer 4
Rev. 0.1
15
Si5317-EVB
Figure 10. Layer 5, FILT_DUT_PWR
16
Rev. 0.1
Si5317-EVB
Figure 11. Layer 6, Bottom
Rev. 0.1
17
Si5317-EVB
Figure 12. Bottom Silkscreen
18
Rev. 0.1
Si5317-EVB
7. Factory Default Configuration
J12
Pin
Jumper
J12.1
not used
—
J12.2
SFOUT0
H
J12.3
SFOUT1
L
J12.4
FRQSEL0
L
J12.5
FRQSEL1
M
J12.6
FRQSEL2
M
J12.7
FRQSEL3
H
J12.8
FRQTBL
L
J12.9
BWSEL0
M
J12.10
BSWEL1
H
J12.11
DBL2_BY
L
J12.12
not used
—
J12.13
RATE0
M
J12.14
RATE1
M
The above jumper settings result in the following:





SFOUT = CMOS output
10.0 MHz input clock
10.0 MHz output clock
BW =88 Hz
RATE[1:0] = 114.285 MHz 3rd overtone crystal
Rev. 0.1
19
Si5317-EVB
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
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20
Rev. 0.1