FAIRCHILD NC7WZ38L8X

Revised April 2003
NC7WZ38
TinyLogic UHS Dual 2-Input NAND Gate
(Open Drain Output)
General Description
Features
The NC7WZ38 is a dual 2-Input NAND Gate with open
drain output stage from Fairchild’s Ultra High Speed Series
of TinyLogic. The device is fabricated with advanced
CMOS technology to achieve ultra high speed with high
output drive while maintaining low static power dissipation
over a very broad VCC operating range. The device is
specified to operate over the 1.65V to 5.5V VCC range. The
inputs and output are high impedance when VCC is 0V.
Inputs tolerate voltages up to 7V independent of VCC operating voltage. The open drain output stage will tolerate voltages up to 7V independent of VCC when in the high
impedance state.
■ Space saving US8 surface mount package
■ MicroPak leadless package
■ Open Drain output stage for OR tied applications
■ Ultra High Speed; tPD 2.2 ns Typ into 50 pF at 5V VCC
■ High Output Sink Drive; 24 mA at 3V VCC
■ Broad VCC Operating Range; 1.65V to 5.5V
■ Matches the performance of LCX when operated at
3.3V VCC
■ Power down high impedance inputs/output
■ Overvoltage Tolerant inputs facilitate 5V to 3V
translation
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Package
Code
Number
Number
Top Mark
NC7WZ38K8X
MAB08A
WZ38
NC7WZ38L8X
(Preliminary)
MAC08A
U5
Package Description
Supplied As
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation
DS500271
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NC7WZ38 TinyLogic UHS Dual 2-Input NAND Gate (Open Drain Output)
April 2000
NC7WZ38
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Descriptions
(Top View)
Pin Names
Pin One Orientation Diagram
Description
An , Bn
Inputs
Yn
Output
Function Table
Y = AB
Inputs
Output
A
B
Y
L
L
*H
L
H
*H
H
L
*H
H
H
L
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
H = HIGH Logic Level
L = LOW Logic Level
*H = HIGH Impedance output state (Open Drain)
(Top Thru View)
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2
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC)
−0.5V to +7V
DC Input Voltage (VIN)
−0.5V to +7V
Supply Voltage Operating (VCC)
DC Output Voltage (VOUT)
−0.5V to +7V
Supply Voltage Data Retention (VCC)
DC Input Diode Current (IIK)
1.65V to 5.5V
1.5V to 5.5V
Input Voltage (VIN)
@VIN < −0.5V
−50 mA
0V to 5.5V
Output Voltage (VOUT)
DC Output Diode Current (IOK)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
@VOUT < −0.5V
−50 mA
Input Rise and Fall Time (tr, tf)
+50 mA
VCC = 1.8V ± 0.15V, 2.5V ± 0.2V
0 ns/V to 20 ns/V
±100 mA
VCC = 3.3V ± 0.3V
0 ns/V to 10 ns/V
−65°C to +150°C
VCC = 5.0V ± 0.5V
0 ns/V to 5 ns/V
DC Output Current (IOUT)
DC VCC/GND Current (ICC/IGND)
Storage Temperature (TSTG)
150°C
Junction Temperature under Bias (TJ)
Thermal Resistance (θJA)
250°C/W
Junction Lead Temperature (TL);
260°C
(Soldering, 10 seconds)
Power Dissipation (PD) @ +85°C
250 mW
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
Parameter
HIGH Level
Input Voltage
VIL
LOW Level
Input Voltage
ILKG
HIGH Level
Output Leakage
VOL
TA = +25°C
VCC
(V)
Min
Typ
TA = −40°C to +85°C
Max
1.65 to 1.95 0.75 VCC
2.3 to 5.5
Min
Max
0.75 VCC
0.7 VCC
0.25 VCC
0.25 VCC
2.3 to 5.5
0.3 VCC
0.3 VCC
5.5
±5
±10
1.65
0.0
0.1
0.1
Output Voltage
2.3
0.0
0.1
0.1
3.0
0.0
0.1
0.1
Input Leakage Current
IOFF
Power Off Leakage Current
ICC
Quiescent Supply Current
Conditions
V
0.7 VCC
1.65 to 1.95
LOW Level
IIN
Units
V
µA
V
VIN = VIL
VOUT = VCC or GND
VIN = VIH
IOL = 100 µA
4.5
0.0
0.1
0.1
1.65
0.08
0.24
0.24
2.3
0.10
0.3
0.3
3.0
0.15
0.4
0.4
3.0
0.22
0.55
0.55
4.5
0.22
0.55
0.55
±0.1
±1
µA
VIN = 5.5V, GND
5.5
IOL = 4 mA
IOL = 8 mA
V
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0.0
1
10
µA
VIN or VOUT = 5.5V
1.65 to 5.5
1
10
µA
VIN = 5.5V, GND
3
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NC7WZ38
Absolute Maximum Ratings(Note 1)
NC7WZ38
AC Electrical Characteristics
Symbol
tPZL
tPLZ
Parameter
Propagation Delay
Propagation Delay
TA = +25°C
VCC
(V)
Min
TA = −40°C to +85°C
Typ
Max
Min
Max
Units
Conditions
1.8 ± 0.15
2.0
5.2
9.2
2.0
9.6
CL = 50 pF
2.5 ± 0.2
1.5
3.5
5.7
1.5
6.1
RU = 500Ω
3.3 ± 0.3
1.0
2.8
4.1
1.0
4.5
ns
RD = 500Ω
5.0 ± 0.5
0.5
2.2
3.4
0.5
3.6
1.8 ± 0.15
2.0
4.6
9.2
2.0
9.6
CL = 50 pF
2.5 ± 0.2
1.5
3.2
5.7
1.5
6.1
RU = 500Ω
3.3 ± 0.3
1.0
2.4
4.1
1.0
4.5
5.0 ± 0.5
0.5
1.6
3.4
0.5
3.6
CIN
Input Capacitance
COUT
Output Capacitance
CPD
Power Dissipation
Capacitance
5.0
9
Figure
Number
Figures
1, 3
VI = 2 × VCC
ns
RD = 500Ω
Figures
1, 3
VI = 2 × VCC
0
2.5
pF
0
4.2
pF
3.3
7
pF
(Note 3)
Figure 2
Note 3: C PD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD ) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD) (VCC) (fIN) + (ICC static).
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tw = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 3. AC Waveforms
Input = AC Waveform; tr = tf = 1.8 ns
PRR = 10 MHz; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
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TAPE FORMAT for US8
Package
Designator
Tape
Number
Cavity
Section
Cavities
Status
Status
125 (typ)
Empty
Sealed
3000
Filled
Sealed
75 (typ)
Empty
Sealed
Cover Tape
Leader (Start End)
K8X
Carrier
Trailer (Hub End)
Cover Tape
TAPE DIMENSIONS inches (millimeters)
TAPE FORMAT for MicroPak
Package
Designator
Tape
Number
Cavity
Section
Cavities
Status
Status
125 (typ)
Empty
Sealed
3000
Filled
Sealed
75 (typ)
Empty
Sealed
Leader (Start End)
L8X
Carrier
Trailer (Hub End)
TAPE DIMENSIONS inches (millimeters)
5
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NC7WZ38
Tape and Reel Specification
NC7WZ38
Tape and Reel Specification
(Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
8 mm
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165
0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40 + 1.50/−0.00)
(14.40)
(W1 + 2.00/−1.00)
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6
NC7WZ38
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
7
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NC7WZ38 TinyLogic UHS Dual 2-Input NAND Gate (Open Drain Output)
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
(Preliminary)
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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8