IRF IRS233JTRPBF

May 8, 2008
IRS233(0,2)(D)(S & J)PbF
3-PHASE-BRIDGE DRIVER
Features
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Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Independent half-bridge drivers
Matched propagation delay for all channels
3.3 V logic compatible
Outputs out of phase with inputs
Cross-conduction prevention logic
Integrated Operational Amplifier
Integrated Bootstrap Diode function (IRS233(0,2)D)
RoHS Compliant
Description
The IRS233(0,2)(D)(S & J) is a high voltage, high speed
power MOSFET and IGBT driver with three independent high
and low side referenced output channels. Proprietary HVIC
technology enables ruggedized monolithic construction.
Logic inputs are compatible with CMOS or LSTTL outputs,
down to 3.3 V logic. A ground-referenced operational
amplifier provides analog feedback of bridge current via an
external current sense resistor. A current trip function which
terminates all six outputs is also derived from this resistor.
An open drain FAULT signal indicates if an over-current or
undervoltage shutdown has occurred. The output drivers
feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are
matched to simplify use at high frequencies. The floating
channel can be used to drive N-channel power MOSFET
or IGBT in the high side configuration which operates up
to 600 volts.
Product Summary
VOFFSET
600V max.
IO+/-
200 mA / 420 mA
VOUT
10 V – 20 V (233(0,2)(D))
ton/off (typ.)
500 ns
Deadtime (typ.)
2.0 us (IRS2330(D))
0.7 us (IRS2332(D))
Applications:
*Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
*Micro/Mini Inverter Drives
Packages
28-Lead SOIC
44-Lead PLCC w/o 12 Leads
Typical Connection
Absolute Maximum Ratings
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IRS233(0,2)(D)(S&J)PbF
†
Qualification Information
Qualification Level
Industrial††
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
SOIC28W
MSL3†††, 260°C
(per IPC/JEDEC J-STD-020)
PLCC44
MSL3†††, 245°C
(per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
Human Body Model
ESD
Machine Model
IC Latch-Up Test
RoHS Compliant
†
††
†††
Class 2
(per JEDEC standard JESD22-A114)
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
Class I, Level A
(per JESD78)
Yes
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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IRS233(0,2)(D)(S&J)PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
VB1,2,3
High Side Floating Supply Voltage
-0.3
620
VS1,2,3
High Side Floating Offset Voltage
VB1,2,3 - 20
VB1,2,3 + 0.3
VHO1,2,3
High Side Floating Output Voltage
VS1,2,3 - 0.3
VB1,2,3 + 0.3
-0.3
20
VCC
VSS
VLO1,2,3
Low Side and Logic Fixed Supply Voltage
Logic Ground
Low Side Output Voltage
VCC - 20
VCC + 0.3
-0.3
VCC + 0.3
Units
V
_______ ______
Logic Input Voltage ( HIN1,2,3, LIN1,2,3 & ITRIP)
VSS -0.3
VFLT
VCAO
FAULT Output Voltage
Operational Amplifier Output Voltage
VSS -0.3
VSS -0.3
(VSS + 15) or
(VCC + 0.3)
Whichever is
lower
VCC +0.3
VCC +0.3
VCA-
Operational Amplifier Inverting Input Voltage
VSS -0.3
VCC +0.3
—
50
V/ns
—
—
1.6
2.0
W
78
63
150
VIN
dVS/dt
PD
Allowable Offset Supply Voltage Transient
Package Power Dissipation @ TA ≤ +25 °C
(28 lead SOIC)
(44 lead PLCC)
(28 lead SOIC)
(44 lead PLCC)
TJ
Junction Temperature
—
—
—
TS
Storage Temperature
-55
150
TL
Lead Temperature (soldering, 10 seconds)
—
300
RthJA
Thermal Resistance, Junction to Ambient
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°C/W
°C
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IRS233(0,2)(D)(S&J)PbF
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is
tested with all supplies biased at 15 V differential.
Symbol
Definition
Min.
Max.
VS1,2,3 +10
VS1,2,3 +20
VSO-8 (Note1)
600
-50 (Note2)
VS1,2,3
600
VB1,2,3
VB1,2,3
High Side Floating Supply Voltage
VS1,2,3
Static High side floating offset voltage
VSt1,2,3
VHO1,2,3
Transient High side floating offset voltage
VCC
Low Side and Logic Fixed Supply Voltage
10
20
VSS
Logic Ground
-5
5
0
VSS
VSS
VCC
VSS + 5
VCC
VLO1,2,3
VIN
VFLT
High Side Floating Output Voltage
Low Side Output Voltage
Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP)
FAULT Output Voltage
VCAO
Operational Amplifier Output Voltage
VSS
VSS + 5
VCA-
Operational Amplifier Inverting Input Voltage
VSS
VSS + 5
Ambient temperature
-40
125
TA
Units
V
°C
Note 1: Logic operational for VS of (VSO -8 V) to (VSO +600 V). Logic state held for VS of (VSO -8 V) to (VSO – VBS).
Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
the Application Information section of this datasheet for more details.
Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
Definition
Min Typ Max Units Test Conditions
ton
Turn-on propagation delay
400
500
700
toff
Turn-off propagation delay
400
500
700
tr
Turn-on rise time
—
80
125
tf
Turn-off fall time
—
35
55
titrip
ITRIP to Output Shutdown Propagation Delay
400
660
920
tbl
tflt
ITRIP Blanking Time
ITRIP to FAULT Indication Delay
Input Filter Time (All Six Inputs)
LIN1,2,3 to FAULT Clear Time (2330/2)
—
350
—
400
550
325
—
870
—
tflt, in
tfltclr
DT
MDT
Deadtime:
(IRS2330(D))
(IRS2332(D))
Deadtime matching: :
(IRS2330(D))
(IRS2332(D))
5300 8500 13700
1300 2000 3100
500 700 1100
—
—
400
—
—
140
MT
Delay matching time (t ON , t OFF)
—
—
50
PM
Pulse width distortion
—
—
75
VS1,2,3 = 0 V to 600 V
VS1,2,3 = 0 V
ns
VIN = 0 V & 5 V
without
external deadtime
VIN = 0 V & 5 V
without
external deadtime
larger than DT
PM input 10 µs
NOTE: For high side PWM, HIN pulse width must be > 1.5 usec
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IRS233(0,2)(D)(S&J)PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
SR+
SR-
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Definition
Operational Amplifier Slew Rate (+)
Operational Amplifier Slew Rate (-)
Min Typ Max Units Test Conditions
5
2.4
10
3.2
—
—
V/µs
1 V input step
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IRS233(0,2)(D)(S&J)PbF
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters
are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
VIH
Logic “0” input Voltage (OUT = LO)
VIL
Min Typ Max Units Test Conditions
—
—
2.2
VIT,TH+
Logic “1” input Voltage (OUT = HI)
ITRIP Input Positive Going Threshold
0.8
400
—
490
—
580
VOH
High Level Output Voltage, VBIAS - VO
—
—
1000
VOL
Low Level Output Voltage, VO
—
—
400
ILK
Offset Supply Leakage Current
—
—
50
IQBS
Quiescent VBS Supply Current
—
30
50
IQCC
Quiescent VCC Supply Current
—
4
6.2
IIN+
IIN-
Logic “1” Input Bias Current (OUT =HI)
Logic “0” Input Bias Current (OUT = LO)
“High” ITRIP Bias Current
“LOW” ITRIP Bias Current
VBS Supply Undervoltage
Positive Going Threshold
VBS Supply Undervoltage
Negative Going Threshold
VCC Supply Undervoltage
Positive going Threshold
VCC Supply Undervoltage
Negative Going Threshold
IITRIP+
IITRIPVBSUV+
VBSUVVCCUV+
VCCUV-
-400 -300 -100
-300 -220 -100
—
5
10
—
—
30
7.5
8.35
9.2
7.1
7.95
8.8
8.3
9
9.7
8
8.7
9.4
VCCUVH
Hysteresis
—
0.3
—
VBSUVH
Hysteresis
FAULT Low On-Resistance
—
0.4
—
—
55
75
IO+
Output High Short Circuit Pulsed Current
—
-250
-180
IO-
Output Low Short Circuit Pulsed Current
420
500
—
—
—
—
200
—
—
—
20
100
—
80
—
Ron, FLT
RBS
VOS
ICACMRR
PSRR
VOH,AMP
VOL,AMP
V
mV
VIN = 5 V, IO = 20 mA
µA
mA
µA
nA
VB = VS = 600 V
VIN = 0 V or 4 V
VIN = 0 V
VIN = 0 V
VIN = 4 V
ITRIP = 4 V
ITRIP = 0 V
V
Ω
mA
Integrated Bootstrap Diode resistance
Operational Amplifier Input Offset Voltage
CA- Input Bias Current
Operational Amplifier Common Mode
Rejection Ratio
Operational Amplifier Power Supply
Rejection Ratio
Operational Amplifier High Level Output
Voltage
Operational Amplifier Low Level Output
Voltage
VIN = 0 V, IO = 20 mA
Ω
mV
nA
dB
VO = 0 V, VIN = 0 V
PW ≤ 10 us
VO = 15 V, VIN = 5 V
PW ≤ 10 us
VSO = 0.2 V
VCA- = 1 V
VSO = 0.1 V & 5 V
VSO = 0.2 V
VCC = 9.7 V & 20 V
—
75
—
4.8
5.2
5.6
V
VCA- = 0 V, VSO =1 V
—
—
40
mV
VCA- = 1 V, VSO =0 V
Note: The integrated bootstrap diode does not work well with the trapezoidal control.
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IRS233(0,2)(D)(S&J)PbF
Static Electrical Characteristics- Continued
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters
are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
ISRC,AMP
Operational Amplifier Output Source Current
—
-7
-4
ISNK,AMP
Operational Amplifier Output Sink Current
1
2.1
—
-30
-10
—
—
4
—
IO+,AMP
IO-,AMP
Min Typ Max Units Test Conditions
Operational Amplifier Output High Short Circuit
Current
Operational Amplifier Output Low Short Circuit
Current
mA
VCA- = 0 V, VSO =1 V
VCAO = 4 V
VCA- = 1 V, VSO =0 V
VCAO = 2 V
VCA- = 0 V, VSO =5 V
VCAO = 0 V
VCA- = 5 V, VSO =0 V
VCAO = 5 V
Functional Block Diagram
IRS2330D/IRS2332D
INPUT
SIGNAL
GENERATOR
HIN1
HIN2
H1
L1
PULSE
GENERATOR
LEVEL
SHIFTER
SET
RESET
VB1
LATCH
UV
DETECTOR
HIN3
DRIVER
HO1
VS1
Integrated BS
Diode
LIN1
INPUT
SIGNAL
GENERATOR
LIN2
H2
L2
LIN3
PULSE
GENERATOR
LEVEL
SHIFTER
SET
VB2
LATCH
UV
RESET DETECTOR
DRIVER
HO2
VS2
Integrated BS
Diode
FAULT
FAULT
LOGIC
CLEAR
LOGIC
C
S
INPUT
SIGNAL
GENERATOR
H3
L3
PULSE
GENERATOR
LEVEL
SHIFTER
SET
RESET
LATCH
UV
DETECTOR
VB3
DRIVER
HO3
VS3
Integrated BS
Diode
VCC
DRIVER
ITRIP
0.5V
CURRENT
COMPARATOR
LO1
UNDER
VOLTAGE
DETECTOR
DRIVER
LO2
DRIVER
LO3
CAO
CURRENT
AMP
CA-
VSO
VSS
Note: IRS2330 & IRS2332 are without integrated bootstrap diode.
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IRS233(0,2)(D)(S&J)PbF
Lead Definitions
Symbol
HIN1,2,3
LIN1,2,3
FAULT
VCC
Description
Logic input for high side gate driver outputs (HO1,2,3), out of phase
Logic input for low side gate driver output (LO1,2,3), out of phase
Indicates over-current or undervoltage lockout (low side) has occurred, negative logic
Low side and logic fixed supply
ITRIP
Input for over-current shutdown
CAO
Output of current amplifier
CA-
Negative input of current amplifier
VSS
VB1,2,3
HO1,2,3
VS1,2,3
Logic Ground
High side floating supply
High side gate drive output
High side floating supply return
LO1,2,3
Low side gate drive output
VSO
Low side return and positive input of current amplifier
Lead Assignments
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IRS233(0,2)(D)(S&J)PbF
Application Information and Additional Details
Information regarding the following topics are included as subsections within this section of the datasheet.
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IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Input Logic Compatibility
Undervoltage Lockout Protection
Shoot-Through Protection
Fault Reporting
Over-Current Protection
Over-Temperature Shutdown Protection
Truth Table: Undervoltage lockout, ITRIP
Advanced Input Filter
Short-Pulse / Noise Rejection
Integrated Bootstrap Functionality
Bootstrap Power Supply Design
Separate Logic and Power Grounds
Negative VS Transient SOA
DC- bus Current Sensing
PCB Layout Tips
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS233(2,0)(D) HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several
parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of
the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the highside power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case
does not differentiate between the high-side or low-side output voltage.
Figure 1: HVIC sourcing current
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Figure 2: HVIC sinking current
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IRS233(0,2)(D)(S&J)PbF
Switching and Timing Relationships
The relationship between the input and output signals of the IRS233(0,2)(D) are illustrated below in Figures 3. From these
figures, we can see the definitions of several timing parameters (i.e., PWIN, PWOUT, tON, tOFF, tR, and tF) associated with this
device.
LINx
(or HINx)
50%
50%
PWIN
tON
LOx
(or HOx)
tR
PWOUT
90%
10%
tOFF
tF
90%
10%
Figure 3: Switching time waveforms
The following two figures illustrate the timing relationships of some of the functionality of the IRS233(0,2)(D); this functionality
is described in further detail later in this document.
During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same
time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output
are held in the off state.
Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the
gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is
reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault
condition is latched until the all LINx become high.
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IRS233(0,2)(D)(S&J)PbF
Figure 4: Input/output timing diagram
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a
minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power
switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is
automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified
by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals.
The deadtime circuitry of the IRS233(0,2)(D) is matched with respect to the high- and low-side outputs of a given channel;
additionally, the deadtimes of each of the three channels are matched.
LINx
HINx
50%
LOx
HOx
DT
50%
DT
50%
50%
Figure 5: Illustration of deadtime
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IRS233(0,2)(D)(S&J)PbF
Matched Propagation Delays
The IRS233(0,2)(D) family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s
response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the lowside channels and the high-side channels. Additionally, the propagation delay for each low-side channel is matched when
compared to the other low-side channels and the propagation delays of the high-side channels are matched with each other.
The propagation turn-on delay (tON) of the IRS233(0,2)(D) is matched to the propagation turn-on delay (tOFF).
Input Logic Compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS233(0,2)(D) family has been designed to
be compatible with 3.3 V and 5 V logic-level signals. The IRS233(0,2)(D) features an integrated 5.2 V Zener clamp on the
HIN, LIN, and ITRIP pins. Figure 6 illustrates an input signal to the IRS233(0,2)(D), its input threshold values, and the logic
state of the IC as a result of the input signal.
Figure 6: HIN & LIN input thresholds
Undervoltage Lockout Protection
This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the
VBS (high-side circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the
waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC
voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault
condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform
the controller of the fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage
decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and
shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to
fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low
voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high
conduction losses within the power device and could lead to power device failure.
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IRS233(0,2)(D)(S&J)PbF
Figure 7: UVLO protection
Shoot-Through Protection
The IRS233(0,2)(D) family of high-voltage ICs is equipped with shoot-through protection circuitry (also known as crossconduction prevention circuitry). Figure 8 shows how this protection circuitry prevents both the high- and low-side switches
from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table.
Note that the IRS233(0,2)(D) has inverting inputs (the output is out-of-phase with its respective input).
Shoot-through
protection enabled
HIN
LIN
HO
LO
Figure 8: Illustration of shoot-through protection circuitry
IRS233(0,2)(D)
HIN
LIN
HO
LO
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
Table 1: Input/output truth table
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IRS233(0,2)(D)(S&J)PbF
Fault Reporting
The IRS233(0,2)(D) family provides an integrated fault reporting output. There are two situations that would cause the HVIC
to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the ITRIP pin recognizes
a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault condition is latched. The fault
output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed,
the voltage on the FAULT pin will return to VCC.
Over-Current Protection
The IRS233(0,2)(D) HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events
in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is
reported through the FAULT pin.
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2)
connected to ITRIP as shown in Figure 9, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the
maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the
over-current threshold (VIT,TH+) at that current level.
VIT,TH+ = R0IDC-(R1/(R1+R2))
Vcc
HIN(x3)
VB ( x3)
LIN(x3)
HO( x3)
FAULT
VS (x3)
LO(x3)
ITRIP
COM
VSS
R1
R2
R0
IDC-
Figure 9: Programming the over-current protection
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5
V; if necessary, an external voltage clamp may be used.
Over-Temperature Shutdown Protection
The ITRIP input of the IRS233(0,2)(D) can also be used to detect over-temperature events in the system and initiate a
shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to
design the resistor network as shown in Figure 10 and select the maximum allowable temperature.
This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the
thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the
voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable
temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.
When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g.,
DL4148) can be used. This network is shown in Figure 11; the OR-ing diodes have been labeled D1 and D2.
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IRS233(0,2)(D)(S&J)PbF
Figure 10: Programming over-temperature protection
Figure 11: Using over-current protection and over-temperature
protection
Truth Table: Undervoltage lockout and ITRIP
Table 2 provides the truth table for the IRS233(0,2)(D). The first line shows that the UVLO for VCC has been tripped; the
FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is
greater than VCCUV, the FAULT output returns to the high impedance state.
The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled.
After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new falling transition of HIN. The third
case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and
that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the
low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the
FAULT pin will return to VCC.
UVLO VCC
UVLO VBS
Normal operation
ITRIP fault
VCC
<VCCUV
15 V
15 V
15 V
VBS
--<VBSUV
15 V
15 V
ITRIP
--0V
0V
>VITRIP
FAULT
0
High impedance
High impedance
0
LO
0
LIN
LIN
0
HO
0
0
HIN
0
Table 2: IRS233(0,2)(D) UVLO, ITRIP & FAULT truth table
Advanced Input Filter
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise
spikes and short pulses. This input filter has been applied to the HIN and LIN. The working principle of the new filter is shown
in Figures 12 and 13.
Figure 12 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1)
show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the difference between the
input signal and tFIL,IN. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then
tFIL,IN; the resulting output is approximately the difference between the input signal and tFIL,IN.
Figure 13 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms
(Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the same
duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer
then tFIL,IN; the resulting output is approximately the same duration as the input signal.
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15
IRS233(0,2)(D)(S&J)PbF
Figure 12: Typical input filter
Figure 13: Advanced input filter
Short-Pulse / Noise Rejection
Example 2
Example 1
This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the input
signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 14 shows the input and output in the low state
with positive noise spikes of durations less than tFIL,IN; the output does not change states. Example 2 of Figure 19 shows the
input and output in the high state with negative noise spikes of durations less than tFIL,IN; the output does not change states.
Figure 14: Noise rejecting input filters
Figures 15 and 16 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses.
The input filter characteristic is shown in Figure 15; the left side illustrates the narrow pulse ON (short positive pulse)
characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure 20 shows
the duration of PWIN, while the y-axis shows the resulting PWOUT duration. It can be seen that for a PWIN duration less than
tFIL,IN, that the resulting PWOUT duration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PWIN
duration exceed tFIL,IN, that the PWOUT durations mimic the PWIN durations very well over this interval with the symmetry
improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for the
high-side inputs be ≥ 500 ns.
The difference between the PWOUT and PWIN signals of both the narrow ON and narrow OFF cases is shown in Figure 16; the
careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PWIN, while the y-axis shows the
resulting PWOUT–PWIN duration. This data illustrates the performance and near symmetry of this input filter.
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16
IRS233(0,2)(D)(S&J)PbF
Narrow Pulse OFF
1000
PWOUT
PWIN
Time (ns)
800
600
400
200
0
0
200
400
600
800
1000
Time (ns)
Figure 15: IRS233(0,2)(D) input filter characteristic
Figure 16: Difference between the input pulse and the output pulse
Integrated Bootstrap Functionality
The new IRS233(0,2)D family features integrated high-voltage bootstrap MOSFETs that eliminate the need of the external
bootstrap diodes and resistors in many applications.
There is one bootstrap MOSFET for each high-side output channel and it is connected between the VCC supply and its
respective floating supply (i.e., VB1, VB2, VB3); see Figure 17 for an illustration of this internal connection.
The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and it has a limited source current due
to RBS. The VBS voltage will be charged each cycle depending on the on-time of LO and the value of the CBS capacitor, the
drain-source (collector-emitter) drop of the external IGBT (or MOSFET), and the low-side free-wheeling diode drop.
The bootstrap MOSFET of each channel follows the state of the respective low-side output stage (i.e., the bootstrap MOSFET
is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately 110% of VCC. In that
case, the bootstrap MOSFET is designed to remain off until VB returns below that threshold; this concept is illustrated in Figure
18.
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17
IRS233(0,2)(D)(S&J)PbF
Figure 17: Internal bootstrap MOSFET connection
Figure 18: Bootstrap MOSFET state diagram
A bootstrap MOSFET is suitable for most of the PWM modulation schemes and can be used either in parallel with the external
bootstrap network (i.e., diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of
the external bootstrap network may have some limitations. An example of this limitation may arise when this functionality is
used in non-complementary PWM schemes (typically 6-step modulations) and at very high PWM duty cycle. In these cases,
superior performances can be achieved by using an external bootstrap diode in parallel with the internal bootstrap network.
Bootstrap Power Supply Design
For information related to the design of the bootstrap power supply while using the integrated bootstrap functionality of the
IRS233(0,2)D family, please refer to Application Note 1123 (AN-1123) entitled “Bootstrap Network Analysis: Focusing on the
Integrated Bootstrap Functionality.” This application note is available at www.irf.com.
For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode) please refer
to Design Tip 04-4 (DT04-4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is available at www.irf.com.
Separate Logic and Power Grounds
The IRS233(0,2)(D) has separate logic and power ground pin (VSS and VSO respectively) to eliminate some of the noise
problems that can occur in power conversion applications. Current sensing shunts are commonly used in many applications
for power inverter protection (i.e., over-current protection), and in the case of motor drive applications, for motor current
measurements. In these situations, it is often beneficial to separate the logic and power grounds.
Figure 19 shows a HVIC with separate VSS and VSO pins and how these two grounds are used in the system. The VSS is
used as the reference point for the logic and over-current circuitry; VX in the figure is the voltage between the ITRIP pin and
the VSS pin. Alternatively, the VSO pin is the reference point for the low-side gate drive circuitry. The output voltage used to
drive the low-side gate is VLO-VSO; the gate-emitter voltage (VGE) of the low-side switch is the output voltage of the driver
minus the drop across RG,LO.
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18
IRS233(0,2)(D)(S&J)PbF
DC+ BUS
DBS
VB
(x3)
VCC
HO
(x3)
HVIC
ITRIP
VSS
CBS
RG,HO
VS
(x3)
LO
(x3)
COM
VS1
VS2
VS3
RG,LO
+
+
+
VGE1
VGE2
VGE3
-
-
-
R2
R0
+
VX
R1
-
DC- BUS
Figure 19: Separate VSS and VSO pins
Negative VS Transient SOA
A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the
power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure
20; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 21 and 22) switches off, while the U phase current is flowing to an
inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch
of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative
DC bus voltage.
Figure 20: Three phase inverter
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19
IRS233(0,2)(D)(S&J)PbF
DC+ BUS
DC+ BUS
Q1
ON
Q1
OFF
D1
IU
VS1
Q2
OFF
VS1
D2
DC- BUS
Figure 21: Q1 conducting
Q2
OFF
IU
D2
DC- BUS
Figure 22: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 23 and 24), and Q4 IGBT
switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the
positive DC bus voltage to the negative DC bus voltage.
DC+ BUS
Q3
OFF
D3
VS2
IV
Q4
ON
DC- BUS
Figure 23: D3 conducting
Figure 24: Q4 conducting
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings
below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 25 depicts one leg of the three phase inverter; Figures 26 and 27 show a simplified illustration of
the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the
PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage
by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power
switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to
VS1 (the load is not shown in these figures). This current flows from the DC- bus (which is connected to the VSO pin of the
HVIC) to the load and a negative voltage between VS1 and the DC- Bus is induced (i.e., the VSO pin of the HVIC is at a higher
potential than the VS pin).
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20
IRS233(0,2)(D)(S&J)PbF
Figure 25: Parasitic Elements
Figure 26: VS positive
Figure 27: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage
can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in
normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the IRS233(0,2)(D)’s robustness can be seen in Figure 28, where there is represented the IRS233(0,2)(D) Safe
Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area
(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC
do not appear if negative Vs transients fall inside SOA.
At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design
the high-side outputs in the off state for 4.5 μs.
Figure 28: Negative VS transient SOA for IRS233(0,2)(D)
Even though the IRS233(0,2)(D) has been shown able to handle these large negative VS transient conditions, it is highly
recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and
component use.
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21
IRS233(0,2)(D)(S&J)PbF
DC- bus Current Sensing
A ground referenced current signal amplifier has been included so that the current in the return leg of the DC bus may be
monitored. A typical circuit configuration is provided in Fig.29. The signal coming from the shunt resistor is amplified by the
ratio (R1+R2)/R2. Additional details can be found on Design Tip DT 92-6. This design tip is available at www.irf.com.
Figure 29: Current amplifier typical configuration
In the following Figures 30, 31, 32, 33 the configurations used to measure the operational amplifier characteristics are shown.
15V
VCC
VSO
CAO
CA-
0.2V
VSS
+
20K
1K
VSO
Figure 30: Operational Amplifier Slew rate measurement
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VSO 0.2V
21
Figure 31: Operational Amplifier Input Offset Voltage
measurement
22
IRS233(0,2)(D)(S&J)PbF
Figure 32: Operational Amplifier Common mode rejection
measurement
Figure 33: Operational Amplifier Power supply rejection
measurement
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating
voltage pins (VB and VS) near the respective high voltage portions of the device. The IRS233(0,2)(D) in the PLCC44 package
has had some unused pins removed in order to maximize the distance between the high voltage and low voltage pins.
Please see the Case Outline PLCC44 information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage
floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 34). In order
to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as
much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus
increasing the possibility of a self turn-on effect.
Figure 34: Antenna Loops
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23
IRS233(0,2)(D)(S&J)PbF
Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and VSS pins. This connection is
shown in Figure 35. A ceramic 1 μF ceramic capacitor is suitable for most applications. This component should be placed as
close as possible to the pins in order to reduce parasitic elements.
Vcc
HIN(x3)
VB ( x3)
LIN(x3)
I RS233(0,2)(D)
FAULT
ITRIP
HO( x3)
VS (x3)
LO(x3)
COM
VSS
R1
R2
R0
IDC-
Figure 35: Supply capacitor
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch
node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended
to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail
stray inductance. However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This
includes placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 36), and in some cases using a
clamping diode between VSS and VS (see Figure 37). See DT04-4 at www.irf.com for more detailed information.
Figure 36: VS resistor
Figure 37: VS clamping diode
Additional Documentation
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and
the document number to quickly locate them. Below is a short list of some of these documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs
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24
IRS233(0,2)(D)(S&J)PbF
Parameter Temperature Trends
Figures 38-76 provide information on the experimental performance of the IRS233(0,2)(D)(S&J) HVIC. The line plotted in each
figure is generated from actual lab data. A small number of individual samples were tested at three temperatures (-40 ºC, 25 ºC,
and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point
at each of the tested temperatures) that have been connected together to illustrate the understood temperature trend. The
individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given
temperature).
800
800
700
700
600
600
Exp.
Exp.
500
tON (ns)
tON (ns)
500
400
400
300
300
200
200
100
100
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
Fig. 38. Turn-on Propagation Delay vs.
Temperature
800
700
700
tOFF (ns)
tOFF (ns)
500
400
300
300
100
100
25
50
75
100
Temperature (o C)
Fig. 40. Turn-off Propagation Delay vs.
Temperature
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125
400
200
0
100
500
200
-25
75
Exp.
600
Exp.
0
-50
50
Fig. 39. Turn-on Propagation Delay vs.
Temperature
800
600
25
Temperature (o C)
Temperature (o C)
125
0
-50
-25
0
25
50
75
100
Temperature (o C)
Fig. 41. Turn-off Propagation Delay vs.
Temperature
25
125
IRS233(0,2)(D)(S&J)PbF
200
60
180
50
160
40
120
tF (ns)
tR (ns)
140
100
80
Exp.
60
30
Exp.
20
40
10
20
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
25
Temperature (oC)
Fig. 42. Turn-on Rise Time vs. Temperature
1000
900
900
800
700
600
tFLT (ns)
tITRIP (ns)
100
125
800
Exp.
500
400
500
400
300
200
200
100
100
-25
0
25
50
75
100
Exp.
600
300
0
-50
0
-50
125
-25
0
Temperature (oC)
50
75
100
125
Fig. 45. ITRIP to FAULT Indication Delay vs.
Temperature
16000
1200
14000
1000
Exp.
Exp.
DLTon1 (ns)
12000
25
Temperature (oC)
Fig. 44. ITRIP to Output Shutdown Propagation
Delay vs. Temperature
TFLTCLR (ns)
75
Fig.43. Turn-off Fall Time vs. Temperature
1000
700
50
Temperature (oC)
10000
8000
6000
800
600
400
4000
200
2000
0
-50
-25
0
25
50
75
100
Temperature (oC)
Fig.46. FAULT Clear Time vs. Temperature
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125
0
-50
-25
0
25
50
75
100
Temperature (oC)
Fig. 47. Dead Time vs. Temperature
26
125
IRS233(0,2)(D)(S&J)PbF
60
6
50
5
SR-_Amp (V/uS)
SR+_Amp (V/uS)
Exp.
40
30
20
4
3
2
Exp.
10
1
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
25
Temperature (oC)
Fig. 48. Operational Amplifier Slew Rate (+) vs.
Temperature
2.0
LIN1_VTH- (V)
LIN1_VTH+ (V)
Exp.
1.0
0.5
Exp.
1.5
1.0
-25
0
25
50
75
100
0.0
-50
125
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Fig. 50. Input Positive Going Threshold vs.
Temperature
Fig. 51. Input Negative Going Threshold vs.
Temperature
800
800
700
700
600
600
VIT,TH- (mV)
VIT,TH+ (mV)
125
0.5
0.0
-50
EXP.
400
300
500
400
Exp.
300
200
200
100
100
0
-50
100
2.5
1.5
500
75
Fig. 49. Operational Amplifier Slew Rate (-) vs.
Temperature
2.5
2.0
50
Temperature (oC)
0
-25
0
25
50
75
100
Temperature (oC)
Fig. 52. ITRIP Input Positive Going Threshold
vs. Temperature
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125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 53. ITRIP Input Negative Going Threshold
vs. Temperature
27
IRS233(0,2)(D)(S&J)PbF
60
450
400
50
ileak1_VCCMAX (µA)
VOL_LO1 (mV)
350
300
250
200
150
Exp.
100
40
30
20
10
Exp.
50
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Fig. 54. Low Level Output Voltage vs.
Temperature
Fig. 55. Offset Supply Leakage Current vs.
Temperature
7
12
6
10
Exp.
5
Exp.
IQCC0 (mA)
IQCC1 (mA)
8
6
4
4
3
2
2
1
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
Temperature (oC)
80
80
70
70
60
60
50
50
Exp.
30
10
10
0
25
50
75
100
Temperature (oC)
Fig. 58. Quiescent VBS Supply Current vs.
Temperature
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100
125
30
20
-25
75
125
Exp.
40
20
0
-50
50
Fig. 57. Quiescent VCC Supply Current vs.
Temperature
IQBS11 (μA)
IQBS10 (μA)
Fig. 56. Quiescent VCC Supply Current vs.
Temperature
40
25
Temperature (oC)
0
-50
-25
0
25
50
75
100
Temperature (oC)
Fig. 59. Quiescent VBS Supply Current vs.
Temperature
28
125
IRS233(0,2)(D)(S&J)PbF
9.6
9.8
9.4
9.6
9.2
9.4
VCCUV+ (V)
VCCUV- (V)
9.0
8.8
8.6
Exp.
8.4
9.2
9.0
Exp.
8.8
8.6
8.2
8.4
8.0
7.8
-50
-25
0
25
50
75
100
8.2
-50
125
-25
0
25
Temperature (oC)
Fig. 60. VCC Supply Undervoltage Negative
Going Threshold vs. Temperature
100
125
9.5
9.0
8.5
8.5
8.0
Exp.
Exp.
VBSUV+ (V)
VBSUV- (V)
75
Fig. 61. VCC Supply Undervoltage Positive
Going Threshold vs. Temperature
9.0
7.5
7.0
8.0
7.5
7.0
6.5
6.5
6.0
-50
-25
0
25
50
75
100
6.0
-50
125
-25
0
25
50
75
100
Fig. 62. VBS Supply Undervoltage Negative
Going Threshold vs. Temperature
Fig. 63. VBS Supply Undervoltage Positive
Going Threshold vs. Temperature
0
-50
-50
90
80
70
-25
0
25
50
75
100
-100
60
-150
50
I O+ (mA)
Exp.
40
30
-200
-250
Exp.
-300
20
-350
10
0
-50
-400
-25
0
25
50
75
100
Temperature (oC)
Fig. 64. FAULT Low On-Resistance vs.
Temperature
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125
Temperature (oC)
Temperature (o C)
RON,FLT (Ω)
50
Temperature (oC)
125
-450
Temperature (oC)
Fig. 65. Output High Short Circuit Pulsed
Current vs. Temperature
29
125
IRS233(0,2)(D)(S&J)PbF
20
706
Exp.
606
15
10
VOS_AMP (mV)
IO- (mA)
506
406
306
206
5
0
-50
-5
Exp.
-25
0
25
50
75
100
125
-10
106
-15
6
-50
-25
0
25
50
75
100
125
-20
Temperature (oC)
Fig. 67. Offset Opamp vs. Temperature
200
200
180
180
160
160
140
140
CMRR_AMP (dB)
PSRR_AMP (dB)
Fig. 66. Output Low Short Circuit Pulsed
Current vs. Temperature
120
100
Exp.
80
60
100
Exp.
80
60
40
20
20
-25
0
25
50
Temperature (oC)
75
100
0
-50
125
Fig. 68. Operational Amplifier Power Supply
Rejection Ratio vs. Temperature
5.6
35
5.5
30
VOH_AMP (mV)
5.3
5.2
5.1
Exp.
5.0
0
25
50
Temperature (oC)
75
100
125
25
20
Exp.
15
10
5
4.9
4.8
-50
-25
Fig. 69. Operational Amplifier Common Mode
Rejection Ratio vs. Temperature
5.4
VOH_AMP (V)
120
40
0
-50
Temperature (oC)
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 70. Operational Amplifier High Level Output
Voltage vs. Temperature
www.irf.com
0
-50
-25
0
25
50
75
100
Temperature (oC)
Fig. 71. Operational Amplifier Low Level
Output Voltage vs. Temperature
30
125
IRS233(0,2)(D)(S&J)PbF
16
6
14
5
Exp.
4
Io-_AMP (mA)
Isnk_AMP (mA)
12
Exp.
3
2
10
8
6
4
1
2
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
Temperature (oC)
Fig. 72. Operational Amplifier Output Sink
Current vs. Temperature
0
-50
-2
-25
0
25
50
75
100
0
-50
125
75
100
-25
0
25
50
75
100
-5
-10
Io+_AMP (mA)
Isrc_AMP (mA)
50
-6
-8
Exp.
-15
Exp.
-20
-25
-12
-30
-14
-16
-35
Temperature (oC)
Temperature (oC)
Fig. 74. Operational Amplifier Output Source
Current vs. Temperature
0
-50
-25
0
Fig. 75. Operational Amplifier Output High
Short Circuit Current vs. Temperature
25
50
75
100
125
Vs1_RST_domin (V)
-2
-4
-6
-8
-10
Exp.
-12
-14
Temperature (o C)
Fig. 76. Max –Vs vs. Temperature
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125
Fig. 73. Operational Amplifier Output Low
Short Circuit Current vs. Temperature
-4
-10
25
Temperature (oC)
31
125
IRS233(0,2)(D)(S&J)PbF
Case Outlines
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32
IRS233(0,2)(D)(S&J)PbF
Case Outlines
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33
IRS233(0,2)(D)(S&J)PbF
Tape and Reel Details: SOIC28W
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
11.90
12.10
B
3.90
4.10
C
23.70
24.30
D
11.40
11.60
E
10.80
11.00
F
18.20
18.40
G
1.50
n/a
H
1.50
1.60
28SOICW
Imperial
Min
Max
0.468
0.476
0.153
0.161
0.933
0.956
0.448
0.456
0.425
0.433
0.716
0.724
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 28SOICW
Metric
Imperial
Code
Min
Max
Min
Max
A
329.60
330.25
12.976
13.001
B
20.95
21.45
0.824
0.844
C
12.80
13.20
0.503
0.519
D
1.95
2.45
0.767
0.096
E
98.00
102.00
3.858
4.015
F
n/a
30.40
n/a
1.196
G
26.50
29.10
1.04
1.145
H
24.40
26.40
0.96
1.039
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34
IRS233(0,2)(D)(S&J)PbF
Tape and Reel Details: PLCC44
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
23.90
24.10
B
3.90
4.10
C
31.70
32.30
D
14.10
14.30
E
17.90
18.10
F
17.90
18.10
G
2.00
n/a
H
1.50
1.60
44PLCC
Imperial
Min
Max
0.94
0.948
0.153
0.161
1.248
1.271
0.555
0.562
0.704
0.712
0.704
0.712
0.078
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 44PLCC
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
38.4
G
34.7
35.8
H
32.6
33.1
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Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
1.511
1.366
1.409
1.283
1.303
35
IRS233(0,2)(D)(S&J)PbF
Ordering Information
Base Part Number Package Type
SOIC28W
IRS233(0,2)(D)
PLCC44
Standard Pack
Form
Quantity
Tube/Bulk
25
Tape and Reel
1000
Tube/Bulk
27
Tape and Reel
500
Complete Part Number
IRS233(0,2)(D)SPbF
IRS233(0,2)(D)STRPbF
IRS233(0,2)(D)JPbF
IRS233(0,2)(D)JTRPbF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document
supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
36