19-6400; Rev 0; 7/12 MAX71020 Single-Chip Electricity Meter AFE General Description Features S0.1% Accuracy Over 2000:1 Current Range SExceeds IEC 62053/ANSI C12.20 Standards STwo Differential Current Sensor Inputs STwo Voltage Sensor Inputs SSelectable Gain of 1 or 9 for One Current Input to Support a Shunt SHigh-Speed Wh/VARh Pulse Outputs with Programmable Width SUp to Four Pulse Outputs with Pulse Count SFour-Quadrant Metering SDigital Temperature Compensation SIndependent 32-Bit Compute Engine S45Hz to 65Hz Line Frequency Range with Same Calibration SPhase Compensation (±10°) SFour Multifunction DIO Pins S SPI Interface S -40°C to +85°C Industrial Temperature Range S 28-Pin TSSOP Lead(Pb)-Free Package The MAX71020 is a single-chip, analog front-end to be used in high-performance revenue meters. It contains the compute engine found in Maxim’s fourth-generation meter SOC and an improved ADC, and interfaces to the host microcontroller of choice over a SPI interface. The MAX71020 comes in a 28-pin TSSOP package. Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX71020.related. Typical Operating Circuit CT NEUTRAL LINE SHUNT LOAD NOTE: THIS SYSTEM IS REFERENCED TO LINE NEUTRAL POWER SUPPLY LINE LINE RESISTORDIVIDER MUX AND ADC IAP IAN V3P3A V3P3SYS GNDA GNDD MAX71020 VA REGULATOR VB IBP TEMPERATURE SENSOR IBN VREF COMPUTE ENGINE POWER-FAULT COMPARATOR DIO, PULSES HOST OSCILLATOR/PLL XIN SPI INTERFACE 9.8304MHz XOUT For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX71020 Single-Chip Electricity Meter AFE ABSOLUTE MAXIMUM RATINGS (All voltages with respect to GNDA.) Voltage and Current Supplies and Ground Pins V3P3SYS, V3P3A...................................................-0.5V to +4.6V GNDD....................................................................-0.1V to +0.1V Analog Input Pins IAP, IAN, IBP, IBN, VA, VB.............................(-10mA to +10mA), (-0.5V to (V3P3A + 0.5V)) XIN, XOUT.......................... (-10mA to +10mA), (-0.5V to +3.0V) Digital Pins Inputs..................................... (-10mA to +10mA), (-0.5V to +6V) Outputs............. (-10mA to +10mA), (-0.5V to (V3P3SYS + 0.5V)) Temperature and ESD Stress Operating Junction Temperature (peak, 100ms)............... 140°C Operating Junction Temperature (continuous).................. 125°C Storage Temperature Range............................. -45°C to +165°C ESD Stress on All Pins...............................................±4kV, HBM Lead Temperature (soldering, 10s)................................... 300°C Soldering Temperature (reflow).......................................+250°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TSSOP Junction-to-Ambient Thermal Resistance (qJA)...........78°C/W Junction-to-Case Thermal Resistance (qJC)................ 13NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN TYP MAX UNITS RECOMMENDED OPERATING CONDITIONS V3P3SYS and V3P3A Supply Voltage Precision metering operation 3.0 3.6 Digital operation 2.8 3.6 -40 +85 Operating Temperature V NC INPUT LOGIC LEVELS Digital High-Level Input Voltage (VIH) 2 V Digital Low-Level Input Voltage (VIL) 0.8 V Input Pullup Current (IIL) RESETZ VV3P3SYS = 3.6V, VIN = 0V 41 78 115 FA Input Pullup Current (IIL) Other Digital Inputs VV3P3SYS = 3.6V, VIN = 0V -1 0 +1 FA Input Pulldown Current (IIH) All Pins VIN = V3P3SYS -1 0 +1 FA OUTPUT LOGIC LEVELS ILOAD = 1mA V3P3SYS - 0.4 ILOAD = 15mA (Note 2) V3P3SYS - 1.1 Digital High-Level Output Voltage (VOH) Digital Low-Level Output Voltage (VOL) V ILOAD = 1mA 0 0.4 ILOAD = 15mA (Note 2) 0 0.96 V TEMPERATURE MONITOR TNOM (Nominal Value at 22NC) VV3P3A = 3.3V 956 LSB 2 MAX71020 Single-Chip Electricity Meter AFE ELECTRICAL CHARACTERISTICS (continued) PARAMETER CONDITIONS Temperature Measurement Equation Temperature Error (Note 2) MIN TYP MAX Temp = 0.33 x STEMP + 21.77 TA = -40NC to +85NC -6 +6 TA = -20NC to +60NC -4.8 +4.8 Duration of Temperature Measurement TEMP_PER = 0 After Setting TEMP_START 15 UNITS NC NC 60 ms 4.3 mA SUPPLY CURRENT PERFORMANCE SPECIFICATIONS V3P3A + V3P3SYS Current (Note 2) VV3P3A = VV3P3SYS = 3.3V, CE_E = 1, ADC_E = 1 INTERNAL POWER-FAULT COMPARATOR SPECIFICATIONS Overall Response Time Falling Threshold 100mV overdrive, falling 20 200 100mV overdrive, rising 8 200 µs 3.0V comparator 2.83 2.93 3.03 2.8V comparator 2.75 2.81 2.89 V 50 136 220 mV 17 45 74 15 42 70 Difference 3.0V and 2.8V comparators Hysteresis (Rising Threshold - Falling 3.0V comparator, TA = +22NC Threshold) 2.8V comparator, TA = +22NC V mV PLL PERFORMANCE SPECIFICATIONS PLL Power-Up Settling Time PLL_FAST Settling Time PLL Lock Frequency at XOUT VV3P3A = 0 to 3.3V step, measured from first edge of MCK 75 VV3P3A = 3.3V, PLL_FAST rise 10 VV3P3A = 3.3V, PLL_FAST fall 10 VV3P3A = 3.3V, MCK frequency error < 1% µs µs 7 9.8 13 MHz 1.200 1.205 1.210 V +1.5 mV/V VREF PERFORMANCE SPECIFICATIONS VREF Output Voltage, VREF (22) TA = +22NC VREF Power-Supply Sensitivity (DVREF/DV3P3A) V3P3A = 3.0V to 3.6V -1.5 VNOM(T) = VREF(22) + TC1(T - 22) + TC2(T - 22)2 V VNOM Temperature Coefficient TC1 29.32 - 1.05 x TRIMT µV/NC VNOM Temperature Coefficient TC2 -0.56 - 0.004 x TRIMT µV/NC2 VNOM Definition VREF(T) Deviation from VNOM(T): VREF(T) - VNOM(T)10 6 VNOM(T) 62 (Note 2) -40 +40 ppm/NC -250 +250 mV peak ADC CONVERTER PERFORMANCE SPECIFICATIONS Recommended Input Range (With Respect to GNDA) VA, VB, IBP, IBN 3 MAX71020 Single-Chip Electricity Meter AFE ELECTRICAL CHARACTERISTICS (continued) PARAMETER CONDITIONS Recommended Input Range (With Respect to GNDA) IAP, IAN (preamplifier enabled) Input Impedance, No Preamplifier fIN = 65Hz MIN TYP -27.78 MAX UNITS +27.78 mV peak 50 ADC Gain Error vs Percentage PowerSupply Variation VIN = 200mV peak, 65Hz 10 6 ∆Nout PK 357nV VIN VV3P3A = 3.0V, 3.6V 100∆V3P3A 3.3 -10 100 kI 81 ppm/% +10 mV Input Offset IAP = IAN = GNDA Total Harmonic Distortion at 250mVpk VIN = 55Hz, 250mVpk, 64kpts FFT, Blackman Harris Window -85 dB Total Harmonic Distortion at 20mVpk VIN = 55Hz, 20mVpk, 64kpts FFT, Blackman Harris Window -85 dB FIRLEN = 15 FIRLEN = VIN = 55Hz, 20mVpk, 64kpts FIRLEN = LSB Size (LSB Values Do Not Include FFT, Blackman-Harris the 9-Bit Left Shift at the CE Input) FIRLEN = window, 10MHz CKADC FIRLEN = Digital Full Scale VIN = 55Hz, 10MHz CKADC 120.46 14 146.20 13 179.82 12 224.59 11 285.54 FIRLEN = 10 370.71 FIRLEN = 15 ±2621440 FIRLEN = 14 ±2160000 400mVpk, FIRLEN = 13 FIRLEN = 12 ±1756160 FIRLEN = 11 ±1105920 FIRLEN = 10 ±851840 ±1406080 nV LSB PREAMPLIFIER PERFORMANCE SPECIFICATIONS Differential Gain, (VIN = 28mV Differential) TA = +25NC, VV3P3A = 3.3V, PRE_E = 1, DIFF0_E = 1 8.9 V/V Gain Variation vs. V3P3 (VIN = 28mV Differential) VV3P3A = 3.0V, 3.6V -72 ppm/% Gain Variation vs. Temperature (VIN = 28mV Differential) (Note 4) TA = -40NC to +85NC -45 ppm/NC Differential Gain (VIN = 15mV Differential) 4 MAX71020 Single-Chip Electricity Meter AFE ELECTRICAL CHARACTERISTICS (continued) PARAMETER CONDITIONS MIN TYP MAX UNITS 8 mN 20 FA Phase Shift (VIN = 28mV Differential) TA = +25NC, VV3P3A = 3.3V (Note 2) 0 Preamplifier Input Current (IADC0) Preamplifier Input Current (IADC1) PRE_E = 1, DIFF0_E = 1, IADC0 = IADC1 = V3P3A 9 Preamplifier and ADC Total Harmonic (VIN = 28mV Differential) TA = +25NC; VV3P3A = 3.3V, PRE_E = 1, DIFF0_E = 1 -80 dB Preamplifier and ADC Total Harmonic TA = +25NC; VV3P3A = 3.3V, PRE_E = 1, Distortion (VIN = 15mV Differential) DIFF0_E = 1 -85 dB 15 SPI SLAVE TIMING SPECIFICATIONS SPI Setup Time SPI_DI to SPI_CK rise 10 ns SPI Hold Time SPI_CLK rise to SPI_DI 10 ns SPI Output Delay SPI_CLK fall to SPI_D0 SPI Recovery Time SPI_CSZ fall to SPI_CLK 10 ns SPI Removal Time SPI_CLK to SPI_CSZ rise 15 ns SPI Clock High 40 ns SPI Clock Low 40 ns 40 SPI Clock Frequency 10 SPI Transaction Space (SPI_CSZ Rise to SPI_CSZ Fall) ns MHz 1 Fs Following power-on 1 ms At all other times 5 RESETZ TIMING Reset Pulse Width Fs Reset Pulse Rise Time (Note 2) 1 Fs VOLTAGE MONITOR Nominal value at +22NC (VNOM) VV3P3A = 3.3V Voltage Measurement Equation 130 LSB VV3P3(CALC) = 3.29V + (BSENSE – 130) x 0.025V + STEMP x 242µV Voltage Error V (CALC) 100 × V3P3 - 1 VV3P3 -4 +4 % Note 2: Guaranteed by design, not production tested. Note 3:V3P3SYS and V3P3A must be connected together. Note 4: AGND and DGND must be connected together. 5 MAX71020 Single-Chip Electricity Meter AFE RECOMMENDED EXTERNAL COMPONENTS NAME FROM TO FUNCTION C1 V3P3A GNDA CSYS V3P3SYS GNDD Bypass capacitor for V3P3SYS C1P8 VDD GNDD XTAL XIN XOUT CXS XIN GNDA CXL XOUT GNDA VALUE R 0.1 ±20% UNITS R 1.0 ±30% µF Bypass capacitor for V1P8 regulator 0.1 ±20% µF At cut crystal specified for 18pF load 9.8304 MHz 32 ±10% pF 32 ±10% pF Bypass capacitor for 3.3V supply Load capacitor values for crystal depend on crystal specifications and board parasitics. Nominal values are based on 4pF board capacitance and include an allowance for chip capacitance. µF Pin Configuration TOP VIEW + VA 1 28 VB GNDA 2 27 TEST0 V3P3A 3 26 XOUT IBN 4 25 XIN IBP 5 24 V3P3SYS IAN 6 23 VDD IAP 7 22 DIO0/WPULSE TEST 8 21 DIO1/VPULSE RESETZ 9 20 DIO2/XPULSE VPP 10 19 INTZ DIO3 / YPULSE 11 18 N.C. GNDD 12 17 N.C. SPI_CSZ 13 16 SPI_CLK SPI_DO 14 15 SPI_DI MAX71020 TSSOP 6 MAX71020 Single-Chip Electricity Meter AFE Pin Description (Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under Figure 1). PIN NAME TYPE CIRCUIT DESCRIPTION POWER AND GROUND PINS 2 GNDA P — Analog Ground. GNDA should be connected directly to the ground plane. 3 V3P3A P — Analog Power Supply. A 3.3V power supply should be connected to V3P3A. V3P3A must be the same voltage as V3P3SYS. 12 GNDD P — Digital Ground. GNDD should be connected directly to the ground plane. 23 VDD O — Output of the 1.8V Regulator. A 0.1µF bypass capacitor to ground should be connected to this pin. 24 V3P3SYS P — System 3.3V Supply. V3P3SYS should be connected to a 3.3V power supply. I 6 Differential or Single-Ended Line Current-Sense Inputs. These pins are voltage inputs to the internal ADC. Typically, these pins are connected to the outputs of current sensors. Unused pins must be tied to GNDA. I 6 Line Voltage Sense Inputs. VA/VB are voltage inputs to the internal ADC. Typically, the pins are connected to the outputs of resistordividers. Unused pins must be tied to GNDA. 8 Crystal Inputs. A 9.8304MHz crystal should be connected to XIN and XOUT. ANALOG PINS 7, 6 IAP, IAN 5, 4 IBP, IBN 1, 28 VA, VB 25 XIN I 26 XOUT O DIGITAL PINS 22 DIO0/WPULSE 21 DIO1/VPULSE 20 DIO2/XPULSE 11 DIO3/YPULSE 8, 27 9 Multiple-Use Pins. Configurable as DIO. Alternative functions with proper selection of associated registers are: DIO0 = WPULSE DIO1 = VPULSE I/O 3, 4 TEST, TEST0 I 3 Connect to GNDD RESETZ I 3 Active-Low Reset 13 SPI_CSZ I 3 14 SPI_DO O 4 15 SPI_DI I 3 16 SPI_CLK I 3 19 INTZ O 4 Active-Low Interrupt Request VPP I — Connect to GNDD SPI Interface OTHER PIN 10 7 MAX71020 Single-Chip Electricity Meter AFE V3P3SYS V3P3SYS DIGITAL INPUT PIN CMOS INPUT ANALOG INPUT PIN GNDA GNDD DIGITAL INPUT EQUIVALENT CIRCUIT TYPE 3 V3P3SYS TO MUX ANALOG INPUT EQUIVALENT CIRCUIT TYPE 6: ADC INPUT V3P3SYS V3P3SYS DIGITAL OUPUT PIN CMOS OUTPUT GNDD GNDA GNDD DIGITAL OUTPUT EQUIVALENT CIRCUIT TYPE 4 TO OSCILLATOR OSCILLATOR PIN GNDA OSCILLATOR EQUIVALENT CIRCUIT TYPE 8: OSCILLATOR I/O Figure 1. I/O Equivalent Circuits 8 MAX71020 Single-Chip Electricity Meter AFE Functional Block Diagram GNDA V3P3A IAP MAX71020 IAN IBP IBN DC MODULATOR INPUT MULTIPLEXER PREAMPLIFIER FIR DECIMATOR VB VA VREF VREF MULTIPLEXER CONTROL XIN XOUT V3P3SYS CRYSTAL OSCILLATOR 9.83MHz MASTER CLOCK PLL VOLTAGE REGULATOR MCK VDD CKADC (10MHz, 5MHz, 2.5MHz, 1.25MHz) CLOCK GENERATOR GNDD 1.8V TO LOGIC SPI_CSZ CKCE 20MHz, 5MHz MUX_SYNC SPI_CLK VSTAT VPULSE 2 XPULSE VSTAT PARITY ERR XFER_BUSY WPULSE V3P3A POWER STATUS SPI_DO START CE 32-BIT COMPUTE ENGINE TEMP SENSE VREF SPI_DI SPI YPULSE 2 INTZ INTZ D10_WPULSE PULSE CONTROL D11_VPULSE IO_CTRL D12_XPULSE D13_YPULSE RESETZ 9 MAX71020 Single-Chip Electricity Meter AFE Hardware Description Hardware Overview The MAX71020 energy meter analog front-end (AFE) integrates all primary functional blocks required to implement a solid-state residential electricity meter. Included on the chip are: ● An analog front-end (AFE) featuring a 22-bit secondorder sigma-delta ADC ● An independent 32-bit digital computation engine (CE) to implement DSP functions ● A precision voltage reference (VREF) ● A temperature sensor for digital temperature compensation ● Four I/O pins ● A zero-crossing interrupt ● Resistive shunt and current transformers are supported ● A SPI slave for connection to a host microcontroller In a typical application, the 32-bit compute engine (CE) of the MAX71020 sequentially processes the samples from the voltage inputs on analog input pinsand performs calculations to measure active energy (Wh) and reactive energy (VARh), as well as A2h, and V2h for four-quadrant metering. These measurements are then accessed by the host microcontroller. In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement, e.g., to meet the requirements of ANSI and IEC standards. Temperature-dependent external components such as crystal oscillator, resistive shunts, current transformers (CTs) and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature range. Communications with the host is conducted over a SPI interface. The communications protocol between the host and the MAX71020 provides a redundant information transfer ensuring the correctness of commands transferred from the host to the AFE, and of data transferred from the AFE to the host. In addition, the MAX71020 has one pin dedicated as an interrupt output to the host. In this way, the MAX71020 notifies the host of asynchronous events. Analog Section Signal Input Pins The MAX71020 has four analog inputs: two single-ended inputs for voltage measurement, and two differential inputs for current measurement. IAP, IAN, IBP, and IBN pins are current sensor inputs. The differential inputs feature preamplifiers with a selectable gain of 1 or 9, and are intended for direct connection to a shunt resistor sensor or a current transformer (CT). The voltage inputs in the MAX71020 are single-ended, and are intended for sensing the line voltage. These single-ended inputs are referenced to the GNDA pin. All analog signal input pins measure voltage. In the case of shunt current sensors, currents are sensed as a voltage drop in the shunt resistor sensor. In the case of Current Transformers (CT), the current is measured as a voltage across a burden resistor that is connected to the secondary winding of the CT. Meanwhile, line voltages are sensed through resistive voltage-dividers. Voltage inputs are single-ended and their common return is the GNDA pin. Some versions of the device implement a preamplifier with a fixed gain of 9 to enhance performance when using sensors with a low-amplitude output (for example, current shunts). When using a device with the preamplifier enabled, you must ensure that the input amplitude is no greater than 27.78mV peak. Input Multiplexer The input multiplexer sequentially applies the input signals from the analog input pins to the input of the ADC. One complete sampling sequence is called a multiplexer frame. The IBP-IBN differential input may be used to sense the neutral current, and VB may be optionally used to sense a second voltage channel.This configuration implies that the multiplexer applies a total of four inputs to the ADC. For this configuration, the multiplexer sequence is as shown in Figure 1. In this configuration IAP-IAN, IBP-IBN, VA and VB are sampled. The physical current sensor for the neutral current measurement and the voltage sensor for VB may be omitted if not required. 10 MAX71020 Single-Chip Electricity Meter AFE For a standard single-phase application with tamper sensor in the neutral path, two current inputs are configured for differential mode, using the pin pairs IAP-IAN and IBP-IBN. In the MAX71020, the system uses two locally connected current sensors via IAP-IAN and IBP-IBN and configured as differential inputs. The VA pin is typically connected to the phase voltage via resistor-dividers. The MAX71020 adds the ability to sample a second phase voltage (applied at the VB pin), which makes it suitable for meters with two voltage and two current sensors, such as meters implementing Equation 2 for dualphase operation (P = VA x IA + VB x IB). Table 1 summarizes the AFE input configuration. Delay Compensation When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that phase must be sampled at the same instant. Otherwise, the phase difference, φ, introduces errors. = φ t delay T × 360 = t delay × f × 360 where f is the frequency of the input signal, T = 1/f and tDELAY is the sampling delay between current and voltage. Table 1. ADC Input Configuration PIN IAP IAN IBP IBN COMMENT The ADC results are stored in register IA. The ADC result is stored in register VA. VB The ADC result is stored in register VB. The constant delay allpass filter provides a broadband delay 360N - θ, which is precisely matched to the difference in sample time between the voltage and the current of a given phase. This digital filter does not affect the amplitude of the signal, but provides a precisely controlled phase response. The ADC multiplexer samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle φ relative to the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., 360N), then routing the voltage samples through the allpass filter, thus delaying the voltage samples by 360N - θ, resulting in the residual phase error between the current and its corresponding voltage of θ - φ. The residual phase error is negligible, and is typically less than ±0.0015N at 100Hz, thus it does not contribute to errors in the energy measurements. ADC Preamplifier The ADC preamplifier is a low-noise differential amplifier with a fixed gain of 9 available on the IAP and IAN currentsensor input pins. It is provided only in versions of the MAX71020 AFE configured for use with current shunts. The ADC results are stored in register IB. VA Traditionally, sampling is accomplished by using two ADCs per phase (one for voltage and the other one for current) controlled to sample simultaneously. Maxim’s Teridian™ Single-Converter Technology®, however, exploits the 32-bit signal processing capability of its CE to implement “constant delay” allpass filters. The allpass filter corrects for the conversion time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed ADC. MULTIPLEXER FRAME MUX DIV = 4 CONVERSIONS SETTLE CK32 MUX STATE S 0 1 2 3 IA VA IB VB S 0 CROSS MUX_SYNC Figure 2. States in a Multiplexer Frame Teridian is a trademark and Single Converter Technology is a registered trademark of Maxim Integrated Products, Inc. 11 MAX71020 Single-Chip Electricity Meter AFE Analog-to-Digital Converter (ADC) A single second-order delta-sigma ADC digitizes the voltage and current inputs to the device. The resolution of the ADC is dependent on several factors. ● Monitoring of the input signal amplitude (for sag detection) Initiation of each ADC conversion is automatically controlled by logic internal to the MAX71020. At the end of each ADC conversion, the FIR filter output data is stored into the register determined by the multiplexer selection. FIR data is stored LSB justified, but shifted left 9 bits. ● Scaling of samples based on temperature compensation information ● Scaling of the processed samples based on calibration coefficients ● Gain and phase compensation FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data is stored into the register determined by the multiplexer selection. Meter Equations The MAX71020 provides hardware assistance to the CE in order to support various meter equations. This assistance is controlled through register EQU[2:0] (equation assist). The Compute Engine (CE) firmware implements the equations listed in Table 2. EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering. Voltage References A bandgap circuit provides the reference voltage to the ADC. Since the VREF bandgap amplifier is chopper stabilized, the DC offset voltage, which is the most significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the chopper circuit. Pulse Generators The MAX71020 provides up to four pulse generators, VPULSE, WPULSE, XPULSE, and YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse generators are used to output CE status indicators and energy usage. Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: ● Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied with the constant sample time) ● Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between samples caused by the multiplexing scheme) ● 90° phase shifter (for VAR calculations) ● Pulse generation ● Monitoring of the input signal frequency (for frequency and phase information) The polarity of the pulses may be inverted with control bit PLS_INV. When this bit is set, the pulses are active-high, rather than the more usual active-low. PLS_INV inverts all four pulse outputs. The function of each pulse generator is determined by the CE code. The MAX71020 provides a mains zerocrossing indication on XPULSE and voltage sag detection on YPULSE. A common use of the zero-crossing pulses is to generate interrupt in order to drive RTC software in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging. A common use for the SAG pulse is to generate an interrupt that alerts the host processor when mains power is about to fail, so that the host processor can store accumulated energy and other data to EEPROM before the supply voltage actually drops. Table 2. Inputs Selected in Multiplexer Cycles EQU DESCRIPTION 0 1 element, 2W, 1j with neutral current sense 1 1 element, 3-W, 1j 2 2 element, 3-W Wh and VARh FORMULA ELEMENT 0 ELEMENT 1 VA ∙ IA VA ∙ IB VA(IA-IB)/2 VA ∙ IB/2 VA ∙ IA VB ∙ IB 12 MAX71020 Single-Chip Electricity Meter AFE Table 3. Pulse Output Function Assignments OUTPUT FUNCTION XPULSE Pulse output on each zero crossing on voltage input YPULSE Pulse output when voltage sag detected VPULSE Pulse output when programmed VARh consumption has occurred WPULSE Pulse output when programmed Wh consumption has occurred XPULSE and YPULSE Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse output pins. Pins D2 and D3 are used for these pulses, respectively. The XPULSE and YPULSE outputs can be updated once on each pass of the CE code. See the CE Interface Description section for details. VPULSE and WPULSE By default, WPULSE and VPULSE are negative pulses (i.e., low level pulses, designed to sink current through an LED). PLS_MAXWIDTH[7:0] determines the maximum negative pulse width TMAX in units of CK_FIR clock cycles based on the pulse interval TI according to the formula: TMAX = (2 x PLS_MAXWIDTH[7:0] + 1) x TI TI is based on an internal value that determines the pulse interval and the ADC clock, both of which are determined by the particular characteristics of the compute engine. In the MAX71020, the default value for TI is 65.772µs, but this value changes in customized versions of this part. If PLS_MAXWIDTH = 255 no pulse-width checking is performed, and the pulses default to 50% duty cycle. TMAX is typically programmed to 10ms (TMAX = 76), which works well with most calibration systems. The polarity of the pulses may be inverted with the control bit PLS_INV. When PLS_INV is set, the pulses are activehigh. The default value for PLS_INV is zero, which selects active-low pulses. Temperature Sensor The MAX71020 includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of current, voltage, and energy measurement. See the Metrology Temperature Compensation section. The temperature sensor is awakened on command from the host microcontroller by setting the TEMP_START control bit. The host microcontroller must wait for the TEMP_START bit to clear before reading STEMP[15:0] and before setting the TEMP_START bit once again. The result of the temperature measurement can be read from the STEMP[15:0] register. The 16-bit value is in two’s complement form and ranges from -1024 to +1023 (decimal). The sensed temperature can be computed from the 16-bit STEMP[15:0] reading using the following formula: Temp (NC) = 0.325 x STEMP + 22 An additional register, VSENSE[7:0], senses the level of supply voltage. Table 4 shows the registers used for temperature measurement. Digital I/O On reset or power-up, all DIO pins are configured as high-impedance. DIO pins can be configured independently by the host microcontroller by manipulating the D0, D1, D2, and D3 bit fields. The WPULSE and VPULSE pulse generator outputs are available on pins D0/WPULSE and D1/VPULSE, respectively. Table 4. Temperature Measurement Registers NAME RST WK DIR TBYTE_BUSY 0 0 R DESCRIPTION Indicates that hardware is still writing the result. Additional writes to this byte are locked out while it is one. Write duration could be as long as 6ms. 13 MAX71020 Single-Chip Electricity Meter AFE Table 4. Temperature Measurement Registers (continued) NAME RST WK DIR DESCRIPTION Sets the period between temperature measurements TEMP_PER TEMP_PER[1:0] 0 — R/W TIME 0 Manual updates (see TEMP_START description) 1 Every accumulation cycle 2 Continuous TEMP_PER[1:0] must be zero in order for TEMP_START to function. If TEMP_PER[1:0] = 0, then setting TEMP_START starts a temperature measurement. Hardware clears TEMP_START when the temperature measurement is complete. The host microcontroller must wait for TEMP_START to clear before reading STEMP[10:0] and before setting TEMP_START again. TEMP_START 0 — R/W STEMP[15:0] — — R The result of the temperature measurement VSENSE[7:0] — — R The result of voltage sense reading: V3P3SYS = VSENSE[7:0]/42.7 SPI Slave Port The slave SPI port communicates directly with the host microcontroller and allows it to read and write the device control registers. The interface to the slave port consists of the SPI_CSZ, SPI_CLK, SPI_DI, and SPI_DO pins. SPI Transactions SPI transactions are configured to provide immunity to electrical noise through redundancy in the command segment and error checking in the data field. The MAX71020 SPI transaction is exactly 64 bits; transactions of any other length are rejected. Each SPI transaction has the following fields: ● A 24-bit setting packet, consisting of 11-bit address, MSB first 1-bit direction (1 means read) 11-bit inverted address, MSB first 1-bit inverted direction ● An 8-bit status, consisting of the following bits concerning the last transaction, starting from bit 7: 11-bit address, MSB Parity of the status byte (0 or 1 could be correct) FIFO overflow status bit (1 means error) FIFO underrun status bit (1 means error) Read or write data parity (0 or 1 could be correct) (never both read and write; address is not included in the parity) Address or direction mismatch error bit (1 means error) Result of the SPI_CSZ glitch detector (1 means error) A bit indicating whether or not the bit count was exactly 64 (1 means error). Out of bounds address, most likely due to SPI safe bit or the memory manager (1 means error). ● A 32-bit packet of data, MSB first If extra clocks are provided at the end during a read, all zero is output and the status will continue to be updated, signaling an error. If extra clocks are provided at the end during a write, the write will be aborted and the status will be updated to signal an error. ● None of the fields above are optional. ● If an error is detected during the address or direction phase, no action will be taken. ● SPI_DO is high-Z while SPI_CSZ is high. ● SPI safe mode will be supported, and SPI will not be locked out of this bit during SPI safe. A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state. During this state, SPI_DO is held in high-Z state and all transitions on SPI_CLK and SPI_DI are ignored. When SPI_CSZ falls, the port will begin the transaction on the first rising edge of SPI_CLK. As shown in Table 5, a transaction consists of a 24-bit setting field, an 8-bit 14 MAX71020 Single-Chip Electricity Meter AFE Table 5. SPI Transaction (64 Bits) 24-BIT SETTING FIELD Address Dir 8-BIT STATUS 32-BIT DATA Status from Previous Transaction: status[7:0] Data Status FIFO FIFO Data Setting CSB Bad Bad Parity OverRun UnderRun Parity Mismatch Glitch CK Cnt Address data[31:0] Inv Address Inv Dir addr[10:0] RD addr_b[10:0] RD_b SERIAL READ 11-BIT ADDRESS RD 11-BIT INVERTED ADDRESS STATUS BYTE RD DATA [ADDR] (FROM HOST) SPI_CSZ 0 (FROM HOST) SPI_CLK A10 (FROM HOST) SPI_DI A9 A1 (FROM AM48) SPI_DO SERIAL WRITE 10 11 A0 HI-Z RD 11-BIT ADDRESS A10 22 23 A0 RD A9 24 31 11-BIT INVERTED ADDRESS 47 48 63 X ST7 ST6 RD 32 RD ST0 D31 D30 D16 D15 D14 D13 STATUS BYTE D1 D0 DATA [ADDR] (FROM HOST) SPI_CSZ 0 (FROM HOST) SPI_CLK (FROM HOST) SPI_DI X A10 A9 A1 (FROM AM48) SPI_DO 10 11 A0 HI-Z RD A10 A9 22 23 A0 RD 24 ST7 ST6 31 32 47 48 D31 D30 D16 D15 D14 D13 63 D1 D0 X ST0 Figure 3. SPI Slave Port—Typical READ and WRITE operations status, and a 32-bit data word. The transaction ends when SPI_CSZ is raised. Assuming phase angles are constant, the following formulae apply: Note that the status byte indicates the status of the previous SPI transaction except for the status byte parity. P = Real Energy [Wh] = V x A x cos φ x t SPI Safe Mode Sometimes it is desirable to prevent the SPI interface from writing to arbitrary registers and possibly disturbing the CE operation. For this reason, the SPI_SAFE mode is created. In this mode, all SPI writes are disabled except to the word containing the SPI_SAFE bit. This affords the host one more layer of protection from inadvertent writes. S = Apparent Energy [VAh] = Functional Description Theory of Operation The energy delivered by a power source into a load can be expressed as: t E = ∫ V(t)I(t)dt 0 Q = Reactive Energy [VARh] = V x A x sin φ x t P 2 + Q2 For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may constantly change. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the MAX71020 functions by emulating the integral operation above, i.e., it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling yield an accurate quantity for the momentary energy. Summing the instantaneous energy quantities over time provides very accurate results for accumulated energy. 15 MAX71020 Single-Chip Electricity Meter AFE voltage. The following discussion assumes that V3P3A and V3P3SYS are connected together at the PCB level. 500 During a power failure, as V3P3A falls, two thresholds are detected. The first threshold, at 3.0V, warns the host microcontroller that the analog modules are no longer accurate. The second threshold, at 2.8V, warns the host microcontroller that a serious reduction in supply voltage has occurred. OTP reads may be affected. 400 300 200 100 0 -100 -200 CURRENT [A] VOLTAGE [V] ENERGY PER INTERVAL [Ws] ACCUMULATED ENERGY [Ws] -300 -400 -500 0 5 10 15 20 Figure 4. Voltage, Current, Momentary and Accumulated Energy Figure 4 shows the shapes of V(t), I(t), the instantaneous power and the accumulated energy resulting from 50 samples of the voltage and current signals over a period of 20ms. The application of 240VAC and 100A results in an accumulation of 480Ws (= 0.133Wh) over the 20ms period, as indicated by the accumulated power curve. The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. Fault and Reset Behavior Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (1.8VDC). V3P3SYS and V3P3A must be connected together at the PCB level, so that the comparators, which are internally connected only to the V3P3A, are able to simultaneously monitor the common V3P3SYS and V3P3A Reset Sequence When the MAX71020 receives a reset signal, either from the RESETZ pin or from the SPI, it asynchronously halts what it was doing. It then clears RAM and initializes configuration bits. An errant RESET can occur during an ESD event. If this happens, the host must be notified. This is accomplished by holding the INTZ output low until the host clears it. Applications Information Sensor Connection Figure 5 to Figure 8 show voltage-sensing resistive dividers, current-sensing current transformers (CTs) and current-sensing resistive shunts and how they are connected to the voltage and current inputs of the MAX71020. All input signals to the MAX71020 sensor inputs are voltage signals providing a scaled representation of either a sensed voltage or current. The analog input pins of the MAX71020 are designed for sensors with low source impedance. RC filters with resistance values higher than those implemented in the demo boards must not be used. Refer to the demo board schematics for complete sensor input circuits and corresponding component values. Table 6. VSTAT[1:0] VSTAT[1:0] 00 DESCRIPTION 01 System Power-OK. VV3P3A > 3.0V. Analog modules are functional and accurate. System Power is low. 2.8V < VV3P3A < 3.0V. Analog modules not accurate. 11 System power below 2.8V. Ability to monitor power is about to fail. 16 MAX71020 Single-Chip Electricity Meter AFE RIN VA VIN ROUT GNDA Figure 5. Resistive Voltage-Divider (Voltage Sensing) IIN IOUT IAP RBURDEN CT VOUT GNDA NOISE FILTER 1:N Figure 6. CT With Single-Ended Input Connection (Current Sensing) IIN IOUT IAP GNDA CT RBURDEN VOUT IAN BIAS NETWORK AND NOISE FILTER 1:N Figure 7. CT With Differential Input Connection (Current Sensing) IAP GNDA RSHUNT VOUT IAN BIAS NETWORK AND NOISE FILTER Figure 8. Differential Resistive Shunt Connections (Current Sensing) 17 MAX71020 Single-Chip Electricity Meter AFE Connecting the MAX71020 configuration implements a single-phase measurement with tamper-detection using one current sensor to measure the neutral current. This configuration can also be used to create a split phase meter (e.g., ANSI Form 2S). Figure 9 shows a typical MAX71020 configuration. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected to a CT and is therefore isolated. This CT NEUTRAL CT OR LINE LOAD NOTE: THIS SYSTEM IS REFERENCED TO LINE SHUNT NEUTRAL POWER SUPPLY LINE MUX AND ADC V3P3A V3P3SYS GNDA GNDD IAP RESISTORDIVIDER IAN LINE MAX71020 VA REGULATOR VB IBP TEMPERATURE SENSOR IBN VREF RAM COMPUTE ENGINE POWER-FAULT COMPARATOR PULSE /AUX RESETZ INTZ HOST OSCILLATOR/PLL XIN SPI INTERFACE 9.8304MHz XOUT Figure 9. Connecting the MAX71020 18 MAX71020 Single-Chip Electricity Meter AFE Metrology Temperature Compensation Voltage Reference Precision Since the VREF bandgap amplifier is chopper-stabilized the DC offset voltage, which is the most significant longterm drift mechanism in the voltage references, is automatically removed by the chopper circuit. Maxim trims the VREF voltage reference during the device manufacturing process to ensure the best possible accuracy. The reference voltage (VREF) is trimmed to a target value of 1.205V nominal. During this trimming process, the TRIMT[7:0] value is stored in nonvolatile fuses. TRIMT[7:0] is trimmed to a value that results in minimum VREF variation with temperature. The TRIMT[7:0] value can be read by the host microcontroller during initialization to calculate parabolic temperature compensation coefficients suitable for each individual device. The resulting temperature coefficient for VREF is ±40ppm/°C. Considering the factory calibration temperature of VREF to be +22°C and the industrial temperature range (-40°C to +85°C), the VREF error at temperature extremes can be calculated as: (85°C - 22°C) x 40ppm/°C = +2520ppm = +1.252% and (-40°C - 22°C) x 40ppm/°C = +2480ppm = -0.248% The above calculation implies that both the voltage and the current measurements are individually subject to a theoretical maximum error of approximately ±0.25%. When the voltage sample and current sample are multiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately ±0.5% maximum energy measurement error. However, this theoretical ±0.5% error considers only the voltage reference (VREF) as an error source. In practice, other error sources exist in the system. The principal remaining error sources are the current sensors (shunts or CTs) and their corresponding signal conditioning circuits, and the resistor voltage-divider used to measure the voltage. The 0.5% grade devices should be used in class 1% designs, allowing sufficient margin for the other error sources in the system. Crystal Oscillator The oscillator drives an AT cut microprocessor crystal at a frequency of 9.8304MHz. Board layouts with minimum capacitance from XIN to XOUT require less current. Good layouts have XIN and XOUT shielded from each other and from digital signals. Since the oscillator is self-biasing, an external resistor must not be connected across the crystal. Meter Calibration Once the MAX71020 energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: ● Establishment of the reference temperature (e.g., typically 22NC). ● Calibration of the metrology section, i.e., calibration for tolerances of the current sensors, voltage-dividers, and signal conditioning components as well as of the internal reference voltage (VREF) at the reference temperature (e.g., typically 22NC). The metrology section can be calibrated using the gain and phase adjustment factors accessible to the CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. Phase adjustment is provided to compensate for phase shifts introduced by the current sensors or by the effects of reactive power supplies. The MAX71020 supports common industry-standard calibration techniques, such as single-point (energy-only) and multipoint (energy, VRMS, IRMS). 19 MAX71020 Single-Chip Electricity Meter AFE Host Microcontroller Interface Register Map Table 7. Register Map NAME BYTE R/W ADDRESS DEFAULT VALUE DESCRIPTION CAL_IA 0x010 R/W 0x0000 4000 Calibration constant for current channel A. Unity gain = 0x0000 4000. CAL_VA 0x011 R/W 0x0000 4000 Calibration constant for current channel B. Unity gain = 0x0000 4000. ADJ_A 0x012 R/W 0x0000 0000 — CAL_IB 0x013 R/W 0x0000 4000 Calibration constant for voltage channel A. Unity gain = 0x0000 4000. CAL_VB 0x014 R/W 0x0000 4000 Calibration constant for voltage channel B. Unity gain = 0x0000 4000. ADJ_B 0x015 R/W 0x0000 0000 — Configures internal CE operation CECONFIG 0x020 R/W WRATE 0x021 R/W 0x0030 DB00 0x0000 0223 BIT NAME DESCRIPTION 0 PULSE_SLOW Reduces pulse output rate by a factor of 64. Must not be used with PULSE_FAST. 1 PULSE_FAST Increases pulse output rate by a factor of 16. Must not be used with PULSE_SLOW. 5:2 Reserved — 6 FREQSEL Select phase for frequency measurement: 0 = A, 1=B 7 Reserved — 19:8 SAG_CNT Number of consecutive voltage samples below SAG_THR before a sag event is declared 20 SAG_INT Enable sag detect output on YPULSE 21 EDGE_INT Enable zero-crossing output on XPULSE 31:22 Reserved — Sets meter constant for pulse outputs. See the Pulse Generation section. KVAR 0x022 R/W 0x0000 192C Scale factor for VAR measurements SAG_THR 0x024 R/W 0x016C AF60 Voltage threshold for sag warnings. See the CE Status and Control section. QUANT_VA 0x025 R/W 0x0000 0000 Truncation/noise compensation for voltage phase A QUANT_IA 0x026 R/W 0x0000 0000 Truncation/noise compensation for current phase A QUANT_A 0x027 R/W 0x0000 0000 Truncation/noise compensation for real power phase A QUANT_VARA 0x028 R/W 0x0000 0000 Truncation/noise compensation for reactive power phase A QUANT_VB 0x029 R/W 0x0000 0000 Truncation/noise compensation for voltage phase B QUANT_IB 0x02A R/W 0x0000 0000 Truncation/noise compensation for current phase B QUANT_B 0x02B R/W 0x0000 0000 Truncation/noise compensation for real power phase B QUANT_VARB 0x02C R/W 0x0000 0000 Truncation/noise compensation for reactive power phase B GAIN_ADJ0 0x040 R/W 0x0000 4000 Scale value for voltage inputs VA and VB. Default value of 16,384 is unity gain. 20 MAX71020 Single-Chip Electricity Meter AFE Table 7. Register Map (continued) NAME BYTE R/W ADDRESS DEFAULT VALUE DESCRIPTION GAIN_ADJ1 0x041 R/W 0x0000 4000 Scale value for current input IA. Default value of 16,384 is unity gain. Scale value for current input IB. Default value of 16,384 is unity gain. GAIN_ADJ2 0x042 R/W 0x0000 4000 WPULSE_CTR 0x045 R — Pulse generator counter (real power) WPULSE_FRAC 0x046 R — Pulse generator numerator (real power) WSUM_ACCUM 0x047 R — Pulse generator rollover accumulator (real power) VPULSE_CTR 0x049 R — Pulse generator counter (reactive power) VPULSE_FRAC 0x04A R — Pulse generator numerator (reactive power) VSUM_ACCUM 0x04B R — Pulse generator rollover accumulator (reactive power) Status of the Compute Engine CESTATUS 0x080 R —- BIT NAME 0 SAG_A Sag status, voltage phase A 1 SAG_B Sag status, voltage phase B 2 Reserved 3 F0 31:4 Reserved DESCRIPTION —Square wave at exact line frequency —- FREQ_X 0x082 R — Fundamental line frequency in units of (2520.6 x 2-32)Hz MAINEDGE_X 0x083 R — Number of zero crossings of either direction during previous accumulation period WSUM_X 0x084 R — Signed sum of real energy from both wattmeter elements W0SUM_X 0x085 R — Real energy from wattmeter element 0 W1SUM_X 0x086 R — Real energy from wattmeter element 1 VARSUM_X 0x088 R — Signed sum of reactive energy from both wattmeter elements VAR0SUM_X 0x089 R — Reactive energy from wattmeter element 0 VAR1SUM_X 0x08A R — Reactive energy from wattmeter element 1 I0SQSUM_X 0x08C R — Sum of squared samples from current sensor 0 I1SQSUM_X 0x08D R — Sum of squared samples from current sensor 1 V0SQSUM_X 0x090 R — Sum of squared samples from voltage sensor 0 V1SQSUM_X 0x091 R — Sum of squared samples from voltage sensor 1 IA 0x100 R — Most recent result of ADC conversion for current channel A IB 0x102 R — Most recent result of ADC conversion for current channel B VB 0x109 R — Most recent result of ADC conversion for voltage channel B VA 0x10A R — Most recent result of ADC conversion for voltage channel A 21 MAX71020 Single-Chip Electricity Meter AFE Table 7. Register Map (continued) NAME BYTE R/W ADDRESS DEFAULT VALUE DESCRIPTION Contains identifying information for the device DEVICEID 0x301 R 0x0000 1100 BIT NAME 7:0 Reserved — DESCRIPTION 15:8 VERSION Version index. Currently, on 0x11 is defined as die type AM48A0A. 31:16 CHIP_ID Family tag and feature tag of the device, currently 0x0000 STEMP 0x30A R — Result of the temperature measurement. Only bits 26:16 are significant; all other bits return zero. BSENSE 0x30B R — Result of the device VDD measurement. Only bits 23:16 are significant; all other bits return zero. 22 MAX71020 Single-Chip Electricity Meter AFE Table 7. Register Map (continued) NAME BYTE R/W ADDRESS DEFAULT VALUE DESCRIPTION Contains the characteristics of the four digital I/O pins IOCFG 0x30C R/W BIT NAME DESCRIPTION 0 DI0 Reflects logic state on DIO0 1 DI1 Reflects logic state on DIO1 2 DI2 Reflects logic state on DIO2 Reflects logic state on DIO3 3 DI3 7:4 Reserved 8 D_OD0 Configures DIO0 as open drain if configured as output 9 D_OD1 Configures DIO1 as open drain if configured as output 10 D_OD2 Configures DIO2 as open drain if configured as output 11 D_OD3 Configures DIO3 as open drain if configured as output 15:12 Reserved — — DO Configures DIO0. 00: Hi-Z 01: WPULSE 10: Logic 1 11: Logic 0 D1 Configures DIO1. 00: Hi-Z 01: VPULSE 10: Logic 1 11: Logic 0 D2 Configures DIO2. 00: Hi-Z 01: XPULSE 10: XFER_BUSY 11: Logic 0 23:22 D3 Configures DIO3. 00: Hi-Z 01: YPULSE 10: CE_BUSY 11: Logic 31:24 Reserved 0x0000 0F00 17:16 19:18 21:20 — Configures hardware aspects of the AFE METER_CFG 0x30D R/W 0xFF00 0080 BIT NAME DESCRIPTION 14:0 Reserved — 15 PLS_INV Force meter pulses to be positive-going rather than negative-going 23:16 Reserved — 31:24 PLS_MAXWID Determines the maximum width of a meter pulse 23 MAX71020 Single-Chip Electricity Meter AFE Table 7. Register Map (continued) NAME BYTE R/W ADDRESS DEFAULT VALUE DESCRIPTION Interrupt configuration register: configure the behavior of the INTZ pin INT_CFG 0x30F R/W 0x0000 8000 BIT NAME DESCRIPTION 0 IE_WPULSE Enables an interrupt to occur on the leading edge of WPULSE 1 IE_VPULSE Enables an interrupt to occur on the leading edge of VPULSE 2 IE_YPULSE Enables an interrupt to occur on the leading edge of YPULSE 3 IE_XPULSE Enables an interrupt to occur on the leading edge of XPULSE 4 IE_XDATA Enables an interrupt to occur at the conclusion of the accumulation interval, indicating that fresh data is available 5 IE_CEBUSY 6 Reserved — 7 IE_VSTAT Enables an interrupt to occur when the VSYS status changes 11:8 INT_POL Interrupt polarity for the PULSE edges. The default polarity is falling edge. INT_POL[3]=1: Interrupt on rising edge of YPULSE INT_POL[2]=1: Interrupt on rising edge of XPULSE INT_POL[1]=1: Interrupt on rising edge of VPULSE INT_POL[0]=1: Interrupt on rising edge of WPULSE 14:12 Reserved — 15 D_ODINTZ 31:16 Reserved Enables an interrupt to occur when the CE cycles is complete Enable open-drain on the INTZ output. By default, the pin is configured as a CMOS totempole output. — 24 MAX71020 Single-Chip Electricity Meter AFE Table 7. Register Map (continued) NAME BYTE R/W ADDRESS DEFAULT VALUE BYTE ADDRESS Reflects the status of several asynchronous events in the AFE M_STAT 0x310 R 0x0100 0100 BIT NAME DESCRIPTION 0 F_WPULSE Set on start of WPULSE 1 F_VPULSE Set on start of VPULSE 2 F_XPULSE Set on start of YPULSE 3 F_YPULSE Set on start of XPULSE 4 F_XDATA Set when data available 5 F_CEBUSY 6 Reserved — 7 F_VSTAT Set when VSYS status changes Set at end of CE code pass 8 F_RESET Set following AFE reset 15:9 Reserved — 16 F_WPULSE Copy of bit 0 17 F_VPULSE Copy of bit 1 18 F_XPULSE Copy of bit 2 19 F_YPULSE Copy of bit 3 20 F_XDATA Copy of bit 4 Copy of bit 5 21 F_CEBUSY 23:22 Reserved — 24 F_RESET Copy of bit 8 31:25 Reserved — 25 MAX71020 Single-Chip Electricity Meter AFE Table 7. Register Map (continued) NAME BYTE R/W ADDRESS DEFAULT VALUE DESCRIPTION Backup of M_STAT – updated when M_STAT is read M_STAT_B 0x311 R 0x0100 0100 BIT NAME DESCRIPTION 0 FB_WPULSE Set on start of WPULSE 1 FB_VPULSE Set on start of VPULSE 2 FB_XPULSE Set on start of YPULSE 3 FB_YPULSE Set on start of XPULSE 4 FB_XDATA Set when data available 5 FB_CEBUSY Set at end of CE code pass 7:6 Reserved — 8 FB_RESET Set following AFE reset 15:9 Reserved — 16 FB_WPULSE Copy of bit 0 17 FB_VPULSE Copy of bit 1 18 FB_XPULSE Copy of bit 2 19 FB_YPULSE Copy of bit 3 20 FB_XDATA Copy of bit 4 21 FB_CEBUSY Copy of bit 5 23:22 Reserved — 24 FB_RESET Copy of bit 8 31:25 Reserved — VSTAT 0x312 R — AFE Supply Voltage Status. Bits 1:0 reflect system power status: 00: System power-OK: VV3P3A > 3.0V 01: System power-low: 2.8V < VV3P3A < 3.0V 11: System power-fail: VV3P3A < 2.8V RESET 0x322 WO — Write 0x8100 0000 to this register to reset the AFE. 26 MAX71020 Single-Chip Electricity Meter AFE Table 7. Register Map (continued) NAME BYTE R/W ADDRESS DEFAULT VALUE DESCRIPTION Configures aspects of the temperature measurement subsystem TEMP_CNF TEMP_START SPI_SAFE 0x323 0x324 0x325 R/W R/W R/W 0x0000 0000 BIT NAME 1:0 Reserved DESCRIPTION — 3:2 TEMP_PER Sets the period between temperature measurements. 01: Measure every accumulation cycle 10: Continuous measurement Other values disable automatic updates. 4 TEMP_SYS When set, VSYS is measured at every temperature measurement cycle 31:5 Reserved — 0x0000 0000 Write 0x8000 0000 to start a temperature conversion cycle. When conversion is complete, the AFE will clear bit 31 and return the register to zero. 0x0000 0000 Write 0x8000 0000 to this word to lock the SPI port. When the SPI port is locked, no read or write operations are possible except to the SPI_SAFE register. Clearing this register to zero disables the SPI lock and restores normal operation. Enables aspects of the AFE METER_EN 0x326 R/W 0x0000 0000 BIT NAME 0 ADC_E 1 CE_E 31:2 Reserved DESCRIPTION Enable ADC and VREF buffer. Must be set by host following initialization. Enable CE. Must be set by host following initialization. — 27 MAX71020 Single-Chip Electricity Meter AFE CE Interface Description The CE reads the ADC and stores its results in the 1KB block at 0x000. Since all CE operations are 32 bits wide, the CE data memory occupies the first 256 32-bit locations, from 0x000 to 0x0FF. Note: The CE interface described in the data sheet is a description of a CE codebase that was available at the time of the writing. Changes may have occurred in the codebase in the interim, and may not be reflected in this document. Please contact your representative or Maxim technical support for the latest information. CE Data Format All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement format (-1 = 0xFFFFFFFF). Calibration parameters are copied to CE data memory by the host microcontroller before enabling the CE. Internal variables are used in internal CE calculations. Input variables allow the MPU to control the behavior of the CE code. Constants Constants used in the CE Data Memory tables are: U f0 is the fundamental frequency of the mains phases. U IMAX is the external RMS current corresponding to the maximum allowed voltage on the current inputs. For the IB input, this is 250mV peak (176.8mVRMS). In the MAX71020, IA normally has a preamplifier enabled on the IA inputs, so IMAX needs to be adjusted to 27.78mV peak (19.64mVRMS) for the IAP-IAN inputs. For a 250µΩ shunt resistor, IMAX becomes 78A (19.64mVRMS/250µΩ = 78.57A) for IA, and 707A (176.8mVRMS/250µΩ = 707.2ARMS) for IB. U VMAX is the external RMS voltage corresponding to 250mV peak at the VA and VB inputs. U NACC, the accumulation count for energy measurements (typically 2520). U The duration of the accumulation interval for energy measurements is NACC/FS = 2520/2,520.6 ≈ 1s. U X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_ SLOW(see Table 13). U Voltage LSB (for sag threshold) = VMAX x 7.879810 - 9V. The system constants IMAX and VMAX are used by the host processor to convert internal digital quantities (as used by the CE) to external, real-world metering quantities. Their values are determined by the scaling of the voltage and current sensors used in an actual meter. The LSB values used in this document relate digital quantities at the CE or MPU interface to external meter input quantities. For example, if a SAG threshold of 80VRMS is desired at the meter input, the digital value that should be programmed into SAG_THR (register 0x024) would be 80VRMS x SQRT(2)/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR (see Table 14). Environment Before starting the CE (that is, before setting the CE_E bit) the host processor must establish the equation to be applied in EQU[2:0]. By default, default settings are assumed to be VMAX = 600V, IMAX = 707A, and kH = 1. CE Calculations In Table 8, The MPU selects the desired equation by writing the EQU[2:0] (register 0x30D[14:12]). Table 8. CE EQU Equations and Element Input Mapping EQU WATT AND VAR FORMULA (WSUM/VARSUM) 0 VA IA – 1 element, 2W 1f 1 VA x (IA-IB)/2 – 1 element, 3W 1f 2 VA x IA + VB x IB– 2 element, 3W 1f INPUTS USED FOR ENERGY/CURRENT CALCULATION W0SUM/ VAR0SUM W1SUM/ VAR1SUM I0SQ SUM I1SQ SUM VA x IA VA x IB IA — VA x (IA-IB)/2 — IA-IB IB VA x IA VB x IB IA IB 28 MAX71020 Single-Chip Electricity Meter AFE Table 9. CE Raw Data Access Locations PIN REGISTER IA 0x100 VA 0x101 IB 0x102 VB 0x103 Table 10. CESTATUSRegister CE ADDRESS NAME 0x80 CESTATUS DESCRIPTION See the description of CESTATUS bits in Table 11 Table 11. CESTATUS (Register 0x080) Bit Definitions CESTATUS BIT NAME 31:4 Not Used 3 F0 2 Not Used 1 SAG_B Set when VB remains below SAG_THR for SAG_CNT samples. Automatically clears when VB rises above SAG_THR. 0 SAG_A Set when VA remains below SAG_THR for SAG_CNT samples. Automatically clears when VA rises above SAG_THR. DESCRIPTION These unused bits are always zero F0 is a square wave at the line frequency This unused bit is always zero CE Front-End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading registers 0x100–0x003 as shown in Table 9. CE Status and Control The CE Status Word, CESTATUS, is useful for generating early warnings to the host processor (Table 10). It contains sag warnings for phase A and B, as well as F0, the derived clock operating at the line frequency. The host microcontroller can read the CE status word at every CE_BUSY interrupt. CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating an early power-fail warning to initiate necessary data storage. CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in CESTATUS is shown in Table 11. 29 MAX71020 Single-Chip Electricity Meter AFE Table 12. CECONFIG Register CE ADDRESS NAME DATA 0x20 CECONFIG 0x0030DB00 DESCRIPTION See the description of the CECONFIG bits in Table 13 Table 13. CECONFIG Bit Definitions CECONFIG BIT NAME DEFAULT DESCRIPTION 21 EDGE_INT 1 When 1, XPULSE produces a pulse for each zero-crossing of the mains phase selected by FREQSEL[1:0] that can be used to interrupt the host microcontroller 20 SAG_INT 1 When 1, activates YPULSE output when a sag condition is detected 19:8 SAG_CNT 252 (0xFC) The number of consecutive voltage samples below SAG_THR (register 0x24) before a sag alarm is declared. The default value is equivalent to 100ms FREQSEL[1:0] selects the phase to be used for the frequency monitor, sag detection, and for the zero-crossing counter (MAINEDGE_X, register 0x083) 7:6 5:2 1 0 FREQSEL[1:0] Reserved PULSE_FAST PULSE_SLOW 0 0 0 FREQ SEL[1:0] PHASE SELECTED 0 0 A 0 1 B 1 X Not allowed Reserved When PULSE_FAST = 1, the pulse generator input is increased 16x. When PULSE_SLOW = 1, the pulse generator input is reduced by a factor of 64. These two parameters control the pulse gain factor X (see table below). Allowed values are either 1 or 0. Default is 0 for both (X = 6). PULSE_FAST PULSE_SLOW X 0 0 1.5 x 22 = 6 1 0 1.5 x 26 = 96 0 1 1.5 x 2-4 = 0.09375 1 1 Do not use 0 The CE is initialized by the host microcontroller using CECONFIG (Table 12). This register contains the SAG_CNT, FREQSEL[1:0], PULSE_SLOW, and PULSE_FAST fields. The CECONFIG bit definitions are given in Table 13. The FREQSEL[1:0] field in CECONFIG (register 0x020[7:6]) selects the phase that is utilized to generate a sag interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag event criteria as set by SAG_THR (register 0x24) and the SAG_CNT field in CECONFIG (register 0x020[19:8]). When the SAG_INT bit (register 0x020[20]) is set to 1, a sag event gener- ates a transition on the YPULSE output. In a two-phase system, and after a sag interrupt, the host microcontroller should change the FREQSEL[1:0] setting to select the other phase, if it is powered. Even though a sag interrupt is only generated on the selected phase, both phases are simultaneously checked for sag. The presence of power on a given phase can be sensed by directly checking the SAG_A and SAG_B bits in CESTATUS (register 0x080[1:0]). The CE controls the pulse rate based on WSUM_X (register 0x084) and VARSUM_X (register 0x088). 30 MAX71020 Single-Chip Electricity Meter AFE CE Transfer Variables When the host microcontroller receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of CE transfer variables always end with “_X”. The transfer variables can be categorized as: U Fundamental energy measurement variables U Instantaneous (RMS) values U Other measurement parameters Fundamental Energy Measurement Variables Table 15 describes each transfer variable for fundamental energy measurement. All variables are signed 32-bit integers. Accumulated variables such as WSUM are internally scaled so that internal values are no more than 50% of the full-scale range when the integration time is one second. Additionally, the hardware does not permit output values to fold back upon overflow. WSUM_X (register 0x084) and VARSUM_X (register 0x088) are the signed sum of Phase-A and Phase-B Wh or VARh values according to the metering equation specified in EQU[2:0](register 0x30D[14:12]). WxSUM_X (x = 0 or 1, registers 0x085 and 0x086) is the watt-hour value accumulated for phase x in the last accumulation interval and can be computed based on the specified LSB value. Table 14. Sag Threshold and Gain Adjust Control CE ADDRESS 0x24 NAME SAG_THR DEFAULT 2.39 x 107 DESCRIPTION The voltage threshold for sag warnings. The default value is equivalent to 113Vpk or 80VRMS if VMAX = 600VRMS. SAG_THR = VRMS × 2 VMAX × 7.8798 × 10 −9 0x40 GAIN_ADJ0 16384 This register scales the voltage measurement channels VA and VB. The default value of 16384 is equivalent to unity gain (1.000). 0x41 GAIN_ADJ1 16384 This register scales the IA current channel for Phase A. The default value of 16384 is equivalent to unity gain (1.000). 0x42 GAIN_ADJ2 16384 This register scales the IB current channel for Phase B. The default value of 16384 is equivalent to unity gain (1.000). Table 15. CE Transfer Variables CE ADDRESS NAME 0x84 WSUM_X 0x85 W0SUM_X 0x86 W1SUM_X 0x88 VARSUM_X 0x89 VAR0SUM_X 0x8A VAR1SUM_X DESCRIPTION CONFIGURATION The signed sum: W0SUM_X + W1SUM_X. Not used for EQU[2:0] = 0 (register 0x30D[14:12]) and EQU[2:0] = 1. The sum of Wh samples from each wattmeter element. LSBW = 6.08040 x 10-13 x VMAX x IMAX Wh The signed sum: VAR0SUM_X + VAR1SUM_X. Not used for EQU[2:0] = 0 and EQU[2:0] = 1. Figure 8 The sum of VARh samples from each wattmeter element. LSBW = 6.08040 x 10-13 x VMAX x IMAX VARh 31 MAX71020 Single-Chip Electricity Meter AFE Instantaneous Energy Measurement Variables I_SQSUM_X and V_SQSUM (see Table 16) are the sum of the squared current and voltage samples acquired during the last accumulation interval. The RMS values can be computed by the host microcontroller from the squared current and voltage samples as follows: I_SQSUM × LSBI × 9,074,160 I RMS = N ACC Other VRMS = V_SQSUM × LSB V × 9,074,160 N ACC Other transfer variables include those available for frequency and those reflecting the count of the zerocrossings of the mains voltage. These transfer variables are listed in Table 17. MAINEDGE_X (register 0x083) reflects the number of half-cycles accounted for in the last accumulated interval for the AC signal of the phase specified in the FREQSEL[1:0] field in CECONFIG (register 0x020[7:6]). MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. Pulse Generation Table 18 describes the CE pulse generation parameters. The combination of the CECONFIG:PULSE_SLOW and CECONFIG:PULSE_FAST bits (register 0x020[0:1]) controls the speed of the pulse rate. The default zero values of these configuration bits maintain the original pulse rate given by the Kh equation, follows in this section. WRATE (register 0x021) controls the number of pulses that are generated per measured Wh and VARh. The lower WRATE is, the slower the pulse rate for the measured energy quantity; or conversely, the greater the measured energy per pulse. By default, the pulse generators take their input from the W0SUM_X (register 0x085) and VAR0SUM_X (register 0x089) result registers. The meter constant Kh is derived from WRATE and represents the amount of energy measured for each pulse. If Kh = 1Wh/pulse and 120V and 30A is applied in-phase to the meter, the meter will produce one pulse per second (120V and 30A results in a load of 3600W, or put another way, energy consumption of one watt-hour per second). If the load is 240V at 150A, ten pulses per second are generated. To compute the WRATE value, see Table 18. The maximum pulse rate is 7.56kHz. Table 16. CE Energy Measurement Variables CE ADDRESS NAME 0x8C I0SQSUM_X 0x8D I1SQSUM_X 0x90 V0SQSUM_X 0x91† V1SQSUM_X DESCRIPTION CONFIGURATION The sum of squared current samples from each element. LSBI = 6.08040 x 10-13 IMAX2 A2h When EQU = 1, I0SQSUM_X is based on IA and IB. Figure 8 The sum of squared voltage samples from each element. LSBV= 6.08040 x 10-13 VMAX2 V2h Table 17. Other Transfer Variables CE ADDRESS NAME 0x82 FREQ_X 0x83 MAINEDGE_X DESCRIPTION Fundamental frequency: LSB ≡ 2520.6Hz 2 32 ≈ 0.509 × 10 -6 The number of edge crossings of the selected voltage in the previous accumulation interval. Edge crossings are either direction and are debounced. 32 MAX71020 Single-Chip Electricity Meter AFE See the VPULSE and WPULSE section for details on how to adjust the timing of the output pulses. The maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67µs) and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67ppm. After 10s, the peak jitter is 6.7ppm. The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is: RATE = WRATE × WSUM × fS × X 2 46 where fS = sampling frequency (2520.6Hz), X = pulse speed factor derived from the CE variables PULSE_SLOW (register 0x020[0]) and PULSE_FAST (register 0x020[1]). Other CE Parameters Table 19 shows the CE parameters used for suppression of noise due to scaling and truncation effects. CE Calibration Parameters Table 20 lists the parameters that are typically entered to effect calibration of meter accuracy. CE Flow Diagrams Figure 10 to Figure 12 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sag detection, scaling, and the processing of meter equations. Hz Table 18. CE Pulse Generation Parameters CE ADDRESS NAME DEFAULT DESCRIPTION Kh = K × VMAX × IMAX Wh pulse SUM_SAMPS × WRATE × X 0x21 WRATE 547 where: K = 42.7868 See Table 13 for the definition of X. The default value yields 1.0 Wh/pulse for VMAX = 600V and IMAX = 208A. The maximum value for WRATE is 32,768 (215). 0x22 KVAR 6444 Scale factor for VAR measurement 0x45 WPULSE_CTR 0 WPULSE counter 0x46 WPULSE_FRAC 0 Unsigned numerator, containing a fraction of a pulse. The value in this register always counts up towards the next pulse. 0x47 WSUM_ACCUM 0 Rollover accumulator for WPULSE 0x4A VPULSE_CTR 0 VPULSE counter 0x4A VPULSE_FRAC 0 Unsigned numerator, containing a fraction of a pulse. The value in this register always counts up towards the next pulse. 0x4B VSUM_ACCUM 0 Rollover accumulator for VPULSE 33 MAX71020 Single-Chip Electricity Meter AFE Table 19. CE Parameters for Noise Suppression and Code Version CE ADDRESS NAME DEFAULT 0x25 QUANT_VA 0 0x26 QUANT_IA 0 0x27 QUANT_A 0 0x28 QUANT_VARA 0 0x29 QUANT_VB 0 0x2A QUANT_IB 0 0x2B QUANT_B 0 0x2C QUANT_VARB 0 DESCRIPTION Compensation factors for truncation and noise in voltage, current, real energy, and reactive energy for phase A. Compensation factors for truncation and noise in voltage, current, real energy, and reactive energy for phase B. QUANT_Ix_LSB= 3.28866 × 10 -13 × IMAX 2 (Amps 2 ) QUANT_Wx_LSB= 6.73518 × 10 -10 × VMAX × IMAX (Watts) QUANT_VARx_LSB= 6.73518 × 10 -10 × VMAX × IMAX (Vars) Table 20. CE Calibration Parameters CE ADDRESS NAME DEFAULT 0x10 CAL_IA 16384 0x11 CAL_VA 16384 0x13 CAL_IB 16384 0x14 CAL_VB 16384 0x12 PHADJ_A 0 DESCRIPTION These constants control the gain of their respective channels. The nominal value for each parameter is 214 = 16384. The gain of each channel is directly proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow, CAL should be increased by 1%. These constants control the CT phase compensation. Compensation does not occur when PHADJ_X = 0. As PHADJ_X is increased, more compensation (lag) is introduced. The range is ±215 – 1. If it is desired to delay the current by the angle F, the equations are: PHADJ_X = 2 20 0x15 PHADJ_B 0 PHADJ_X = 2 20 0.02229 × TANF at 60Hz 0.1487 - 0.0131× TANF 0.0155 × TANF at 50Hz 0.1241- 0.009695 × TANF 34 MAX71020 Single-Chip Electricity Meter AFE MULTIPLEXER I0 V0 I1 VREF DC MOD DEMULTIPLEXER I0_RAW V0_RAW I1_RAW DECIMATOR fS = 2520Hz (ON EACH CHANNEL) fCLK = 4.9152MHz Figure 10. CE Data Flow (Multiplexer and ADC) I0_RAW I0 OFFSET NULL F0 CAL_I0 PHASE COMP LPF W0 PHADJ_0 LPF VAR0 V0_RAW V0 OFFSET NULL 90° F0 CAL_V0 I1_RAW OFFSET NULL F0 PHASE COMP CAL_I1 GAIN_ADJ LPF VAR1 LPF W1 PHADJ_1 I1 F0 GENERATOR F0 Figure 11. CE Data Flow (Scaling, Gain Control, Intermediate Variables) 35 MAX71020 Single-Chip Electricity Meter AFE SUM W0 C W1 C VAR0 C VAR01 C W0SUM_X W1SUM_X VAS0SUM_X VAR1SUM_X SUM_SAMPS = 2520 SUM SQUARE I0 I2 V0 V2 I1 I2 MPU IOSQ VOSQ IISQ C C C IOSQSUM_X VOSQSUM_X IISQSUM_X F0 Figure 12. CE Data Flow (Squaring and Summation Stages) Ordering Information PART PINACCURACY PACKAGING PACKAGE (%) MAX71020AEUI+ 28 TSSOP 0.5 Bulk MAX71020AEUI+R 28 TSSOP 0.5 Tape and reel Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)–free/RoHS-compliant package. Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 TSSOP U28+1 21-0066 90-0171 36 MAX71020 Single-Chip Electricity Meter AFE Revision History REVISION NUMBER REVISION DATE 0 7/12 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products 37 Maxim is a registered trademark of Maxim Integrated Products, Inc.