TC75S63TU TOSHIBA CMOS Linear Integrated Circuit Silicon Monolithic TC75S63TU Single Operational Amplifier (Low Noise Operational Amplifier) TC75S63TU Features • Low Noise. VNI = 7.8nV/√Hz(typ.)@ VDD = 3.3 V • Small Phase Delay. -2.5degrees@VDD = 3.3 V (typ.), f = 2kHz • Low-current supply. 500μA @ VDD = 3.3 V (typ.) • Ultra-compact package. SON5-P-0202-0.65S UFV Weight: 7m g (typ.) Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit VDD, VSS 6 V DVIN ±6 V Input voltage VIN VDD to VSS V Output current IOUT ±4 mA Power dissipation PD 450(Note1) mW Operating temperature Topr −40 to 85 °C Storage temperature Tstg −55 to 125 °C Supply voltage Differential input voltage Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note1: Mounted on a glass epoxy circuit board of 30 mm × 30 mm. Pad dimension of 35mm2 Operating Ratings (Ta = 25°C) Characteristics Supply voltage Symbol Rating Unit VDD, VSS 2.2 to 5.5 V Note2: Do not use this product in a voltage follower circuit or outside the range of the common mode input voltage. (For the common mode input voltage, see DC Characteristics on Page 2). Failure to follow this instruction may cause voltage oscillation. :A higher load capacitance will increase the risk of voltage oscillation, even if this product is used within the range of the common mode input voltage. Allow sufficient capacitance value margin when designing your circuit and using this product to prevent voltage oscillation. 1 2012-03-14 TC75S63TU Marking (top view) 5 Pin Connection (top view) OUT 4 VDD 5 4 SP 1 2 1 IN (+) 3 2 VSS 3 IN (−) Electrical Characteristics DC Characteristics (VDD = 3.3 V, VSS = GND, Ta = 25°C) Symbol Test Circuit Input offset voltage VIO 1 Input offset current IIO − II − CMVIN 2 GV − VOH 3 VOL Common mode input signal rejection ratio Supply voltage rejection ratio Characteristics Min Typ. Max Unit − 1 7 mV − − 1 − pA − − 1 − pA 0 − 2.4 V − 100 − dB RL ≥ 100 kΩ 3.2 − − 4 RL ≥ 100 kΩ − − 0.1 CMRR 2 VIN = 0 to 2.4 V 60 80 − dB SVRR 1 VDD = 2.2 to 5.5 V 60 80 − dB Supply current IDD 5 − − 500 650 μA Source current Isource 6 − 1500 − − μA Isink 7 − 1500 − − μA Input bias current Common mode input voltage Voltage gain (open loop) Maximum output voltage Sink current Test Condition RS = 1 kΩ, RF = 100 kΩ RS = 1 kΩ, RF = 100 kΩ − V AC Characteristics (VDD = 3.3 V, VSS = GND, Ta = 25°C) Symbol Test Circuit Test Condition Min Typ. Max Unit VNI − f=1kHz, GV=40dB,RS=100Ω,Rf=10kΩ − 7.8 − nV/√Hz Unity Gain Cross Frequency fT − GV = 40 dB − 3.5 − MHz Phase delay φD 8 f=2kHz − -2.5 − degrees Min Typ. Max Unit − 1.0 − V/μs Characteristics Equivalent input Noise Voltage AC Characteristics (VDD = 1.65 V, VSS = -1.65V, Ta = 25°C) Characteristics Slew Rate Symbol Test Circuit SR 9 Test Condition GV = 12 dB,VIN=0.4V 2 2012-03-14 TC75S63TU Test Circuit 1. SVRR, VIO • • VDD RF RS VOUT ⎛ V 1 − V OUT 2 RS SVRR = 20 log ⎜ OUT × ⎜ V 1− V 2 RF + RS DD DD ⎝ RF RS • VDD/2 ⎞ ⎟ ⎟ ⎠ VIO Measure the value of VOUT and calculate the value of VIO using the following equation. ⎛ RS VDD ⎞ ⎟× VIO = ⎜⎜ V OUT − 2 ⎟⎠ RF + RS ⎝ 2. CMRR, CMVIN VDD • RF RS CMRR Measure the VOUT value, as indicated below, and calculate the value of the CMRR using the equation shown. When VIN = 0 V, VIN = VIN1 and VOUT = VOUT1 When VIN = 2.4 V, VIN = VIN2 and VOUT = VOUT2 ⎛ V 1 − V OUT 2 RS CMRR = 20 log ⎜ OUT × ⎜ RF + RS 1 − VIN 2 V IN ⎝ VOUT RS ⎞ ⎟ ⎟ ⎠ RF VIN SVRR For each of the two VDD values, measure the VOUT value, as indicated below, and calculate the value of SVRR using the equation shown. When VDD = 2.2 V, VDD = VDD1and VOUT = VOUT1 When VDD = 5.5 V, VDD = VDD2 and VOUT = VOUT2 VDD/2 • CMVIN Input range within which the CMRR specification guarantees VOUT value (as varied by the VIN value). • VOH 3. VOH VDD VDD − 0.05 V 2 VIN2 = VDD + 0.05 V 2 RL VOH VIN1 = VIN1 VIN2 4. VOL VDD VOL VIN1 = VDD + 0.05 V 2 VIN2 = VDD − 0.05 V 2 RL • VOL VIN1 VIN2 3 2012-03-14 TC75S63TU 5. IDD VDD 100kΩ M IDD 1kΩ 100kΩ VOUT 1kΩ VDD/2 VDD/2 6. Isource 7. Isink VDD VDD M VDD 2 VDD 2 M V DD + 0.1 V 2 VDD − 0.1 V 2 Voltage gain GV (dB) 8. φD VDD RF VOUT RS 2kHz VIN VSS -180 Frequency f (Hz) Phase delay ΦD Phase (degrees) 0 Network Analyzer 4 2012-03-14 TC75S63TU 9.SR VDD=1.65V RF=39kΩ RS=13kΩ VOUT VIN VSS= -1.65V z 0.4V SR R GV = 1 + F = 12dB R S SR = Input voltage VIN - 0.4V Δt ΔV 90% Output voltage VOUT ΔV 10% Δt 5 2012-03-14 TC75S63TU VOH – Isource VOH – Isource 3.5 (V) VOH VOH 5.0 4.5 High-level output voltage 4.0 3.0 2.5 2.0 1.5 VDD = 5.5 V 1.0 VSS = GND 0.5 0 0 3.5 3.0 2.5 High-level output voltage (V) 5.5 Ta = 25°C 2.0 1.5 1.0 0.5 Test Circuit 6 1.0 2.0 Source current 3.0 0 0 4.0 Isource (mA) VDD = 3.3 V VSS = GND Ta = 25°C Test Circuit 6 1.0 Source current VOH – Isource (V) VOL (V) 1.5 Low-level output voltage VOH High-level output voltage 2.0 1.0 VDD = 2.2 V VSS = GND Ta = 25°C Test Circuit 6 1.0 2.0 Source current 3.0 4.5 4.0 VDD = 5.5 V VSS = GND Ta = 25°C Test Circuit 7 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 Isource (mA) 1.0 VOL – Isink VOL (V) VSS = GND Test Circuit 7 Low-level output voltage VOL (V) Low-level output voltage 4.0 5.0 (mA) VOL – Isink Ta = 25°C 2.0 1.5 1.0 0.5 0 0 3.0 2.5 VDD = 3.3 V 2.5 2.0 Sink current Isink 3.5 3.0 Isource (mA) 5.5 5.0 0 0 3.0 VOL – Isink 2.5 0.5 2.0 1.0 2.0 3.0 Sink current Isink 4.0 VDD = 2.2 V VSS = GND Test Circuit 7 1.5 1.0 0.5 0 0 5.0 (mA) Ta = 25°C 2.0 1.0 2.0 3.0 Sink current Isink 6 4.0 5.0 (mA) 2012-03-14 TC75S63TU VNI – f Equivalent input Noise Voltage VNI (nV/√Hz) IDD – VDD 800 (μA) 500 Supply current 600 IDD 700 400 300 200 VSS = GND Ta = 25°C 100 Test Circuit 5 0 0 1 2 3 4 5 6 VDD = 3.3 V, VSS = GND 45 GV=40dB, RS=100Ω Rf=10kΩ, Ta = 25°C 40 35 30 25 20 15 10 5 0 10 100 1k 10k Frequency f (Hz) Supply voltage VDD (V) GV,φ – f GV – f 50 225 40 180 30 135 120 0 0 -10 -45 Phase -20 -30 -40 100 -90 VDD = 3.3 V, VSS = GND (dB) 40 -135 GV=40dB, Ta = 25°C 1k GV 45 Ta = 25°C 80 Voltage gain 10 (degrees) 90 φ Voltage gain 20 VSS = GND Phase Voltage gain GV (dB) VDD = 3.3 V 10k 100k 1M 0 10 -180 10M Frequency f (Hz) 100 1k 10 k 100 k 1M 10 M Frequency f (Hz) PD – Ta Power dissipation PD (mW) 500 400 300 200 Circuit board material: glass epoxy, Circuit board dimention: 30 mm × 30 mm, pad area: 35 mm2 (t = 0.8 mm) 100 −40 0 40 80 120 Ambient temperature Ta (°C) 7 2012-03-14 TC75S63TU Package Dimension Unit:mm SON5-P-0202-0.65S Weight : 7m g (typ.) 8 2012-03-14 TC75S63TU RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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