CYPRESS CY8C55

PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
®
Programmable System-on-Chip (PSoC )
General Description
With its unique array of configurable blocks, PSoC® 5 is a true system-level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on
every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including
interfaces such as USB, multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C55
family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3
microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean
primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities
for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware
updates.
❐ Library of advanced peripherals
Features
• Cyclic redundancy check (CRC)
■ 32-bit ARM Cortex-M3 CPU core
• Pseudo random sequence (PRS) generator
❐ DC to 67 MHz operation
• Local interconnect network (LIN) bus 2.0
❐ Flash program memory, up to 256 KB, 100,000 write cycles,
• Quadrature decoder
20-year retention, and multiple security features
■ Analog peripherals (2.7 V ≤ VDDA ≤ 5.5 V)
❐ Up to 64 KB SRAM memory
❐ 1.024 V ±1% internal voltage reference across –40 °C to
❐ 2-KB electrically erasable programmable read-only memory
+85 °C (128 ppm/°C)
(EEPROM) memory, 1 million cycles, and 20 years retention
❐ Configurable delta-sigma ADC with 8- to 20-bit resolution
❐ 24-channel direct memory access (DMA) with multilayer
• Sample rates up to 192 ksps
AMBA high-performance bus (AHB) bus access
• Programmable gain stage: ×0.25 to ×16
• Programmable chained descriptors and priorities
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion
• High bandwidth 32-bit transfer support
ratio (SINAD), ±1-bit INL/DNL
■ Low voltage, ultra low power
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL
❐ Operating voltage range:2.7 V to 5.5 V
[2]
❐ Two SAR ADCs, each 12-bit at 1 Msps
❐ High-efficiency boost regulator from 1.8 V input to 5.0 V
❐ Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs
output
❐ Four comparators with 95-ns response time
❐ 5 mA at 6 MHz
❐ Four uncommitted opamps with 25-mA drive capability
❐ Low power modes including:
❐ Four configurable multifunction analog blocks. Example
• 3-µA sleep mode with real time clock (RTC) and
configurations are programmable gain amplifier (PGA),
low-voltage detect (LVD) interrupt
transimpedance amplifier (TIA), mixer, and Sample and Hold
• 1-µA hibernate mode with RAM retention
❐ CapSense support
■ Versatile I/O system
■ Programming, debug, and trace
❐ 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs)
❐ Single-wire debug (SWD) and single wire viewer (SWV)
❐ Any GPIO to any digital or analog peripheral routability
interfaces
❐ LCD direct drive from any GPIO, up to 46×16 segments
❐ Cortex-M3 flash patch and breakpoint (FPB) block
®
[1]
❐ CapSense support from any GPIO
❐ Cortex-M3 data watchpoint and trace (DWT) generates data
❐ 1.2 V to 5.5 V I/O interface voltages, up to 4 domains
trace information
❐ Maskable, independent IRQ on any pin or port
❐ Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
❐ Schmitt-trigger transistor-transistor logic (TTL) inputs
used for printf-style debugging
❐ All GPIOs configurable as open drain high/low,
❐ DWT and ITM blocks communicate with off-chip debug and
pull-up/pull-down, High-Z, or strong output
trace systems via the SWV interface
2
❐ 25 mA sink on SIO
❐ Bootloader programming supportable through I C, SPI,
■ Digital peripherals
UART, USB, and other interfaces
❐ 20 to 24 programmable logic device (PLD) based universal
■ Precision, programmable clocking
digital blocks (UDBs)
❐ 3 to 62 MHz internal oscillator over full temperature and
[2]
voltage range
❐ Full CAN 2.0b 16 RX, 8 TX buffers
❐ 4- to 25 MHz crystal oscillator for crystal PPM accuracy
❐ Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator
❐ Internal PLL clock generation up to 67 MHz
❐ Four 16-bit configurable timers, counters, and PWM blocks
❐ 32.768 KHz watch crystal oscillator
❐ 67 MHz, 24-bit fixed point digital filter block (DFB) to
❐ Low power internal oscillator at 1, 33, and 100 kHz
implement finite impulse response (FIR) and infinite impulse
■ Temperature and packaging
response (IIR) filters
❐ –40 °C to +85 °C industrial temperature
❐ Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
❐ 68-pin QFN and 100-pin TQFP package options.
• SPI, UART, and I2C
• Many others available in catalog
Notes
1. GPIOs with opamp outputs are not recommended for use with CapSense.
2. This feature on select devices only. See Ordering Information on page 106 for details.
Cypress Semiconductor Corporation
Document Number: 001-66235 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 10, 2011
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Contents
1. Architectural Overview .................................................... 3
2. Pinouts .............................................................................. 5
3. Pin Descriptions ............................................................... 9
4. CPU .................................................................................. 10
4.1 ARM Cortex-M3 CPU .............................................. 10
4.2 Cache Controller ..................................................... 11
4.3 DMA and PHUB ...................................................... 12
5. Memory ............................................................................ 16
5.1 Static RAM .............................................................. 16
5.2 Flash Program Memory ........................................... 16
5.3 Flash Security .......................................................... 16
5.4 EEPROM ................................................................. 16
5.5 Memory Map ...........................................................17
6. System Integration ......................................................... 18
6.1 Clocking System ...................................................... 18
6.1.4 6.2 Power System ................................................ 21
7. Digital Subsystem .......................................................... 32
7.1 Example Peripherals ............................................... 32
7.4 DSI Routing Interface Description ........................... 39
7.5 CAN .........................................................................41
7.6 USB .........................................................................42
7.7 Timers, Counters, and PWMs ................................. 42
7.8 I2C ........................................................................... 43
7.9 Digital Filter Block .................................................... 44
8. Analog Subsystem ......................................................... 44
8.1 Analog Routing ........................................................ 46
8.2 Delta-sigma ADC ..................................................... 48
8.3 Successive Approximation ADC .............................. 49
8.4 Comparators ............................................................ 49
8.5 Opamps ................................................................... 51
8.6 Programmable SC/CT Blocks ................................. 51
8.7 LCD Direct Drive ..................................................... 52
8.8 CapSense ................................................................ 53
8.9 Temp Sensor ...........................................................53
8.10 DAC ....................................................................... 53
Document Number: 001-66235 Rev. *A
8.11 Up/Down Mixer ...................................................... 54
8.12 Sample and Hold ................................................... 54
9. Programming, Debug Interfaces, Resources ............... 55
9.1 Debug Port Acquisition ............................................ 55
9.2 SWD Interface ......................................................... 55
9.3 Debug Features ....................................................... 57
9.4 Trace Features ........................................................ 57
9.5 SWV Interface ......................................................... 57
9.6 Programming Features ............................................ 57
9.7 Device Security ....................................................... 57
10. Development Support .................................................. 58
10.1 Documentation ...................................................... 58
10.2 Online .................................................................... 58
10.3 Tools ...................................................................... 58
11. Electrical Specifications .............................................. 59
11.1 Absolute Maximum Ratings ................................... 59
11.2 Device Level Specifications ................................... 60
11.3 Power Regulators .................................................. 62
11.4 Inputs and Outputs ................................................ 65
11.5 Analog Peripherals ................................................ 73
11.6 Digital Peripherals ................................................. 94
11.7 Memory ................................................................. 98
11.8 PSoC System Resources .................................... 100
11.9 Clocking ............................................................... 102
12. Ordering Information .................................................. 106
12.1 Part Numbering Conventions .............................. 106
13. Packaging .................................................................... 108
14. Acronyms .................................................................... 110
15. Reference Documents ................................................ 111
16. Document Conventions ............................................. 112
16.1 Units of Measure ................................................. 112
17. Revision History ......................................................... 113
18. Sales, Solutions, and Legal Information ................... 114
Page 2 of 114
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PSoC® 5: CY8C55 Family Datasheet
1. Architectural Overview
Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Clock Tree
IMO
Digital System
8- Bit
Timer
Quadrature Decoder
UDB
UDB
UDB
UDB
I 2C Slave
Sequencer
Universal Digital Block Array (24 x UDB)
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22 Ω
UDB
UDB
UDB
UDB
UDB
FS USB
2.0
4x
Timer
Counter
PWM
12- Bit SPI
UDB
Master/
Slave
UDB
UDB
8- Bit
Timer
Logic
8- Bit SPI
UDB
I2C
CAN
2.0
16- Bit PRS
Logic
UART
UDB
UDB
USB
PHY
GPIOs
32.768 KHz
( Optional)
GPIOs
Xtal
Osc
SIO
System Wide
Resources
Usage Example for UDB
4- 25 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
Memory System
WDT
and
Wake
CPU System
SRAM
8051 or
Cortex M3 CPU
Interrupt
Controller
FLASH
Cache
Controller
PHUB
DMA
Program &
Debug
GPIOs
System Bus
Program
GPIOs
EEPROM
ILO
Debug
Trace
LCD Direct
Drive
Digital
Filter
Block
POR and
LVD
2.7 to
5.5 V
Sleep
Power
1.8 V LDO
SMP
4 x SC / CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
CapSense
GPIOs
Power Management
System
Analog System
ADCs
2x
SAR
ADC
+
4x
Opamp
-
+
4x DAC
1x
Del Sig
ADC
4x
CMP
-
3 per
Opamp
GPIOs
SIOs
Clocking System
1.8 to 3.6 V
(Optional)
Document Number: 001-66235 Rev. *A
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Figure 1-1 illustrates the major components of the CY8C55
family. They are:
PSoC® 5: CY8C55 Family Datasheet
■
ARM Cortex-M3 CPU subsystem
■
Nonvolatile subsystem
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. One of the ADCs in the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
■
Programming, debug, and test subsystem
■
Less than 0.5 mV offset
■
Inputs and outputs
■
A gain error of 0.2%
■
Clocking
■
Integral non linearity (INL) less than ±2 LSB
■
Power
■
Digital subsystem
■
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. The designer can also easily create a digital
circuit using boolean primitives by means of graphical design
entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C55 family, these blocks can include four 16-bit timers,
counters, and PWM blocks; I2C slave, master, and multimaster;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the “Example
Peripherals” section on page 32 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 32 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1% error over
temperature and voltage. The configurable analog subsystem
includes:
■
Analog muxes
■
Comparators
■
Analog mixers
■
Voltage references
■
ADCs
■
DACs
■
Digital filter block (DFB)
Document Number: 001-66235 Rev. *A
■
Differential non linearity (DNL) less than ±1 LSB
■ SINAD better than 84 dB in 16-bit mode
This converter addresses a wide variety of precision analog
applications including some of the most demanding sensors.
The CY8C55 family also offers up to two SAR ADCs. Featuring
12-bit conversions at up to 1 M samples per second, they also
offer low nonlinearity and offset errors and SNR better than
70 dB. They are well-suited for a variety of higher speed analog
applications.
The output of any of the ADCs can optionally feed the
programmable DFB via DMA without CPU intervention. The
designer can configure the DFB to perform IIR and FIR digital
filters and several user defined custom functions. The DFB can
implement filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high-speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
■
Comparators
■
Uncommitted opamps
■
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
❐ Transimpedance amplifiers
❐ Programmable gain amplifiers
❐ Mixers
❐ Other similar analog components
See the “Analog Subsystem” section on page 44 of this data
sheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 67 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
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PSoC’s nonvolatile subsystem consists of flash and
byte-writeable EEPROM. It provides up to 256 KB of on-chip
flash. The CPU can reprogram individual blocks of flash,
enabling boot loaders. A powerful and flexible protection model
secures the user's sensitive information, allowing selective
memory block locking for read and write protection. Two KB of
byte-writable EEPROM is available on-chip to store application
data.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow VOH
to be set independently of VDDIO when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I2C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with FS USB, the USB physical interface is also
provided (USBIO). When not using USB, these pins may also be
used for limited digital functionality and device programming. All
the features of the PSoC I/Os are covered in detail in the “6.4 I/O
System and Routing” section on page 26 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has one-percent accuracy at 3 MHz. The IMO
can be configured to run from 3 MHz up to 62MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power ILO for the sleep and watchdog timers. A
32.768 kHz external watch crystal is also supported for use in
RTC applications. The clocks, together with programmable clock
dividers, provide the flexibility to integrate most timing
requirements.
Document Number: 001-66235 Rev. *A
PSoC® 5: CY8C55 Family Datasheet
The CY8C55 family supports a wide supply operating range from
2.7 to 5.5 V. This allows operation from regulated supplies such
as 3.3 V ± 10% or 5.0 V ± 10%, or directly from a wide range of
battery types. It also provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 1.8 V. The designer can use the boost
converter to generate other voltages required by the device,
such as a 3.3 V supply for LCD glass drive. The boost’s output
is available on the VBOOST pin, allowing other devices in the
application to be powered from the PSoC.
PSoC supports a wide range of low power modes. These include
a 1-µA hibernate mode with RAM retention and a 3-µA sleep
mode with RTC. In the second mode, the optional 32.768 kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the “6.2
Power System” section on page 21 of this data sheet.
PSoC uses a SWD interface for programming, debug, and test.
Using this standard interface enables the designer to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. The Cortex-M3 debug and trace
modules include FPB, DWT, and ITM. These modules have
many features to help solve difficult debug and trace problems.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 55 of this data sheet.
2. Pinouts
The VDDIO pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1 and
Figure 2-2. Using the VDDIO pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each VDDIO may sink up to 100 mA total to its
associated I/O pins and opamps. On the 68-pin and 100-pin
devices, each set of VDDIO associated pins may sink up to
100 mA. The 48 pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
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PSoC® 5: CY8C55 Family Datasheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P0[5] (GPIO, OpAmp2-)
P0[4] (GPIO, OpAmp2+)
Vddio0
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
55
54
53
52
58
57
56
P15[5] (GPOI)
P15[4] (GPIO)
Vddd
Vssd
Vccd
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
Vddio2
P2[4] (GPIO)
P2[3] (GPIO)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Lines show Vddio
to I/O supply
association
QFN
P12[1] (SIO)
P12[0] (SIO)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
Vddio3
(OpAmp1+, GPIO) P3[5]
MHz XTAL: Xi
(IDAC1, GPIO) P3[0]
(IDAC3, GPIO) P3[1]
(OpAmp3-/Extref1, GPIO) P3[2]
(OpAmp3+, GPIO) P3[3]
(OpAmp1-, GPIO) P3[4]
Vddd
Vssd
Vccd
MHz XTAL: Xo
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
[3]
(USBIO, D+, SWDIO) P15[6]
[3] (USBIO, D-, SWDCK) P15[7]
(GPIO) P1[6]
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
28
29
30
31
32
33
34
(Top View)
18
19
20
21
22
23
24
25
26
27
(GPIO) P2[6]
(GPIO) P2[7]
(SIO) P12[4]
(SIO) P12[5]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(SWDIO, GPIO) P1[0]
(SWDCK, GPIO) P1[1]
(GPIO) P1[2]
(SWV, GPIO) P1[3]
(GPIO) P1[4]
(GPIO) P1[5]
Vddio1
66
65
64
63
62
61
60
59
68
67
P2[5] (GPIO)
Figure 2-1. 68-pin QFN Part Pinout[4]
Notes
3. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
4. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
77
76
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, OpAmp2-)
P0[4] (GPIO, OpAmp2+)
87
86
85
84
83
82
81
80
79
78
90
89
88
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
Vddd
Vssd
Vccd
P4[7] (GPIO)
P4[6] (GPIO)
98
97
96
95
94
93
92
91
75
74
Lines show Vddio
to I/O supply
association
TQFP
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Vddio0
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
[5]
(OpAmp1+, GPIO) P3[5]
Vddio3
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
(USBIO, D-, SWDCK) P15[7]
Vddd
Vssd
Vccd
NC
NC
(MHz XTAL: Xo, GPIO) P15[0]
(MHz XTAL: Xi, GPIO) P15[1]
(IDAC1, GPIO) P3[0]
(IDAC3, GPIO) P3[1]
(OpAmp3-/Extref1, GPIO) P3[2]
(OpAmp3+, GPIO) P3[3]
(OpAmp1-, GPIO) P3[4]
54
53
52
51
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Vddio1
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
[5]
(USBIO, D+, SWDIO) P15[6]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(SWDIO, GPIO) P1[0]
(SWDCK, GPIO) P1[1]
(GPIO) P1[2]
(SWV, GPIO) P1[3]
(GPIO) P1[4]
(GPIO) P1[5]
100
99
Vddio2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
Figure 2-2. 100-pin TQFP Part Pinout
Figure 2-3 and Figure 2-4 on page 9 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a two-layer board.
■
The two pins labeled VDDD must be connected together.
■
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-3 and 6.2 Power System on
page 21. The trace between the two VCCD pins should be as short as possible.
■
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-66235 Rev. *A
Page 7 of 114
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PSoC® 5: CY8C55 Family Datasheet
Figure 2-3. Example Schematic for 100-pin TQFP Part with Power Connections
Vddd
Vddd
C1
1 uF
Vddd
C2
0.1 uF
C6
0.1 uF
Vddd
100
99
98
97
96
95
94
93
92
91
90
89
Vddd
88
Vssd
87
86
85
84
83
82
81
80
79
78
77
76
Vccd
Vssd
Vssd
U2
CY8C55xx
Vddio0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0out, P0[1]
OA2out, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
kHzXin, P15[3]
kHzXout, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3out, P3[7]
OA1out, P3[6]
Vddio1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
USB D+, P15[6]
USB D-, P15[7]
Vddd
Vssd
Vccd
NC
NC
P15[0], MHzXout
P15[1], MHzXin
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1P3[5], OA1+
Vddio3
Vssd
Vddd
C12
0.1 uF
Vccd
Vddd
Vssd
Vssd
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWDIO
P1[1], SWDCK
P1[2]
P1[3], SWV
P1[4]
P1[5]
Vdda
Vddd
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C8
0.1 uF
C17
1 uF
Vssd
Vssa
Vssd
Vdda
Vssd
Vdda
Vssa
Vcca
C9
1 uF
C10
0.1 uF
Vssa
Vddd
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
P32 47
48
49
50
Vssd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Vddio2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
Vddd
Vssd
Vccd
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
Vssd
C11
0.1 uF
C13
10 uF, 6.3 V
C14
0.1 uF Vssd
C15
1 uF
C16
0.1 uF
Vssa
Vssa
Vssd
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-4.
Document Number: 001-66235 Rev. *A
Page 8 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
Vssa
Vddd
Vssd
Plane
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for
high-current DACs (IDAC).
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High
current output of uncommitted opamp.[6]
Extref0, Extref1. External reference input to the analog system.
OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to
uncommitted opamp.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting
input to uncommitted opamp.
GPIO. Provides interfaces to the CPU, digital peripherals,
analog peripherals, interrupts, LCD segment drive, and
CapSense.[6]
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 KHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator
pin. If a crystal is not used, then Xi must be shorted to ground
and Xo must be left floating.
SIO. Provides interfaces to the CPU, digital peripherals and
interrupts with a programmable high threshold voltage, analog
comparator, high sink current, and high impedance state when
the device is unpowered.
Vssd
Vdda
Vssa
Plane
of from a VDDIO. Pins are Do Not Use (DNU) on devices without
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
of from a VDDIO. Pins are DNU on devices without USB.
VBOOST. Power sense connection to boost pump.
VBAT. Battery supply to boost pump.
VCCA. Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to VSSA. Regulator output not for
external use.
VCCD. Output of digital core regulator and input to digital core.
The two VCCD pins must be shorted together, with the trace
between them as short as possible, and a 1 µF capacitor to VSSD;
see 6.2 Power System on page 21. Regulator output not for
external use.
VDDA. Supply for all analog peripherals and analog core
regulator. VDDA must be the highest voltage present on the
device. All other supply pins must be less than or equal to
VDDA.
VDDD. Supply for all digital peripherals and digital core regulator.
VDDD must be less than or equal to VDDA.
VSSA. Ground for all analog peripherals.
VSSB. Ground connection for boost pump.
SWDCK. SWD Clock programming and debug port connection.
VSSD. Ground for all digital logic and I/O pins.
SWDIO. SWD Input and Output programming and debug port
connection.
VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each
VDDIO must be tied to a valid operating voltage (2.7 V to 5.5 V),
and must be less than or equal to VDDA.
SWV. SWV output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
XRES. External reset pin. Active low with internal pull-up.
Note
6. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-66235 Rev. *A
Page 9 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C55 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low-power 32-bit three-stage pipelined
Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt
handling features.
Figure 4-1. ARM Cortex-M3 Block Diagram
Interrupt Inputs
Nested
Vectored
Interrupt
Controller
(NVIC)
Flash Patch and
Breakpoint
(FPB)
I- Bus
SWD
Cortex M3 CPU Core
D-Bus
Instrumentation
Trace Module
(ITM)
S-Bus
Debug Block
(SWD)
Trace Port
Interface Unit
(TPIU)
SWV
Cortex M3 Wrapper
C-Bus
AHB
32 KB
SRAM
Data
Watchpoint and
Trace (DWT)
AHB
Bus
Matrix
Bus
Matrix
Cache
256 KB
Flash
AHB
32 KB
SRAM
Bus
Matrix
AHB Bridge and Bus Matrix
DMA
PHUB
AHB Spokes
GPIO
Prog.
Digital
Prog.
Analog
Special
Functions
Peripherals
The Cortex-M3 CPU subsystem includes these features:
4.1.1 Cortex-M3 Features
■
ARM Cortex-M3 CPU
The Cortex-M3 CPU features include:
■
Programmable nested vectored interrupt controller (NVIC),
tightly integrated with the CPU core
■
Full featured debug and trace module, tightly integrated with
the CPU core
■
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
■
Cache controller
■
Peripheral HUB (PHUB)
■
DMA controller
Document Number: 001-66235 Rev. *A
■
4 GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
■
The Thumb®-2 instruction set, which offers ARM-level
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
❐ Bit-field control
❐ Hardware multiply and divide
❐ Saturation
❐ If-Then
❐ Wait for events and interrupts
❐ Exclusive access and barrier
❐ Special register access
Page 10 of 114
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The Cortex-M3 does not support ARM instructions.
■
Bit-band support. Atomic bit-level write and read operations.
■
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
■
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
■
Extensive interrupt and system exception support.
PSoC® 5: CY8C55 Family Datasheet
Table 4-2. Cortex M3 CPU Registers (continued)
Register
R13
R14
4.1.2 Cortex-M3 Operating Modes
R15
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
Because the handler mode is only enabled at the privileged level,
there are actually only three states, as shown in Table 4-1.
xPSR
Table 4-1. Operational Level
Condition
Privileged
User
Running an exception Handler mode
Not used
Running main program Thread mode
Thread mode
At the user level, access to certain instructions, special registers,
configuration registers, and debugging components is blocked.
Attempts to access them cause a fault exception. At the
privileged level, access to all instructions and registers is
allowed.
The processor runs in the handler mode (always at the privileged
level) when handling an exception, and in the thread mode when
not.
4.1.3 CPU Registers
The Cortex-M3 CPU registers are listed in Table 4-2. Registers
R0-R15 are all 32 bits wide.
Table 4-2. Cortex M3 CPU Registers
Register
R0-R12
Description
General purpose registers R0-R12 have no
special architecturally defined uses. Most
instructions that specify a general purpose
register specify R0-R12.
■
Low registers: Registers R0-R7 are accessible
by all instructions that specify a general
purpose register.
■
High registers: Registers R8-R12 are
accessible by all 32-bit instructions that specify
a general purpose register; they are not
accessible by all 16-bit instructions.
Description
R13 is the stack pointer register. It is a banked
register that switches between two 32-bit stack
pointers: the main stack pointer (MSP) and the
process stack pointer (PSP). The PSP is used
only when the CPU operates at the user level in
thread mode. The MSP is used in all other
privilege levels and modes. Bits[0:1] of the SP
are ignored and considered to be 0, so the SP is
always aligned to a word (4 byte) boundary.
R14 is the link register (LR). The LR stores the
return address when a subroutine is called.
R15 is the program counter (PC). Bit 0 of the PC
is ignored and considered to be 0, so instructions
are always aligned to a half word (2 byte)
boundary.
The program status registers are divided into
three status registers, which are accessed either
together or separately:
■
Application program status register (APSR)
holds program execution status bits such as
zero, carry, negative, in bits[27:31].
■
Interrupt program status register (IPSR) holds
the current exception number in bits[0:8].
■
Execution program status register (EPSR)
holds control bits for interrupt continuable and
IF-THEN instructions in bits[10:15] and
[25:26]. Bit 24 is always set to 1 to indicate
Thumb mode. Trying to clear it causes a fault
exception.
PRIMASK
A 1-bit interrupt mask register. When set, it
allows only the nonmaskable interrupt (NMI) and
hard fault exception. All other exceptions and
interrupts are masked.
FAULTMASK A 1-bit interrupt mask register. When set, it
allows only the NMI. All other exceptions and
interrupts are masked.
BASEPRI
A register of up to nine bits that define the
masking priority level. When set, it disables all
interrupts of the same or higher priority value. If
set to 0 then the masking function is disabled.
CONTROL
A 2-bit register for controlling the operating
mode.
Bit 0: 0 = privileged level in thread mode,
1 = user level in thread mode.
Bit 1: 0 = default stack (MSP) is used,
1 = alternate stack is used. If in thread mode or
user level then the alternate stack is the PSP.
There is no alternate stack for handler mode; the
bit must be 0 while in handler mode.
4.2 Cache Controller
The CY8C55 family has a 1 KB instruction cache between the
CPU and the flash memory. This improves instruction execution
rate and reduces system power consumption by requiring less
frequent flash access.
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
4.3 DMA and PHUB
■
Transactions can be stalled or canceled
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
■
Supports transaction size of infinite or 1 to 64k bytes
■
Large transactions may be broken into smaller bursts of 1 to
127 bytes
■
A central hub that includes the DMA controller, arbiter, and
router
■
TDs may be nested and/or chained for complex transactions
■
Multiple spokes that radiate outward from the hub to most
peripherals
4.3.3 Priority Levels
■
CPU and DMA controller are both bus masters to the PHUB
■
Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
■
Simultaneous CPU and DMA access to peripherals located on
different spokes
■
Simultaneous DMA source and destination burst transactions
on different spokes
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100% of the bus bandwidth. If a tie occurs
on two DMA requests of the same priority level, a simple round
robin method is used to evenly share the allocated bandwidth.
The round robin allocation can be disabled for each DMA
channel, allowing it to always be at the head of the line. Priority
levels 2 to 7 are guaranteed the minimum bus bandwidth shown
in Table 4-4 after the CPU and DMA priority levels 0 and 1 have
satisfied their requirements.
■
Supports 8-, 16-, 24-, and 32-bit addressing and data
Table 4-4. Priority Levels
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.3.1 PHUB Features
Table 4-3. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU
2
PHUB local configuration, Power manager,
Clocks, IC, EEPROM, Flash programming
interface
Priority Level
% Bus Bandwidth
0
100.0
1
100.0
2
50.0
3
25.0
4
12.5
5
6.2
3
Analog interface and trim, Decimator
6
3.1
4
USB, CAN, I2C, Timers, Counters, and PWMs
7
1.5
5
DFB
6
UDBs group 1
7
UDBs group 2
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.3.2 DMA Features
4.3.4 Transaction Modes Supported
■
24 DMA channels
■
Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 127 total TDs can be
defined
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
■
TDs can be dynamically updated
■
Eight levels of priority per channel
■
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
■
Each channel can generate up to two interrupts per transfer
Document Number: 001-66235 Rev. *A
4.3.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-5. For more description on other transfer modes, refer
to the Technical Reference Manual.
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PSoC® 5: CY8C55 Family Datasheet
Figure 4-5. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
ADDR 16/32
DATA Phase
CLK
A
B
ADDR 16/32
WRITE
A
B
WRITE
DATA (A)
DATA
READY
DATA (A)
DATA
READY
Basic DMA Read Transfer without wait states
4.3.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.3.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.3.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.3.4.5 Indexed DMA
In an indexed DMA case, an external master requires access to
locations on the system bus as if those locations were shared
memory. As an example, a peripheral may be configured as an
SPI or I2C slave where an address is received by the external
master. That address becomes an index or offset into the internal
system bus memory space. This is accomplished with an initial
“address fetch” TD that reads the target address location from
the peripheral and writes that value into a subsequent TD in the
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
4.3.4.6 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
Document Number: 001-66235 Rev. *A
Basic DMA Write Transfer without wait states
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
4.3.4.7 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.3.4.8 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
Page 13 of 114
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PSoC® 5: CY8C55 Family Datasheet
4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-6.
Table 4-6. Cortex-M3 Exceptions and Interrupts
Exception
Number
Exception Type
Priority
Exception Table
Address Offset
Function
0x00
Starting value of R13 / MSP
1
Reset
-3 (highest)
0x04
Reset
2
NMI
-2
0x08
Non maskable interrupt
3
Hard fault
-1
0x0C
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or
masked
4
MemManage
Programmable
0x10
Memory management fault, for example, instruction
fetch from a nonexecutable region
5
Bus fault
Programmable
0x14
Error response received from the bus system; caused
by an instruction prefetch abort or data access error
6
Usage fault
Programmable
0x18
Typically caused by invalid instructions or trying to
switch to ARM mode
7 – 10
-
-
0x1C – 0x28
Reserved
11
SVC
Programmable
0x2C
System service call via SVC instruction
12
Debug monitor
Programmable
0x30
Debug monitor
13
-
-
0x34
Reserved
14
PendSV
Programmable
0x38
Deferred request for system service
15
SYSTICK
Programmable
0x3C
System tick timer
16 – 47
IRQ
Programmable
0x40 – 0x3FC
Peripheral interrupt request #0 - #31
Bit 0 of each exception vector indicates whether the exception is
executed using ARM or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See “DSI Routing Interface Description” section on
page 39.
The Nested Vectored Interrupt Controller (NVIC) handles
interrupts from the peripherals, and passes the interrupt vectors
to the CPU. It is closely integrated with the CPU for low latency
interrupt handling. Features include:
■
32 interrupts. Multiple sources for each interrupt.
■
Configurable number of priority levels: from 3 to 8.
■
Dynamic reprioritization of interrupts.
■
Priority grouping. This allows selection of preempting and non
preempting interrupt levels.
Document Number: 001-66235 Rev. *A
■
Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
■
Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. All
interrupt sources may be routed to any interrupt vector using the
UDB interrupt source connections.
Page 14 of 114
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PSoC® 5: CY8C55 Family Datasheet
Table 4-7. Interrupt Vector Table
Interrupt #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Cortex-M3 Exception #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Document Number: 001-66235 Rev. *A
Fixed Function
Low voltage detect (LVD)
Cache
Reserved
Sleep (Pwr Mgr)
PICU[0]
PICU[1]
PICU[2]
PICU[3]
PICU[4]
PICU[5]
PICU[6]
PICU[12]
PICU[15]
Comparators Combined
Switched Caps Combined
I2C
CAN
Timer/Counter0
Timer/Counter1
Timer/Counter2
Timer/Counter3
USB SOF Int
USB Arb Int
USB Bus Int
USB Endpoint[0]
USB Endpoint Data
Reserved
Reserved
DFB Int
Decimator Int
phub_err_int
eeprom_fault_int
DMA
phub_termout0[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
phub_termout1[6]
phub_termout1[7]
phub_termout1[8]
phub_termout1[9]
phub_termout1[10]
phub_termout1[11]
phub_termout1[12]
phub_termout1[13]
phub_termout1[14]
phub_termout1[15]
UDB
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
udb_intr[22]
udb_intr[23]
udb_intr[24]
udb_intr[25]
udb_intr[26]
udb_intr[27]
udb_intr[28]
udb_intr[29]
udb_intr[30]
udb_intr[31]
Page 15 of 114
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PRELIMINARY
5. Memory
5.1 Static RAM
CY8C55 static RAM (SRAM) is used for temporary data storage.
Code can be executed at full speed from the portion of SRAM
that is located in the code space. This process is slower from
SRAM above 0x20000000. The device provides up to 64 KB of
SRAM. The CPU or the DMA controller can access all of SRAM.
The SRAM can be accessed simultaneously by the Cortex-M3
CPU and the DMA controller if accessing different 32-KB blocks.
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data and bulk data storage.
The main flash memory area contains up to 256 KB of user
program space.
Up to an additional 32 KB of flash space is available for storing
device configuration data and bulk user data. User code may not
be run out of this flash memory section. The flash output is 9
bytes wide with 8 bytes of data and 1 additional byte.
The CPU or DMA controller read both user code and bulk data
located in flash through the cache controller. This provides
higher CPU performance. Flash programming is performed
through a special interface and preempts code execution out of
flash. Code execution out of cache may continue during flash
programming as long as that code is contained inside the cache.
The flash programming interface performs flash erasing,
programming and setting code protection levels. Flash In
System Serial Programming (ISSP), typically used for production
programming, is possible through the SWD interface. In-system
programming, typically used for bootloaders, is also possible
using serial interfaces such as I2C, USB, UART, and SPI, or any
communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of configuration or
general-purpose data.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
“Device Security” section on page 57). For more information on
Document Number: 001-66235 Rev. *A
PSoC® 5: CY8C55 Family Datasheet
how to take full advantage of the security features in PSoC, see
the PSoC 5 TRM.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
Unprotected
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
External read
Field Upgrade Internal read and write
External read and
write
Full Protection Internal read
External read and
write + internal write
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the produ]ct as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte addressable nonvolatile
memory. The CY8C55 has 2 KB of EEPROM memory to store
user data. Reads from EEPROM are random access at the byte
level. Reads are done directly; writes are done by sending write
commands to an EEPROM programming interface. CPU code
execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into two sections, each containing 64 rows
of 16 bytes each.
The CPU cannot execute out of EEPROM.
Page 16 of 114
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PRELIMINARY
5.5 Memory Map
PSoC® 5: CY8C55 Family Datasheet
Table 5-3. Peripheral Data Address Map (continued)
The Cortex-M3 has a fixed address map, which allows
peripherals to be accessed by simple memory access
instructions.
Address Range
0x40004900 – 0x400049FF
Purpose
I 2C
controller
0x40004E00 – 0x40004EFF Decimator
5.5.1 Address Map
0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs
The 4-GB address space is divided into the ranges shown in
Table 5-2:
0x40005000 – 0x400051FF I/O ports control
0x40005800 – 0x40005FFF Analog Subsystem Interface
Table 5-2. Address Map
Address Range
0x40006000 – 0x400060FF USB Controller
Size
Use
0x40006400 – 0x40006FFF UDB Configuration
0x00000000 –
0x1FFFFFFF
0.5 GB
Program code. This includes the
exception vector table at power
up, which starts at address 0.
0x40007000 – 0x40007FFF PHUB Configuration
0x20000000 –
0x3FFFFFFF
0.5 GB
Static RAM. This includes a 1
MByte bit-band region starting at
0x20000000 and a 32 Mbyte
bit-band alias region starting at
0x22000000.
0x4000A000 – 0x4000A400 CAN
Peripherals. This includes a
1 MByte bit-band region starting
at 0x40000000 and a 32 Mbyte
bit-band alias region starting at
0x42000000.
0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,
including NVIC, debug, and trace
0x40000000 –
0x5FFFFFFF
0.5 GB
0x60000000 –
0x9FFFFFFF
1 GB
External RAM.
0xA0000000 –
0xDFFFFFFF
1 GB
External peripherals.
0xE0000000 –
0xFFFFFFFF
0.5 GB
Internal peripherals, including the
NVIC and debug and trace
modules.
Table 5-3. Peripheral Data Address Map
Address Range
Purpose
0x00000000 – 0x0003FFFF 256 KB flash
0x1FFF8000 – 0x1FFFFFFF 32 KB SRAM in Code region
0x20000000 – 0x20007FFF 32 KB SRAM in SRAM region
0x40004000 – 0x400042FF Clocking, PLLs, and oscillators
0x40004300 – 0x400043FF Power management
0x40004500 – 0x400045FF Ports interrupt control
0x40004700 – 0x400047FF Flash programming interface
0x40004800 – 0x400048FF Cache controller
Document Number: 001-66235 Rev. *A
0x40008000 – 0x400087FF EEPROM
0x4000C000 – 0x4000C800 Digital Filter Block
0x40010000 – 0x4001FFFF Digital Interconnect Configuration
The bit-band feature allows individual bits in words in the
bit-band region to be read or written as atomic operations. This
is done by reading or writing bit 0 of corresponding words in the
bit-band alias region. For example, to set bit 3 in the word at
address 0x20000000, write a 1 to address 0x2200000C. To test
the value of that bit, read address 0x2200000C and the result is
either 0 or 1 depending on the value of the bit.
Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
accesses of words and 16-bit half-words on nonword boundary
addresses can also be done, although they are less efficient.
5.5.2 Address Map and Cortex-M3 Buses
The ICode and DCode buses are used only for accesses within
the Code address range, 0 - 0x1FFFFFFF.
The System bus is used for data accesses and debug accesses
within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000
- 0xFFFFFFFF. Instruction fetches can also be done within the
range 0x20000000 - 0x3FFFFFFF, although these can be slower
than instruction fetches via the ICode bus.
The private peripheral bus (PPB) is used within the Cortex-M3 to
access system control registers and debug and trace module
registers.
Page 17 of 114
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PRELIMINARY
6. System Integration
6.1 Clocking System
Key features of the clocking system include:
■
Seven general purpose clock sources
❐ 3 to 62 MHz IMO, ±4% at 3 MHz
❐ 4- to 25 MHz external crystal oscillator (MHzECO)
❐ Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 21.
❐ DSI signal from an external I/O pin or other logic
❐ 24 to 67 MHz fractional phase-locked loop (PLL) sourced
from IMO, MHzECO, or DSI
❐ 1 KHz, 33 KHz, 100 KHz ILO for watchdog timer (WDT) and
Sleep Timer
❐ 32.768 KHz external crystal oscillator (ECO) for RTC
■
Independently sourced clock dividers in all clocks
■
Eight 16-bit clock dividers for the digital system
■
Four 16-bit clock dividers for the analog system
■
Dedicated 16-bit divider for the CPU bus and CPU clock
■
Automatic clock configuration in PSoC Creator
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 67 MHz clock, accurate to ±4% over voltage and
temperature. Additional internal and external clock sources allow
each design to optimize accuracy, power, and cost. All of the
system clock sources can be used to generate other clock
frequencies in the 16-bit clock dividers and UDBs for anything
you want, for example a UART baud rate generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows designers to build clocking
systems with minimal input. The designer can specify desired
clock frequencies and accuracies, and the software locates or
builds a clock that meets the required specifications. This is
possible because of the programmability inherent PSoC.
Document Number: 001-66235 Rev. *A
PSoC® 5: CY8C55 Family Datasheet
Page 18 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Table 6-1. Oscillator Summary
Source
Fmin
IMO
3 MHz
±4% over voltage and temperature
Tolerance at Fmin
62 MHz
Fmax
±10%
Tolerance at Fmax
10 µs max
Startup Time
MHzECO
4 MHz
Crystal dependent
25 MHz
Crystal dependent
5 ms typ, max is
crystal dependent
DSI
0 MHz
Input dependent
66 MHz
Input dependent
Input dependent
PLL
24 MHz
Input dependent
67 MHz
Input dependent
250 µs max
Doubler
48 MHz
Input dependent
48 MHz
Input dependent
1 µs max
ILO
1 kHz
–50%, +100%
100 kHz
–55%, +100%
15 ms max in lowest
power mode
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
500 ms typ, max is
crystal dependent
Figure 6-1. Clocking Subsystem
3-24 MHz
IMO
4-25 MHz
ECO
External IO
or DSI
0-40 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU
Clock
48 MHz
Doubler for
USB
24-40 MHz
PLL
System
Clock Mux
Bus
Clock
Bus Clock Divider
16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
6.1.1 Internal Oscillators
6.1.1.2 Clock Doubler
6.1.1.1 Internal Main Oscillator
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
In most designs the IMO is the only clock source required, due
to its ±4% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±4% at 3 MHz, up to ±10% at 62 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see USB
Clock Domain on page 21). The IMO provides clock outputs at
3, 6, 12, 24, 48, and 62 MHz.
Document Number: 001-66235 Rev. *A
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
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The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 67 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the CPU and system
clocks up to the device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO, or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low power modes.
PSoC® 5: CY8C55 Family Datasheet
used then Xi must be shorted to ground and Xo must be left
floating. MHzECO accuracy depends on the crystal chosen.
Figure 6-2. MHzECO Block Diagram
4 - 25 MHz
Crystal Osc
XCLK_ MHZ
Xo
Xi
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 KHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW). The central
timewheel is a 1 kHz, free running, 13-bit counter clocked by the
ILO. The central timewheel is always enabled except in
hibernate mode and when the CPU is stopped during debug on
chip mode. It can be used to generate periodic interrupts for
timing purposes or to wake the system from a low power mode.
Firmware can reset the central timewheel.
The central timewheel can be programmed to wake the system
periodically and optionally issue an interrupt. This enables
flexible, periodic wakeups from low power modes or coarse
timing applications. Systems that require accurate timing should
use the RTC capability instead of the central timewheel.
The 100 KHz clock (CLK100K) works as a low power system
clock to run the CPU. It can also generate time intervals such as
fast sleep intervals using the fast timewheel.
The fast timewheel is a 100 KHz, 5-bit counter clocked by the
ILO that can also be used to wake the system. The fast
timewheel settings are programmable, and the counter
automatically resets when the terminal count is reached. This
enables flexible, periodic wakeups of the CPU at a higher rate
than is allowed using the central timewheel. The fast timewheel
can generate an optional interrupt each time the terminal count
is reached.
The 33 KHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768 KHz ECO clock with no need for a crystal.
4 – 25 MHz
crystal
External
Components
Capacitors
6.1.2.2 32.768 kHz ECO
The 32.768 KHz external crystal oscillator (32kHzECO) provides
precision timing with minimal power consumption using an
external 32.768 KHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1 second interrupt to
implement the RTC functionality in firmware. The oscillator works
in two distinct power modes. This allows users to trade off power
consumption with noise immunity from neighboring circuits. The
GPIO pins connected to the external crystal and capacitors are
fixed.
Figure 6-3. 32kHzECO Block Diagram
32 kHz
Crystal Osc
Xi
(Pin P15[3])
External
Components
XCLK32K
Xo
(Pin P15[2])
32 kHz
crystal
Capacitors
6.1.2 Internal Oscillators
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate CPU and system
clocks up to the device's maximum frequency (see
Phase-Locked Loop on page 19). The GPIO pins connecting to
the external crystal and capacitors are fixed. If a crystal is not
Document Number: 001-66235 Rev. *A
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and UDBs.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
Page 20 of 114
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PRELIMINARY
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
■
The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
■
Bus clock 16-bit divider uses the system clock to generate the
system’s bus clock used for data transfers and the CPU. The
CPU clock is directly derived from the bus clock.
■
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the UDBs and fixed function timer/counter/PWMs can
also generate clocks.
■
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADCs and mixers.
The analog clock dividers include skew control to ensure that
critical analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
PSoC® 5: CY8C55 Family Datasheet
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(VCCD) and analog (VCCA) supplies for the internal core logic.
The output pins of the regulators (VCCD and VCCA) and the VDDIO
pins must have capacitors connected as shown in Figure 6-4.
The two VCCD pins must be shorted together, with as short a
trace as possible, and connected to a 1 µF ±10% X5R capacitor.
The power system also contains a sleep regulator and a
hibernate regulator.
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
Document Number: 001-66235 Rev. *A
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 6-4. PSoC Power System
1 µF
Vddio2
Vddd
Vddd
I/O Supply
Vssd
Vccd
Vddio2
Vddio0
0.1 µF
0.1 µF
I/O Supply
Vddio0
0.1 µF
Sleep
Regulator
Digital
Domain
Vdda
Vdda
Digital
Regulators
Vssb
Vcca
Analog
Regulator
0.1 µF
1 µF
.
Vssa
Analog
Domain
0.1 µF
I/O Supply
Vddio3
Vddd
Vssd
I/O Supply
Vccd
Vddio1
Hibernate
Regulator
0.1 µF
0.1 µF
Vddio1
Vddd
Vddio3
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-4.
6.2.1 Power Modes
PSoC 5 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:
■
Active
■
Alternate active
■
Sleep
■
Hibernate
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins. Figure 6-5 illustrates the allowable transitions between
power modes. Sleep and hibernate modes should not be entered
until all VDDIO supplies are at valid voltage levels.
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
Table 6-2. Power Modes
Power Modes
Description
Active
Primary mode of operation, all
peripherals available (programmable)
Entry Condition Wakeup Source Active Clocks
Regulator
Wakeup, reset, Any interrupt
Any
All regulators available.
manual register
(programmable) Digital and analog
entry
regulators can be disabled
if external regulation used.
Alternate
Active
Similar to Active mode, and is
Manual register
typically configured to have
entry
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Sleep
All subsystems automatically
disabled
PICU, RTC,
CTW, LVD
ILO/kHzECO
Hibernate
All subsystems automatically
Manual register
disabled
entry
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
Manual register
entry
PICU
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(Typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Active
–
5 mA[7]
Yes
All
All
All
–
All
Alternate
Active
–
–
User
defined
All
All
All
–
All
20 µs typ
3 µA
No
None
None
ILO/kHzECO
PICU, RTC, CTW,
LVD
XRES, LVD,
WDR,
<100 µs
1 µA
No
None
None
None
PICU
XRES
Sleep
Hibernate
Figure 6-5. Power Mode Transitions
6.2.1.1 Active Mode
Active
Manual
Sleep
Alternate
Active
Wakeup Sources Reset Sources
Hibernate
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
Note
7. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 60.
Document Number: 001-66235 Rev. *A
Page 23 of 114
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PRELIMINARY
6.2.1.2 Alternate Active Mode
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
PSoC® 5: CY8C55 Family Datasheet
Figure 6-6. Application for Boost Converter
Vboost Vdda Vddd
Optional Schottky
Diode. Only
required when Vdd
>3.6 V.
IND
22
µF
PSoC
0.1
µF
10 µH
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
6.2.1.5 Wakeup Events
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Interrupt sources include internally generated interrupts,
power supervisor, central timewheel, and I/O interrupts. The
central timewheel provides periodic interrupts to allow the
system to wake up, poll peripherals, or perform real-time
functions. Reset event sources include the external reset I/O pin
(XRES) and WDT.
6.2.2 Boost Converter
Applications that use a supply voltage of less than 2.7 V, such as
solar or single cell battery supplies, may use the on-chip boost
converter. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides.
For instance, this includes driving 5.0 V LCD glass in a 3.3 V
system. The boost converter accepts an input voltage as low as
2.7 V. With one low cost inductor it produces a selectable output
voltage sourcing enough current to operate the PSoC and other
on-board components.
The boost converter accepts an input voltage VBAT from 1.8 V to
3.6 V, and can start up with VBAT as low as 1.8 V. The converter
provides a user configurable output voltage of 3.3 to 5.0 V
(VBOOST). VBAT is typically less than VBOOST; if VBAT is greater
than or equal to VBOOST, then VBOOST will be the same as VBAT.
The block can deliver up to 50 mA (IBOOST) depending on
configuration.
Four pins are associated with the boost converter: VBAT, VSSB,
VBOOST, and Ind. The boosted output voltage is sensed at the
VBOOST pin and must be connected directly to the chip’s supply
inputs. An inductor is connected between the VBAT and Ind pins.
The designer can optimize the inductor value to increase the
boost converter efficiency based on input voltage, output
voltage, current and switching frequency. The External Schottky
diode shown in Figure 6-6 is required only in cases when
VBOOST>3.6 V.
Document Number: 001-66235 Rev. *A
22
µF
Vbat
Vssb
Vssa
Vssd
The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz,
or 32 kHz to optimize efficiency and component cost. The
100 kHz, 400 kHz, and 2 MHz switching frequencies are
generated using oscillators internal to the boost converter block.
When the 32 KHz switching frequency is selected, the clock is
derived from a 32 kHz external crystal oscillator. The 32 KHz
external clock is primarily intended for boost standby mode.
At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz
Vboost is limited to 4 × Vbat.
The boost converter can be operated in two different modes:
active and standby. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage. In standby mode, most boost functions are disabled,
thus reducing power consumption of the boost circuit. The
converter can be configured to provide low power, low current
regulation in the standby mode. The external 32 kHz crystal can
be used to generate inductor boost pulses on the rising and
falling edge of the clock when the output voltage is less than the
programmed value. This is called automatic thump mode (ATM).
The boost typically draws 200 µA in active mode and 12 µA in
standby mode. The boost operating modes must be used in
conjunction with chip power modes to minimize the total chip
power consumption. Table 6-4 lists the boost power modes
available in different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes
Boost Power Modes
Chip -Active mode
Boost can be operated in either active
or standby mode.
Chip -Sleep mode
Boost can be operated in either active
or standby mode. However, it is recommended to operate boost in standby
mode for low power consumption
Chip-Hibernate mode
Boost can only be operated in active
mode. However, it is recommended not
to use boost in chip hibernate mode
due to high current consumption in
boost active mode
If the boost converter is not used in a given application, tie the
VBAT, VSSB, and VBOOST pins to ground and leave the Ind pin
unconnected.
Page 24 of 114
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PRELIMINARY
6.3 Reset
CY8C55 has multiple internal and external reset sources
available. The reset sources are:
■ Power source monitoring - The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
■ External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to Vddio1. VDDD, VDDA, and Vddio1 must all
have voltage applied before the part comes out of reset.
■ Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset. The watchdog timer should not be used
during sleep and hibernate modes.
■ Software - The device can be reset under program control.
PSoC® 5: CY8C55 Family Datasheet
circuits to be reset and to hold their reset state. The monitor
generates a reset pulse that is at least 100 ns wide. It may be
much wider if one or more of the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. When the voltage is high enough, the
IMO starts.
■ ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
Interrupt circuits are available to detect when VDDA and VDDD
go outside a voltage range. For AHVI, VDDA is compared to a
fixed trip level. For ALVI and DLVI, VDDA and VDDD are
compared to trip levels that are programmable, as listed in
Table 6-5. ALVI and DLVI can also be configured to generate
a device reset instead of an interrupt.
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Interrupt Supply
VDDD
2.7 V-5.5 V 2.71 V-5.45 V in
250 mV
increments
±2%
ALVI
VDDA
±2%
Processor
Interrupt
2.7 V-5.5 V 2.71 V-5.45 V in
250 mV
increments
AHVI
VDDA
2.7 V-5.5 V 5.75 V
±2%
System
Reset
The monitors are disabled until after IPOR. During sleep
mode these circuits are periodically activated (buzzed). If an
interrupt occurs during buzzing then the system first enters its
wakeup sequence. The interrupt is then recognized and may
be serviced.
Vddd Vdda
Reset
Pin
External
Reset
Reset
Controller
Available Trip Accuracy
Settings
DLVI
Figure 6-7. Resets
Power
Voltage
Level
Monitors
Normal
Voltage
Range
6.3.1.2 Other Reset Sources
■
XRES - External Reset
CY8C55 has a dedicated XRES pin which holds the part in
reset while held active (low). The response to an XRES is the
same as to an IPOR reset. The external reset is active low. It
includes an internal pull-up resistor. XRES is active during
sleep and hibernate modes.
■
SRES - Software Reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
■
WRES - Watchdog Timer Reset
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Watchdog
Timer
Software
Reset
Register
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power on reset.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
■ IPOR - Initial Power on Reset
At initial power on, IPOR monitors the power voltages VDDD
and VDDA, both directly at the pins and at the outputs of the
corresponding internal regulators. The trip level is not precise.
It is set to approximately 1 volt, which is below the lowest
specified operating voltage but high enough for the internal
Document Number: 001-66235 Rev. *A
Another register bit exists to disable this function.
Note IPOR disables the watchdog function. The program
must enable the watchdog function at an appropriate point in
the code by setting a register bit. When this bit is set, it cannot
be cleared again except by an IPOR power on reset event.
The watchdog timer should not be used if the device is to be
put into sleep or hibernate mode.
Page 25 of 114
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PRELIMINARY
❐
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the VDDIO pins.
There are two types of I/O pins on every device; those with USB
provide a third type. Both general purpose I/O (GPIO) and
special I/O (SIO) provide similar digital functionality. The primary
differences are their analog capability and drive strength.
Devices that include USB also provide two USBIO pins that
support specific USB functionality as well as limited GPIO
capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense[8], and LCD segment drive,
while SIO pins are used for voltages in excess of VDDA and for
programmable output voltages.
■
Features supported by both GPIO and SIO:
❐ Separate I/O supplies and voltages for up to four groups of I/O
❐ Digital peripherals use DSI to connect the pins
❐ Input or output or both for CPU and DMA
❐ Eight drive modes
❐ Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
❐ Dedicated port interrupt vector for each port
❐ Slew rate controlled digital output drive mode
❐ Access port control and configuration registers on either port
basis or pin basis
PSoC® 5: CY8C55 Family Datasheet
Separate port read (PS) and write (DR) data registers to avoid
read modify write errors
❐ Special functionality on a pin by pin basis
■
Additional features only provided on the GPIO pins:
❐ LCD segment drive on LCD equipped devices
[8]
❐ CapSense on CapSense equipped devices
❐ Analog input and output capability
❐ Continuous 100 µA clamp current capability
❐ Standard drive strength down to 2.7 V
■
Additional features only provided on SIO pins:
❐ Higher drive strength than GPIO
❐ Hot swap capability (5 V tolerance at any operating VDD)
❐ Programmable and regulated high input and output drive
levels down to 1.2 V
❐ No analog input or LCD capability
❐ Over voltage tolerance up to 5.5 V
❐ SIO can act as a general purpose analog comparator
■
USBIO features:
❐ Full speed USB 2.0 compliant I/O
❐ Highest drive strength for general purpose use
❐ Input, output, or both for CPU and DMA
❐ Input, output, or both for digital peripherals
❐ Digital output (CMOS) drive mode
❐ Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges
Note
8. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-66235 Rev. *A
Page 26 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 6-8. GPIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
Vddio Vddio
PRT[x]DR
0
In
Digital System Output
1
Vddio
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Analog
Slew
Cntl
PIN
OE
1
0
1
Capsense Global Control
0
1
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global Enable
PRT[x]AMUX
Analog Mux Enable
LCD
Display
Data
PRT[x]LCD_COM_SEG
Logic & MUX
PRT[x]LCD_EN
LCD Bias Bus
Document Number: 001-66235 Rev. *A
5
Page 27 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Buffer
Thresholds
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
PRT[x]DR
Driver
Vhigh
0
Digital System Output
In
1
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Slew
Cntl
PIN
OE
Figure 6-10. USBIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
USB Receiver Circuitry
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SYNC_OUT
D+ pin only
USBIO_CR1[7]
USB or I/O
USB SIE Control for USB Mode
USBIO_CR1[4,5]
Digital System Output
PRT[x]BYP
Vddd
Vddd
Vddd Vddd
0
In
1
Drive
Logic
5k
1.5 k
PIN
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
Document Number: 001-66235 Rev. *A
D+ 1.5 k
D+D- 5 k
Open Drain
Page 28 of 114
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PRELIMINARY
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in Table 6-6. Three configuration bits
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers. Figure 6-11 depicts a simplified pin view based on
each of the eight drive modes. Table 6-6 shows the I/O pin’s drive
state based on the port data register value or digital array signal
PSoC® 5: CY8C55 Family Datasheet
if bypass mode is selected. Note that the actual I/O pin voltage
is determined by a combination of the selected drive mode and
the load at the pin. For example, if a GPIO pin is configured for
resistive pull-up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage
unmeasured at the pin is a low logic state.
Figure 6-11. Drive Mode
Vddio
DR
PS
0.
Pin
High Impedance
Analog
DR
PS
Pin
1. High Impedance
Digital
DR
PS
Pin
2. Resistive
Pull-Up
Vddio
DR
PS
Pin
4. Open Drain,
Drives Low
DR
PS
Vddio
DR
PS
3. Resistive
Pull-Down
Vddio
Pin
5. Open Drain,
Drives High
DR
PS
Vddio
Pin
6. Strong Drive
Pin
DR
PS
Pin
7. Resistive
Pull-Up and Pull-Down
Table 6-6. Drive Modes
Diagram
■
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
0
High impedence analog
Drive Mode
0
0
0
High-Z
High-Z
1
High Impedance digital
0
0
1
High-Z
High-Z
2
Resistive pull-up[9]
0
1
0
Res High (5K)
Strong Low
3
Resistive pull-down[9]
0
1
1
Strong High
Res Low (5K)
4
Open drain, drives low
1
0
0
High-Z
Strong Low
5
Open drain, drive high
1
0
1
Strong High
High-Z
6
Strong drive
1
1
0
Strong High
Strong Low
7
Resistive pull-up and pull-down[9]
1
1
1
Res High (5K)
Res Low (5K)
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog
mode, or have their pins driven to a power supply rail by the
PSoC device or by external circuitry.
High Impedance Analog
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not
provide digital input functionality.
■
High Impedance Digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Note
9. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Document Number: 001-66235 Rev. *A
Page 29 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
■
Resistive Pull-up or Resistive Pull-down
Resistive pull-up or pull-down, respectively, provides a series
resistance in one of the data states and strong drive in the
other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common
application for these modes. Resistive pull-up and pull-down
are not available with SIO in regulated output mode.
6.4.5 Pin Interrupts
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
■
Open Drain, Drives High and Open Drain, Drives Low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for
digital input and output in these modes. A common
application for these modes is driving the I2C bus signal lines.
■
Strong Drive
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal
circumstances. This mode is often used to drive digital output
signals or external FETs.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to “1” and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
■
Resistive Pull-up and Pull-down
Similar to the resistive pull-up and resistive pull-down modes
except the pin is always in series with a resistor. The high data
state is pull-up while the low data state is pull-down. This
mode is most often used when other signals that may cause
shorts can drive the bus. Resistive pull-up and pull-down are
not available with SIO in regulated output mode.
6.4.2 Pin Registers
Registers to configure and interact with pins come in two forms
that may be used interchangeably. All I/O registers are available
in the standard port form, where each bit of the register
corresponds to one of the port pins. This register form is efficient
for quickly reconfiguring multiple port pins at the same time.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
6.4.3 Bidirectional Mode
High speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRTxDM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The
bidirectional capability is useful for processor busses and
communications interfaces such as the SPI Slave MISO pin that
requires dynamic hardware control of the output buffer. The
auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRTxSLW registers.
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
While level sensitive interrupts are not directly supported;
Universal Digital Blocks (UDB) provide this functionality to the
system when needed.
6.4.6 Input Buffer Mode
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
6.4.7 I/O Power Supplies
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (VDDA) pin. This feature allows
users to provide different I/O voltage levels for different pins on
the device. Refer to the specific device package pinout to
determine VDDIO capability for a given port and pin. The SIO port
pins support an additional regulated high output capability, as
described in 6.4.11 Adjustable Output Level.
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the VDDIO supply voltage to which
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, select pins provide direct connections to specific
analog features such as the high current DACs or uncommitted
opamps.
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders[10]. See the
“CapSense” section on page 53 for more information.
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the “LCD Direct Drive” section on
page 52 for details.
Note
10. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-66235 Rev. *A
Page 30 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
6.4.11 Adjustable Output Level
6.4.13 SIO as Comparator
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective VDDIO. SIO pins are individually configurable to output
either the standard VDDIO level or the regulated output, which is
based on an internally generated reference. Typically a voltage
DAC (VDAC) is used to generate the reference (see Figure
6-12). The “DAC” section on page 53 has more details on VDAC
use and reference routing to the SIO pins. Resistive pull-up and
pull-down drive modes are not available with SIO in regulated
output mode.
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the 6.4.12 Adjustable Input
Level section can be used to construct a comparator. The
threshold for the comparator is provided by the SIO's reference
generator. The reference generator has the option to set the
analog signal routed through the analog global line as threshold
for the comparator. Note that a pair of SIO pins share the same
threshold.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from VDDIO. The
reference sets the pins voltage threshold for a high logic level
(see Figure 6-12). Available input thresholds are:
■ 0.5 × VDDIO
■ 0.4 × VDDIO
■ 0.5 × VREF
■ VREF
Typically a voltage DAC (VDAC) generates the VREF reference.
“DAC” section on page 53 has more details on VDAC use and
reference routing to the SIO pins.
Figure 6-12. SIO Reference for Input and Output
The digital input path in Figure 6-9 on page 28 illustrates this
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage (VDDIO < VIN < VDDA)
tolerance feature at any operating VDD.
■
There are no current limitations for the SIO pins as they present
a high impedance load to the external circuit.
■
The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the VDDIO supply.
■
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the VDDIO supply
voltage to which the GPIO belongs.
Input Path
Digital
Input
Vinref
Reference
Generator
SIO_Ref
PIN
Voutref
Output Path
Driver
Vhigh
Digital
Output
A common application for this feature is connection to a bus such
as I2C where different devices are running from different supply
voltages. In the I2C case, the PSoC chip is configured into the
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull-up to pull the I2C bus voltage above the PSoC pin
supply. For example, the PSoC chip could operate at 2.7 V, and
an external device could run from 5 V. Note that the SIO pin’s VIH
and VIL levels are determined by the associated VDDIO supply
pin.
The I/O pin must be configured into a high impedance drive
mode, open drain low drive mode, or pull-down drive mode, for
over voltage tolerance to work properly. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
Drive
Logic
At reset, all I/Os are reset to the High Impedance Analog state.
6.4.17 Low Power Functionality
In all low power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low power modes.
Document Number: 001-66235 Rev. *A
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Figure 7-1. CY8C55 Digital Programmable Architecture
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in “Pinouts” on page 5. The special
features are:
Analog
❐ Opamp inputs and outputs
❐ High current IDAC outputs
❐ External reference inputs
IO Port
7. Digital Subsystem
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture.
Designers do not need to interact directly with the programmable
digital system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
The main components of the digital programmable system are:
■
■
■
Universal Digital Blocks (UDB) - These form the core
functionality of the digital programmable system. UDBs are a
collection of uncommitted logic (PLD) and structural logic
(Datapath) optimized to create all common embedded
peripherals and customized functionality that are application or
design specific.
Universal Digital Block Array - UDB blocks are arrayed within
a matrix of programmable interconnect. The UDB array
structure is homogeneous and allows for flexible mapping of
digital functions onto the array. The array supports extensive
and flexible routing interconnects between UDBs and the
Digital System Interconnect.
Digital System Interconnect (DSI) - Digital signals from
Universal Digital Blocks (UDBs), fixed function peripherals, I/O
pins, interrupts, DMA, and other system core signals are
attached to the Digital System Interconnect to implement full
featured device connectivity. The DSI allows any digital function
to any pin or other feature routability when used with the
Universal Digital Block Array.
Document Number: 001-66235 Rev. *A
IO Port
DSI Routing Interface
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
DSI Routing Interface
IO Port
Digital
❐ 4- to 25 MHz crystal oscillator
❐ 32.768 KHz crystal oscillator
❐ SWD and SWV interface pins
❐ External reset
UDB Array
■
IO Port
■
Digital Core System
and Fixed Function Peripherals
UDB Array
6.4.18 Special Pin Functionality
PSoC® 5: CY8C55 Family Datasheet
Digital Core System
and Fixed Function Peripherals
7.1 Example Peripherals
The flexibility of the CY8C55 family’s UDBs and analog blocks
allow the user to create a wide range of components
(peripherals). The most common peripherals were built and
characterized by Cypress and are shown in the PSoC Creator
component catalog, however, users may also create their own
custom components using PSoC Creator. Using PSoC Creator,
users may also create their own components for reuse within
their organization, for example sensor interfaces, proprietary
algorithms, and display interfaces.
The number of components available through PSoC Creator is
too numerous to list in the data sheet, and the list is always
growing. An example of a component available for use in
CY8C55 family, but, not explicitly called out in this data sheet is
the UART component.
7.1.1 Example Digital Components
The following is a sample of the digital components available in
PSoC Creator for the CY8C55 family. The exact amount of
hardware resources (UDBs, routing, RAM, flash) used by a
component varies with the features selected in PSoC Creator for
the component.
■
Communications
2
❐ I C (1 to 3 UDBs)
❐ UART (1 to 3 UDBs)
■
Functions
❐ PWM (1 to 2 UDBs)
■
Logic (x CPLD product terms per logic function)
❐ NOT
❐ OR
❐ XOR
❐ AND
Page 32 of 114
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PSoC® 5: CY8C55 Family Datasheet
7.1.2 Example Analog Components
7.1.4 Designing with PSoC Creator
The following is a sample of the analog components available in
PSoC Creator for the CY8C55 family. The exact amount of
hardware resources (SC/CT blocks, routing, RAM, flash) used
by a component varies with the features selected in PSoC
Creator for the component.
7.1.4.1 More Than a Typical IDE
■
PSoC Creator is that design tool.
Amplifiers
❐ TIA
❐ PGA
❐ opamp
■
ADCs
❐ Delta-Sigma
❐ Successive Approximation (SAR)
■
DACs
❐ Current
❐ Voltage
❐ PWM
■
Comparators
■
Mixers
7.1.3 Example System Function Components
The following is a sample of the system function components
available in PSoC Creator for the CY8C55 family. The exact
amount of hardware resources (UDBs, DFB taps, SC/CT blocks,
routing, RAM, flash) used by a component varies with the
features selected in PSoC Creator for the component.
■
CapSense
■
LCD Drive
■
LCD Control
■
Filters
Document Number: 001-66235 Rev. *A
A successful design tool allows for the rapid development and
deployment of both simple and complex designs. It reduces or
eliminates any learning curve. It makes the integration of a new
design into the production stream straightforward.
PSoC Creator is a full featured Integrated Development
Environment (IDE) for hardware and software design. It is
optimized specifically for PSoC devices and combines a modern,
powerful software development platform with a sophisticated
graphical design tool. This unique combination of tools makes
PSoC Creator the most flexible embedded design platform
available.
Graphical design entry simplifies the task of configuring a
particular part. You can select the required functionality from an
extensive catalog of components and place it in your design. All
components are parameterized and have an editor dialog that
allows you to tailor functionality to your needs.
PSoC Creator automatically configures clocks and routes the I/O
to the selected pins and then generates APIs to give the
application complete control over the hardware. Changing the
PSoC device configuration is as simple as adding a new
component, setting its parameters, and rebuilding the project.
At any stage of development you are free to change the
hardware configuration and even the target processor. To
retarget your application (hardware and software) to new
devices, even from 8- to 32-bit families, just select the new
device and rebuild.
You also have the ability to change the C compiler and evaluate
an alternative. Components are designed for portability and are
validated against all devices, from all families, and against all
supported tool chains. Switching compilers is as easy as editing
the from the project options and rebuilding the application with
no errors from the generated APIs or boot code.
Page 33 of 114
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PSoC® 5: CY8C55 Family Datasheet
Figure 7-2. PSoC Creator Framework
Document Number: 001-66235 Rev. *A
Page 34 of 114
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PSoC® 5: CY8C55 Family Datasheet
7.1.4.2 Component Catalog
7.1.4.4 Software Development
Figure 7-3. Component Catalog
Figure 7-4. Code Editor
The component catalog is a repository of reusable design
elements that select device functionality and customize your
PSoC device. It is populated with an impressive selection of
content; from simple primitives such as logic gates and device
registers, through the digital timers, counters and PWMs, plus
analog components such as ADCs, DACs, and filters, and
communication protocols, such as I2C, USB and CAN. See
“Example Peripherals” section on page 32 for more details about
available peripherals. All content is fully characterized and
carefully documented in datasheets with code examples, AC/DC
specifications, and user code ready APIs.
Anchoring the tool is a modern, highly customizable user
interface. It includes project management and integrated editors
for C and assembler source code, as well the design entry tools.
Project build control leverages compiler technology from top
commercial vendors such as ARM® Limited, Keil™, and
CodeSourcery (GNU). Free versions of Keil C51 and GNU C
Compiler (GCC) for ARM, with no restrictions on code size or end
product distribution, are included with the tool distribution.
Upgrading to more optimizing compilers is a snap with support
for the professional Keil C51 product and ARM RealView™
compiler.
7.1.4.5 Nonintrusive Debugging
Figure 7-5. PSoC Creator Debugger
7.1.4.3 Design Reuse
The symbol editor gives you the ability to develop reusable
components that can significantly reduce future design time. Just
draw a symbol and associate that symbol with your proven
design. PSoC Creator allows for the placement of the new
symbol anywhere in the component catalog along with the
content provided by Cypress. You can then reuse your content
as many times as you want, and in any number of projects,
without ever having to revisit the details of the implementation.
Document Number: 001-66235 Rev. *A
With SWD debug connectivity available on all devices, the PSoC
Creator debugger offers full control over the target device with
minimum intrusion. Breakpoints and code execution commands
are all readily available from toolbar buttons and an impressive
lineup of windows—register, locals, watch, call stack, memory
and peripherals—make for an unparalleled level of visibility into
the system. PSoC Creator contains all the tools necessary to
complete a design, and then to maintain and extend that design
for years to come. All steps of the design flow are carefully
integrated and optimized for ease-of-use and to maximize
productivity.
Page 35 of 114
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PSoC® 5: CY8C55 Family Datasheet
Figure 7-6. UDB Block Diagram
Clock
and Reset
Control
PT6
PT7
IN0
TC
TC
TC
TC
TC
TC
TC
TC
IN1
TC
TC
TC
TC
TC
TC
TC
TC
IN2
TC
TC
TC
TC
TC
TC
TC
TC
IN3
TC
TC
TC
TC
TC
TC
TC
TC
IN4
TC
TC
TC
TC
TC
TC
TC
TC
IN5
TC
TC
TC
TC
TC
TC
TC
TC
IN6
TC
TC
TC
TC
TC
TC
TC
TC
IN7
TC
TC
TC
TC
TC
TC
TC
TC
IN8
TC
TC
TC
TC
TC
TC
TC
TC
IN9
TC
TC
TC
TC
TC
TC
TC
TC
IN10
TC
TC
TC
TC
TC
TC
TC
TC
IN11
TC
TC
TC
TC
TC
TC
TC
TC
PLD
12C4
(8 PTs)
OUT0
MC0
T
T
T
T
T
T
T
T
OUT1
MC1
T
T
T
T
T
T
T
T
OUT2
MC2
T
T
T
T
T
T
T
T
OUT3
MC3
T
T
T
T
T
T
T
T
SELOUT
(carry out)
Status and
Control
Datapath
OR
Array
Datapath
Chaining
Routing Channel
The main component blocks of the UDB are:
■ PLD blocks - There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or
combinational sum-of-products logic. PLDs are used to
implement state machines, state bits, and combinational logic
equations. PLD configuration is automatically generated from
graphical primitives.
■ Datapath Module - This 8-bit wide datapath contains structured
logic to implement a dynamically configurable ALU, a variety
of compare configurations and condition generation. This block
also contains input/output FIFOs, which are the primary parallel
data interface between the CPU/DMA system and the UDB.
■ Status and Control Module - The primary role of this block is to
provide a way for CPU firmware to interact and synchronize
with UDB operation.
■ Clock and Reset Module - This block provides the UDB clocks
and reset selection and control.
Document Number: 001-66235 Rev. *A
AND
Array
SELIN
(carry in)
PLD
Chaining
PLD
12C4
(8 PTs)
PT5
Figure 7-7. PLD 12C4 Structure
PT4
To achieve this, UDBs consist of a combination of uncommitted
logic (PLD), structured logic (Datapath), and a flexible routing
scheme to provide interconnect between these elements, I/O
connections, and other peripherals. UDB functionality ranges
from simple self contained functions that are implemented in one
UDB, or even a portion of a UDB (unused resources are
available for other functions), to more complex functions that
require multiple UDBs. Examples of basic functions are timers,
counters, CRC generators, PWMs, dead band generators, and
communications functions, such as UARTs, SPI, and I2C. Also,
the PLD blocks and connectivity provide full featured general
purpose programmable logic within the limits of the available
resources.
PT3
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, look up tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
PT2
The Universal Digital Block (UDB) represents an evolutionary
step to the next generation of PSoC embedded digital peripheral
functionality. The architecture in first generation PSoC digital
blocks provides coarse programmability in which a few fixed
functions with a small number of options are available. The new
UDB architecture is the optimal balance between configuration
granularity and efficient implementation. A cornerstone of this
approach is to provide the ability to customize the devices digital
operation to match application requirements.
PT1
7.2.1 PLD Module
PT0
7.2 Universal Digital Block
One 12C4 PLD block is shown in Figure 7-7. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
7.2.2 Datapath Module
The datapath contains an 8-bit single cycle ALU, with associated
compare and condition generation logic. This datapath block is
optimized to implement embedded functions, such as timers,
counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
Page 36 of 114
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PSoC® 5: CY8C55 Family Datasheet
Figure 7-8. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
F1
F0
A0
A1
D0
D1
D1
Data Registers
D0
To/From
Previous
Datapath
A1
Conditions: 2 Compares,
2 Zero Detect, 2 Ones
Detect Overflow Detect
6
Control Store RAM
8 Word X 16 Bit
Input from
Programmable
Routing
Datapath Control
FIFOs
Input
Muxes
Chaining
Output
Muxes
6
Output to
Programmable
Routing
To/From
Next
Datapath
Accumulators
A0
PI
Parallel Input/Output
(To/From Programmable Routing)
PO
ALU
Shift
Mask
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
Table 7-1. Working Datapath Registers
ALU
7.2.2.1 Working Registers
Name
Function
Description
The ALU performs eight general purpose functions. They are:
These are sources and sinks for
the ALU and also sources for the
compares.
■
Increment
■
Decrement
D0 and D1 Data Registers
These are sources for the ALU
and sources for the compares.
■
Add
■
Subtract
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumulators or ALU. Each FIFO is four
bytes deep.
■
Logical AND
■
Logical OR
■
Logical XOR
■
Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register
A0 and A1 Accumulators
7.2.2.2 Dynamic Datapath Configuration RAM
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
x 16-bit configuration RAM, which stores eight unique 16-bit wide
configurations. The address input to this RAM controls the
Document Number: 001-66235 Rev. *A
Independent of the ALU operation, these functions are available:
■
Shift left
■
Shift right
■
Nibble swap
■
Bitwise OR mask
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7.2.2.3 Conditionals
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These
conditions are the primary datapath outputs, a selection of which
can be driven out to the UDB routing matrix. Conditional
computation can use the built in chaining to neighboring UDBs
to operate on wider data widths without the need to use routing
resources.
7.2.2.4 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.5 Built in CRC/PRS
The datapath has built in support for single cycle Cyclic
Redundancy Check (CRC) computation and Pseudo Random
Sequence (PRS) generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be
implemented in conjunction with PLD logic, or built in chaining
may be use to extend the function into neighboring UDBs.
PSoC® 5: CY8C55 Family Datasheet
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.9 Datapath I/O
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the
configuration for the datapath operation to perform in each cycle,
and the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated
conditions, and the serial data outputs. Outputs can be routed to
other UDB blocks, device peripherals, interrupt and DMA
controller, I/O pins, and so on.
7.2.3 Status and Control Module
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Figure 7-10. Status and Control Registers
System Bus
7.2.2.6 Input/Output FIFOs
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
Figure 7-9. Example FIFO Configurations
System Bus
System Bus
F0
D0/D1
A0/A1/ALU
F1
A0/A1/ALU
A0/A1/ALU
F0
F0
F1
D0
A0
D1
A1
F1
System Bus
System Bus
TX/RX
Dual Capture
Dual Buffer
8-bit Status Register
(Read Only)
8-bit Control Register
(Write/Read)
Routing Channel
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
7.2.3.1 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
7.2.2.7 Chaining
7.2.3.2 Clock Generation
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
7.2.2.8 Time Multiplexing
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
Document Number: 001-66235 Rev. *A
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Figure 7-11 shows an example of a 16 UDB array. In addition to
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Figure 7-12. Function Mapping Example in a Bank of UDBs
8-Bit
Timer
Sequencer
7.3 UDB Array Description
PSoC® 5: CY8C55 Family Datasheet
Quadrature Decoder
UDB
UDB
HV
A
16-Bit
PWM
16-Bit PYRS
UDB
HV
B
UDB
HV
A
HV
B
Figure 7-11. Digital System Interface Structure
System Connections
UDB
UDB
UDB
8-Bit
Timer Logic
UDB
8-Bit SPI
HV
B
HV
A
HV
B
I2C Slave
HV
A
12-Bit SPI
UDB
UDB
UDB
HV
A
UDB
HV
B
UDB
UDB
UDB
UDB
HV
A
HV
B
HV
B
HV
A
HV
B
HV
A
Logic
UDB
UDB
UDB
UDB
UDB
UDB
UART
UDB
UDB
HV
B
UDB
UDB
HV
A
UDB
HV
A
UDB
12-Bit PWM
UDB
HV
B
UDB
HV
B
UDB
HV
A
UDB
HV
A
HV
B
System Connections
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-13 illustrates the concept of the digital system
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
7.3.1 UDB Array Programmable Resources
Signals in this category include:
Figure 7-12 shows an example of how functions are mapped into
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
■
Interrupt requests from all digital peripherals in the system.
■
DMA requests from all digital peripherals in the system.
■
Digital peripheral data signals that need flexible routing to I/Os.
■
Digital peripheral data signals that need connections to UDBs.
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
■
Connections to the interrupt and DMA controllers.
■
Connection to I/O pins.
■
Connection to analog system digital signals.
Document Number: 001-66235 Rev. *A
Page 39 of 114
[+] Feedback
PRELIMINARY
Figure 7-13. Digital System Interconnect
Timer
Counters
CAN
Interrupt
Controller
I2C
DMA
Controller
IO Port
Pins
Global
Clocks
PSoC® 5: CY8C55 Family Datasheet
the system clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-15. I/O Pin Synchronization Routing
DO
Digital System Routing I/F
DI
UDB ARRAY
Digital System Routing I/F
Figure 7-16. I/O Pin Output Connectivity
8 IO Data Output Connections from the
UDB Array Digital System Interface
Global
Clocks
IO Port
Pins
Del-Sig
SC/CT
Blocks
DACs
Comparators
Interrupt and DMA routing is very flexible in the CY8C55
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-14 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
DO
PIN 0
DO
PIN1
DO
PIN2
DO
PIN3
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
Port i
Figure 7-14. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX
Fixed Function IRQs
0
1
IRQs
UDB Array
2
Edge
Detect
Interrupt
Controller
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-17. I/O Pin Output Enable Connectivity
3
4 IO Control Signal Connections from
UDB Array Digital System Interface
DRQs
DMA termout (IRQs)
0
Fixed Function DRQs
1
Edge
Detect
DMA
Controller
2
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
Document Number: 001-66235 Rev. *A
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
Page 40 of 114
[+] Feedback
PRELIMINARY
7.5 CAN
The CAN peripheral is a fully functional Controller Area Network
(CAN) supporting communication baud rates up to 1 Mbps. The
CAN controller implements the CAN2.0A and CAN2.0B
specifications as defined in the Bosch specification and
conforms to the ISO-11898-1 standard. The CAN protocol was
originally designed for automotive applications with a focus on a
high level of fault detection. This ensures high communication
PSoC® 5: CY8C55 Family Datasheet
reliability at a low cost. Because of its success in automotive
applications, CAN is used as a standard communication protocol
for motion oriented machine control networks (CANOpen) and
factory automation applications (DeviceNet). The CAN controller
features allow the efficient implementation of higher level
protocols without affecting the performance of the
microcontroller CPU. Full configuration support is provided in
PSoC Creator.
Figure 7-18. CAN Bus System Implementation
CAN Node 1
CAN Node 2
CAN Node n
PSoC
CAN
Drivers
CAN Controller
En
Tx Rx
CAN Transceiver
CAN_H
CAN_L
CAN_H
CAN_L
CAN_H
CAN_L
CAN Bus
7.5.1 CAN Features
■
CAN2.0A/B protocol implementation - ISO 11898 compliant
❐ Standard and extended frames with up to 8 bytes of data per
frame
❐ Message filter capabilities
❐ Remote Transmission Request (RTR) support
❐ Programmable bit rate up to 1 Mbps
■
Listen Only mode
■
SW readable error counter and indicator
■
Sleep mode: Wake the device from sleep with activity on the
Rx pin
■
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
■
Enhanced interrupt controller
❐ CAN receive and transmit buffers status
❐ CAN controller error status including BusOff
Document Number: 001-66235 Rev. *A
■
Receive path
❐ 16 receive buffers each with its own message filter
❐ Enhanced hardware message filter implementation that
covers the ID, IDE and RTR
❐ DeviceNet addressing support
❐ Multiple receive buffers linkable to build a larger receive
message array
❐ Automatic transmission request (RTR) response handler
❐ Lost received message notification
■
Transmit path
❐ Eight transmit buffers
❐ Programmable transmit priority
❐ Round robin
❐ Fixed priority
❐ Message transmissions abort capability
7.5.2 Software Tools Support
CAN Controller configuration integrated into PSoC Creator:
■
CAN Configuration walkthrough with bit timing analyzer
■
Receive filter setup
Page 41 of 114
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 7-19. CAN Controller Block Diagram
TxMessage0
TxReq
TxAbort
Tx Buffer
Status
TxReq
Pending
TxMessage1
TxReq
TxAbort
Bit Timing
Priority
Arbiter
TxMessage6
TxReq
TxAbort
TxInterrupt
Request
(if enabled)
TxMessage7
TxReq
TxAbort
RxMessage0
Acceptance Code 0
Acceptance Mask 0
RxMessage1
Acceptance Code 1
Acceptance Mask 1
Rx
RxMessage
Handler
RxInterrupt
Request
(if enabled)
RxMessage14
Acceptance Code 14
Acceptance Mask 14
RxMessage15
Acceptance Code 15
Acceptance Mask 15
ErrInterrupt
Request
(if enabled)
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the “6.4 I/O System
and Routing” section on page 26.
USB includes the following features:
Rx
CAN
Framer
CRC Check
WakeUp
Request
Error Detection
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
Figure 7-20. USB
Arbiter
System Bus
7.6 USB
CRC
Generator
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
RTR RxMessages
0-15
Rx Buffer
Status
RxMessage
Available
Tx
Tx
CAN
Framer
512 X 8
SRAM
D+
SIE
(Serial Interface
Engine)
External 22 Ω
Resistors
USB
I/O
Interrupts
D–
■
Eight unidirectional data endpoints
■
One bidirectional control endpoint 0 (EP0)
■
Shared 512-byte buffer for the eight data endpoints
■
Dedicated 8-byte buffer for EP0
7.7 Timers, Counters, and PWMs
■
Two memory modes
❐ Manual Memory Management with No DMA Access
❐ Manual Memory Management with Manual DMA Access
Internal 3.3 V regulator for transceiver
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows designers to choose the timer, counter, and
PWM features that they require. The tool set utilizes the most
optimal resources available.
■
■
Internal 48 MHz oscillator that auto locks to USB bus clock,
requiring no external crystal for USB (USB equipped parts only)
■
Interrupts on bus and each endpoint event, with device wakeup
■
USB Reset, Suspend, and Resume operations
■
Bus powered and self powered modes
Document Number: 001-66235 Rev. *A
48 MHz
IMO
Page 42 of 114
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PRELIMINARY
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
PSoC® 5: CY8C55 Family Datasheet
7.8 I2C
The I2C peripheral provides a synchronous two wire interface
designed to interface the PSoC device with a two wire I2C serial
communication bus. The bus is compliant with Philips ‘The I2C
Specification’ version 2.1. Additional I2C interfaces can be
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
■
16-bit timer/counter/PWM (down count only)
■
Selectable clock source
■
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
■
Period reload on start, reset, and terminal count
■
Interrupt on terminal count, compare true, or capture
To eliminate the need for excessive CPU intervention and
overhead, I2C specific support is provided for status detection
and generation of framing bits. I2C operates as a slave, a master,
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I2C interfaces through the
DSI routing and allows direct connections to any GPIO or SIO
pins.
■
Dynamic counter reads
I2C features include:
■
Timer capture mode
■
Slave and Master, Transmitter, and Receiver operation
■
Count while enable signal is asserted mode
■
Byte processing for low CPU overhead
■
Free run mode
■
Interrupt or polling CPU interface
■
One-shot mode (stop at end of period)
■
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
■
Complementary PWM outputs with deadband
■
■
PWM output kill
7 or 10-bit addressing (10-bit addressing requires firmware
support)
Timer/Counter/PWM features include:
■
SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
Data transfers follow the format shown in Figure 7-22. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
Figure 7-21. Timer/Counter/PWM
Clock
Reset
Enable
Capture
Kill
IRQ
TC / Compare!
Compare
Timer / Counter /
PWM 16-bit
Figure 7-22. I2C Complete Transfer Timing
SDA
1-7
SCL
START
Condition
ADDRESS
Document Number: 001-66235 Rev. *A
8
9
R/W
ACK
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
STOP
Condition
Page 43 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
7.9 Digital Filter Block
8. Analog Subsystem
Some devices in the CY8C55 family of devices have a dedicated
HW accelerator block used for digital filtering. The DFB has a
dedicated multiplier and accumulator that calculates a 24-bit by
24-bit multiply accumulate in one system clock cycle. This
enables the mapping of a direct form FIR filter that approaches
a computation rate of one FIR tap for each clock cycle. The MCU
can implement any of the functions performed by this block, but
at a slower rate that consumes significant MCU bandwidth.
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
The PSoC Creator interface provides a wizard to implement FIR
and IIR digital filters with coefficients for LPF, BPF, HPF, Notch
and arbitrary shape filters. 64 pairs of data and coefficients are
stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of
either FIR or IIR formulation.
■
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses
■
High resolution Delta-Sigma ADC
■
Two successive approximation (SAR) ADCs
Figure 7-23. DFB Application Diagram (pwr/gnd not shown)
■
Four 8-bit DACs that provide either voltage or current output
■
Four comparators with optional connection to configurable LUT
outputs
■
Four configurable switched capacitor/continuos time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer
■
Four opamps for internal use and connection to GPIO that can
be used as high current output buffers
■
CapSense subsystem to enable capacitive touch sensing
■
Precision reference for generating an accurate analog voltage
for internal analog blocks
BUSCLK
read_data
Data
Source
(PHUB)
write_data
Digital
Routing
addr
System
Bus
Digital Filter
Block
Data
Dest
(PHUB)
DMA
Request
DMA
CTRL
The typical use model is for data to be supplied to the DFB over
the system bus from another on-chip system data source such
as an ADC. The data typically passes through main memory or
is directly transferred from another chip resource through DMA.
The DFB processes this data and passes the result to another
on chip resource such as a DAC or main memory through DMA
on the system bus.
Data movement in or out of the DFB is typically controlled by the
system DMA controller but can be moved directly by the MCU.
Document Number: 001-66235 Rev. *A
Page 44 of 114
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 8-1. Analog Subsystem Block Diagram
SAR
ADC
DAC
DAC
DelSig
ADC
A
N
A
L
O
G
SAR
ADC
Precision
Reference
DAC
DAC
SC/CT Block
SC/CT Block
Op
Amp
Op
Amp
SC/CT Block
Comparators
CMP
CMP
CMP
Op
Amp
R
O
U
T
I
N
G
Op
Amp
SC/CT Block
GPIO
Port
A
N
A
L
O
G
R
O
U
T
I
N
G
GPIO
Port
CMP
CapSense Subsystem
Analog
Interface
DSI
Array
Clock
Distribution
Config &
Status
Registers
PHUB
CPU
Decimator
The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and
various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries
that allow you to configure the various analog blocks to perform application specific functions (PGA, transimpedance amplifier, voltage
DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the
communication between the analog peripheral and CPU/Memory.
Document Number: 001-66235 Rev. *A
Page 45 of 114
[+] Feedback
PRELIMINARY
8.1 Analog Routing
The CY8C38 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks. All analog routing
switches are open when the device is in sleep or hibernate mode.
For information on how to make pin selections for optimal analog
routing, refer to the application note, AN58304 - PSoC® 3 and
PSoC® 5 - Pin Selection for Analog Designs.
8.1.1 Features
■
Flexible, configurable analog routing architecture
■
16 analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
■
Each GPIO is connected to one analog global and one analog
mux bus
Document Number: 001-66235 Rev. *A
PSoC® 5: CY8C55 Family Datasheet
■
Eight analog local buses (abus) to route signals between the
different analog blocks
■
Multiplexers and switches for input and output selection of the
analog blocks
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C38 family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2.
Page 46 of 114
[+] Feedback
PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 8-2. CY8C55 Analog Interconnect
Vssd
Vcca
*
Vssa
*
*
*
*
AGL[6]
AGL[7]
AGL[4]
AGL[5]
swinp
01 2 3 456 7 0123
*
swfol
opamp3
opamp1
swfol
swfol
GPIO
P3[5]
GPIO
swinp P3[4]
GPIO
swinn P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
*P15[1]
GPXT
*P15[0]
3210 76543210
swinn
swfol
swinn
*
cmp0_vref
(1.024V)
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
out1
swout
COMPARATOR
+
comp3 -
90
abuf_vref_int
(1.024V)
swin
comp1 +
-
+
- comp2
cmp_muxvn[1:0]
vref_cmp1
(0.256V)
in1
5
comp0
+
-
cmp1_vref
refbufl_
cmp
i2
*
LPF
out0
swin
ExVrefR
i3
refbufr_
cmp
in0
swout
abuf_vref_int
(1.024V)
cmp1_vref
i0
*
cmp0_vref
(1.024V)
i1
cmp1_vref
bg_vda_res_en
bg_vda_swabusl0
refsel[1:0]
sc0
Vin
Vref
out
vssa
sc0_bgref
(1.024V)
sc1_bgref
(1.024V)
104
v0
DAC0
i0
DAC1
v1
i1
v2
DAC2
i2
DAC3
v3
i3
USB IO
36
USB IO
* P15[6]
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
*P1[7]
GPIO
*P1[6]
dac_vref (0.256V)
vpwra
vpwra/2
dsm0_vcm_vref1
(0.8V)
dsm0_vcm_vref2 (0.7V)
+
DSM0
-
dsm0_qtz_vref2 (1.2V)
dsm0_qtz_vref1 (1.024V)
Vdda
Vdda/4
en_resvda
vssa
28
ExVrefL
Vp (+)
Vn (-) SAR0
Vrefhi_out
refs
SAR_vref1 (1.024V)
SAR_vref2 (1.2V)
ExVrefR
(+) Vp
SAR1 (-) Vn
Vrefhi_out
refs
SAR_vref1 (1.024V)
SAR_vref2 (1.2V)
SAR ADC
Vdda
Vdda/2
en_resvda
DSM
vcm
refs
qtz_ref
vref_vss_ext
refmux[2:0]
ExVrefL1
refmux[2:0]
ExVrefL2
refmux[2:0]
Vdda
Vdda/2
en_resvda
CY8C55 only
01 23456 7 0123
3210 76543210
AGR[3]
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
*
13
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C38,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in Figure 8-2. Using the abus saves the analog
globals and analog mux buses from being used for
interconnecting the analog blocks.
Document Number: 001-66235 Rev. *A
Vssd
XRES
Vbat
Vboost
Ind
Vssb
GPIO
P2[5]
GPIO
P2[6]
GPIO
P2[7]
SIO
P12[4]
SIO
P12[5]
GPIO
P6[4]
GPIO
P6[5]
GPIO
P6[6]
GPIO
P6[7]
*
*
Large ( ~200 Ohms)
*
*
Switch Resistance
Small ( ~870 Ohms )
*
*
Connection
*
*
Mux Group
Switch Group
Vddio1
AGL[3]
AGL[2]
AGL[1]
AGL[0]
AMUXBUSL
AGR[0]
AMUXBUSR
AGR[3]
AGR[2]
AGR[1]
LPF
*
AGL[1]
AGL[2]
AGL[3]
VBE
Vss ref
GPIO
P5[0]
GPIO
P5[1]
GPIO
P5[2]
GPIO
P5[3]
GPIO
P1[0]
GPIO
P1[1]
GPIO
P1[2]
GPIO
P1[3]
GPIO
P1[4]
GPIO
P1[5]
TS
ADC
:
AMUXBUSR
ANALOG ANALOG
BUS
GLOBALS
*
AMUXBUSL
AGL[0]
ANALOG ANALOG
GLOBALS
BUS
Notes:
* Denotes pins on all packages
LCD signals are not shown.
*
AMUXBUSL
Vssd
Vddd
* P15[7]
VIDAC
vcmsel[1:0]
en_resvpwra
Vccd
ABUSR0
ABUSR1
ABUSR2
ABUSR3
ABUSL0
ABUSL1
ABUSL2
ABUSL3
*
*
Vddio2
sc2_bgref
(1.024V)
sc3_bgref
(1.024V)
Vin
Vref
out
sc3
*
*
Vddd
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3] *
GPIO
P2[4] *
Vssa
*
*
Vssd
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
sc1
Vin
Vref
out
SC/CT
Vin
Vref
out
sc2
out
ref
in
*
Vccd
refbufr
AGR[4]
AMUXBUSR
CAPSENSE
out
ref
in refbufl
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
AGR[7]
AGR[6]
AGR[5]
Vdda
Vdda/2
*
*
*
*
AMUXBUSL
*
44
*
*
opamp2
*
AGR[6]
AGR[7]
AGL[7]
ExVrefL2
opamp0
*
AGR[4]
AGR[5]
AGL[4]
AGL[5]
AGL[6]
swinp
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
*
*
AMUXBUSR
AMUXBUSL
ExVrefL
ExVrefL1
Vddio3
GPIO
P3[6]
GPIO
P3[7]
SIO
P12[0]
SIO
P12[1]
GPIO
P15[2]
GPIO
P15[3]
swinp
*
Vdda
SIO
P12[2]
SIO
P12[3]
GPIO
P4[0]
GPIO
P4[1]
GPIO
P0[0]
GPIO
P0[1]
GPIO
P0[2]
GPIO
P0[3]
Vddio0
swinn
Rev #51
2-April-2010
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2,
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
Page 47 of 114
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PRELIMINARY
8.2 Delta-sigma ADC
The CY8C38 device contains one delta-sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for both audio signal processing
and measurement applications. The converter's nominal
operation is 16 bits at 48 ksps. The ADC can be configured to
output 20-bit resolution at data rates of up to 187 sps. At a fixed
clock rate, resolution can be traded for faster data rates as
shown in Table 8-1 and Figure 8-3.
PSoC® 5: CY8C55 Family Datasheet
modulator/decimator frequency response is [(sin x)/x]4; a typical
frequency response is shown in Figure 8-5.
Figure 8-4. Delta-sigma ADC Block Diagram
Positive
Input Mux
(Analog Routing)
Input
Buffer
Negative
Input Mux
Delta
Sigma
Modulator
Decimator
Table 8-1. Delta-sigma ADC Performance
Maximum Sample Rate
(sps)
Bits
12 to 20 Bit
Result
EOC
SOC
SINAD (dB)
Figure 8-5. Delta-sigma ADC Frequency Response, Normalized to Output, Sample Rate = 48 kHz
20
187
–
16
48 k
84
0
12
192 k
66
-10
8
384 k
43
-20
Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V
1000000
100000
10000
frequency Response. dB
-30
-40
-50
-60
-70
-80
-90
-100
Sample rate SPS)
100
1,000
10,000
100,000
1,000,000
Input Frequency, Hz
Input frequency, Hz
1000
Resolution and sample rate are controlled by the Decimator.
Data is pipelined in the decimator; the output is a function of the
last four samples. When the input multiplexer is switched, the
output data is not valid until after the fourth sample after the
switch.
Continuous
Multi-Sample
100
Multi-SampleTurbo
10
8.2.2 Operational Modes
1
6
8
10
12
14
16
18
20
22
Resolution,
bitsbits
Resolution,
8.2.1 Functional Description
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
block diagram is shown in Figure 8-4. The signal from the input
muxes is delivered to the delta-sigma modulator either directly or
through the input buffer. The delta-sigma modulator performs the
actual analog to digital conversion. The modulator over-samples
the input and generates a serial data stream output. This high
speed data stream is not useful for most applications without
some type of post processing, and so is passed to the decimator
through the Analog Interface block. The decimator converts the
high speed serial data stream into parallel ADC results. The
Document Number: 001-66235 Rev. *A
The ADC can be configured by the user to operate in one of four
modes: Single Sample, Multi Sample, Continuos, or Multi
Sample (Turbo). All four modes are started by either a write to
the start bit in a control register or an assertion of the Start of
Conversion (SoC) signal. When the conversion is complete, a
status bit is set and the output signal End of Conversion (EoC)
asserts high and remains high until the value is read by either the
DMA controller or the CPU.
8.2.2.1 Single Sample
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
first three conversions prime the decimator. The ADC result is
valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status. When the transfer
is done the ADC reenters the standby state where it stays until
another SoC event.
Page 48 of 114
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PRELIMINARY
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
Figure 8-6. SAR ADC Block Diagram
vin
vrefp
vrefn
S/H
DAC
array
D0:D11
8.2.2.2 Continuous
PSoC® 5: CY8C55 Family Datasheet
comparator
SAR
digital
D0:D11
autozero
reset
clock
8.2.2.3 Multi Sample
clock
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
The input is connected to the analog globals and muxes. The
frequency of the clock is 16 times the sample rate; the maximum
clock rate is 16 MHz.
8.2.2.4 Multi Sample (Turbo)
8.3.2 Conversion Signals
The multi sample (turbo) mode operates identical to the
Multi-sample mode for resolutions of 8 to 16 bits. For resolutions
of 17 to 20 bits, the performance is about four times faster than
the multi sample mode, because the ADC is only reset once at
the end of conversion.
Writing a start bit or assertion of a start of frame (SOF) signal is
used to start a conversion. SOF can be used in applications
where the sampling period is longer than the conversion time, or
when the ADC needs to be synchronized to other hardware. This
signal is optional and does not need to be connected if the SAR
ADC is running in a continuous mode. A digital clock or UDB
output can be used to drive this input. When the SAR is first
powered up or awakened from any of the sleeping modes, there
is a power up wait time of 10 µs before it is ready to start the first
conversion.
More information on output formats is provided in the Technical
Reference Manual.
8.2.3 Start of Conversion Input
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
POWER
GROUND
power
filtering
vrefp
vrefn
When the conversion is complete, a status bit is set and the
output signal end of frame (EOF) asserts and remains asserted
until the value is read by either the DMA controller or the CPU.
The EOF signal may be used to trigger an interrupt or a DMA
request.
8.3.3 Operational Modes
8.3 Successive Approximation ADC
The CY8C55 family of devices has two Successive
Approximation (SAR) ADCs. These ADCs are 12-bit at up to 1
Msps, with single-ended or differential inputs, making them
useful for a wide variety of sampling and control applications.
8.3.1 Functional Description
In a SAR ADC an analog input signal is sampled and compared
with the output of a DAC. A binary search algorithm is applied to
the DAC and used to determine the output bits in succession
from MSB to LSB. A block diagram of one SAR ADC is shown in
Figure 8-6.
Document Number: 001-66235 Rev. *A
A ONE_SHOT control bit is used to set the SAR ADC conversion
mode to either continuous or one conversion per SOF signal.
DMA transfer of continuous samples, without CPU intervention,
is supported.
8.4 Comparators
The CY8C55 family of devices contains four comparators.
Comparators have these features:
■ Input offset factory trimmed to less than 5 mV
■ Rail-to-rail common mode input range (VSSA to VCCA)
■ Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low power
■ Comparator outputs can be routed to look up tables to perform
simple logic functions and can also be routed to digital blocks
■ The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
■ Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
Page 49 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
8.4.1 Input and Output Interface
The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus
and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The
output of that LUT is routed to the UDB DSI.
Figure 8-7. Analog Comparator
From
Analog
Routing
From
Analog
Routing
ANAIF
+
comp0
_
+
comp1
_
+
_
comp3
+
_
From
Analog
Routing
From
Analog
Routing
comp2
4
4
LUT0
4
4
4
LUT1
4
LUT2
4
4
LUT3
UDBs
8.4.2 LUT
The CY8C55 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-2.
Document Number: 001-66235 Rev. *A
Table 8-2. LUT Function vs. Program Word and Inputs
Control Word
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Output (A and B are LUT inputs)
FALSE (‘0’)
A AND B
A AND (NOT B)
A
(NOT A) AND B
B
A XOR B
A OR B
A NOR B
A XNOR B
NOT B
A OR (NOT B)
NOT A
(NOT A) OR B
A NAND B
TRUE (‘1’)
Page 50 of 114
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PRELIMINARY
8.5 Opamps
The CY8C55 family of devices contain four general purpose
opamps.
Figure 8-8. Opamp
GPIO
PSoC® 5: CY8C55 Family Datasheet
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
8.6 Programmable SC/CT Blocks
Analog
Global Bus
Opamp
Analog
Global Bus
VREF
Analog
Internal Bus
GPIO
=
Analog Switch
GPIO
The opamp is uncommitted and can be configured as a gain
stage or voltage follower on external or internal signals.
See Figure 8-9. In any configuration, the input and output signals
can all be connected to the internal global signals and monitored
with an ADC, or comparator. The configurations are
implemented with switches between the signals and GPIO pins.
Figure 8-9. Opamp Configurations
Vout to Pin
Vin
b) External Uncommitted
Opamp
Opamp
Switched capacitor is a circuit design technique that uses
capacitors plus switches instead of resistors to create analog
functions. These circuits work by moving charge between
capacitors by opening and closing different switches.
Nonoverlapping in phase clock signals control the switches, so
that not all switches are ON simultaneously.
The PSoC Creator tool offers a user friendly interface, which
allows you to easily program the SC/CT blocks. Switch control
and clock phase control configuration is done by PSoC Creator
so users only need to determine the application use parameters
such as gain, amplifier polarity, VREF connection, and so on.
The same opamps and block interfaces are also connectable to
an array of resistors which allows the construction of a variety of
continuous time functions.
a) Voltage Follower
Opamp
The CY8C55 family of devices contains four switched
capacitor/continuous time (SC/CT) blocks. Each switched
capacitor/continuous time block is built around a single rail-to-rail
high bandwidth opamp.
Vout to GPIO
Vp to GPIO
Vn to GPIO
c) Internal Uncommitted
Opamp
The opamp and resistor array is programmable to perform
various analog functions including
■
Naked Operational Amplifier - Continuous Mode
■
Unity-Gain Buffer - Continuous Mode
■
Programmable Gain Amplifier (PGA) - Continuous Mode
■
Transimpedance Amplifier (TIA) - Continuous Mode
■
Up/Down Mixer - Continuous Mode
■
Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode
■
First Order Analog to Digital Modulator - Switched Cap Mode
8.6.1 Naked Opamp
The Naked Opamp presents both inputs and the output for
connection to internal or external signals. The opamp has a unity
gain bandwidth greater than 6.0 MHz and output drive current up
to 650 µA. This is sufficient for buffering internal signals (such as
DAC outputs) and driving external loads greater than 7.5 kohms.
Vn
To Internal Signals
8.6.2 Unity Gain
Opamp
Vout to Pin
Vp
GPIO Pin
Document Number: 001-66235 Rev. *A
The Unity Gain buffer is a Naked Opamp with the output directly
connected to the inverting input for a gain of 1.00. It has a -3 dB
bandwidth greater than 6.0 MHz.
Page 51 of 114
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PRELIMINARY
8.6.3 PGA
Figure 8-11. Continuous Time TIA Schematic
The PGA amplifies an external or internal signal. The PGA can
be configured to operate in inverting mode or noninverting mode.
The PGA function may be configured for both positive and
negative gains as high as 50 and 49 respectively. The gain is
adjusted by changing the values of R1 and R2 as illustrated in
Figure 8-10. The schematic in Figure 8-10 shows the
configuration and possible resistor settings for the PGA. The
gain is switched from inverting and non inverting by changing the
shared select value of the both the input muxes. The bandwidth
for each gain case is listed in Table 8-3.
Gain
1
24
48
50
Bandwidth
6.0 MHz
340 kHz
220 kHz
215 kHz
Vref
1
R1
20 k or 40 k
R2
20 k to 980 k
S
Vref
0
Vin
1
The PGA is used in applications where the input signal may not
be large enough to achieve the desired resolution in the ADC, or
dynamic range of another SC/CT block such as a mixer. The gain
is adjustable at runtime, including changing the gain of the PGA
prior to each ADC sample.
8.6.4 TIA
The Transimpedance Amplifier (TIA) converts an internal or
external current to an output voltage. The TIA uses an internal
feedback resistor in a continuous time configuration to convert
input current to output voltage. For an input current Iin, the output
voltage is VREF - Iin x Rfb, where VREF is the value placed on the
non inverting input. The feedback resistor Rfb is programmable
between 20 KΩ and 1 MΩ through a configuration register.
Table 8-4 shows the possible values of Rfb and associated
configuration settings.
Table 8-4. Feedback Resistor Settings
Configuration Word
000b
001b
010b
011b
100b
101b
110b
111b
Document Number: 001-66235 Rev. *A
I in
V ref
V out
8.7 LCD Direct Drive
Figure 8-10. PGA Resistor Settings
0
R fb
The TIA configuration is used for applications where an external
sensor's output is current as a function of some type of stimulus
such as temperature, light, magnetic flux etc. In a common
application, the voltage DAC output can be connected to the
VREF TIA input to allow calibration of the external sensor bias
current by adjusting the voltage DAC output voltage.
Table 8-3. Bandwidth
Vin
PSoC® 5: CY8C55 Family Datasheet
Nominal Rfb (KΩ)
20
30
40
60
120
250
500
1000
The PSoC Liquid Crystal Display (LCD) driver system is a highly
configurable peripheral designed to allow PSoC to directly drive
a broad range of LCD glass. All voltages are generated on chip,
eliminating the need for external components. With a high
multiplex ratio of up to 1/16, the CY8C55 family LCD driver
system can drive a maximum of 736 segments. The PSoC LCD
driver module was also designed with the conservative power
budget of portable devices in mind, enabling different LCD drive
modes and power down modes to conserve power.
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
Key features of the PSoC LCD segment system are:
■ LCD panel direct driving
■ Type A (standard) and Type B (low power) waveform support
■ Wide operating voltage range support (2 V to 5 V) for LCD
panels
■ Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
■ Internal bias voltage generation through internal resistor ladder
■ Up to 62 total common and segment outputs
■ Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
■ Up to 62 front plane/segment outputs for direct drive
■ Drives up to 736 total segments (16 backplane x 46 front plane)
■ Up to 64 levels of software controlled contrast
■ Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
■ Adjustable LCD refresh rate from 10 Hz to 150 Hz
■ Ability to invert LCD display for negative image
■ Three LCD driver drive modes, allowing power optimization
■ LCD driver configurable to be active when PSoC is in limited
active mode
Page 52 of 114
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PRELIMINARY
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
Figure 8-12. LCD System
LCD
DAC
Global
Clock
PSoC® 5: CY8C55 Family Datasheet
8.8 CapSense
UDB
LCD Driver
Block
DMA
PIN
Display
RAM
PHUB
8.7.1 LCD Segment Pin Driver
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.7.2 Display Data Flow
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense. Specific
resource usage is detailed in the CapSense component in PSoC
Creator.
A capacitive sensing method using a Delta-Sigma Modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
8.9 Temp Sensor
Die temperature is used to establish programming parameters
for writing flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
8.10 DAC
The CY8C55 parts contain four Digital to Analog Convertors
(DACs). Each DAC is 8-bit and can be configured for either
voltage or current output. The DACs support CapSense, power
supply regulation, and waveform generation. Each DAC has the
following features.
■
Adjustable voltage or current output in 255 steps
■
Programmable step size (range selection)
8.7.3 UDB and LCD Segment Control
■
Eight bits of calibration to correct ± 25% of gain error
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
■
Source and sink option for current output
■
8 Msps conversion rate for current output
■
1 Msps conversion rate for voltage output
■
Monotonic in nature
8.7.4 LCD DAC
■
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
Data and strobe inputs can be provided by the CPU or DMA,
or routed directly from the DSI
■
Dedicated low-resistance output pin for high-current mode
Document Number: 001-66235 Rev. *A
Page 53 of 114
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PRELIMINARY
PSoC® 5: CY8C55 Family Datasheet
Figure 8-13. DAC Block Diagram
I source Range 1x , 8x , 64x
Reference Source Vout Scaler R Iout 3R I sink Range 1x , 8x , 64x 8.10.1 Current DAC
8.12 Sample and Hold
The current DAC (IDAC) can be configured for the ranges 0 to
32 µA, 0 to 256 µA, and 0 to 2.04 mA. The IDAC can be
configured to source or sink current.
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some
applications require multiple signals to be sampled
simultaneously, such as for power calculations (V and I).
8.10.2 Voltage DAC
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.024 V and 0 to 4.096 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
Figure 8-15. Sample and Hold Topology
(Φ1 and Φ2 are opposite phases of a clock)
Φ1
Vi
C1
C2
Φ1
V ref
n
Φ1
Φ2
V out
Φ2
Φ2
8.11 Up/Down Mixer
In continuous time mode, the SC/CT block components are used
to build an up or down mixer. Any mixing application contains an
input signal frequency and a local oscillator frequency. The
polarity of the clock, Fclk, switches the amplifier between
inverting or noninverting gain. The output is the product of the
input and the switching function from the local oscillator, with
frequency components at the local oscillator plus and minus the
signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level
frequency components at odd integer multiples of the local
oscillator frequency. The local oscillator frequency is provided by
the selected clock source for the mixer.
Continuous time up and down mixing works for applications with
input signals and local oscillator frequencies up to 1 MHz.
Figure 8-14. Mixer Configuration
Φ1
Φ2
Φ1
Φ1
V ref
Φ2
C3
C4
Φ2
Vref
8.12.1 Down Mixer
The S+H can be used as a mixer to down convert an input signal.
This circuit is a high bandwidth passive sample network that can
sample input signals up to 14 MHz. This sampled value is then
held using the opamp with a maximum clock rate of 4 MHz. The
output frequency is at the difference between the input frequency
and the highest integer multiple of the Local Oscillator that is less
than the input.
C2 = 1.7 pF
8.12.2 First Order Modulator - SC Mode
C1 = 850 fF
Rmix 0 20 k or 40 k
sc_clk
Rmix 0 20 k or 40 k
Vin
0
Vref
1
sc_clk
Document Number: 001-66235 Rev. *A
Vout
A first order modulator is constructed by placing the switched
capacitor block in an integrator mode and using a comparator to
provide a 1-bit feedback to the input. Depending on this bit, a
reference voltage is either subtracted or added to the input
signal. The block output is the output of the comparator and not
the integrator in the modulator case. The signal is downshifted
and buffered and then processed by a decimator to make a
delta-sigma converter or a counter to make an incremental
converter. The accuracy of the sampled data from the first-order
modulator is determined from several factors. The main
application for this modulator is for a low frequency ADC with
high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement.
Page 54 of 114
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PRELIMINARY
9. Programming, Debug Interfaces,
Resources
The Cortex-M3 has internal debugging components, tightly
integrated with the CPU, providing the following features:
■ SWD access
■ Flash Patch and Breakpoint (FPB) block for implementing
breakpoints and code patches
■ Data Watchpoint and Trigger (DWT) block for implementing
watchpoints, trigger resources, and system profiling
■ Instrumentation Trace Macrocell (ITM) for support of printf-style
debugging
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
SWD supports all programming and debug features of the
device. The SWV provides trace output from the DWT and ITM.
For more information on PSoC 5 programming, refer to the
application note AN64359 - In-System Programming for
PSoC® 5.
Cortex-M3 debug and trace functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC interfaces are fully compatible
with industry standard third party tools.
All Cortex-M3 debug and trace modules are disabled by default
and can only be enabled in firmware. If not enabled, the only way
to reenable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables them. Disabling debug and trace features, robust flash
protection, and hiding custom analog and digital functionality
Document Number: 001-66235 Rev. *A
PSoC® 5: CY8C55 Family Datasheet
inside the PSoC device provide a level of security not possible
with multichip application solutions. Additionally, all device
interfaces can be permanently disabled (Device Security) for
applications concerned about phishing attacks due to a
maliciously reprogrammed device. Permanently disabling
interfaces is not recommended in most applications because the
designer then cannot access the device. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
9.1 Debug Port Acquisition
Prior to programming or debugging, the debug port must be
acquired. There is a time window after reset within which the Port
Acquire must be completed. This window is initially 8 µs; if eight
clocks are detected on the SWDCK line within the 8 µs period,
the time window will then be extended to 400 µs to complete the
port acquire operation. The port acquire key must be transmitted
over one of the two SWD pin pairs; see the SWD Interface
section. For a detailed description of the acquire key sequence,
refer to the Technical Reference Manual.
9.2 SWD Interface
SWD uses two pins, either two port 1 pins or the USBIO D+ and
D- pins. The USBIO pins are useful for in system programming
of USB solutions that would otherwise require a separate
programming connector. One pin is used for the data clock and
the other is used for data input and output. SWD can be enabled
on only one of the pin pairs at a time. SWD is used for debugging
or for programming the flash memory. In addition, the SWD
interface supports the SWV trace output. The SWD interface
also includes the SWV interface, see SWV Interface on page 57.
When using the SWD/SWV pins as standard GPIO, make sure
that the GPIO functionality and PCB circuits do not interfere with
SWD/SWV use. The SWV trace output is automatically activated
whenever the SWD is activated.
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PSoC® 5: CY8C55 Family Datasheet
Figure 9-1. SWD Interface Connections between PSoC 5 and Programmer
VDD
Host Programmer
PSoC 5
VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3
VDD
SWDCK (P1[1] or P15[7]) 4
SWDCK
SWDIO
SWDIO (P1[0] or P15[6])
XRES
XRES
GND
GND
VSSD, VSSA
1
The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in programming should be
the same. XRES pin is powered by VDDIO1. The USB SWD pins are powered by VDDD. So for
programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1 of PSoC 5 should be at the same voltage
level as Host VDD. Rest of PSoC 5 voltage domains (VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage
level as host Programmer. The Port 1 SWD pins are powered by VDDIO1. So VDDIO1 of PSoC 5 should be at same
voltage level as host VDD for Port 1 SWD programming. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.
3
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require
external interface circuitry to toggle power which will depend on the programming setup. The power
supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or
equal to all other supplies.
4
When USB SWD pins are used for Programming, the P1[1] SWDCK pin must be externally connected to Ground
using external pull-down resistor (around 100 K resistor). This is required for P15[7] SWDCK signal to be seen by
PSoC 5's internal logic.
Document Number: 001-66235 Rev. *A
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9.3 Debug Features
The CY8C55 supports the following debug features:
■ Halt and single-step the CPU
■ View and change CPU and peripheral registers, and RAM
addresses
■ Six program address breakpoints and two literal access
breakpoints
■ Data watchpoint events to CPU
■ Patch and remap instruction from flash to SRAM
■ Debugging at the full speed of the CPU
■ Compatible with PSoC Creator and MiniProg3 programmer and
debugger
9.4 Trace Features
The following trace features are supported:
■ Data watchpoint on access to data address, address range, or
data value
■ Software event monitoring, “printf-style” debugging
9.5 SWV Interface
The SWV interface provides trace data to a debug host via the
Cypress MiniProg3 or an external trace port analyzer.
9.6 Programming Features
The SWD interface provides full programming support. The
entire device can be erased, programmed, and verified.
Designers can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 5 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0x50536F43) to a Write Once Latch (WOL). The WOL must be
programmed at VDDD ≤ 3.3 V.
The WOL is a type of nonvolatile latch (NVL). The cell itself is an
NVL with additional logic wrapped around it. Each WOL device
contains four bytes (32 bits) of data. The wrapper outputs a ‘1’ if
a super-majority (28 of 32) of its bits match a pre-determined
pattern (0x50536F43); it outputs a ‘0’ if this majority is not
Document Number: 001-66235 Rev. *A
PSoC® 5: CY8C55 Family Datasheet
reached. When the output is 1, the Write Once NV latch locks the
part out of Debug and Test modes; it also permanently gates off
the ability to erase or alter the contents of the latch. Matching all
bits is intentionally not required, so that single (or few) bit failures
do not deassert the WOL output. The state of the NVL bits after
wafer processing is truly random with no tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0x50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
The user can write the key into the WOL to lock out external
access only if no flash protection is set (see “Flash Security”
section on page 16). However, after setting the values in the
WOL, a user still has access to the part until it is reset. Therefore,
a user can write the key into the WOL, program the flash
protection data, and then reset the part to lock it.
If the device is protected with a WOL setting, Cypress cannot
perform failure analysis and, therefore, cannot accept RMAs
from customers. The WOL can be read out via SWD port to
electrically identify protected parts. The user can write the key in
WOL to lock out external access only if no flash protection is set.
For more information on how to take full advantage of the
security features in PSoC see the PSoC 5 TRM.
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
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10. Development Support
PSoC® 5: CY8C55 Family Datasheet
The CY8C55 family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit
psoc.cypress.com/getting-started to find out more.
Technical Reference Manual: PSoC Creator makes designing
with PSoC as easy as dragging a peripheral onto a schematic,
but, when low level details of the PSoC device are required, use
the technical reference manual (TRM) as your guide.
Note Visit www.arm.com for detailed documentation about the
Cortex-M3 CPU.
10.1 Documentation
10.2 Online
A suite of documentation, to ensure that you can find answers to
your questions quickly, supports the CY8C55 family. This section
contains a list of some of the key documents.
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
10.3 Tools
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component datasheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
With industry standard cores, programming, and debugging
interfaces, the CY8C55 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 001-66235 Rev. *A
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11. Electrical Specifications
Specifications are valid for -40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator
components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example Peripherals”
section on page 32 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Recommended storage temperature is +25 °C ±25 °C. Extended
duration storage temperatures
above 85 °C degrade reliability.
–55
25
100
°C
Analog supply voltage relative to
VSSA
–0.5
–
6
V
VDDD
Digital supply voltage relative to
VSSD
–0.5
–
6
V
VDDIO
I/O supply voltage relative to VSSD
–0.5
–
6
V
VCCA
Direct analog core voltage input
–0.5
–
1.95
V
VCCD
Direct digital core voltage input
VSSA
Analog ground voltage
VGPIO[11]
DC input voltage on GPIO
VSIO
DC input voltage on SIO
TSTG
Storage temperature
VDDA
VIND
Voltage at boost converter input
VBAT
Boost converter supply
Ivddio
Current per VDDIO supply pin
Vextref
ADC external reference inputs
–0.5
–
1.95
V
VSSD – 0.5
–
VSSD +
0.5
V
Includes signals sourced by VDDA
and routed internal to the pin.
VSSD – 0.5
–
VDDIO +
0.5
V
Output disabled
VSSD – 0.5
–
7
V
Output enabled
VSSD – 0.5
–
6
V
Pins P0[3], P3[2]
current[12]
0.5
–
5.5
V
VSSD – 0.5
–
5.5
V
–
–
20
mA
–
–
2
V
LU
Latch up
–140
–
140
mA
ESDHBM
Electrostatic discharge voltage
Human body model
500
–
–
V
ESDCDM
ESD voltage
Charge device model
500
–
–
V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Notes
11. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ VDDIO ≤ VDDA.
12. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
Document Number: 001-66235 Rev. *A
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11.2 Device Level Specifications
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Parameter
Description
VDDA
Analog supply voltage and input to analog core
regulator
VDDA
Analog supply voltage, analog regulator bypassed
VDDD
Digital supply voltage relative to VSSD
Digital supply voltage, digital regulator bypassed
VDDD
[14]
VDDIO
I/O supply voltage relative to VSSIO
Direct analog core voltage input (Analog regulator
VCCA
bypass)
VCCD
Direct digital core voltage input (Digital regulator
bypass)
Active Mode, VDD = 2.7 V–5.5 V
IDD[15]
Execute from Flash cache, see Cache Controller
on page 11 and Flash Program Memory on page 16
Conditions
Analog core regulator enabled
Min
2.7
Typ
–
Max
5.5
Units
V
Analog core regulator disabled
Digital core regulator enabled
Digital core regulator disabled
Analog core regulator disabled
1.71
2.7
1.71
2.7
1.71
1.8
–
1.8
–
1.8
1.89
VDDA[13]
1.89
VDDA[13]
1.89
V
V
V
V
V
Digital core regulator disabled
1.71
1.8
1.89
V
T = –40 °C
T = 25 °C
T = 85 °C
–
–
–
–
5
–
–
–
–
mA
mA
mA
T = –40 °C
T = 25 °C
T = 85 °C
–
–
–
–
–
–
–
–
–
µA
µA
µA
T = –40 °C
T = 25 °C
T = 85 °C
–
–
–
–
3
–
–
–
–
µA
µA
µA
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
–
–
–
–
–
–
–
–
–
–
1000
–
–
–
–
–
–
–
nA
nA
nA
nA
nA
nA
CPU at 6 MHz
Sleep Mode[16]
CPU = OFF
VDD = VDDIO = 4.5–5.5 V
RTC = ON (= ECO32K ON, in low power mode)
Sleep timer = ON (= ILO ON at 1 kHz)
WDT = OFF
POR = ON
VDD = VDDIO = 2.7–3.6 V
Boost = OFF
SIO pins in single ended input, unregulated output
mode
Hibernate Mode
VDD = VDDIO = 4.5–5.5 V
Hibernate mode current
All regulators and oscillators off.
SRAM retention
GPIO interrupts are active
VDD = VDDIO = 2.7–3.6 V
Boost = OFF
SIO pins in single ended input, unregulated output
mode
Notes
13. The power supplies can be brought up in any sequence however once stable Vdda must be greater than or equal to all other supplies.
14. The VDDIO supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ VDDIO ≤ VDDA.
15. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device data sheet and component datasheets.
16. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
Document Number: 001-66235 Rev. *A
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Table 11-3. AC Specifications[17]
Parameter
Description
Conditions
Min
Typ
Max
Units
FCPU
CPU frequency
DC
–
67.01
MHz
FBUSCLK
Bus frequency
DC
–
67.01
MHz
Svdd
VDD ramp rate
–
–
1
V/ns
TIO_INIT
Time from VDDD/VDDA/VCCD/VCCA
≥ IPOR to I/O ports set to their reset
states
–
–
10
µs
TSTARTUP
Time from VDDD/VDDA/VCCD/VCCA No PLL used, IMO boot mode 12 MHz typ.
≥ min operating voltage to CPU
executing code at reset vector
–
–
66
µs
TSLEEP
Wakeup from limited active mode –
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
–
20
–
µs
THIBERNATE Wakeup form hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
–
–
100
µs
Note
17. Based on device characterization (Not production tested).
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
11.3 Power Regulators
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted.
11.3.1 Digital Core Regulator
Table 11-4. Digital Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDD
Output voltage
VCCD
Regulator output capacitor
Figure 11-1. Regulators VCC vs VDD
Document Number: 001-66235 Rev. *A
Conditions
±10%, X5R ceramic or better. The two VCCD
pins must be shorted together, with as short
a trace as possible, see 6.2 Power System
on page 21
Min
2.7
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Figure 11-2. Digital Regulator PSRR vs Frequency and VDD
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11.3.2 Analog Core Regulator
Table 11-5. Analog Core Regulator DC Specifications
Parameter
Description
VDDA
Input voltage
VCCA
Output voltage
Regulator output capacitor
Conditions
±10%, X5R ceramic or better
Min
2.7
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Figure 11-3. Analog Regulator PSRR vs Frequency and VDD
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PSoC® 5: CY8C55 Family Datasheet
11.3.3 Inductive Boost Regulator.
Table 11-6. Inductive Boost Regulator DC Specifications
Unless otherwise specified, operating conditions are: VBAT = 2.4 V, VOUT = 3.3 V, IOUT = 40 mA, FSW = 400 kHz, LBOOST = 10 µH,
CBOOST = 22 µF || 0.1 µF
Parameter
Description
Min
Typ
Max
Units
1.8
–
3.6
V
VBAT = 1.8 – 3.6 V, VOUT = 3.6 – 5.0 V,
external diode
–
–
50
mA
VBAT = 1.8 – 3.6 V, VOUT = 2.7 – 3.6 V,
internal diode
–
–
75
mA
–
–
700
mA
Boost active mode
–
200
–
µA
Boost standby mode, 32 khz external crystal
oscillator, IOUT < 1 µA
–
12
–
µA
3.0 V
2.85
3.00
3.15
V
3.3 V
3.14
3.30
3.47
V
VBAT
Input voltage
Includes startup
IOUT
Load current[18, 19]
ILPK
Inductor peak current
IQ
Quiescent current
VOUT
Conditions
Boost voltage range[20, 21]
3.6 V
5.0 V
External diode required
3.42
3.60
3.78
V
4.75
5.00
5.25
V
RegLOAD
Load regulation
–
–
3.8
%
RegLINE
Line regulation
–
–
4.1
%
η
Efficiency
LBOOST = 10 µH
70
85
–
%
LBOOST = 22 µH
82
90
–
%
Table 11-7. Inductive Boost Regulator AC Specifications
Unless otherwise specified, operating conditions are: VBAT = 2.4 V, VOUT = 3.3 V, IOUT = 40 mA, FSW = 400 kHz, LBOOST = 10 µH,
CBOOST = 22 µF || 0.1 µF.
Parameter
Description
VRIPPLE
Ripple voltage
(peak-to-peak)
FSW
Switching frequency
Conditions
FSW = 400 kHz, IOUT = 10 mA
Min
Typ
Max
Units
–
–
100
mV
–
0.1, 0.4,
or 2
–
MHz
Notes
18. For output voltages above 3.6 V, an external diode is required.
19. Maximum output current applies for output voltages ≤ 4x input voltage.
20. Based on device characterization (Not production tested).
21. At boost frequency of 2 MHz, VOUT is limited to 2 x VBAT. At 400 kHz,VOUT is limited to 4 x VBAT.
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PSoC® 5: CY8C55 Family Datasheet
Table 11-8. Recommended External Components for Boost Circuit
Parameter
LBOOST
Description
Conditions
Boost inductor
capacitor[22]
CBOOST
Filter
IF
External Schottky diode
average forward current
External Schottky diode is required for
VOUT > 3.6 V
VR
Min
Typ
Max
Units
4.7
10
47
µH
10
22
47
µF
1
–
–
A
20
–
–
V
11.4 Inputs and Outputs
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted. Unless otherwise specified, all charts and graphs show typical values.
11.4.1 GPIO
Table 11-9. GPIO DC Specifications
Parameter
Description
VIH
Input voltage high threshold
VIL
Input voltage low threshold
Conditions
CMOS Input, PRT[x]CTL = 0
CMOS Input, PRT[x]CTL = 0
Min
0.7 × VDDIO
–
Typ
–
–
Max
–
0.3 ×
VDDIO
Units
V
V
VIH
LVTTL Input, PRT[x]CTL = 1
LVTTL Input, PRT[x]CTL = 1
IOH = 4 mA at 3.3 VDDIO
IOL = 8 mA at 3.3 VDDIO
2.0
–
VDDIO – 0.6
–
3.5
3.5
–
–
–
–
–
5.6
5.6
–
–
0.8
–
0.6
8.5
8.5
2
V
V
V
V
kΩ
kΩ
nA
–
–
–
–
–
40
7
18
–
pF
pF
mV
–
–
100
µA
–
–
320
220
–
–
Ω
Ω
Input voltage high threshold
VIL
Input voltage low threshold
VOH
Output voltage high
VOL
Output voltage low
Rpullup
Pull-up resistor
Rpulldown Pull-down resistor
IIL
Input leakage current (absolute
value)[22]
CIN
Input capacitance[22]
VH
Idiode
25 °C, VDDIO = 3.0 V
GPIOs without opamp outputs
GPIOs with opamp outputs
Input voltage hysteresis
(Schmitt-Trigger)[22]
Current through protection diode
to VDDIO and VSSIO
Rglobal
Resistance pin to analog global bus 25 °C, VDDIO = 3.0 V
Rmux
Resistance pin to analog mux bus 25 °C, VDDIO = 3.0 V
Note
22. Based on device characterization (Not production tested).
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Figure 11-4. GPIO Output High Voltage and Current
PSoC® 5: CY8C55 Family Datasheet
Figure 11-5. GPIO Output Low Voltage and Current
Table 11-10. GPIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Fgpioout
Fgpioin
Description
Rise time in Fast Strong Mode[23]
Fall time in Fast Strong Mode[23]
Rise time in Slow Strong Mode[23]
Fall time in Slow Strong Mode[23]
GPIO output operating frequency
Fast strong drive mode
3.3 V < VDDIO < 5.5 V, slow strong drive mode
2.7 V < VDDIO < 3.3 V, slow strong drive mode
GPIO input operating frequency
2.7 V < VDDIO < 5.5 V
Conditions
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
Min
–
–
–
–
Typ
–
–
–
–
Max
12
12
60
60
Units
ns
ns
ns
ns
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
–
–
–
–
–
–
33
7
3.5
MHz
MHz
MHz
90/10% VDDIO
–
–
66
MHz
Figure 11-6. GPIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-7. GPIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Note
23. Based on device characterization (Not production tested).
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11.4.2 SIO
Table 11-11. SIO DC Specifications
Parameter
Vinmax
Description
Maximum input voltage
Vinref
Input voltage reference (differential
0.5
input mode)
Output voltage reference (regulated output mode)
VDDIO > 3.7
1
1
VDDIO < 3.7
Input voltage high threshold
GPIO mode
CMOS input
0.7 × VDDIO
Hysteresis disabled
SIO_ref + 0.2
Differential input mode[24]
Input voltage low threshold
GPIO mode
CMOS input
–
Hysteresis disabled
–
Differential input mode[24]
Output voltage high
Unregulated mode
IOH = 4 mA, VDDIO = 3.3 V
VDDIO – 0.4
IOH = 1 mA
SIO_ref – 0.65
Regulated mode[24]
Regulated mode[24]
IOH = 0.1 mA
SIO_ref – 0.3
Output voltage low
VDDIO = 3.30 V, IOL = 25 mA
–
Pull-up resistor
3.5
Pull-down resistor
3.5
Input leakage current (absolute
value)[25]
VIH < Vddsio
25 °C, Vddsio = 3.0 V, VIH = 3.0 V
–
VIH > Vddsio
25 °C, Vddsio = 0 V, VIH = 3.0 V
–
Input Capacitance[25]
–
Input voltage hysteresis
Single ended mode (GPIO mode)
–
(Schmitt-Trigger)[25]
Differential mode
–
Current through protection diode to
–
VSSIO
Voutref
VIH
VIL
VOH
VOL
Rpullup
Rpulldown
IIL
CIN
VH
Idiode
Conditions
All allowed values of Vddio and
Vddd, see Section 11.2.1
Min
–
Typ
–
Max
5.5
Units
V
–
0.52 × VDDIO
V
–
–
VDDIO – 1
VDDIO – 0.5
V
V
–
–
–
–
V
V
–
–
0.3 × VDDIO
SIO_ref – 0.2
V
V
–
–
–
–
5.6
5.6
–
SIO_ref + 0.2
SIO_ref + 0.2
0.8
8.5
8.5
V
V
V
V
kΩ
kΩ
–
–
–
40
35
–
14
10
7
–
–
100
nA
µA
pF
mV
mV
µA
Notes
24. See Figure 6-9 on page 28 and Figure 6-12 on page 31 for more information on SIO reference.
25. Based on device characterization (Not production tested).
Document Number: 001-66235 Rev. *A
Page 67 of 114
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Figure 11-8. SIO Output High Voltage and Current,
Unregulated Mode
PSoC® 5: CY8C55 Family Datasheet
Figure 11-9. SIO Output Low Voltage and Current,
Unregulated Mode
Figure 11-10. SIO Output High Voltage and Current, Regulated Mode
Table 11-12. SIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Description
Rise time in fast strong mode
(90/10%)[26]
Fall time in fast strong mode
(90/10%)[26]
Rise time in slow strong mode
(90/10%)[26]
Fall time in slow strong mode
(90/10%)[26]
Conditions
Cload = 25 pF, VDDIO = 3.3 V
Min
–
Typ
–
Max
12
Units
ns
Cload = 25 pF, VDDIO = 3.3 V
–
–
12
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
75
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
60
ns
Note
26. Based on device characterization (Not production tested).
Document Number: 001-66235 Rev. *A
Page 68 of 114
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Table 11-12. SIO AC Specifications (continued)
Parameter
Fsioout
Fsioin
Description
SIO output operating frequency
Unregulated output (GPIO)
mode, fast strong drive mode
3.3 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, slow
strong drive mode
2.7 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow
strong drive mode
Regulated output mode, fast
strong drive mode
Regulated output mode, slow
strong drive mode
SIO input operating frequency
Conditions
Min
Typ
Max
Units
90/10% VDDIO into 25 pF
–
–
33
MHz
90/10% VDDIO into 25 pF
–
–
5
MHz
90/10% VDDIO into 25 pF
–
–
4
MHz
Output continuously switching
into 25 pF
Output continuously switching
into 25 pF
90/10% VDDIO
–
–
20
MHz
–
–
2.5
MHz
–
–
66
MHz
Figure 11-11. SIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Document Number: 001-66235 Rev. *A
Figure 11-12. SIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Page 69 of 114
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PSoC® 5: CY8C55 Family Datasheet
11.4.3 USBIO
For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 60.
Table 11-13. USBIO DC Specifications
Min
Typ
Max
Units
Rusbi
Parameter
USB D+ pull-up resistance
Description
With idle bus
Conditions
0.900
–
1.575
kΩ
Rusba
USB D+ pull-up resistance
While receiving traffic
1.425
–
3.090
kΩ
Vohusb
Static output high
15 kΩ ±5% to Vss, internal pull-up
enabled
2.8
–
3.6
V
Volusb
Static output low
15 kΩ ±5% to Vss, internal pull-up
enabled
–
–
0.3
V
Vihgpio
Input voltage high, GPIO mode
VDDD ≥ 3 V
2
–
–
V
Vilgpio
Input voltage low, GPIO mode
VDDD ≥ 3 V
–
–
0.8
V
Vohgpio
Output voltage high, GPIO mode
IOH = 4 mA, VDDD ≥ 3 V
2.4
–
–
V
Volgpio
Output voltage low, GPIO mode
IOL = 4 mA, VDDD ≥ 3 V
–
–
0.3
V
Vdi
Differential input sensitivity
|(D+)–(D–)|
–
–
0.2
V
Vcm
Differential input common mode range
0.8
–
2.5
V
Vse
Single ended receiver threshold
0.8
–
2
V
Rps2
PS/2 pull-up resistance
In PS/2 mode, with PS/2 pull-up
enabled
3
–
7
kΩ
Rext
External USB series resistor
In series with each USB pin
21.78
(–1%)
22
22.22
(+1%)
Ω
Zo
USB driver output impedance
Including Rext
28
–
44
Ω
CIN
USB transceiver input capacitance
–
–
20
pF
IIL
Input leakage current (absolute value) 25 °C, VDDD = 3.0 V
–
–
2
nA
Figure 11-13. USBIO Output High Voltage and Current, GPIO
Mode
Document Number: 001-66235 Rev. *A
Figure 11-14. USBIO Output Low Voltage and Current, GPIO
Mode
Page 70 of 114
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PSoC® 5: CY8C55 Family Datasheet
Table 11-14. USBIO AC Specifications
Min
Typ
Max
Units
Tdrate
Parameter
Full-speed data rate average bit rate
Description
Conditions
12 – 0.25%
12
12 +
0.25%
MHz
Tjr1
Receiver data jitter tolerance to next
transition
–8
–
8
ns
Tjr2
Receiver data jitter tolerance to pair
transition
–5
–
5
ns
Tdj1
Driver differential jitter to next transition
–3.5
–
3.5
ns
Tdj2
Driver differential jitter to pair transition
–4
–
4
ns
Tfdeop
Source jitter for differential transition to
SE0 transition
–2
–
5
ns
Tfeopt
Source SE0 interval of EOP
160
–
175
ns
Tfeopr
Receiver SE0 interval of EOP
82
–
–
ns
Tfst
Width of SE0 interval during differential
transition
–
–
14
ns
Fgpio_out
GPIO mode output operating frequency 3 V ≤ VDDD ≤ 5.5 V
–
–
20
MHz
–
–
6
MHz
Tr_gpio
Rise time, GPIO mode, 10%/90% VDDD VDDD > 3 V, 25 pF load
–
–
12
ns
–
–
40
ns
Tf_gpio
Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load
–
–
12
ns
–
–
40
ns
Min
Typ
Max
Units
VDDD = 2.7 V
VDDD = 2.7 V, 25 pF load
VDDD = 2.7 V, 25 pF load
Figure 11-15. USBIO Output Rise and Fall Times, GPIO Mode,
VDDD = 3.3 V, 25 pF Load
Table 11-15. USB Driver AC Specifications
Parameter
Description
Conditions
Tr
Transition rise time
–
–
20
ns
Tf
Transition fall time
–
–
20
ns
TR
Rise/fall time matching
90%
–
111%
Vcrs
Output signal crossover voltage
1.3
–
2
Document Number: 001-66235 Rev. *A
VUSB_5, VUSB_3.3, see USB DC
Specifications on page 97
V
Page 71 of 114
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11.4.4 XRES
Table 11-16. XRES DC Specifications
Parameter
VIH
VIL
Rpullup
CIN
VH
Idiode
Description
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
Input capacitance[27]
Input voltage hysteresis
(Schmitt-Trigger)[27]
Current through protection diode to
VDDIO and VSSIO
Conditions
Min
0.7 × VDDIO
–
3.5
–
–
Typ
–
–
5.6
3
100
Max
Units
–
V
0.3 × VDDIO
V
8.5
kΩ
pF
–
mV
–
–
100
µA
Min
Typ
Max
Units
1
–
–
µs
Table 11-17. XRES AC Specifications
Parameter
TRESET
Description
Reset pulse width
Conditions
Note
27. Based on device characterization (Not production tested).
Document Number: 001-66235 Rev. *A
Page 72 of 114
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PSoC® 5: CY8C55 Family Datasheet
11.5 Analog Peripherals
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted.
11.5.1 Opamp
Table 11-18. Opamp DC Specifications
Parameter
Description
VIOFF
Input offset voltage
Vos
Conditions
Input offset voltage
Operating temperature –40 °C to
70 °C
Min
–
Typ
–
Max
2
Units
mV
–
–
2.5
mV
–
–
2
mV
TCVos
Input offset voltage drift with temperature Power mode = high
–
–
±30
µV / °C
Ge1
Gain error, unity gain buffer mode
Rload = 1 kΩ
–
–
±0.1
%
Cin
Input capacitance
Routing from pin
–
–
18
pF
Vo
Output voltage range
1 mA, source or sink, power mode = VSSA + 0.05
high
–
Iout
Output current, source or sink
VSSA + 500 mV ≤ Vout ≤ VDDA
–500 mV
–
Idd
Quiescent current
Power mode = min
–
200
270
uA
Power mode = low
–
250
400
uA
Power mode = med
–
330
950
uA
Power mode = high
–
1000
2500
uA
25
VDDA –
0.05
–
V
mA
CMRR
Common mode rejection ratio
80
–
–
dB
PSRR
Power supply rejection ratio
85
–
–
dB
Figure 11-16. Opamp Voffset Histogram, 3388 samples/847
parts, 25 °C, Vdda = 5 V
Figure 11-17. Opamp Voffset vs Temperature, Vdda = 5V
Note
28. Based on device characterization (Not production tested).
Document Number: 001-66235 Rev. *A
Page 73 of 114
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PRELIMINARY
Figure 11-18. Opamp Voffset vs Vcommon and
Vdda, 25 °C
PSoC® 5: CY8C55 Family Datasheet
Figure 11-19. Opamp Output Voltage vs Load Current and
Temperature, High Power Mode, 25 °C, Vdda = 2.7 V
Figure 11-20. Opamp Operating Current vs Vdda and Power
Mode
O
Table 11-19. Opamp AC Specifications
Parameter
Description
GBW
Gain-bandwidth product
SR
Slew rate, 20% - 80%
en
Input noise density
Document Number: 001-66235 Rev. *A
Conditions
Power mode = minimum, 200 pF
load
Power mode = low, 200 pF load
Power mode = medium, 200 pF load
Power mode = high, 200 pF load
Power mode = low, 200 pF load
Power mode = medium, 200 pF load
Power mode = high, 200 pF load
Power mode = high, Vdda = 5 V, at
100 kHz
Min
1
Typ
–
Max
–
Units
MHz
2
1
3
1.1
0.9
3
–
–
–
–
–
–
–
45
–
–
–
–
–
–
–
MHz
MHz
MHz
V/µs
V/µs
V/µs
nV/sqrtHz
Page 74 of 114
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PRELIMINARY
Figure 11-21. Opamp Noise vs Frequency, Power Mode =
High, Vdda = 5V
PSoC® 5: CY8C55 Family Datasheet
Figure 11-22. Opamp Step Response, Rising
Figure 11-23. Opamp Step Response, Falling
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
11.5.2 Delta-Sigma ADC
Unless otherwise specified, operating conditions are:
■
Operation in continuous sample mode
■
fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits
■
Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
■
Unless otherwise specified, all charts and graphs show typical values
Table 11-20. 20-bit Delta-sigma ADC DC Specifications
Parameter
Description
Conditions
Resolution
Number of channels, single ended
Number of channels, differential
Monotonic
Ge
Gain error
Gd
Gain drift
Vos
Input offset voltage
TCVos
PSRRb
CMRRb
INL20
DNL20
INL16
DNL16
INL12
DNL12
INL8
DNL8
Rin_Buff
Temperature coefficient, input offset
voltage
Input voltage range, single ended[29]
Input voltage range, differential unbuffered[29]
Input voltage range, differential,
buffered[29]
Differential pair is formed using a
pair of GPIOs.
Yes
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode, 25 °C
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode
Buffered, 16-bit mode, VDDA = 2.7 V,
25 °C
Buffer gain = 1, 16-bit,
Range = ±1.024 V
Buffer gain = 1, 16-bit,
Range = ±1.024 V
Buffer gain = 1, 16 bit,
Common mode rejection ratio, buffered[29]
Range = ±1.024 V
Range = ±1.024 V, unbuffered, using
Integral non linearity[29]
external clock source
Range = ±1.024 V, unbuffered, using
[29]
Differential non linearity
external clock source
Range = ±1.024 V, unbuffered, using
Integral non linearity[29]
external clock source
Range = ±1.024 V, unbuffered, using
[29]
Differential non linearity
external clock source
Range = ±1.024 V, unbuffered, using
[29]
Integral non linearity
external clock source
Range = ±1.024 V, unbuffered, using
Differential non linearity[29]
external clock source
Range = ±1.024 V, unbuffered, using
[29]
Integral non linearity
external clock source
Range = ±1.024 V, unbuffered, using
Differential non linearity[29]
external clock source
ADC input resistance
Input buffer used
Power supply rejection ratio, buffered[29]
Min
8
Typ
–
Units
bits
–
Max
20
No. of
GPIO
No. of
GPIO/2
–
–
–
–
–
–
–
–
±0.2
%
–
–
50
ppm/°
C
–
–
±0.5
mV
–
–
55
µV/°C
VSSA
–
VDDA
V
VSSA
–
VDDA
V
VSSA
–
VDDA – 1
V
90
–
–
dB
85
–
–
dB
–
–
±32
LSB
–
–
±1
LSB
–
–
±2
LSB
–
–
±1
LSB
–
–
±1
LSB
–
–
±1
LSB
–
–
±1
LSB
–
–
±1
LSB
10
–
–
MΩ
–
–
–
Notes
29. Based on device characterization (not production tested).
30. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional
to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
Document Number: 001-66235 Rev. *A
Page 76 of 114
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PSoC® 5: CY8C55 Family Datasheet
Table 11-20. 20-bit Delta-sigma ADC DC Specifications (continued)
Parameter
Description
Rin_ADC16 ADC input resistance
Rin_ADC12 ADC input resistance
ADC external reference input voltage, see
also internal reference in Voltage
Reference on page 80
Current Consumption
IDD_20
Current consumption, 20 bit[31]
IDD_16
Current consumption, 16 bit[31]
IDD_12
Current consumption, 12 bit[31]
IBUFF
Buffer current consumption[31]
Vextref
Conditions
Input buffer bypassed, 16-bit, Range
= ±1.024 V
Input buffer bypassed, 12 bit, Range
= ±1.024 V
Min
Typ
Max
Units
–
74[30]
–
kΩ
–
148[30]
–
kΩ
Pins P0[3], P3[2]
0.9
–
1.3
V
–
–
–
–
–
–
–
–
1.25
1.2
1.4
2.5
mA
mA
mA
mA
187 sps, unbuffered
48 ksps, unbuffered
192 ksps, unbuffered
Table 11-21. Delta-sigma ADC AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
–
–
4
Samples
–
–
0.0032
%
Range = ±1.024 V, unbuffered
7.8
–
187
sps
Range = ±1.024 V, unbuffered
–
40
–
Hz
Startup time
THD
Total harmonic distortion[31]
Buffer gain = 1, 16 bit,
Range = ±1.024 V
20-Bit Resolution Mode
SR20
BW20
Sample rate[31]
Input bandwidth at max sample
rate[31]
16-Bit Resolution Mode
SR16
Sample rate[31]
Range = ±1.024 V, unbuffered
2
–
48
ksps
BW16
Input bandwidth at max sample rate[31]
Range = ±1.024 V, unbuffered
–
11
–
kHz
SINAD16int
Signal to noise ratio, 16-bit, internal
reference[31]
Range = ±1.024V, unbuffered
81
–
–
dB
SINAD16ext Signal to noise ratio, 16-bit, external
reference[31]
Range = ±1.024 V, unbuffered
84
–
–
dB
Range = ±1.024 V, unbuffered
4
–
192
ksps
Range = ±1.024 V, unbuffered
–
44
–
kHz
Range = ±1.024 V, unbuffered
66
–
–
dB
12-Bit Resolution Mode
SR12
Sample rate, continuous, high power[31]
rate[31]
BW12
Input bandwidth at max sample
SINAD12int
Signal to noise ratio, 12-bit, internal
reference[31]
8-Bit Resolution Mode
SR8
Sample rate, continuous, high power[31]
Range = ±1.024 V, unbuffered
8
–
384
ksps
BW8
Input bandwidth at max sample rate[31]
Range = ±1.024 V, unbuffered
–
88
–
kHz
SINAD8int
Signal to noise ratio, 8-bit, internal
reference[31]
Range = ±1.024 V, unbuffered
43
–
–
dB
Note
31. Based on device characterization (not production tested).
Document Number: 001-66235 Rev. *A
Page 77 of 114
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PSoC® 5: CY8C55 Family Datasheet
Table 11-22. Delta-sigma ADC Sample Rates, Range = ±1.024 V
Resolution, Bits
Continuous
Multi-Sample
Multi-Sample Turbo
Min
Max
Min
Max
Min
Max
8
8000
384000
1911
91701
1829
87771
9
6400
307200
1543
74024
1489
71441
10
5566
267130
1348
64673
1307
62693
11
4741
227555
1154
55351
1123
53894
12
4000
192000
978
46900
956
45850
13
3283
157538
806
38641
791
37925
14
2783
133565
685
32855
674
32336
15
2371
113777
585
28054
577
27675
16
2000
48000
495
11861
489
11725
17
500
12000
124
2965
282
6766
18
125
3000
31
741
105
2513
19
16
375
4
93
15
357
20
8
187.5
2
46
8
183
Figure 11-24. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Figure 11-25. Delta-sigma ADC Noise Histogram, 1000 SamContinuous Sample Mode, Input Buffer Bypassed
ples, 20-Bit, 187 sps, Ext Ref, VIN = VREF/2, Range = ±1.024 V
Document Number: 001-66235 Rev. *A
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Figure 11-26. Delta-sigma ADC Noise Histogram, 1000 sam- Figure 11-27. Delta-sigma ADC Noise Histogram, 1000 samples, 16-bit, 48 ksps, Ext Ref, VIN = VREF/2, Range = ±1.024 V ples, 16-bit, 48 ksps, Int Ref, VIN = VREF/2, Range = ±1.024 V
Table 11-23. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Single Ended
Sample rate,
Input Voltage Range
sps
0 to VREF
0 to VREF x 2
VSSA to VDDA
0 to VREF x 6
2000
1.21
1.02
1.14
0.99
3000
1.28
1.15
1.25
1.22
6000
1.36
1.22
1.38
1.22
12000
1.44
1.33
1.43
1.40
24000
1.67
1.50
1.43
1.53
48000
1.91
1.60
1.85
1.67
Table 11-24. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Differential
Sample rate,
Input Voltage Range
sps
±VREF
±VREF / 2
±VREF / 4
±VREF / 8
±VREF / 16
2000
0.56
0.65
0.74
1.02
1.77
4000
0.58
0.72
0.81
1.10
1.98
8000
0.53
0.72
0.82
1.12
2.18
15625
0.58
0.72
0.85
1.13
2.20
32000
0.60
0.76
43750
0.58
0.75
48000
0.59
INVALID OPERATING REGION
Table 11-25. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Single Ended
Sample rate,
Input Voltage Range
sps
0 to VREF
0 to VREF x 2
VSSA to VDDA
0 to VREF x 6
8
1.28
1.24
6.02
0.97
23
1.33
1.28
6.09
0.98
45
1.77
1.26
6.28
0.96
90
1.65
0.91
6.84
0.95
187
1.87
1.06
7.97
1.01
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
Table 11-26. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Differential
Sample rate, sps
Input Voltage Range
±VREF
±VREF / 2
±VREF / 4
±VREF / 8
±VREF / 16
8
0.70
0.84
1.02
1.40
2.65
11.3
0.69
0.86
0.96
1.40
2.69
22.5
0.73
0.82
1.25
1.77
2.67
45
0.76
0.94
1.02
1.76
2.75
61
0.75
1.01
1.13
1.65
2.98
170
0.75
0.98
187
0.73
INVALID OPERATING REGION
Figure 11-28. Delta-sigma ADC DNL vs Output Code, 16-bit,
48 ksps, 25 °C VDDA = 3.3 V
Figure 11-29. Delta-sigma ADC INL vs Output Code, 16-bit,
48 ksps, 25 °C VDDA = 3.3 V
11.5.3 Voltage Reference
Table 11-27. Voltage Reference Specifications
See also ADC external reference specifications in Section 11.5.2.
Parameter
VREF
Description
Min
Typ
Max
Units
1.017
(–0.7%)
1.024
1.033
(+0.9%)
V
Temperature drift[32]
–
–
20
ppm/°C
Long term drift
–
100
–
ppm/Khr
Thermal cycling drift (stability)[32]
–
100
–
ppm
Precision reference voltage
Conditions
Initial trimming
Note
32. Based on device characterization (Not production tested).
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11.5.4 SAR ADC
Table 11-28. SAR ADC DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
bits
Resolution
–
–
12
Number of channels – single-ended
–
–
No of
GPIO
–
–
No of
GPIO/2
Yes
–
–
Number of channels – differential
Differential pair is formed using a
pair of neighboring GPIO.
Monotonicity[33]
Ge
Gain error
–
–
±0.1
%
VOS
Input offset voltage
–
–
±0.2
mV
IDD
Current consumption
–
–
1
mA
Input voltage range –
single-ended[33]
VSSA
–
VDDA
V
VSSA
–
VDDA
V
Input voltage range – differential[33]
ratio[33]
PSRR
Power supply rejection
CMRR
Common mode rejection ratio
INL
Integral non linearity[33]
DNL
Differential non linearity[33]
RIN
Input
70
–
–
dB
35
–
–
dB
Internal reference
–
–
±2
LSB
Internal reference
–
–
±2
LSB
–
TBD
–
KΩ
Min
Typ
Max
Units
–
–
770
ksps
resistance[33]
Table 11-29. SAR ADC AC Specifications
Parameter
Description
Conditions
Sample rate[33]
time[33]
–
–
10
µs
SINAD
Signal-to-noise ratio[33]
44
–
–
dB
THD
Total harmonic distortion[33]
–
–
0.02
%
Startup
11.5.5 Analog Globals
Table 11-30. Analog Globals AC Specifications
Min
Typ
Max
Units
Rppag
Parameter
Resistance pin-to-pin through
analog global
Description
VDDA = 3.0 V
Conditions
–
939
1461
Ω
Rppmuxbus
Resistance pin-to-pin through
analog mux bus
VDDA = 3.0 V
–
721
1135
Ω
Note
33. Based on device characterization (Not production tested).
Document Number: 001-66235 Rev. *A
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11.5.6 Comparator
Table 11-31. Comparator DC Specifications
Parameter
VOS
Description
Conditions
Min
Typ
Max
Units
Input offset voltage in fast mode
Factory trim, Vin ≥ 0.5 V
–
10
mV
Input offset voltage in slow mode
Factory trim, Vin ≥ 0.5 V
–
9
mV
Custom trim
–
–
4
mV
Input offset voltage in slow mode[34] Custom trim
–
–
4
mV
VOS
Input offset voltage in ultra low
power mode
–
±12
–
mV
VHYST
Hysteresis
Hysteresis enable mode
–
10
32
mV
VICM
Input common mode voltage
High current / fast mode
VSSA
–
VDDA – 0.1
V
Low current / slow mode
VSSA
–
VDDA
V
Ultra low power mode
VSSA
–
VDDA – 0.9
VOS
Input offset voltage in fast
mode[34]
CMRR
Common mode rejection ratio
–
50
–
dB
ICMP
High current mode/fast mode[35]
–
–
400
µA
Low current mode/slow mode[35]
–
–
100
µA
Ultra low power mode[35]
–
6
–
µA
Table 11-32. Comparator AC Specifications
Parameter
TRESP
Min
Typ
Max
Units
Response time, high current
mode[35]
Description
50 mV overdrive, measured
pin-to-pin
Conditions
–
75
110
ns
Response time, low current
mode[35]
50 mV overdrive, measured
pin-to-pin
–
155
200
ns
Response time, ultra low power
mode[35]
50 mV overdrive, measured
pin-to-pin
–
55
–
µs
Notes
34. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.
35. Based on device characterization (Not production tested).
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11.5.7 Current Digital-to-analog Converter (IDAC)
See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-33. IDAC DC Specifications
Parameter
Description
Conditions
Resolution
Min
Typ
Max
Units
–
–
8
bits
Range = 2.04 mA, code = 255,
Rload = 600 Ω
–
2.04
–
mA
Range = 255 µA, code = 255, Rload
= 600 Ω
–
255
–
µA
Range = 31.875 µA, code = 255,
Rload = 600 Ω
–
31.875
–
µA
Monotonicity
–
–
Yes
Ezs
Zero scale error
–
0
±2.5
LSB
Eg
Gain error
–
–
±5
%
TC_Eg
Temperature coefficient of gain
error
Range = 2.04 mA
–
–
0.04
% / °C
Range = 255 µA
–
–
0.04
% / °C
IOUT
Output current at code = 255
Range = 31.875 µA
–
–
0.05
% / °C
INL
Integral nonlinearity
Range = 255 µA, Codes 8 – 255,
Rload = 600 Ω, Cload = 15 pF
–
–
±3
LSB
DNL
Differential nonlinearity,
non-monotonic
Range = 255 µA, Rload = 600 Ω,
Cload = 15 pF
–
–
±1.6
LSB
Vcompliance
Dropout voltage, source or sink
mode
Voltage headroom at max current,
Rload to Vdda or Rload to Vssa,
Vdiff from Vdda
1
–
–
V
Note
36. Based on device characterization (Not production tested).
Document Number: 001-66235 Rev. *A
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Table 11-33. IDAC DC Specifications (continued)
Parameter
IDD
Description
Operating current, code = 0
Conditions
Min
Typ
Max
Units
Slow mode, source mode, range =
31.875 µA
–
44
100
µA
Slow mode, source mode, range =
255 µA,
–
33
100
µA
Slow mode, source mode, range =
2.04 mA
–
33
100
µA
Slow mode, sink mode, range =
31.875 µA
–
36
100
µA
Slow mode, sink mode, range =
255 µA
–
33
100
µA
Slow mode, sink mode, range =
2.04 mA
–
33
100
µA
Fast mode, source mode, range =
31.875 µA
–
310
500
µA
Fast mode, source mode, range =
255 µA
–
305
500
µA
Fast mode, source mode, range =
2.04 mA
–
305
500
µA
Fast mode, sink mode, range =
31.875 µA
–
310
500
µA
Fast mode, sink mode, range =
255 µA
–
300
500
µA
Fast mode, sink mode, range =
2.04 mA
–
300
500
µA
Figure 11-30. IDAC INL vs Input Code, Range = 255 µA,
Source Mode
Document Number: 001-66235 Rev. *A
Figure 11-31. IDAC INL vs Input Code, Range = 255 µA, Sink
Mode
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Figure 11-32. IDAC DNL vs Input Code, Range = 255 µA,
Source Mode
Figure 11-33. IDAC DNL vs Input Code, Range = 255 µA, Sink
Mode
Figure 11-34. IDAC INL vs Temperature, Range = 255 µA, Fast
Mode
Figure 11-35. IDAC DNL vs Temperature, Range = 255 µA,
Fast Mode
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Figure 11-36. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Source Mode
Figure 11-37. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Sink Mode
Figure 11-38. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Source Mode
Figure 11-39. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Sink Mode
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Table 11-34. IDAC AC Specifications
Parameter
Description
FDAC
Update rate
TSETTLE
Settling time to 0.5 LSB
Conditions
Range = 31.875 µA or 255 µA, full
scale transition, fast mode, 600 Ω
15-pF load
Figure 11-40. IDAC Step Response, Codes 0x40 - 0xC0,
255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V
Min
Typ
Max
Units
–
–
–
8
Msps
–
125
ns
Figure 11-41. IDAC Glitch Response, Codes 0x7F - 0x80,
255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V
Figure 11-42. IDAC PSRR vs Frequency
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11.5.8 Voltage Digital to Analog Converter (VDAC)
See the VDAC component data sheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-35. VDAC DC Specifications
Parameter
Description
Conditions
Resolution
Min
Typ
Max
Units
–
8
–
bits
INL1
Integral nonlinearity
1 V scale
–
±2.1
±2.5
LSB
DNL1
Differential nonlinearity
1 V scale
–
±0.3
±1
LSB
Rout
Output resistance
1 V scale
–
4
–
kΩ
4 V scale
–
16
–
kΩ
VOUT
Output voltage range, code = 255
1 V scale
–
1
–
V
4 V scale, Vdda = 5 V
–
4
–
V
–
–
Yes
–
Monotonicity
VOS
Zero scale error
Eg
Gain error
–
0
±0.9
LSB
1 V scale
–
–
±2.5
%
TC_Eg
4 V scale
–
–
±2.5
%
Temperature coefficient, gain error 1 V scale
–
–
0.03
%FSR / °C
IDD
Operating current
4 V scale
–
–
0.03
%FSR / °C
Slow mode
–
–
100
µA
Fast mode
–
–
500
µA
Figure 11-43. VDAC INL vs Input Code, 1 V Mode
Document Number: 001-66235 Rev. *A
Figure 11-44. VDAC DNL vs Input Code, 1 V Mode
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Figure 11-45. VDAC INL vs Temperature, 1 V Mode
Figure 11-46. VDAC DNL vs Temperature, 1 V Mode
Figure 11-47. VDAC Full Scale Error vs Temperature, 1 V
Mode
Figure 11-48. VDAC Full Scale Error vs Temperature, 4 V
Mode
Figure 11-49. VDAC Operating Current vs Temperature, 1V
Mode, Slow Mode
Figure 11-50. VDAC Operating Current vs Temperature, 1 V
Mode, Fast Mode
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Table 11-36. VDAC AC Specifications
Parameter
FDAC
Description
Update rate
Conditions
Min
Typ
Max
Units
1 V scale
–
–
1000
ksps
4 V scale
–
–
250
ksps
0.45
1
µs
TsettleP
Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF
75%
–
4 V scale, Cload = 15 pF
–
0.8
3.2
µs
TsettleN
Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF
25%
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.7
3
µs
Figure 11-51. VDAC Step Response, Codes 0x40 - 0xC0, 1 V
Mode, Fast Mode, Vdda = 5 V
Figure 11-52. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V
Mode, Fast Mode, Vdda = 5 V
Figure 11-53. VDAC PSRR vs Frequency
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11.5.9 Mixer
The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications
and APIs.
Table 11-37. Mixer DC Specifications
Parameter
VOS
G
Min
Typ
Max
Units
Input offset voltage
Description
Conditions
–
–
20
mV
Quiescent current
–
0.9
2
mA
Gain
–
0
–
dB
Min
Typ
Max
Units
Table 11-38. Mixer AC Specifications
Parameter
Description
Conditions
fLO
Local oscillator frequency
Down mixer mode
–
–
4
MHz
fin
Input signal frequency
Down mixer mode
–
–
14
MHz
fLO
Local oscillator frequency
Up mixer mode
–
–
1
MHz
fin
Input signal frequency
Up mixer mode
–
–
1
MHz
SR
Slew rate
3
–
–
V/µs
11.5.10 Transimpedance Amplifier
The TIA is created using a SC/CT analog block; see the TIA component data sheet in PSoC Creator for full electrical specifications
and APIs.
Table 11-39. Transimpedance Amplifier (TIA) DC Specifications
Parameter
Description
VIOFF
Input offset voltage
Rconv
Conversion resistance[37]
Conditions
Min
Typ
Max
Units
–
–
20
mV
R = 20K; 40 pF load
–25
–
+35
%
R = 30K; 40 pF load
–25
–
+35
%
R = 40K; 40 pF load
–25
–
+35
%
R = 80K; 40 pF load
–25
–
+35
%
R = 120K; 40 pF load
–25
–
+35
%
R = 250K; 40 pF load
–25
–
+35
%
R= 500K; 40 pF load
–25
–
+35
%
R = 1M; 40 pF load
–25
–
+35
%
–
1.1
2
mA
Min
Typ
Max
Units
R = 20K; 40 pF load
1500
–
–
kHz
R = 120K; 40 pF load
300
–
–
kHz
R = 1M; 40 pF load
46
–
–
kHz
Quiescent current
Table 11-40. Transimpedance Amplifier (TIA) AC Specifications
Parameter
BW
Description
Input bandwidth (–3 dB)
Conditions
Note
37. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component datasheets. External precision
resistors can also be used.
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11.5.11 Programmable Gain Amplifier
The PGA is created using a SC/CT analog block; see the PGA component data sheet in PSoC Creator for full electrical specifications
and APIs.
Unless otherwise specified, operating conditions are:
■
Operating temperature = 25 °C for typical values
■
Unless otherwise specified, all charts and graphs show typical values
Table 11-41. PGA DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Vssa
–
Vdda
V
Vin
Input voltage range
Power mode = minimum
Vos
Input offset voltage
Power mode = high,
gain = 1
–
–
20
mV
TCVos
Input offset voltage drift
with temperature
Power mode = high,
gain = 1
–
–
±30
µV/°C
Ge1
Gain error, gain = 1
–
–
±0.61
%
Ge16
Gain error, gain = 16
–
–
±6.1
%
Ge50
Gain error, gain = 50
–
–
±9
%
Vonl
DC output nonlinearity
–
–
±0.01
% of
FSR
Cin
Input capacitance
–
–
7
pF
Voh
Output voltage swing
Power mode = high,
gain = 1, Rload = 100 kΩ
to VDDA / 2
VDDA – 0.15
–
–
V
Vol
Output voltage swing
Power mode = high,
gain = 1, Rload = 100 kΩ
to VDDA / 2
–
–
VSSA + 0.15
V
Vsrc
Output voltage under load
Iload = 250 µA, power
mode = high
–
–
300
mV
Idd
Operating current
Power mode = high
–
1.5
1.65
mA
PSRR
Power supply rejection
ratio
48
–
–
dB
Gain = 1
Figure 11-54. PGA Voffset Histogram, 4096 samples/
1024 parts
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Table 11-42. PGA AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
6.7
8
–
MHz
Power mode = high,
gain = 1, 20% to 80%
3
–
–
V/µs
Power mode = high,
Vdda = 5 V, at 100 kHz
–
43
–
nV/sqrtHz
BW1
–3 dB bandwidth
Power mode = high,
gain = 1, noninverting
mode, 300 mV ≤ VIN ≤
VDDA – 1.2 V, Cl ≤ 25 pF
SR1
Slew rate
en
Input noise density
Figure 11-55. Bandwidth vs. Temperature, at Different Gain
Settings, Power Mode = High
Figure 11-56. Noise vs. Frequency, Vdda = 5 V,
Power Mode = High
11.5.12 Temperature Sensor
Table 11-43. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +85 °C
Min
Typ
Max
Units
–
±8
–
°C
11.5.13 LCD Direct Drive
Table 11-44. LCD Direct Drive DC Specifications
Conditions
Min
Typ
Max
Units
ICC
Parameter
LCD system operating current
Description
Bus clock = 3 Mhz, Vddio = Vdda =
3 V, 4 commons, 16 segments, 1/4
duty cycle, 50 Hz frame rate, no
glass connected
–
63
–
μA
ICC_SEG
Current per segment driver
Strong drive mode
–
260
–
µA
VBIAS
LCD bias range (VBIAS refers to the VDDA ≥ 3 V and VDDA ≥ VBIAS
main output voltage(V0) of LCD DAC)
2
–
5
V
VDDA ≥ 3 V and VDDA ≥ VBIAS
–
9.1 × VDDA
–
mV
Drivers may be combined
–
500
5000
pF
–
–
20
mV
355
–
710
µA
LCD bias step size
LCD capacitance per
segment/common driver
Long term segment offset
IOUT
Output drive current per segment
driver)
Document Number: 001-66235 Rev. *A
Vddio = 5.5V, strong drive mode
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Table 11-45. LCD Direct Drive AC Specifications
Parameter
fLCD
Description
Conditions
LCD frame rate
Min
Typ
Max
Units
10
50
150
Hz
11.6 Digital Peripherals
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted.
11.6.1 Timer
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for
more information, see the Timer component data sheet in PSoC Creator.
Table 11-46. Timer DC Specifications
Parameter
Description
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
48 MHz
–
260
–
µA
67 MHz
–
350
–
µA
Min
DC
13
30
13
13
30
13
30
Typ
–
–
–
–
–
–
–
–
Max
67.01
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
Table 11-47. Timer AC Specifications
Parameter
Description
Operating frequency
Capture pulse width (Internal)
Capture pulse width (external)
Timer resolution
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Conditions
11.6.2 Counter
The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in
UDBs; for more information, see the Counter component data sheet in PSoC Creator.
Table 11-48. Counter DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
16-bit counter, at listed input clock
frequency
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
48 MHz
–
260
–
µA
67 MHz
–
350
–
µA
Min
DC
13
13
Typ
–
–
–
Max
67.01
–
–
Units
MHz
ns
ns
Block current consumption
Table 11-49. Counter AC Specifications
Parameter
Description
Operating frequency
Capture pulse
Resolution
Document Number: 001-66235 Rev. *A
Conditions
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Table 11-49. Counter AC Specifications (continued)
Parameter
Description
Conditions
Pulse width
Pulse width (external)
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Min
13
30
13
30
13
30
Typ
–
Max
–
–
–
–
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
11.6.3 Pulse Width Modulation
The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented
in UDBs; for more information, see the PWM component data sheet in PSoC Creator.
Table 11-50. PWM DC Specifications
Parameter
Description
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
48 MHz
–
260
–
µA
67 MHz
–
350
–
µA
Min
Typ
Max
Units
Operating frequency
DC
–
67.01
MHz
Pulse width
13
–
–
ns
Pulse width (external)
30
–
–
ns
Kill pulse width
13
–
–
ns
Kill pulse width (external)
30
–
–
ns
Enable pulse width
13
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width
13
–
–
ns
Reset pulse width (external)
30
–
–
ns
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
Table 11-51. PWM AC Specifications
Parameter
Description
Conditions
11.6.4 I2C
Table 11-52. Fixed I2C DC Specifications
Parameter
Description
Block current consumption
Conditions
Min
Typ
Max
Units
Enabled, configured for 100 kbps
–
–
64
µA
Enabled, configured for 400 kbps
–
–
74
µA
Min
Typ
Max
Units
–
–
1
Mbps
Table 11-53. Fixed I2C AC Specifications
Parameter
Description
Bit rate
Document Number: 001-66235 Rev. *A
Conditions
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Controller Area Network[38]
Table 11-54. CAN DC Specifications
Parameter
Description
IDD
Block current consumption
Conditions
Min
–
Typ
–
Max
200
Units
µA
Conditions
Min
Typ
Max
Units
–
–
1
Mbit
Min
Typ
Max
Units
100 kHz (1.3 ksps)
–
0.03
0.05
mA
500 kHz (6.7 ksps)
–
0.16
0.27
mA
1 MHz (13.4 ksps)
–
0.33
0.53
mA
10 MHz (134 ksps)
–
3.3
5.3
mA
48 MHz (644 ksps)
–
15.7
25.5
mA
67 MHz (900 ksps)
–
21.8
35.6
mA
Min
Typ
Max
Units
DC
–
67.01
MHz
Table 11-54. CAN AC Specifications
Parameter
Description
Bit rate
Minimum 8 MHz clock
11.6.5 Digital Filter Block
Table 11-55. DFB DC Specifications
Parameter
Description
DFB operating current
Conditions
64-tap FIR at FDFB
Table 11-56. DFB AC Specifications
Parameter
FDFB
Description
DFB operating frequency
Conditions
Note
38. Refer to ISO 11898 specification for details.
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11.6.6 USB
Table 11-57. USB DC Specifications
Parameter
Min
Typ
Max
Units
USB configured, USB regulator
enabled
4.35
–
5.25
V
VUSB_3.3
USB configured, USB regulator
bypassed
3.15
–
3.6
V
VUSB_3
USB configured, USB regulator
bypassed[39]
2.85
–
3.6
V
VUSB_5
Description
Device supply for USB operation
Conditions
IUSB_Configured Device supply current in device active VDDD = 5 V, FCPU = 1.5 MHz
mode, bus clock and IMO = 24 MHz V
DDD = 3.3 V, FCPU = 1.5 MHz
–
10
–
mA
–
8
–
mA
–
0.5
–
mA
VDDD = 5 V, disconnected from
USB host
–
0.3
–
mA
VDDD = 3.3 V, connected to USB
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 3.3 V, disconnected from
USB host
–
0.3
–
mA
IUSB_Suspended Device supply current in device sleep VDDD = 5 V, connected to USB
mode
host, PICU configured to wake on
USB resume signal
11.6.7 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-58. UDB AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FMAX_TIMER Maximum frequency of 16-bit timer in
a UDB pair
–
–
67.01
MHz
FMAX_ADDER Maximum frequency of 16-bit adder in
a UDB pair
–
–
67.01
MHz
FMAX_CRC
–
–
67.01
MHz
–
–
67.01
MHz
Datapath Performance
Maximum frequency of 16-bit
CRC/PRS in a UDB pair
PLD Performance
FMAX_PLD
Maximum frequency of a two-pass
PLD function in a UDB pair
Clock to Output Performance
tCLK_OUT
Propagation delay for clock in to data 25 °C
out, see Figure 11-57.
–
20
25
ns
tCLK_OUT
Propagation delay for clock in to data Worst-case placement, routing,
out, see Figure 11-57.
and pin selection
–
–
55
ns
Note
39. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 71.
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Figure 11-57. Clock to Output Performance
11.7 Memory
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted.
11.7.1 Flash
Table 11-59. Flash DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
2.7
–
5.5
V
Min
Typ
Max
Units
Table 11-60. Flash AC Specifications
Parameter
Description
Conditions
TWRITE
Row write time (erase + program)
–
15
20
ms
TERASE
Row erase time
–
10
13
ms
Row program time
–
5
7
ms
Bulk erase time (256 KB)
–
–
140
ms
Sector erase time (16 KB)
–
–
15
ms
Total device program time
(including SWD and other overhead
–
–
20
seconds
Average ambient temp.
TA ≤ 55 °C, 100 K erase/program
cycles
20
–
–
years
Average ambient temp.
TA ≤ 85 °C, 10 K erase/program
cycles
10
–
–
TBULK
Flash data retention time, retention
period measured from last erase cycle
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11.7.2 EEPROM
Table 11-61. EEPROM DC Specifications
Parameter
Description
Conditions
Erase and program voltage
Min
Typ
Max
Units
2.7
–
5.5
V
Table 11-62. EEPROM AC Specifications
Parameter
TWRITE
Min
Typ
Max
Units
Single row erase/write cycle time
Description
Conditions
–
2
20
ms
EEPROM data retention time, retention Average ambient temp, TA ≤ 25 °C,
period measured from last erase cycle 1M erase/program cycles
20
–
–
years
Average ambient temp, TA ≤ 55 °C,
100 K erase/program cycles
20
–
–
Average ambient temp. TA ≤ 85 °C,
10 K erase/program cycles
10
–
–
Conditions
Min
Typ
Max
Units
1.2
–
–
V
Min
Typ
Max
Units
DC
–
67.01
MHz
11.7.3 SRAM
Table 11-63. SRAM DC Specifications
Parameter
VSRAM
Description
SRAM retention voltage
Table 11-64. SRAM AC Specifications
Parameter
FSRAM
Description
SRAM operating frequency
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Conditions
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11.8 PSoC System Resources
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted.
11.8.1 Voltage Monitors
Table 11-65. Voltage Monitors DC Specifications
Parameter
LVI
HVI
Description
Conditions
Min
Typ
Max
Units
LVI_A/D_SEL[3:0] = 0011b
2.38
2.45
2.53
V
LVI_A/D_SEL[3:0] = 0100b
2.62
2.71
2.79
V
LVI_A/D_SEL[3:0] = 0101b
2.87
2.95
3.04
V
LVI_A/D_SEL[3:0] = 0110b
3.11
3.21
3.31
V
LVI_A/D_SEL[3:0] = 0111b
3.35
3.46
3.56
V
LVI_A/D_SEL[3:0] = 1000b
3.59
3.70
3.81
V
LVI_A/D_SEL[3:0] = 1001b
3.84
3.95
4.07
V
LVI_A/D_SEL[3:0] = 1010b
4.08
4.20
4.33
V
LVI_A/D_SEL[3:0] = 1011b
4.32
4.45
4.59
V
LVI_A/D_SEL[3:0] = 1100b
4.56
4.70
4.84
V
LVI_A/D_SEL[3:0] = 1101b
4.83
4.98
5.13
V
LVI_A/D_SEL[3:0] = 1110b
5.05
5.21
5.37
V
LVI_A/D_SEL[3:0] = 1111b
5.30
5.47
5.63
V
5.57
5.75
5.92
V
Min
Typ
Max
Units
–
–
1
µs
Min
Typ
Max
Units
Delay from interrupt signal input to ISR
code execution from main line code[40]
–
–
12
Tcy CPU
Delay from interrupt signal input to ISR
code execution from ISR code
(tail-chaining)[40]
–
–
6
Tcy CPU
Trip voltage
Trip voltage
Table 11-66. Voltage Monitors AC Specifications
Parameter
Description
Conditions
Response time
11.8.2 Interrupt Controller
Table 11-67. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Note
40. ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU.
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11.8.3 SWD Interface
Table 11-68. SWD Interface AC Specifications[41]
Parameter
Description
Conditions
Min
Typ
Max
Units
MHz
3.3 V ≤ VDDD ≤ 5 V
–
–
12[42]
2.7 V ≤ VDDD < 3.3 V
–
–
7[42]
MHz
–
–
5.5[42]
MHz
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T/4
–
–
T_SWDI_hold
T/4
–
–
f_SWDCK
SWDCLK frequency
2.7 V ≤ VDDD < 3.3 V, SWD over
USBIO pins
SWDIO input hold after SWDCK high
T = 1/f_SWDCK max
T_SWDO_valid SWDCK high to SWDIO output
T = 1/f_SWDCK max
–
–
2T/5
T_SWDO_hold SWDIO output hold after SWDCK low
T = 1/f_SWDCK max
T/4
–
–
Min
Typ
Max
Units
–
33[43]
Mbit
11.8.4 TPIU Interface
Table 11-69. TPIU Interface AC Specifications[41]
Parameter
Description
Conditions
SWV bit rate
–
Notes
41. Based on device characterization (Not production tested).
42. f_SWDCK must also be no more than 1/3 CPU clock frequency.
43. SWV signal frequency and bit rate are limited by GPIO output frequency, see “GPIO AC Specifications” on page 66.
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11.9 Clocking
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 2.7 V to 5.5 V, except
where noted. Unless otherwise specified, all charts and graphs show typical values.
11.9.1 32 kHz External Crystal
Table 11-70. 32 kHz External Crystal DC Specifications[44]
Parameter
ICC
Description
Operating current
Conditions
Low power mode
Min
Typ
Max
Units
–
0.25
1.0
µA
CL
External crystal capacitance
–
6
–
pF
DL
Drive level
–
–
1
µW
Min
Typ
Max
Units
–
32.768
–
kHz
–
1
–
s
Min
Typ
Max
Units
–
–
600
µA
Table 11-71. 32 kHz External Crystal AC Specifications
Parameter
Description
F
Frequency
TON
Startup time
Conditions
High power mode
11.9.2 Internal Main Oscillator)
Table 11-72. IMO DC Specifications
Parameter
Description
Conditions
Supply current
62.6 MHz
48 MHz
–
–
500
µA
24 MHz
–
–
300
µA
12 MHz
–
–
200
µA
6 MHz
–
–
180
µA
3 MHz
–
–
150
µA
Figure 11-58. IMO Current vs. Frequency
Note
44. Based on device characterization (Not production tested).
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Table 11-76. IMO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
62.6 MHz
–10
–
10
%
48 MHz
–10
–
10
%
24 MHz
–6
–
6
%
12 MHz
–6
–
6
%
6 MHz
–4
–
4
%
–4
–
4
%
–
–
12
µs
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
1.6
–
ns
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
12
–
ns
IMO frequency stability (with factory trim)
FIMO
3 MHz
Startup time[44]
From enable (during normal system
operation) or wakeup from low
power state
Jitter (peak to peak)[45]
Jp-p
Jitter (long term)[45]
Jperiod
Figure 11-59. IMO Frequency Variation vs. Temperature
Figure 11-60. IMO Frequency Variation vs. VCCD
Note
45. Based on device characterization (Not production tested).
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11.9.3 Internal Low Speed Oscillator
Table 11-77. ILO DC Specifications
Parameter
Description
Operating current
Conditions
Min
Typ
Max
Units
FOUT = 1 kHz
–
0.3
1.7
µA
FOUT = 33 kHz
–
1.0
2.6
µA
FOUT = 100 kHz
–
1.0
2.6
µA
Power down mode
–
2.0
15
nA
Min
Typ
Max
Units
–
–
2.5
ms
100 kHz
45
100
200
kHz
1 kHz
0.5
1
2
kHz
100 kHz
30
100
300
kHz
1 kHz
0.3
1
3.5
kHz
ICC
Leakage current
Table 11-78. ILO AC Specifications
Parameter
Description
Startup time, all frequencies
Conditions
Turbo mode
ILO frequencies (trimmed)
FILO
ILO frequencies (untrimmed)
Figure 11-61. ILO Frequency Variation vs. Temperature
Document Number: 001-66235 Rev. *A
Figure 11-62. ILO Frequency Variation vs. VDD
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11.9.4 External Crystal Oscillator
Table 11-79. ECO AC Specifications
Parameter
F
Description
Conditions
Crystal frequency range
Min
Typ
Max
Units
4
–
25
MHz
Min
Typ
Max
Units
11.9.5 External Clock Reference
Table 11-80. External Clock Reference AC Specifications[46]
Parameter
Description
Conditions
External frequency range
0
–
33
MHz
Input duty cycle range
Measured at VDDIO/2
30
50
70
%
Input edge rate
VIL to VIH
0.1
–
–
V/ns
11.9.6 Phase-Locked Loop
Table 11-81. PLL DC Specifications
Parameter
IDD
Description
PLL operating current
Min
Typ
Max
Units
In = 3 MHz, Out = 67 MHz
Conditions
–
400
–
µA
In = 3 MHz, Out = 24 MHz
–
200
–
µA
Min
Typ
Max
Units
Table 11-82. PLL AC Specifications
Parameter
Fpllin
Description
PLL input
1
–
48
MHz
1
–
3
MHz
PLL output frequency[47]
24
–
67
MHz
Lock time at startup
–
–
250
µs
(rms)[46]
–
–
250
ps
PLL intermediate frequency[48]
Fpllout
Conditions
frequency[47]
Jperiod-rms Jitter
Output of prescaler
Notes
46. Based on device characterization (Not production tested).
47. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
48. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
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12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C55 device includes: up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a
precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more.
In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting
the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C55
derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details.
Table 12-1. CY8C55 Family with ARM Cortex-M3 CPU
I/O[51]
UDBs[50]
16-bit Timer/PWM
FS USB
CAN 2.0b
Total I/O
GPIO
SIO
USBIO
1x 20-bit Del-Sig
2x 12-bit SAR
4
4
4
4
✔ ✔ 24
4
✔ ✔
70
60
8
2
CY8C5568LTI-114
67 256
64
2
✔
1x 20-bit Del-Sig
2x 12-bit SAR
4
4
4
4
✔ ✔ 24
4
✔ ✔
46
36
8
2
CY8C5567AXI-019
67 128
32
2
✔
1x 20-bit Del-Sig
1x 12-bit SAR
4
4
4
4
✔ ✔ 24
4
✔ ✔
70
60
8
2
CY8C5567LTI-079
67 128
32
2
✔
1x 20-bit Del-Sig
1x 12-bit SAR
4
4
4
4
✔ ✔ 24
4
✔ ✔
46
36
8
2
CY8C5566AXI-061
67
64
16
2
✔
1x 20-bit Del-Sig
1x 12-bit SAR
4
4
4
4
✔ ✔ 24
4
✔ ✔
70
60
8
2
CY8C5566LTI-017
67
64
16
2
✔
1x20-bit Del-Sig
1x12-bit SAR
4
4
4
4
✔ ✔ 24
4
✔ ✔
46
36
8
2
CapSense
✔
DFB
Comparators
2
SC/CT
Analog Blocks[49]
Opamps
DAC
64
ADCs
67 256
Flash (KB)
CY8C5568AXI-060
Part Number
CPU Speed (MHz)
LCD Segment Drive
Digital
EEPROM (KB)
Analog
SRAM (KB)
MCU Core
Device ID[52]
Package
100-pin TQFP 0x0E116069
68-pin QFN
0x0E134069
100-pin TQFP 0x0E141069
68-pin QFN
0x0E114069
100-pin TQFP 0x0E143069
68-pin QFN
0x0E13C069
12.1 Part Numbering Conventions
PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A,
B, …, Z) unless stated otherwise.
CY8Cabcdefg-xxx
■
■
■
■
■
a: Architecture
❐ 3: PSoC 3
❐ 5: PSoC 5
b: Family group within architecture
❐ 2: CY8C52 family
❐ 3: CY8C53 family
❐ 4: CY8C54 family
❐ 5: CY8C55 family
c: Speed grade
❐ 4: 40 MHz
❐ 8: 67 MHz
d: Flash capacity
❐ 5: 32 KB
❐ 6: 64 KB
❐ 7: 128 KB
❐ 8: 256 KB
❐
Two character alphanumeric
AX: TQFP
❐ LT: QFN
❐
■
g: Temperature range
❐ C: commercial
❐ I: industrial
❐ A: automotive
■
xxx: Peripheral set
❐ Three character numeric
❐ No meaning is associated with these three characters
ef: Package code
Notes
49. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 32 for more information on how analog blocks
can be used.
50. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs can be used.
51. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See 6.4 I/O System and Routing on page 26 for details on the functionality of each of
these types of I/O.
52. The device ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
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Examples
CY8C
5 5 8 8 AX/PV I
- x x x
Cypress Prefix
5: PSoC 5
5: CY8C55 Family
Architecture
Family Group within Architecture
8: 80 MHz
Speed Grade
8: 256 KB
Flash Capacity
AX: TQFP
Package Code
I: Industrial
Temperature Range
Peripheral Set
All devices in the PSoC 5 CY8C55 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of
life” requirements.
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13. Packaging
Table 13-1. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
–
100
°C
Tja
Package θJA (68-pin QFN)
–
15
–
°C/Watt
Tja
Package θJA (100-pin TQFP)
–
34
–
°C/Watt
Tjc
Package θJC (68-pin QFN)
–
13
–
°C/Watt
Tjc
Package θJC (100-pin TQFP)
–
10
–
°C/Watt
Table 13-2. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at
Peak Temperature
68-pin QFN
260 °C
30 seconds
100-pin TQFP
260 °C
30 seconds
Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
68-pin QFN
MSL 3
100-pin TQFP
MSL 3
Figure 13-1. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version)
001-09618 *C
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Figure 13-2. 100-pin TQFP (14 x 14 x 1.4 mm) Package Outline
51-85048 *E
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14. Acronyms
Table 14-1. Acronyms Used in this Document (continued)
Table 14-1. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
PSoC® 5: CY8C55 Family Datasheet
Controller Area Network, a communications
protocol
Acronym
Description
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
I2C,
or IIC
IIR
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
IPSR
interrupt program status register
IRQ
interrupt request
instrumentation trace macrocell
CMRR
common-mode rejection ratio
ITM
CPU
central processing unit
LCD
liquid crystal display
CRC
cyclic redundancy check, an error-checking
protocol
LIN
Local Interconnect Network, a communications
protocol.
DAC
digital-to-analog converter, see also IDAC, VDAC
LR
link register
DFB
digital filter block
LUT
lookup table
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
EMI
electromagnetic interference
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
Document Number: 001-66235 Rev. *A
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
PHUB
peripheral hub
PHY
physical layer
PICU
port interrupt control unit
Page 110 of 114
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Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PLA
programmable logic array
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
PMDD
package material declaration datasheet
POR
power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
2C
serial clock
PSoC® 5: CY8C55 Family Datasheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
SPI
Description
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TRM
technical reference manual
TTL
transistor-transistor logic
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
SCL
I
WDT
watchdog timer
SDA
I2C serial data
WOL
write once latch, see also NVL
S/H
sample and hold
WRES
watchdog timer reset
SINAD
signal to noise and distortion ratio
XRES
external reset I/O pin
SIO
special input/output, GPIO with advanced
features. See GPIO.
XTAL
crystal
SOC
start of conversion
15. Reference Documents
SOF
start of frame
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 5 Registers TRM
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
16. Document Conventions
16.1 Units of Measure
Table 16-1. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibels
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohours
kHz
kilohertz
kΩ
kilohms
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
MΩ
megaohms
Msps
megasamples per second
µA
microamperes
µF
microfarads
µH
microhenrys
µs
microseconds
µV
microvolts
µW
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts
Ω
ohms
pF
picofarads
ppm
parts per million
ps
picoseconds
s
seconds
sps
samples per second
sqrtHz
square root of hertz
V
volts
Document Number: 001-66235 Rev. *A
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PSoC® 5: CY8C55 Family Datasheet
17. Revision History
Description Title: PSoC® 5: CY8C55 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-66235
Submission
Date
Orig. of
Change
Rev.
ECN No.
**
3198501
03/17/2011
MKEA
New data sheet.
*A
3279676
06/10/2011
MKEA
Updated condition for offset voltage spec in delta-sigma ADC DC specs
Changed MHzECO range
Updated Flash and EEPROM AC specs
Added solder reflow peak temperature table
Changed IDAC IDD numbers and VDAC
Added flash retention specs
Added JTAG and SWD interface diagrrams
Removed mention of comparator wakeup from sleep
Updated PSoC Power system diagram
Updated opamp dc specs table
Updated SAR electrical specs
Updated clocking sections
Removed references to JTAG interface
Updated opamp and I/O graphs
Added note that Interrupt Specs are ARM Specs
Changed JTAG and SWD max speeds
Modified ILO startup time
Removed references to ETM and TRACEPORT
Updated IDAC range limits
Updated Vddio pin description
Updated Power Modes section
Added note on watchdog timer in the Reset section
Updaed ESDHBM value
Updated Boost Converter section
Document Number: 001-66235 Rev. *A
Description of Change
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PSoC® 5: CY8C55 Family Datasheet
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
Clocks & Buffers
Interface
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-66235 Rev. *A
®
®
®
®
Revised June 10, 2011
Page 114 of 114
®
CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.
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