SDAS054B − DECEMBER 1982 − REVISED JANUARY 1995
•
•
DW OR N PACKAGE
(TOP VIEW)
Low-Power Version of SN74ALS240A
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
pnp Inputs Reduce dc Loading
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (N) 300-mil DIPs
•
•
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
description
1
20
2
19
3
18
4
17
5
16
6
15
7
14
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
13
This octal buffer and line driver is designed
12
9
specifically to improve both the performance and
11
10
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The designer has a choice of selected combinations of inverting and noninverting outputs,
symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs. This device features
high fan-out and improved fan-in.
8
The SN74ALS1240 is characterized for operation from 0°C to 70°C.
logic symbol†
1OE
1A1
1A2
1A3
1A4
1
logic diagram (positive logic)
1OE
EN
2
18
4
16
6
14
8
12
1A1
1Y1
19
1Y3
1A2
2A2
2A3
2A4
18
4
16
6
14
8
12
1Y1
1Y2
1Y4
1Y3
EN
1A4
2A1
2
1Y2
1A3
2OE
1
11
9
13
7
15
5
17
3
1Y4
2Y1
2Y2
2OE
2Y3
19
2Y4
2A1
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2A2
2A3
2A4
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Copyright 1995, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
POST OFFICE BOX 1443
1
SDAS054B − DECEMBER 1982 − REVISED JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
−15
mA
IOL
TA
Low-level output current
16
mA
70
°C
High-level input voltage
2
Operating free-air temperature
V
V
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = − 18 mA
IOH = − 0.4 mA
VCC = 4.5 V
IOH = − 3 mA
IOH = − 15 mA
VOL
VCC = 4.5 V
IOL = 8 mA
IOL = 16 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH§
IIL§
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VOH
IO¶
Outputs high
ICC
VCC = 5.5 V
MIN
VCC − 2
2.4
TYP‡
MAX
UNIT
−1.2
V
3.2
V
2
0.25
0.4
0.35
0.5
20
−30
V
µA
−20
µA
0.1
mA
20
µA
−0.1
mA
−112
mA
5
8
Outputs low
8.5
14
Outputs disabled
8.1
13
mA
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ For I/O ports, the parameters IIH and IIL include the off-state output current.
¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
2
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SDAS054B − DECEMBER 1982 − REVISED JANUARY 1995
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
MIN
MAX
2
13
2
13
4
20
6
22
2
10
3
13
UNIT
ns
ns
ns
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
3
SDAS054B − DECEMBER 1982 − REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
From Output
Under Test
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
3.5 V
Input
tPHZ
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
VOL
0.3 V
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
[3.5 V
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
0.3 V
[0 V
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
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