CY22050, CY220501 One-PLL General Purpose Flash Programmable Clock Generator Features Benefits ■ Integrated phase-locked loop (PLL) ■ ■ Commercial and Industrial operation Internal PLL to generate six outputs up to 200 MHz. Able to generate custom frequencies from an external reference crystal or driven source. ■ Flash-programmable ■ ■ Field-programmable Performance guaranteed for applications that require an extended temperature range. ■ Low-skew, low-jitter, high-accuracy outputs ■ ■ 3.3V operation with 2.5V output option ■ 16-Pin TSSOP package (CY22050) ■ 16-Pin TSSOP package with NiPdAu lead finish (CY220501) Reprogrammable technology allows easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. Parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. ■ In-house programming of samples and prototype quantities is available using the CY3672 FTG Development Kit. Production quantities are available through Cypress’s value-added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. ■ Industry standard packaging saves on board space. Table 1. Device Selection Part Number Outputs Input Frequency Range Output Frequency Range Specifications CY22050KFZXC 6 8 MHz–30 MHz (external crystal) 1 MHz–133 MHz (driven clock) 80 kHz–200 MHz (3.3V) 80 KHz–166.6 MHz (2.5V) Field-programmable commercial temperature CY22050KFZXI 6 8 MHz–30 MHz (external crystal) 1 MHz–133 MHz (driven clock) 80 kHz–166.6 MHz (3.3V) 80 KHz–150 MHz (2.5V) Field-programmable industrial temperature CY220501KFZXI 6 8 MHz–30 MHz (external crystal) 1 MHz–133 MHz (driven clock) 80 kHz–166.6 MHz (3.3V) 80 KHz–150 MHz (2.5V) Field-programmable industrial temperature NiPdAu lead finish Logic Block Diagram LCLK1 Divider Bank 1 XIN OSC. Q LCLK2 Output Select Matrix Φ VCO XOUT LCLK3 LCLK4 P Divider Bank 2 PLL CLK5 CLK6 OE VDD Cypress Semiconductor Corporation Document #: 38-07006 Rev. *G • AVDD AVSS VSS VDDL 198 Champion Court VSSL • PWRDWN San Jose, CA 95134-1709 • 408-943-2600 Revised July 24, 2009 [+] Feedback CY22050, CY220501 Pin Configuration Figure 1. 16-Pin TSSOP XIN VDD 1 16 XOUT 2 15 AVDD 3 14 PWRDWN 4 13 CLK6 CLK5 VSS AVSS 5 12 LCLK4 VSSL 6 11 VDDL LCLK1 7 10 LCLK2 8 9 OE LCLK3 Table 2. Pin Definitions Name Pin Number Description XIN 1 Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based on manufacturer, process, performance, or quality. VDD 2 3.3V voltage supply AVDD 3 3.3V analog voltage supply PWRDWN[1] 4 Power Down. When pin 4 is driven LOW, the CY22050 goes into shut down mode. AVSS 5 Analog ground VSSL 6 LCLK ground LCLK1 7 Configurable clock output 1 at VDDL level (3.3V or 2.5V) LCLK2 8 Configurable clock output 2 at VDDL level (3.3V or 2.5V) LCLK3 9 Configurable clock output 3 at VDDL level (3.3V or 2.5V) OE[1] 10 Output Enable. When pin 10 is driven LOW, all outputs are three-stated. VDDL 11 LCLK voltage supply (2.5V or 3.3V) LCLK4 12 Configurable clock output 4 at VDDL level (3.3V or 2.5V) VSS 13 Ground CLK5 14 Configurable clock output 5 (3.3V) CLK6 15 Configurable clock output 6 (3.3V) XOUT[2] 16 Reference output Notes 1. The CY22050 has no internal pull up or pull down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground. 2. Float XOUT if XIN is driven by an external clock source. Document #: 38-07006 Rev. *G Page 2 of 10 [+] Feedback CY22050, CY220501 Functional Description Applications The CY22050 is the next-generation programmable FTG (frequency timing generator) for use in networking, telecommunication, datacom, and other general-purpose applications. The CY22050 offers up to six configurable outputs in a 16-pin TSSOP, running off a 3.3V power supply. The on-chip reference oscillator is designed to run off an 8–30-MHz crystal, or a 1–133-MHz external clock signal. Controlling Jitter The CY22050 has a single PLL driving 6 programmable output clocks. The output clocks are derived from the PLL or the reference frequency (REF). Output post dividers are available for either. Four of the outputs can be set as 3.3V or 2.5V, for use in a wide variety of portable and low-power applications. The CY220501 is the CY22050 with NiPdAu lead finish. Field Programming the CY22050F The CY22050 is programmed at the package level, that is, in a programmer socket, prior to installation on a PCB. The CY22050 is flash-technology based, so the parts can be reprogrammed up to 100 times. This allows for fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Samples and small prototype quantities can be programmed on the CY3672 programmer. Cypress’s value-added distribution partners and third-party programming systems from BP Microsystems, HiLo Systems, and others are available for large-production quantities. CyberClocks™ Software CyberClocks is an easy-to-use software application that allows the user to custom-configure the CY22050. Within CyberClocks, select the CyClocksRT™ tool. Users can specify the REF, PLL frequency, output frequencies and/or post-dividers, and different functional options. CyClocksRT outputs an industry-standard JEDEC file used for programming the CY22050. Jitter is defined in many ways, including: phase noise, long-term jitter, cycle-to-cycle jitter, period jitter, absolute jitter, and deterministic jitter. These jitter terms are usually given in terms of rms, peak-to-peak, or in the case of phase noise dBC/Hz with respect to the fundamental frequency. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL (2.5V or 3.3V), temperature, and output load. Power supply noise and clock output loading are two major system sources of clock jitter. Power supply noise can be mitigated by proper power supply decoupling (0.1-μF ceramic cap) of the clock and ensuring a low-impedance ground to the chip. Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs also reduce jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. The rate and magnitude that the PLL corrects the VCO frequency is directly related to jitter performance. If the rate is too slow, then long term jitter and phase noise is poor. Therefore, to improve long-term jitter and phase noise, reducing Q to a minimum is advisable. This technique increases the speed of the phase frequency detector, which in turn drives the input voltage of the VCO. In a similar manner, increasing P until the VCO is near its maximum rated speed also decreases long term jitter and phase noise. For example: input reference of 12 MHz; desired output frequency of 33.3 MHz. One might arrive at the following solution: Set Q = 3, P = 25, Post Div = 3. However, the best jitter results are Q = 2, P = 50, Post Div = 9. For additional information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cypress.com (click on “Application Notes”), or contact your local Cypress Field Applications Engineer. CyClocksRT can be downloaded free of charge from the Cypress website at http://www.cypress.com. Install and run it on any PC running the Windows operating system. CY3672 Development Kit The Cypress CY3672 Development Kit comes complete with everything needed to design with the CY22050 and program samples and small prototype quantities. The kit comes with the latest version of CyClocksRT and a small portable programmer that connects to a PC for on-the-fly programming of custom frequencies. The JEDEC file output of CyClocksRT can be downloaded to the portable programmer for small-volume programming, or for use with a production programming system for larger volumes. Document #: 38-07006 Rev. *G Page 3 of 10 [+] Feedback CY22050, CY220501 CY22050 Frequency Calculation The CY22050 is an extremely flexible clock generator with up to six individual outputs, generated from an integrated PLL. There are four variables used to determine the final output frequency. They are: the input REF, the P and Q dividers, and the post divider. The three basic formulas for determining the final output frequency of a CY22150-based design are: ■ CLK = ((REF * P)/Q)/Post Divider ■ CLK = REF/Post Divider ■ CLK = REF The basic PLL block diagram is shown in Figure 2. Each of the six clock outputs has a total of seven output options available to it. There are six post divider options: /2 (two of these), /3, /4, /DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated and can be independent of each other. The post divider options can be applied to the calculated PLL frequency or to the REF directly. In addition to the six post divider options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix. Clock Output Settings: Crosspoint Switch Matrix Each of the six clock outputs can come from any of seven unique frequency sources. The crosspoint switch matrix defines which source is attached to each individual clock output. Although it may seem that there are an unlimited number of divider options, there are several rules that must be taken into account when selecting divider options. Figure 2. Basic PLL Block Diagram Divider Bank 1 REF Q /DIV1N LCLK1 /2 LCLK2 /3 LCLK3 VCO PFD P Divider Bank 2 /4 /2 /DIV2N Crosspoint Switch Matrix LCLK4 CLK5 CLK6 Table 3. Clock Output Definition Clock Output Divider None Definition and Notes Clock output source is the reference input frequency /DIV1N Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. /2 Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible by 4. /3 Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6. /DIV2N Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. /2 Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 4. /4 Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 8. Document #: 38-07006 Rev. *G Page 4 of 10 [+] Feedback CY22050, CY220501 Reference Crystal Input The input crystal oscillator of the CY22050 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference clock source. The oscillator inverter has programmable gain, allowing for maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. The value of the input load capacitors is determined by eight bits in a programmable register. Total load capacitance is determined by the formula: CapLoad = (CL – CBRD – CCHIP)/0.09375 pF In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22050. If you require greater control over the CapLoad value, consider using the CY22150 for serial configuration and control of the input load capacitors. For an external clock source, the default is 0. Input load capacitors are placed on the CY22050 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes. Absolute Maximum Conditions Min Max Unit VDD Parameter Supply Voltage Description –0.5 7.0 V VDDL I/O Supply Voltage –0.5 7.0 V –65 125 °C 125 °C Temperature[3] TS Storage TJ Junction Temperature Package Power Dissipation—Commercial Temp 450 mW Package Power Dissipation—Industrial Temp 380 mW Digital Inputs ESD AVSS – 0.3 AVDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDDL VSS – 0.3 VDDL +0.3 V 2000 V Static Discharge Voltage per MIL-STD-833, Method 3015 Recommended Operating Conditions Parameter Description Min Typ. Max Unit VDD Operating Voltage 3.135 3.3 3.465 V VDDLHI Operating Voltage 3.135 3.3 3.465 V VDDLLO Operating Voltage 2.375 2.5 2.625 V TAC Ambient Commercial Temp 70 °C TAI Ambient Industrial Temp CLOAD Max. Load Capacitance VDD/VDDL = 3.3V CLOAD Max. Load Capacitance VDDL = 2.5V fREFD Driven REF fREFC Crystal REF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0 –40 85 °C 15 pF 15 pF 133 MHz 8 30 MHz 0.05 500 ms 1 Note 3. Rated for 10 years Document #: 38-07006 Rev. *G Page 5 of 10 [+] Feedback CY22050, CY220501 DC Electrical Characteristics Parameter[4] Name Description Min Typ. Max Unit IOH3.3 Output High Current VOH = VDD – 0.5V, VDD/VDDL = 3.3V 12 24 mA IOL3.3 Output Low Current VOL = 0.5V, VDD/VDDL = 3.3V 12 24 mA IOH2.5 Output High Current VOH = VDDL – 0.5V, VDDL = 2.5V 8 16 mA IOL2.5 Output Low Current VOL = 0.5V, VDDL = 2.5V 8 16 mA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 1.0 VDD VIL Input Low Voltage CMOS levels, 30% of VDD 0 0.3 VDD IVDD[5,6] IVDDL3.3[5,6] IVDDL2.5[5,6] Supply Current AVDD/VDD Current 45 mA Supply Current VDDL Current (VDDL = 3.465V) 25 mA Supply Current VDDL Current (VDDL = 2.625V) 17 mA IDDS Power Down Current VDD = VDDL = AVDD = 3.465V 50 μA IOHZ IOLZ Output Leakage VDD = VDDL = AVDD = 3.465V 10 μA AC Electrical Characteristics Parameter[4] t1 t2 Name Max Unit Clock output limit, 3.3V 0.08 (80 kHz) 200 MHz Clock output limit, 2.5V 0.08 (80 kHz) 166.6 MHz Output frequency, indus- Clock output limit, 3.3V trial temp Clock output limit, 2.5V 0.08 (80 kHz) 166.6 MHz Output frequency, commercial temp Output duty cycle Description Min Typ. 150 MHz Duty cycle is defined in Figure 4; t1/t2 fOUT > 166 MHz, 50% of VDD 0.08 (80 kHz) 40 50 60 % Duty cycle is defined in Figure 4; t1/t2 fOUT < 166 MHz, 50% of VDD 45 50 55 % t3LO Rising edge slew rate (VDDL = 2.5V) Output clock rise time, 20% – 80% of VDDL. Defined in Figure 5 0.6 1.2 V/ns t4LO Falling edge slew rate (VDDL = 2.5V) Output clock fall time, 80% – 20% of VDDL. Defined in Figure 5 0.6 1.2 V/ns t3HI Rising edge slew rate (VDDL = 3.3V) Output clock rise time, 20% – 80% of VDD/VDDL. Defined in Figure 5 0.8 1.4 V/ns t4HI Falling edge slew rate (VDDL = 3.3V) Output clock fall time, 80% – 20% of VDD/VDDL. Defined in Figure 5 0.8 1.4 V/ns t5[7] Skew Output-output skew between related outputs t6[8] Clock jitter Peak-to-peak period jitter (see Figure 6) t10 PLL lock time 250 250 0.30 ps ps 3 ms Notes 4. Not 100% tested, guaranteed by design. 5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. All outputs are loaded with 15pF. 6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations. 7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information. 8. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL (2.5V or 3.3V), temperature, and output load. For more information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cypress.com, or contact your local Cypress Field Applications Engineer. Document #: 38-07006 Rev. *G Page 6 of 10 [+] Feedback CY22050, CY220501 Figure 3. Test Circuit VDD CLK out 0.1 μF OUTPUTS AVDD CLOAD VDDL 0.1 μF 0.1 μF GND Figure 4. Duty Cycle Definition: DC = t2/t1 t1 t2 CLK 50% 50% Figure 5. Rise and Fall Time Definitions t3 t4 80% CLK 20% Figure 6. Peak-to-Peak Jitter t6 CLK Document #: 38-07006 Rev. *G Page 7 of 10 [+] Feedback CY22050, CY220501 Ordering Information Ordering Code Temperature Operating Range Package Type Operating Voltage CY22050FC[9] 16-lead TSSOP Commercial (0 to 70°C) 3.3V CY22050FI[9] 16-lead TSSOP Industrial (–40 to 85°C) 3.3V CY22050ZC-xxx[9, 10] 16-lead TSSOP Commercial (0 to 70°C) 3.3V CY22050KFC 16-lead TSSOP Commercial (0 to 70°C) 3.3V CY22050KFI 16-lead TSSOP Industrial (–40 to 85°C) 3.3V Pb-Free CY220501KFZXI 16-lead TSSOP with NiPdAu lead finish Industrial (–40 to 85°C) 3.3V CY22050FZXC[9] 16-lead TSSOP Commercial (0 to 70°C) 3.3V CY22050FZXI[9] 16-lead TSSOP Industrial (–40 to 85°C) 3.3V CY22050ZXC-xxx[9, 10] 16-lead TSSOP Commercial (0 to 70°C) 3.3V CY22050ZXC-xxxT[9, 10] 16-lead TSSOP-Tape and Reel Commercial (0 to 70°C) 3.3V CY22050ZXI-xxx[9, 10] 16-lead TSSOP Industrial (–40 to 85°C) 3.3V CY22050ZXI-xxxT[9, 10] 16-lead TSSOP-Tape and Reel Industrial (–40 to 85°C) 3.3V CY22050KFZXC 16-lead TSSOP Commercial (0 to 70°C) 3.3V CY22050KFZXI 16-lead TSSOP Industrial (–40 to 85°C) 3.3V CY22050KZXC-xxx[10] 16-lead TSSOP Commercial (0 to 70°C) 3.3V CY22050KZXC-xxxT[10] 16-lead TSSOP-Tape and Reel Commercial (0 to 70°C) 3.3V CY22050KZXI-xxx[10] 16-lead TSSOP Industrial (–40 to 85°C) 3.3V CY22050KZXI-xxxT[10] 16-lead TSSOP-Tape and Reel Industrial (–40 to 85°C) 3.3V Programmer CY3672-USB Programming Kit CY3695 CY22050F, CY22050KFand CY220501KF Adapter for CY3672 Programmer 16-Pin TSSOP Package Characteristics Parameter Name Value Unit θJA theta JA 115 °C/W Complexity Transistor Count 74,600 Transistors Notes 9. Not recommended for new designs. Part numbers without a “K” are being replaced by part numbers with a “K”. There are no changes to device specifications as a result of the part number change. 10. The CY22050KZXC-xxx and CY22050KZXI-xxx are factory-programmed configurations. Factory programming is available for high-volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress field application engineer or Cypress sales representative. Document #: 38-07006 Rev. *G Page 8 of 10 [+] Feedback CY22050, CY220501 Package Drawing and Dimensions Figure 7. 16-Pin TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 1 MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05gms 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Document #: 38-07006 Rev. *G Page 9 of 10 [+] Feedback CY22050, CY220501 Document History Page Document Title: CY22050, CY220501 One-PLL General Purpose Flash-Programmable Clock Generator Document Number: 38-07006 REV. ECN Orig. of Change Submission Date ** 108185 CKN 08/08/01 New Data Sheet. *A 110054 CKN 03/04/02 Changed from Preliminary to Final. *B 121862 RBI 12/14/02 Power up requirements added to Operating Conditions Information. Description of Change *C 310575 RGL 01/20/05 Added Lead-free devices. *D 314233 RGL 01/31/05 Removed the Tape and Reel devices in the non-dash parts. *E 2440826 AESA 05/15/08 Updated template. Added Note “Not recommended for new designs.” and “38-07409, CY3672 PTG Programming Kit”. Corrected "FTG" to PTG" in Ordering information table. Added part numbers CY22050KFC, CY22050KFI, CY22050KFZXC, CY22050KFZXI, CY22050KZXC-xxx, CY22050KZXC-xxxT, CY22050KZXI-xxx, and CY22050KZXI-xxxT in ordering information table. Changed Lead-Free to Pb-Free. *F 2642064 KVM 01/21/09 Added CY220501 to title. Added CY220501KFZXI to ordering table. *G 2743347 KVM 07/24/09 Revised the Device Selection table on page 1 and renamed it. Updates to programmer and softwre descriptions. Clarified that IVDD and IVDDL are for loaded outputs. Updated footnotes to show that the standard part numbers are now with a “K”. Changed CY3672 part number to CY3672-USB, changed CY3672ADP000 to CY3695, and repositioned them in the Ordering Information table. Deleted part numbers CY22050ZC-xxxT, CY22050ZI-xxx and CY22050ZI-xxxT. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07006 Rev. *G Revised July 24, 2009 Page 10 of 10 BP Microsystems is a trademark of BP Microsystems. Hilo Systems is a trademark of Hi-Lo Systems. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback