Advanced Power Electronics Corp. AP1270 3A SINK/SOURCE BUS TERMINATION REGULATOR DESCRIPTIOON FEATURES Ideal for DDR-I, DDR-II and DDR-III V TT Applications Sink and Source 3A Continuous Current Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL_18, HSTL, SCSI-2 and SCSI-3 Interfaces. High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in TO-252-5L & ESOP-8 Packages VIN and VCNTL No Power Sequence Issue RoHS Compliant and 100% Lead (Pb)-Free The AP1270 is a simple, cost-effective and highspeed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 3A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2V DDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The AP1270 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AP1270 are available in the TO-252-5L & ESOP-8 (Exposed Pad) surface mount packages. APPLICATION Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems TYPICAL APPLICATION VCNTL=3.3V VIN=2.5V/1.8V/1.5V CIN VIN R1 RTT AP1270 REFEN VOUT 2N7002 EN CCNTL VCNTL CSS R2 GND COUT RDUMMY R1 = R2 = 100KΩ, RTT = 50Ω / 33Ω / 25Ω COUT,min = 10uF (Ceramic) + 1000uF under the worst case testing condition CSS = 1µF, CIN = 470µF(Low ESR), CCNTL = 47µF Data and specifications subject to change without notice 1 201011055 Advanced Power Electronics Corp. AP1270 ABSOLUTE MAXIMUM RATINGS(Note1) Input Voltage (VIN) ------------------------------------------- 6V CNTL Pin Voltage (VCNTL) --------------------------------- 6V Power Dissipation (PD) ------------------------------------- Internally Limited Storage Temperature Range (TST) ---------------------- -65 to +150°C Lead Temperature (Soldering, 10sec.) ---------------- 260°C Thermal Resistance from Junction to Case (R thjc) ESOP-8 28°C/W TO-252-5L 6°C/W Note1 : Exceeding the absolute maximum rating may damage the device. OPERATING RATING(Note2) Input Voltage (VIN) ------------------------------------------- 2.5V to 1.5V +3% CNTL Pin Voltage (VCNTL) --------------------------------- 5.5V or 3.3V +5% Junction Temperature Range (TJ) ----------------------- -40 to +125°C Ambient Temperature Range (T A) ---------------------- -40 to +85°C Note2 : The device is not guaranteed to function outside its operating conditions. ORDERING / PACKAGE INFORMATION ( Top View ) AP1270X-HF Halogen-Free VIN 1 8 NC ( Side View ) GND 2 7 NC ( Top View ) REFEN 3 VOUT 4 MP : ESOP-8 H : TO-252-5L GND 6 VCNTL 5 NC 5 4 3 2 1 Metal Tab VCNTL ESOP-8 Rthja = 75oC/W VOUT VREFEN VCNTL GND VIN TO-252-5L Rthja = 40oC/W ELECTRICAL SPECIFICATIONS (VIN=1.8V, VCNTL=3.3V, VREFEN=0.9V, COUT=10uF(Ceramic), TA =25oC, unless otherwise specified) Parameter SYM TEST CONDITION MIN TYP MAX UNITS Input VCNTL Operation Current ICNTL IOUT = 0A - 1 2.5 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown), RLOAD = 180Ω - 50 90 uA VOS IOUT = 0A -20 - 20 IOUT = 10mA ~ 3A -20 - 20 IOUT = -10mA ~ -3A -20 - 20 3.2 - - Output (DDR / DDRII / DDRIII) Output Offset Voltage (Note3) (Note4) Load Regulation ΔVLoad mV Protection Current Limit Thermal Shutdown Temperature Thermal Shutdown Hysteresis ILIM TSD 3.3V < VCNTL < 5V 130 160 - ΔTSD 3.3V < VCNTL < 5V - 30 - 0.65 - - - - 0.2 A o C REFEN Shutdown Shutdown Threshold VIH Enable VIL Shutdown V Note3. VOS offset is the voltage measurement defined as V OUT subtracted from VREFEN. Note4. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 3A. 2 Advanced Power Electronics Corp. AP1270 PIN DESCRIPTIONS PIN SYMBOL VIN PIN DESCRIPTION Power Input Voltage. GND VOUT Ground Pin VCNTL Gate Drive Voltage Output Voltage REFEN Reference Voltage Input and Chip Enable BLOCK DIAGRAM VCNTL VIN Current Limit Thermal Protection REFEN + EA - VOUT APPLICATION INFORMATION Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the AP1270. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AP1270 and the preceding powe converter. 3 Advanced Power Electronics Corp. AP1270 Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. Thermal Consideration AP1270MP regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125 oC. The power dissipation definition in device is: P D = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( TJ(MAX) -TA ) / Rthja Where T J(MAX) is the maximum operation junction temperature 125 oC, TA is the ambient temperature and the R thja is the junction to ambient thermal resistance. The junction to ambient o thermal resistance (Rthja is layout dependent) for ESOP-8 package (Exposed Pad) is 75 C/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at T A = o 25 C can be calculated by following formula: P D(MAX) = (125oC - 25oC) / 75oC/W = 1.33W The thermal resistance R thja of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. 4 Advanced Power Electronics Corp. AP1270 TYPICAL PERFORMANCE CHARACTERISTICS Load Transient (Source test) Load Transient (Sink test) VIN VIN VOUT VOUT IOUT IOUT VIN = 1.8V, VCNTL = 3.3V VIN = 1.8V, VCNTL = 3.3V VREF = 0.9V Supplied by a regulator VREF = 0.9V Supplied by a regulator Output Voltage vs. Temperature 1.1 Shutdown Threshold vs. Temperature 0.55 Turn On Shutdown Threshold (V) Output Voltage (V) 0.5 1 0.9 0.8 0.45 Turn Off 0.4 0.35 0.3 0.7 0.25 -50 -25 0 25 50 75 100 125 -50 -25 0 o VCNTL Current (mA) VIN Current (uA) 125 VCNTL Current vs. Temperature 4 VIN=1.8V, VCNTL=5V VIN=1.8V, VCNTL=3.3V VIN=1.5V, VCNTL=5V VIN=1.5V, VCNTL=3.3V 13 100 VIN = 1.8V, VCNTL = 3.3V, IOUT = 10mA, Source test VIN Current vs. Temperature 14 75 Temperature ( C) VIN = 1.8V, VCNTL = 3.3V, IOUT = 0A, Source test 15 50 o Temperature ( C) 16 25 12 11 10 9 8 3.5 VIN=1.8V, VCNTL=5V 3 2.5 VIN=1.8V, VCNTL=3.3V 2 7 6 1.5 -50 -25 0 25 50 75 o Temperature ( C) IOUT = 0A, Source test 100 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) IOUT = 0A, Source test 5 Advanced Power Electronics Corp. AP1270 TYPICAL PERFORMANCE CHARACTERISTICS 5.5 Sink Current Limit (A) Source Current Limit (A) Sink Current Limit vs. Temperature Source Current Limit vs. Temperature 5.5 5 4.5 5 4.5 4 3.5 VIN=1.8V, VCNTL=3.3V VIN=1.8V, VCNTL=5V VIN=1.8V, VCNTL=3.3V VIN=1.8V, VCNTL=5V 3 4 -50 -25 0 25 50 75 o Temperature ( C) 100 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) 6 Advanced Power Electronics Corp. AP1270 MARKING INFORMATION ESOP-8 Part Number Package Code 1270MP YWWSSS Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence TO-252-5L Part Number Package Code 1270H LOGO YWWSSS Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence 7