3D7438 MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE Super-Fine Resolution (SERIES 3D7438) FEATURES PACKAGES All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Leading- and trailing-edge accuracy Programmable via serial or parallel interface Increment range: 50ps through 250ps Delay tolerance: 0.5% (See Table 1) Supply current: 3mA typical Temperature stability: 1.5% max (-40C to 85C) Vdd stability: 0.5% max (4.75V to 5.25V) IN SO AE GND IN AE SO/P0 P1 P2 P3 P4 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD OUT MD P7 P6 SC P5 SI 3D7438S-xx SOW16 1 2 3 4 8 7 6 5 VDD OUT SC SI 3D7438Z-xx SOIC8 IN AE P0 P1 P2 P3 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD OUT P7 P6 P5 P4 GND 3D7438D-xx SOIC14 For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7438 device is a versatile 8-bit programmable monolithic delay line. The input (IN) is reproduced at the output (OUT) without inversion, shifted in time as per the user selection. Delay values, programmed either via the serial or parallel interface, can be varied over 255 equal steps according to the formula: IN OUT MD AE P0-P7 SC SI SO VDD GND Ti,nom = Tinh + i * Tinc where i is the programmed address, Tinc is the delay increment (equal to the device dash number), and Tinh is the inherent (address zero) delay. The device features both rising- and falling-edge accuracy. Signal Input Signal Output Mode Select Address Enable Parallel Data Input Serial Clock Serial Data Input Serial Data Output +5 Volts Ground The all-CMOS 3D7438 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard surface mount 16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed. Similarly, a 14-pin SOIC is offered for applications where the serial interface is not needed. TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER 3D7438x-50 3D7438x-60 3D7438x-75 3D7438x-80 3D7438x-100 3D7438x-125 3D7438x-150 3D7438x-200 3D7438x-250 DELAYS AND TOLERANCES Inherent Delay (ns) 7.0 0.5 7.0 0.5 7.0 0.5 7.0 0.5 7.0 0.5 7.0 0.5 7.0 0.5 7.0 0.5 7.0 0.5 Delay Range (ns) 12.750 .05 15.300 .06 19.125 .08 20.400 .08 25.500 .10 31.875 .13 38.250 .15 51.000 .20 63.750 .25 Delay Step (ps) 50 25 60 30 75 38 80 40 100 50 125 63 150 75 200 100 250 125 INPUT RESTRICTIONS Max Freq (Addr=0) 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz Max Freq (Addr=255) 98 MHz 82 MHz 65 MHz 61 MHz 49 MHz 39 MHz 32 MHz 24 MHz 19 MHz Min P.Width (Addr=0) 3.3 ns 3.3 ns 3.3 ns 3.3 ns 3.3 ns 3.3 ns 3.3 ns 3.3 ns 3.3 ns NOTES: Replace the ‘x’ in the part number with D, S or Z, depending on choice of package. Any dash number between 50 and 250 not shown is also available as standard. See application notes section for more details Doc #10004 7/8/2010 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 Min P.Width (Addr=255) 5.1 ns 6.1 ns 7.6 ns 8.1 ns 10.0 ns 12.7 ns 15.3 ns 20.4 ns 25.5 ns 2010 Data Delay Devices 1 3D7438 APPLICATION NOTES GENERAL INFORMATION The 8-bit programmable 3D7438 delay line architecture is comprised of a sequence of five identical delay cells connected in series, all of which are controlled by a common current. This current, in turn, is controlled by the user-selected programming data (the address). The delay cells produce at their output a replica of the signal present at the input, shifted in time. The change in delay from one address setting to the next is called the increment, or LSB. It is nominally equal to the device dash number. The minimum delay, achieved by setting the address to zero, is called the inherent delay. For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible. DELAY ACCURACY There are a number of ways of characterizing the delay accuracy of a programmable line. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the increment at a given address from its nominal value. For all dash numbers, the DNL is within 0.5 LSB at every address (see Table 1: Delay Step). The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the delay-versus-address data. The INL is then the deviation of a given delay from this line. For all dash numbers, the INL is within 1.0 LSB at every address. where Tinh is the nominal inherent delay. The absolute error is limited to 1.5 LSB or 1.0 ns, whichever is greater, at every address. The inherent delay error is the deviation of the inherent delay from its nominal value. For all dash numbers, it is limited to 0.5 ns. DELAY STABILITY The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The 3D7438 utilizes novel compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. The 3D7438 is designed to be most stable at the maximum address setting (255). At this operating condition, the thermal coefficient of the absolute delay is limited to 250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of 1.5% from the roomtemperature delay. At smaller address settings the thermal coefficient will be somewhat larger. At the maximum address, the power supply sensitivity of the absolute delay is 0.5% over the 4.75V to 5.25V operating range, with respect to the delay at the nominal 5.0V power supply. At smaller address settings the sensitivity will be somewhat larger. INPUT SIGNAL CHARACTERISTICS The maximum input frequency and minimum input pulse width are both limited by the device. Exceeding either limit will cause the signal to be blocked by the line. Furthermore, for a given device, these limitations vary with the userspecified address. The relationships are: The relative error is defined as follows: FMax = 1250 / (i * Tinc) PWMin = 0.4 * (i * Tinc), erel = (Ti – T0) – i * Tinc where i is the address, Ti is the measured delay at the i’th address, T0 is the measured inherent delay, and Tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For all dash numbers, the relative error is less than 1.0 LSB at every address (see Table 1: Delay Range). The absolute error is defined as follows: eabs = Ti – (Tinh + i * Tinc) Doc #10004 7/8/2010 where FMax is in MHz, and PWMin & Tinc are in ns. These relationships break down for small delays: FMax can never be greater than 150 MHz, and PWMin can never be smaller than 3.3 ns. PROGRAMMING INTERFACE Figure 1 illustrates the main functional blocks of the 3D7438 delay program interface. Since the 3D7438 is a CMOS design, all unused input pins must be returned to well defined logic levels, VDD or Ground. DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D7438 APPLICATION NOTES (CONT’D) order, thus allowing cascading of multiple devices by connecting the serial output pin (SO) of the preceding device to the serial data input pin (SI) of the succeeding device, as illustrated in Figure 5. The total number of serial data bits in a cascade configuration must be eight times the number of units, and each group of eight bits must be transmitted in MSB-to-LSB order. TRANSPARENT PARALLEL MODE (MD = 1, AE = 1) The eight program pins P0 - P7 directly control the output delay. A change on one or more of the program pins will be reflected on the output delay after a time tPDV, as shown in Figure 2. A register is required if the programming data is bused. To initiate a serial read, enable (AE) is driven high. After a time tEQV, bit 7 (MSB) is valid at the serial output port pin (SO). On the first rising edge of the serial clock (SC), bit 7 is loaded with the value present at the serial data input pin (SI), while bit 6 is presented at the serial output pin (SO). To retrieve the remaining bits seven more rising edges must be generated on the serial clock line. The read operation is destructive. Therefore, if it is desired that the original delay setting remain unchanged, the read data must be written back to the device(s) before the enable (AE) pin is brought low. LATCHED PARALLEL MODE (MD = 1, AE PULSED) The eight program pins P0 - P7 are loaded by the falling edge of the Enable pulse, as shown in Figure 3. After each change in delay value, a settling time tEDV is required before the input is accurately delayed. SERIAL MODE (MD = 0) While observing data setup (tDSC) and data hold (tDHC) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of the clock (SC) while the enable (AE) is high, as shown in Figure 4. The falling edge of the enable (AE) activates the new delay value which is reflected at the output after a settling time tEDV. As data is shifted into the serial data input (SI), the previous contents of the 8-bit input register are shifted out of the serial output port pin (SO) in MSB-to-LSB The SO pin, if unused, must be allowed to float if the device is configured in the serial programming mode. The serial mode is the only mode available on the 8-pin version of the 3D7438, and this mode is unavailable on the 14-pin version of the 3D7438. PROGRAMMABLE DELAY LINE SIGNAL IN IN ADDRESS ENABLE AE OUT SIGNAL OUT LATCH SO SERIAL INPUT SI SHIFT CLOCK SERIAL OUTPUT 8-BIT INPUT REGISTER SC MODE SELECT MD P0 P1 P2 P3 P4 P5 P6 P7 PARALLEL INPUTS Figure1: Functional block diagram PARALLEL INPUTS P0-P7 PREVIOUS DELAY TIME PREVIOUS NEW VALUE tPDX tPDV NEW VALUE Figure 2: Non-latched parallel mode (MD=1, AE=1) Doc #10004 7/8/2010 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D7438 APPLICATION NOTES (CONT’D) tEW ENABLE (AE) tDSE PARALLEL INPUTS P0-P7 tDHE NEW VALUE tEDX DELAY TIME tEDV PREVIOUS NEW VALUE Figure 3: Latched parallel mode (MD=1) tEW ENABLE (AE) tCW tCW tES tEH CLOCK (SC) tDSC SERIAL INPUT (SI) tDHC NEW BIT 7 NEW BIT 6 tEGV SERIAL OUTPUT (SO) NEW BIT 0 tCQV OLD BIT 7 tCQX OLD BIT 6 tEQZ OLD BIT 0 tEDV tEDX DELAY TIME NEW VALUE PREVIOUS VALUE Figure 4: Serial mode (MD=0) 3D7438 SI SC FROM WRITING DEVICE 3D7438 SO SI SO SC AE AE 3D7438 SI SO SC AE TO NEXT DEVICE Figure 5: Cascading Multiple Devices TABLE 2: DELAY VS. PROGRAMMED ADDRESS PARALLEL SERIAL STEP 0 STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 253 STEP 254 STEP 255 CHANGE Doc #10004 7/8/2010 P7 PROGRAMMED ADDRESS P6 P5 P4 P3 P2 P1 Msb NOMINAL DELAY (NS) PER 3D7438 DASH NUMBER P0 Lsb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 -50 7.000 7.050 7.100 7.150 7.200 7.250 -75 7.000 7.075 7.150 7.225 7.300 7.375 -100 7.000 7.100 7.200 7.300 7.400 7.500 -125 7.000 7.125 7.250 7.375 7.500 7.625 -150 7.000 7.150 7.300 7.450 7.600 7.750 -200 7.000 7.200 7.400 7.600 7.800 8.000 -250 7.000 7.250 7.500 7.750 8.000 8.250 19.650 19.700 19.750 12.750 25.975 26.050 26.125 19.125 32.300 32.400 32.500 25.500 38.625 38.750 38.875 31.875 44.950 45.100 45.250 38.250 57.600 57.800 58.000 51.000 70.250 70.500 70.750 63.750 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 3D7438 DEVICE SPECIFICATIONS TABLE 3: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 4: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH MIN IOL 4.0 TYP 3.0 MAX 5.0 -35.0 0.8 1.0 1.0 -4.0 2.0 15.0 TR & TF mA 2.0 *IDD(Dynamic) = CLD * VDD * F where: CLD = Average capacitance load/line (pf) F = Input frequency (GHz) UNITS mA V V A A mA 2.5 ns NOTES Addr = 128 VIH = VDD VIL = 0V VDD = 4.75V VOH = 2.4V VDD = 4.75V VOL = 0.4V CLD = 5 pf Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max TABLE 5: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Clock Frequency Enable Width Clock Width Data Setup to Clock Data Hold from Clock Data Setup to Enable Data Hold from Enable Enable to Serial Output Valid Enable to Serial Output High-Z Clock to Serial Output Valid Clock to Serial Output Invalid Enable Setup to Clock Enable Hold from Clock Parallel Input Valid to Delay Valid Parallel Input Change to Delay Invalid Enable to Delay Valid Enable to Delay Invalid Input Pulse Width Input Period Input to Output Delay Doc #10004 7/8/2010 SYMBOL fC tEW tCW tDSC tDHC tDSE tDHE tEQV tEQZ tCQV tCQX tES tEH tPDV tPDX tEDV tEDX tWI Period tPLH, tPHL MIN TYP MAX 80 10 10 10 3 10 3 20 20 20 10 10 10 20 40 35 45 0 0 40 80 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns % of Delay % of Delay ns NOTES See Table 1 See Table 1 See Table 2 5 3D7438 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High = 3.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 2 x Max Delay Period: PERIN = 10 x Max Delay OUTPUT: Rload: Cload: Threshold: 10K 10% 5pf 10% 1.5V (Rising & Falling) Device Under Test Digital Scope 10K 470 5pf NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM REF PULSE GENERATOR OUT IN DEVICE UNDER TEST (DUT) TRIG IN OUT DIGITAL SCOPE/ TIME INTERVAL COUNTER TRIG Figure 6: Test Setup PERIN PW IN tRISE INPUT SIGNAL tFALL VIH 2.4 1.5 0.6 2.4 1.5 0.6 VIL tPLH OUTPUT SIGNAL tPHL VOH 1.5 1.5 VOL Figure 7: Timing Diagram Doc #10004 7/8/2010 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 6