[AK4420] AK4420 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output AK4420 2Vrms 24 ΔΣ DAC (SCF) 192kHz 5V Set-Top-Box, DVD, AC-3 2Vrms 16pin TSSOP 128 64 32 24 2Vrms : 8kHz ∼ 192kHz 2 4 8 FIR SCF I/F : 24 : 512fs, 768fs or 1152fs 256fs or 384fs 2 128fs or 192fs 4 , I2S THD+N: –92dB Dynamic Range: 105dB : +4.5 ∼ +5.5V Ta = -20 to 85°C (ET), -40 to 85°C (VT) : 16pin TSSOP (6.4mm x 5.0mm) MCLK SMUTE DIF VDD Clock Divider Control Interface DZF VSS1 LRCK BICK SDTI Audio Data Interface 8X Interpolator ΔΣ Modulator SCF LPF AOUTL 8X Interpolator ΔΣ Modulator SCF LPF AOUTR Charge Pump CP CN 1μ MS0683-J-04 -1- VEE VSS2 CVDD 1μ 2010/06 [AK4420] ■ -20 ∼ +85°C -40 ∼ +85°C AK4420 AK4420ET AK4420VT AKD4420 16pin TSSOP (0.65mm pitch) 16pin TSSOP (0.65mm pitch) ■ ■ AK4420 CN 1 16 VEE CP 2 15 VSS2 SMUTE 3 14 CVDD MCLK 4 13 DZF BICK 5 12 VSS1 SDTI 6 11 VDD LRCK 7 10 AOUTL DIF 8 9 AOUTR AK4420 Top View AK4421,AK4424 Digital de-emphasis I/F format Pin out Pin#3 Pin#8 Power Supply THD+N DR Operating Temperature AK4420 24-bit MSB justified I²S SMUTE DIF +4.5 ∼ +5.5V -92dB 105dB ET: -20 ∼ +85°C VT: -40 ∼ +85°C AK4421 24-bit MSB justified I²S SMUTE DIF +3.0 ∼ +3.6V -92dB (-3dBFS) 102dB AK4424 X DEM SMUTE +4.5 ∼ +5.5V -92dB 105dB ET: -20 ∼ +85°C ET: -20 ∼ +85°C I²S -: Not available X: Available MS0683-J-04 -2- 2010/06 [AK4420] No. Pin Name Function Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0μF capacitor that should have the low ESR 1 CN I (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0μF capacitor that should have the low ESR 2 CP I (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Soft Mute Enable Pin (Internal pull down: 100k ) 3 SMUTE I “H”: Enable, “L”: Disable Master Clock Input Pin 4 MCLK I An external TTL clock should be input on this pin. 5 BICK I Audio Serial Data Clock Pin 6 SDTI I Audio Serial Data Input Pin 7 LRCK I L/R Clock Pin Audio Data Interface Format Pin 8 DIF I “L”: Left Justified, “H”: I2S Rch Analog Output Pin 9 AOUTR O When power down, outputs VSS(0V, typ). Lch Analog Output Pin 10 AOUTL O When power down, outputs VSS(0V, typ). 11 VDD DAC Power Supply Pin: 4.5V∼5.5V 12 VSS1 Ground Pin1 13 DZF O Zero Input Detect Pin 14 CVDD Charge Pump Power Supply Pin: 4.5V∼5.5V 15 VSS2 Ground Pin2 Negative Voltage Output Pin Connect to VSS2 with a 1.0μF capacitor that should have the low ESR 16 (Equivalent Series Resistance) over all temperature range. When this VEE O capacitor has the polarity, the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be used. Note: All input pins except for the CN pin should not be left floating. MS0683-J-04 I/O -3- 2010/06 [AK4420] (VSS1=VSS2=0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature AK4420ET AK4420VT Storage Temperature Note 1. Note 2. VSS1 VSS2 Symbol VDD CVDD IIN VIND Ta Ta Tstg Min -0.3 -0.3 -0.3 -20 -40 -65 max +6.0 +6.0 ±10 VDD+0.3 85 85 150 Units V V mA V °C °C °C : (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD CVDD min +4.5 typ +5.0 VDD max +5.5 Units V Note 3. VDD CVDD : MS0683-J-04 -4- 2010/06 [AK4420] ( Ta = 25°C; VDD=CVDD = +5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) THD+N (0dBFS) fs=44.1kHz, BW=20kHz -92 -84 dB fs=96kHz, BW=40kHz -92 dB fs=192kHz, BW=40kHz -92 dB Dynamic Range (-60dBFS with A-weighted, Note 5) 98 105 dB S/N (A-weighted, Note 6) 98 105 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Audio Bias Voltage (at output pin) -60 0 +60 mV Gain Drift 100 ppm/°C Output Voltage (Note 7) 1.97 2.12 2.27 Vrms Load Capacitance (Note 8) 25 pF Load Resistance 5 kΩ Power Supplies Power Supply Current: (Note 9) 24 36 mA Normal Operation (fs≤96kHz) 27 40 mA Normal Operation (fs=192kHz) 10 100 Power-Down Mode (Note 10) μA Note 4. Audio Precision (System Two) Note 5. 98dB at 16bit data Note 6. S/N Note 7. (0dB) VDD AOUT (typ.@ 0dB) = 2.12Vrms × VDD/5. Note 8. Note 9. VDD CVDD Note 10. (MCLK, BICK, LRCK) VDD VSS MS0683-J-04 -5- 2010/06 [AK4420] (Ta = 25°C; VDD=CVDD= +4.5 ∼ +5.5V; fs = 44.1kHz) Parameter Symbol Digital filter PB Passband ±0.05dB (Note 11) -6.0dB Stopband (Note 11) SB Passband Ripple PR Stopband Attenuation SA Group Delay (Note 12) GD Digital Filter + LPF Frequency Response 20.0kHz fs=44.1kHz FR 40.0kHz fs=96kHz FR 80.0kHz fs=192kHz FR Note 11. fs ( PB=0.4535×fs(@±0.05dB) SB=0.546×fs Note 12. 16/24 min typ max Units 0 24.1 22.05 20.0 - 54 - 19.3 - kHz kHz kHz dB dB 1/fs - ± 0.05 ± 0.05 ± 0.05 - dB dB dB typ - max 0.8 0.4 ± 10 Units V V V V µA ± 0.02 ) DC (Ta = 25°C; VDD=CVDD = 4.5 ∼ 5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout = -80µA) Low-Level Output Voltage (Iout = 80µA) Input Leakage Current (Note 13) Note 13. SMUTE pin SMUTE pin MS0683-J-04 Symbol VIH VIL VOH VOL Iin -6- min 2.2 VDD-0.4 - (typ. 100kΩ) 2010/06 [AK4420] (Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 14) LRCK Edge to BICK “↑” (Note 14) SDTI Hold Time SDTI Setup Time Note 14. LRCK BICK MS0683-J-04 Symbol fCLK dCLK min 4.096 30 fsn fsd fsq Duty 8 32 120 45 tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 typ 11.2896 max 36.864 70 Units MHz % 48 96 192 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns “↑” -7- 2010/06 [AK4420] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 2. Serial Interface Timing MS0683-J-04 -8- 2010/06 [AK4420] ■ MCLK, LRCK, BICK (MCLK) (LRCK) ΔΣ (Table 1) MCLK MCLK MCLK, LRCK MCLK, LRCK LRCK fs 32.0kHz 44.1kHz 48.0kHz 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs - 22.5792 24.5760 AK4420 0V (typ) MCLK, LRCK ON 192fs - 256fs 8.192 11.2896 12.288 22.5792 24.5760 - 33.8688 36.8640 MCLK (MHz) 384fs 512fs 16.3840 22.5792 24.5760 12.288 16.9344 18.432 33.8688 36.8640 - 768fs 24.5760 33.8688 36.8640 1152fs 36.8640 - Sampling Speed Normal Double - - Quad Table 1. MCLK= 256fs/384fs DR, S/N 32kHz~96kHz MCLK= 512fs/768fs (Table 1) (Table 2) MCLK 256fs/384fs 512fs/768fs Table 2. MCLK 32kHz~48kHz DR,S/N 102dB 105dB DR, S/N (fs = 44.1kHz) ■ BICK LRCK MSB 16/20 Mode 0 1 SDTI 2’s complement LSB “0” 2 (Table 3) DIF L H BICK ≥48fs ≥48fs DIF pin BICK LRCK SDTI Format 24bit 24bit I2S DIF pin 8 H Figure Figure 3 Figure 4 Table 3. MS0683-J-04 -9- 2010/06 [AK4420] LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 0 1 Don’t care 23 22 0 1 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 0 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 BICK (64fs) SDTI 1 23 22 0 Don’t care 23 22 1 0 23 Don’t care 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 1 Timing ■ 8192 DZF pin MS0683-J-04 “0” DZF pin “H” “0” “L” - 10 - 2010/06 [AK4420] ■ AK4420 (Figure 5) 2Vrms (Figure 6) Ca Cb ) CP (Figure 5) AK4420 VSS(0V,typ) 1.0μF ESR( VSS2 VSS(0V,typ) AK4420 CVDD Charge Pump CP CN Negative Power VSS2 (+) 1uF Ca Cb (+) VEE 1uF Figure 5. AK4420 2.12Vrms 0V AOUTR (AOUTL) Figure 6. Audio MS0683-J-04 - 11 - 2010/06 [AK4420] ■ SMUTE pin “H” Normal Speed Mode SMUTE pin “L” -∞ 1024LRCK -∞ (“0”) 0dB 1024LRCK -∞ 1024LRCK 0dB SMUTE pin 1024/fs 0dB 1024/fs (1) (3) Attenuation -∞ GD (2) GD AOUT (4) 8192/fs DZF pin : (1) Normal Speed Mode 1024LRCK (1024/fs) -∞(“0”) Double Speed Mode 2048LRCK (2048/fs) Quad Speed Mode (4096/fs) -∞(“0”) (2) (GD) (3) 1024LRCK Normal Speed Mode 0dB (4) 8192 “0” DZF pin “H” “0” DZF pin “L” 4096LRCK Figure 7. MS0683-J-04 - 12 - 2010/06 [AK4420] ■ ON AK4420 MCLK LRCK “↑” LRCK Power Supply (VDD, CVDD) (6) MCLK Low 20 us Analog Circuit Digital (1) Power down (2) Power down Circuit Charge Pump Circuit Power-up 2, 3 LRCK Power-up Power down Power-up (3) Charge Pump Time A Counter circuit D/A In (Digital) “0” data D/A Out (Analog) MUTE (D/A Out) (4) (5) DZF (1) (2) MCLK (3) MCLK 2, 3 LRCK 20us time A D/A Time A = 1024/ (fs x 16): Normal speed mode Time A = 1024/ (fs x 8): Double speed mode Time A = 1024/ (fs x 4): Quadruple speed mode (4) (5) (6) MCLK pin DZF PIN “L” “L” VDD CVDD 80% min.20us MCLK Figure 8. System Reset Diagram MS0683-J-04 - 13 - 2010/06 [AK4420] ■ MCLK LRCK MCLK LRCK AK4420 Internal State VSS(0V,typ) Normal Operation Reset D/A In (Digital) Normal Operation (1) GD (3) D/A Out (Analog) VSS (2) (3) <Case1:MCLK Stop> Clock In (4) MCLK Stop MCLK, BICK, LRCK (6) DZF <Case2:LRCK Stop> Clock In (4) (5) LRCK Stop MCLK, BICK, LRCK (6) DZF : (1) “0” (2) (3) (4) (MCLK (5) MCLK 2048fs (6) MCLK LRCK (GD) LRCK ) LRCK DZF pin (MCLK, BICK, LRCK) LRCK LRCK LRCK “L” Figure 9. MS0683-J-04 - 14 - 2010/06 [AK4420] Figure 10 (AKD4420) CN VEE 16 2 CP VSS2 15 3 SMUTE 4 MCLK 64fs 5 BICK 24bit Audio Data 6 SDTI fs 7 LRCK AOUTL 10 8 DIF AOUTR 1u (1) + Master Clock ModeSetting Digital Ground CVDD 14 DZF 13 AK4420 VSS1 12 VDD 11 9 Analog 5.0V 1u (1) + 1 0.1u + 10u 10Ω External Mute Circuits 0.1u + 10u Lch Out Rch Out Analog Ground ESR CP, VSS2 VSS1, VSS2 Figure 10. Typical Connection Diagram MS0683-J-04 - 15 - 2010/06 [AK4420] 1. VDD CVDD VDD CVDD VDD VSS VDD CVDD CVDD VSS2 2. ΔΣ (CTF) 10kΩ 100kΩ VSS(0V,typ) ) ( 1 2.12Vrms(typ, @VDD=5V) (SCF) LPF(Figure 11) Figure 12 2’s complement (2 800000H(@24bit) DC ±60 V ) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT 0V(VSS) AK4420 470 Analog Out AOUT 2.2nF ( 2.12Vrms (typ) = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz) Figure 11. External 1st order LPF Circuit Example1 AK4420 47μ 820 220 AOUT 47k 1000pF Analog Out 10kÆ1.92Vrms (typ) 100kÆ2.1Vrms (typ) Figure 12. External 1st order LPF Circuit Example2 MS0683-J-04 - 16 - 2010/06 [AK4420] 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 M 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ : : : MS0683-J-04 - 17 - 2010/06 [AK4420] AKM 4420ET XXYYY 1) 2) 3) 4) Pin #1 indication Date Code: XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code: 4420ET Asahi Kasei Logo AKM 4420VT XXYYY 5) 6) 7) 8) MS0683-J-04 Pin #1 indication Date Code: XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code: 4420VT Asahi Kasei Logo - 18 - 2010/06 [AK4420] Date (YY/MM/DD) 07/11/05 07/12/04 07/12/17 Revision 00 01 02 Reason First Edition Page Contents 13 14 Figure 8 Figure 9 MCLK 14 2 AK4420VT AK4420 AK4421,AK4424 AK4421 2 03 (Ambient Operating Temperature) 4 AK4420VT 18 AK4420VT Note13. 6 10/06/23 04 BICK MCLK LRCK BICK (Ta) AK4420VT 1 08/04/01 LRCK ■ 9 17 MS0683-J-04 - 19 - 2010/06 [AK4420] z z z z z z MS0683-J-04 - 20 - 2010/06