Enabling MIPI
Physical Layer Test
High Speed Test
and Characterization
High Speed Digital Test
Enabling MIPI Physical Layer Test
July, 2008
The Explosion of Functions within Mobile Devices
Multiple RF functions
– GPS
– Bluetooth
– WCDMA
– GSM
Request for more bandwidth
– WLAN
High speed serialization
– FM
Multiple Peripherals
– Camera
Digitization of IQ
Power Management
– Display
– Audio in /out
– Mobile TV
– DVB-H
– Other IOs
Enabling MIPI Physical Layer Test
Page 2
July, 2008
Emergence of Standard Digital Interconnects
From Analog to Digital
The Digital Interface
• Is easier and cheaper to implement
LTE
Wireless
Domain
WiMAX
• Will consume less battery power
RF IC
• Provides higher bandwidth
• Reduces the number of IC pins
DigRF
• Allows for easier “plug and play”
between devices
MIPI
DPHY CSI
BB IC
MIPI
DPHY DSI
AP
Standards
inherited from the
computer industry
BUT
• Breaking the GBit barrier requires
dedicated jitter stress test – on clock
and data separately
Digital
Domain
• Power safe requires wake up and
therefore different signal extremes, low
power and high speed
Wireless
Handset
Mobile Industry
specific
standards
Enabling MIPI Physical Layer Test
Page 3
July, 2008
Digital Domain
Wireless Domain
Agilent Solution Offering
Wireless Protocol
Layer Validation
Wireless Physical
Layer Validation
Digital Protocol Layer
Debug / Validation
Protocol Viewer
Digital Physical Layer
Debug / Validation
Pulse Function
Arbitrary Noise
Generator
BERT
Dig RF tester
Wide Band Oscilloscope
Enabling MIPI Physical Layer Test
Page 4
July, 2008
The MIPI Evolution
Test & Debug Port
BB-IC debug ports
Shared pins
Physical layers
Protocol layers
Status
DigRF v3
DigRF v3
- Shipping today
MIPI DPhy
DSI Display
- In development
CSI Camera
- DPhy is in definition,
almost final
- Physical layer solution
volume Shipment Oct 08
Unipro Other
MIPI MPhy
DigRF v4
- MPhy definition to
start end of the year
- DPhy Solution also
requires Logic Analyzer.
Minor adaptations to
configuration are possible
because standard is not
defined yet!
Enabling MIPI Physical Layer Test
Page 5
July, 2008
How to Get Confidence on the Physical Layer
Characterizing the Parameters
TX Tests:
Data bus timing
Transition times
Timing
Signal
Integrity
Levels
DC levels and AC swing
Low Power / High Speed mode
switching
Jitter
2.5G
3GPP
RX
MIPI D-Phy DSI
RX Tests:
Data bus timing
Min. pulsewidth
Sensitivity (min/max amplitude)
TX
BB-IC TX
DigRF v3
RX
MIPI D-Phy CSI
TX
RX
TX RF-IC
RX
MIPI D-Phy
WiMAX
Camera
Jitter Tolerance on Clock and Data
Differential and common mode, termination switching
Enabling MIPI Physical Layer Test
Page 6
July, 2008
Enabling MIPI D-PHY Physical Layer Test
Control the transition
MIPI D-PHY operates in two modes with dynamic transitions
Low Power
Signaling
Low Power Signal High Speed Signal
- Max 20 Mbit
- > 1 Gbit
-Single ended
-Differential
- CMOS
-LVDS
High Speed Digital Test
High Speed
Signal
Low Power
Signaling
The ParBERT 81250A
- Generates the signal you need
- Controls the sequences
- Forces the bus through low to high
speed transition and vice versa
- Glitch free change of timing parameters
Enabling MIPI Physical Layer Test
July, 2008
Enabling Physical Layer Test – Bit Error Testing
Stress your device to its limits
RX Tests: Sensitivity and jitter tolerance on clock and data
Expected
Data
Stress
RX
Device
Under
Test
Generator
Solution
Compare
Bit
Error
Ratio
Data Analyzer
Error Detector
- For several lanes at least 2 data and clock
- Devices show immunity at combined jitter testing; data and clock
needs to be tested independently
- For all kinds of jitter and stress test
- Jitter injection from 81150A via delay line to the ParBERT 81250A
High Speed Digital Test
Enabling MIPI Physical Layer Test
July, 2008
Enabling MIPI D-PHY Physical Layer Test
Characterization at your fingertips
Next Level of Performance and Convenience through Test Automation
N5990A Test Automation Software and MIPI Frame Generator
One button Rx and Tx
compliance tests and
characterization
• MIPI D-PHY Editor
• Pre-canned test pattern
• Calibrated test cases
• Easy post processing
• SQL data base interface
• Interaction with legacy
code
Enabling MIPI Physical Layer Test
Page 9
July,
2008
July
3, 2008
The Stimulus Test Setup
• Full coverage of stimulus signal generation with flexible signal conditioning
• Full Stress / Jitter tolerance testing
• Modular configuration for 1, 2 or multiple lanes
• Test Automation Software with MIPI Editor and pre-canned test pattern
• Multi-application support by ParBERT platform (e.g. HDMI)
• Depending on device design, full BER Analysis possible
Economic High speed Tester
3.35 Gbit/s
81150A Noise / Jitter source
81250A ParBERT
N5990A Test
Automation Software
High Speed Digital Test
Multi Application Tester
7 Gbit/s
E4438C Signal Generator /
clock source
81150A Noise / Jitter source
81250A ParBERT
N5990A Test
Automation Software
Enabling MIPI Physical Layer Test
July, 2008
Transition
between LP and HS
is critical
Generate the signal you need
Control and synchronize transitions
between different modes and channels
N5990A Test
Automation Software
High Speed
From nominal to
stress test
Agilent 81250A ParBERT
Agilent 81150A Noise Source
Agilent MIPI D-PHY Physical Layer Test
Ease-of-use through test automation
Multiple Lanes
with separate Clock
and Data
Low Power
Signaling
High Speed Digital Test
High Speed
Signal
Low Power
Signaling
Enabling MIPI Physical Layer Test
July, 2008
Appendix
Test Details
Enabling MIPI Physical Layer Test
Page 12
July, 2008
Design For Testability
Display
RX
MIPI D-Phy DSI
MIPI D-Phy
TX
TX
RF-IC
RX
BB-IC TX
RX
MIPI D-Phy CSI
RX
MIPI M-Phy
TX
Camera
Provide Access Point and
Method by Design /
Standardization
Enabling MIPI Physical Layer Test
Page 13
July, 2008
Recommended ParBERT MIPI D-PHY Configurations
Configurations vary in max data rate and jitter injection
capabilities:
3.35 GBit/s economic with 500 ps jitter injection capability
The maximum data rate of 3.35 GBit/s limits the usage of ParBERT
modules for other standards respectively applications
7 GBit/s multi-application setup
With 7GBit/s ParBERT modules the setup can support a wider range of
standards and applications
Enabling MIPI Physical Layer Test
Page 14
July,
2008
July
3, 2008
Jitter Injection Capabilities of ParBERT Configurations
Separate jitter on clock and
data lanes
Economic Solution
Multi-application solution
Possible –
setup suggests clean clock lane and
jitter on data lanes only
Possible –
setup suggests clean clock lane and
jitter on data lanes only
500ps delay line
200ps delay line plus
jittered ParBERT clock (see below)
Not possible
Data rate dependent – example
Jitter capabilities
Externally jittered
ParBERT clock
UI
at 1 GBit/s
78
7
.15
.4
4
40
MHz
Max supported jitter
Data
500ps
Jittered Clock + 200ps
Clock
500ps (capability not used in setup)
Jittered Clock + 200ps
(capability not used in setup)
Enabling MIPI Physical Layer Test
Page 15
July,
2008
July
3, 2008
Noise Generation Capability of ParBERT Configurations
Same for economic and multiple application setups
Suggest to test either noise or jitter at one time
Îuse the same equipment for both and change setup
(parallel test would require more accessories)
Perform noise test only on one lane at a time
Îin a setup with mutliple data lanes this means to test all lanes
sequentially and change setup in-between
(parallel test would require more accessories)
Enabling MIPI Physical Layer Test
Page 16
July,
2008
July
3, 2008
Economic ParBERT 3.35 GBit/s System Configuration –
Single Lane Shown
Scope Trigger
Trigger Out
LP Signal Generation
675M
675M
675M
675M
Generator Generator Generator Generator
internal channel add
internal channel add
Data Out
Data Out
Noise
Generation
11667B
Pwr Splitter
15438A
2ns
Transition
Time
Converter
11667B
Pwr Splitter
1250-2015
8493C 11636B 8493C
Adapter
6dB Pwr Divider 6dB
Lane 3
Lane 3
Delay
Control In
3.35G
3.35G
Generator Generator
Data Out
15432B
250ps
Transition
Time
Converter
Lane 4
Lane 4
HS Signal Generation
15438A
2ns
Transition
Time
Converter
11636B
Pwr Divider
11636B
Pwr Divider
1250-1159
Adapter
all SMA cables
15442-61601
11636B
Pwr Divider
Start In
Lane 2
Lane 2
Lane 1
Data Out Lane 1
15432B
11636B
11636B
250ps
Pwr Divider Pwr Divider
Transition
Time
11636B
1250-1159 Pwr Divider
Converter
Adapter
1250-2015
Adapter
81150A opt 002
+ D-Phy Clock or Data Lane
11636B
11636B
Pwr Divider Pwr Divider
11636B
Pwr Divider
81150A opt 002
Jitter Generation
(4 lanes shown)
81150A opt 002
Enabling MIPI Physical Layer Test
Page 17
July,
2008
July
3, 2008
Economic ParBERT 3.35 GBit/s System Summary
1 clock
1 data lane
1 clock
2 data lanes
1 clock
4 data lanes
2
2
4
4
4
3
3
3
6
6
6
5 (2 cables not used)
5
5
10
10
10
8 (2 cables not used)
LP signaling and HS offset
HS signaling
HS transition time
LP transition time, 3rd part product
combine HS and LP signals
signal connect
HS clock
LP clock
Signal Generation
4x 675MBit/s generators
2x 3.35GBit/s generators
250ps transition time converter
2ns transition time converter
power splitter
set of 4 SMA cables
1x E4832A with 4x E4838A
1x E4861B with 2x E4862B
15432B
15438A
11667B
15442-61601
Other ParBERT Items
clock module
clock module
ParBERT mainframe
IEEE 1394 PC link to VXI
ParBERT 81250 software license
Laptop including PCMCIA IEEE 1394 card
power divider
set of 4 SMA cables
E4808A
E4805B
81250A-149
81250A-013
E4875A
81250A-015
11636B
15442-61601
1
1
1
1
1
1
1
1 (1 cable not used)
1
1
1
1
1
1
1
1 (1 cable not used)
1
1
1
1
1
1
1
1 (1 cable not used)
Jitter Generation
81150A with two channels
BNC to SMA adapter
SMA to SMA adapter
power divider
set of 4 SMA cables
81150A, option 002
1250-2015
1250-1159
11636B
15442-61601
1
1
0
1
1 (1 cable not used)
1
1
2
3
2 (3 cables not used)
2
2
4
6
3 (2 cables not used)
2
2
2
0
0
0
2
0
0
0
0
2
0
0
0
1
2
2
2
1
2
2
2
1
2
2
2
1
1
3
1 (2 cables not used)
-1
1
1
3
1 (2 cables not used)
-2
1
1
4
1 (2 cables not used)
-1
Noise Generation (one lane - use equipment for jitter generation)
power divider
11636B
6dB attenuator
8493C
SMA to SMA adapter
1250-1159
BNC to SMA adapter
1250-2015
set of 4 SMA cables
15442-61601
Comments
software
PC to operate the setup
split LP trigger out to HS and scope
trigger signals
noise generator
81150 output adapter
connect power dividers
split noise to ParBERT delay lines
re-use power divider for jitter generation
re-use adapter for jitter generation
re-use adapter for jitter generation
re-use cables for jitter generation
Other
9GHz or better DSO 90000 Scope
differential probe
differential probe head
high impedance probe head
options t.b.d
1169A
5380A
t.b.d
Control Software and Test Automation
LAN hub
LAN cable
set of 4 SMA cables
set of 4 SMA cables
N5990A option t.b.d
no Agilent part
no Agilent part
15442-61601
15442-61601
timing and level measurement with DSO
timing and level measurement with DSO
level measurement with DSO
control software
remote control instruments
remote control instruments
to connect scope
balance unused SMA cables
Enabling MIPI Physical Layer Test
Page 18
July,
2008
July
3, 2008
Multi Application ParBERT 7 GBit/s System Configuration – Single Lane Shown
1250-1159 Adapter
Scope
Trigger
Clock In
11636B
Pwr Divider
HS Clock System
7G
Generator
11636B
Pwr Divider
10 MHz
Trigger Out
Start In
7G
Generator
1250-1743 Adapter 8120-1839 BNC cable
clean clock
clock w SJ
11636B
ESG 1
ESG 2
Pwr Divider
LP Clock and Data System
675M
Generator
675M
Generator
internal channel add
Data Out
675M
Generator
675M
Generator
internal channel add
Data Out
to D-Phy Clock Lane
(LP clock generation
not shown)
7G
Generator
Data Out
15432B
250ps
Transition
Time
Converter
11667B
Pwr Splitter
15438A
2ns
Transition
Time
Converter
8493C 11636B 8493C
6dB Pwr Divider 6dB
11667B
Pwr Splitter
1250-2015
Adapter
Clock In
HS Data System
15438A
2ns
Transition
Time
Converter
1250-1159
Adapter
11636B
Pwr Divider
11636B
Pwr Divider
Noise
Generation
Start In
Clock In
1250-1744
Adapter
Delay
Control In
7G
Generator
Data Out
15432B
250ps
Transition
Time
Converter
+ D-Phy Clock or Data Lane
Lane 2
Lane 1
Lane 4
Lane 3
11636B
11636B
11636B
11636B
Pwr
Divider
Pwr
Divider
Pwr Divider Pwr Divider
11636B
11636B
Pwr
Divider
1250-1159 Pwr Divider
Adapter
1250-2015
Adapter
81150A opt 002
Random Jitter Generation
(4 lanes shown)
81150A opt 002
Enabling MIPI Physical Layer Test
Page 19
July,
2008
July
3, 2008
Multi Application 7GBit/s System Summary
1 clock,
1 data lane
1 clock,
2 data lanes
1 clock,
4 data lanes
2
4
4
4
4
8
8
4
3
3
6
6
6
6
12
12
6
5 (2 cables not used)
5
10
10
10
10
20
20
10
8 (2 cables not used)
LP signaling and HS offset
HS signaling
HS transition time
LP transition time, 3rd part product
combine HS and LP signals
Comments
Signal Generation
4x 675MBit/s generators
7GBit/s generator
250ps transition time converter
2ns transition time converter
power splitter
adapter 3.5mm(f) to 2.4mm(m)
2.4mm 50 Ohm termination
3.5mm 50 Ohm termination
set of 4 SMA cables
1x E4832A with 4x E4838A
N4874B
15432B
15438A
11667B
N4911A-002
N4912A
1250-2206
15442-61601
Other ParBERT Items
clock module
clock module
ParBERT mainframe
IEEE 1394 PC link to VXI
ParBERT extender mainframe with IEEE1394 link
ParBERT 81250 software license
Laptop including PCMCIA IEEE 1394 card
BNC cable
power divider
ESG
adapter n to 3.5mm (m)
adapter n to 3.5mm (f)
SMA to SMA adapter
set of 4 SMA cables
E4809A
E4805B
81250A-149
81250A-013
81250A-152
E4875A
81250A-015
8120-1839
11636B
E4438C, options 1E5, 506, 601
1250-1743
1250-1744
1250-1159
15442-61601
2
1
1
1
0
1
1
1
3
2
1
1
1
2 (1 cable not used)
2
1
1
1
1
1
1
1
3
2
1
1
1
2 (1 cable not used)
2
1
1
1
1
1
1
1
3
2
1
1
1
2 (1 cable not used)
HS clock
LS clock
Jitter Generation
81150A with two channels
BNC to SMA adapter
SMA to SMA adapter
power divider
set of 4 SMA cables
81150A, option 002
1250-2015
1250-1159
11636B
15442-61601
1
1
0
1
1 (1 cable not used)
1
2
0
2
2 (2 cables not used)
1
2
4
6
3 (2 cables not used)
noise generator
81150 output adapter
connect power dividers
split noise to ParBERT delay lines
1, 2 or 4 needed to distribute noise
2
2
2
0
0
0
2
0
0
0
0
2
0
0
0
1
2
2
2
1
1
5
1 (2 cables not used)
-1
1
2
2
2
1
1
5
1 (2 cables not used)
-1
1
2
2
2
1
1
5
1 (2 cables not used)
-1
Noise Generation (one lane - use equipment for jitter generation)
power divider
11636B
6dB attenuator
8493C
SMA to SMA adapter
1250-1159
BNC to SMA adapter
1250-2015
set of 4 SMA cables
15442-61601
terminate unused outputs of 7G ParBERT
terminate unused outputs of 7G ParBERT
signal connect
PC to operate the setup
synchronize ESGs
clock and triggering
signal generators
ESG output to power divider
ESG output to SMA cable
combine power splitters for triggering
re-use power divider for jitter generation
re-use adapter for jitter generation
re-use adapter for jitter generation
re-use cables for jitter generation
Other
9GHz or better DSO 90000 Scope
differential probe
differential probe head
high impedance probe head
Control Software and Test Automation
LAN hub
LAN cable
set of 4 SMA cables
set of 4 SMA cables
options t.b.d
1169A
5380A
t.b.d
N5990A option t.b.d
no Agilent part
no Agilent part
15442-61601
15442-61601
timing and level measurement with DSO
timing and level measurement with DSO
level measurement with DSO
remote control instruments
remote control instruments
clock to data skew measurement with DSO
balance unused SMA cables
Enabling MIPI Physical Layer Test
Page 20
July,
2008
July
3, 2008
Combined D-PHY High Speed And Low Power Signal
Generated by ParBERT
Enabling MIPI Physical Layer Test
Page 21
July, 2008
Transition Details: High Speed Signaling to Low Power
Signaling
Enabling MIPI Physical Layer Test
Page 22
July, 2008
Voltage Levels as defined
1300mV
1300mV
1100mV
880mV
880mV
550mV
550mV
450mV
460mV
330mV
200mV
70mV
50mV
-50mV
-40mV
max Differential input high threshold VIDTH = 70mV
min Differential input low threshold VIDTL=-70mV
Enabling MIPI Physical Layer Test
Page 23
July, 2008
MIPI D-PHY Application Programming Tool for simple
editing of data rate, pattern, timing and levels
Enabling MIPI Physical Layer Test
Page 24
July, 2008
How Does D-Phy Compliance Test Work…
MIPI Standard Workgroup
(key industry players, including
Agilent, lead the effort)
defines
Base
Specification
owner
CTS is based on
main specification
subcontract
work
with
industry
leaders
University of New
Hampshire
Interoperability Lab
(UNH-IOL)
defines
Protocol
tester
Scopes
generic
test
description
MOI is based on
CTS
loan equipment
for CTS developement
Agilent
(LPT, DVD, HSDT)
Compliance
Test
Specification
(CTS)
defines
Method
of
Implementation
(MOI)
how to do
test with
specific
instrument
BERTs
Enabling MIPI Physical Layer Test
Page 25
July, 2008
Enabling MIPI D-PHY Physical Layer Test
Characterization at your fingertips
Next Level of Performance and Convenience through Test Automation
N5990A Test Automation Software and MIPI Frame Generator
One button Rx and Tx
compliance tests and
characterization
• MIPI D-PHY Editor
• Pre-canned test pattern
• Calibrated test cases
• Easy post processing
• SQL data base interface
• Interaction with legacy
code
Enabling MIPI Physical Layer Test
Page 26
July,
2008
July
3, 2008
ParBERT System Configuration
Timing and Trigger, based on 7 Gb/s data modules
10 MHz
ESG 1
Clock (clean)
ParBERT
Clock System
Start In
ESG 2
Clock (SJ)
ParBERT
HS Data System
Start In
ParBERT
LP Data System
Trigger Out
To Scope Trigger
• 1 BNC cable for 10 MHz synchronization
• 4 SMA cables for clock distribution + 1 power divider
• 5 SMA cables for trigger distribution + 2 power dividers
Enabling MIPI Physical Layer Test
Page 27
July, 2008
ParBERT System Configuration
High Speed Jitter Distribution, based on 7 GBit/s
data modules
ARB
Power Divider
To Delay Control Inputs
ParBERT
Clock System
ParBERT
HS Data System
ParBERT
LP Data System
• 1 BNC-to-SMA adapter
• 7 SMA cables
• 3 power dividers
Enabling MIPI Physical Layer Test
Page 28
July, 2008
Enabling MIPI D-PHY Physical Layer Test
High Speed Test and Characterization with
Agilent 81250A ParBERT
Agilent 81150A Pulse Function Arbitrary Noise Generator
Agilent N5990A Test Automation Platform
3 Reasons to go with 81250A:
81150A Noise Source
-
High Speed Digital Test
1. Full coverage of stimulus
signal with flexible & modular
signal & stress generation
2. Easy-to-use MIPI D-Phy
Editor and Test Automation
including pre-canned test
pattern
3. Depending on device design,
full BER analysis possible
Enabling MIPI Physical Layer Test
July, 2008
MIPI Test Software
• Features and Pattern
N5990A Test Automation and
MIPI Frame Generator
Enabling MIPI Physical
Agilent Layer
Restricted
Test
Page 30
July,
2008
July
3, 2008
Overview
MIPI Frame Generator N5990A-362
Manual Test Tool for MIPI Receiver Testing using the
81250A as a generic MIPI Stimulus
Enabling MIPI Physical Layer Test
Page 31
July,
2008
July
3, 2008
Features
Included:
• Automatically setting up the 81200A for generating MIPI
conformance signals and pattern
• Modify HS and LP pattern
• Modify Data Rates of HS and LP transmission
• Modify Timing between LP and HS data transfer switching
• Modify Voltage Levels
• Adding Jitter to HS data
Not included:
• Measure and analyze bit error ratio
• Generate complete video frames for testing displays
• Switching between Receiver and Transmitter mode
• PPI capability for DUT control
Enabling MIPI Physical Layer Test
Page 32
July,
2008
July
3, 2008
Pattern Capabilites
(beta)= already available in beta version end of March
(final)= will be part of the final version
Pure LP pattern transmission (beta)
Pure HS pattern transmission (beta)
Predefined pattern (high transition density, low transition
density, lonely 0/1 bit, PRBS) (beta)
Integrated protocol layer for LP-HS-LP transmission with
variable timing (beta)
LP Triggers (Table 8 MIPI Spec): Low-Power Data
Transmission, Ultra-Low Power State, Reset-Trigger (final)
Programmable Escape Mode State Machine (final)
User-defined pattern for LP and HS data separately
(transmission switch protocol will be automatically added by
the software)
Integrated 8/9 bit coding
Enabling MIPI Physical Layer Test
Page 33
July,
2008
July
3, 2008
Overview
N5990A Test Automation Software
•
•
•
•
•
Full test automation (Rx, Tx, Rx test system calibration)
Generic, common N5990A user interface
On- button compliance tests and expert mode for characterization,
debugging and margin test
Open, modular software platform
N5990A-010, -160, -260, -361 (-001 and -500 recommended)
Enabling MIPI Physical Layer Test
Page 34
July,
2008
July
3, 2008
ParBERT 81250A System Configuration
Jitter Injection Capabilities (1)
Economic solution (based on 3.4 Gb/s generator)
• 500 ps delay line, 200 MHz bandwidth
• All jitter types as available from 81150A (RJ, SJ, custom)
Multi – application solution (based on 7 Gb/s generator)
• 200 ps delay line + SJ from ESG
• Delay line can create any jitter type as available from 81150A
Enabling MIPI Physical Layer Test
Page 35
July, 2008
Generated Pattern
All measurements done into 50 Ohms
Low-power = 10MHz, high-speed = 1GHz
Enabling MIPI Physical Layer Test
Page 36
July, 2008
D-Phy Timing
MIN: 50ns
MIN:
40ns+4*UI
MAX:
85ns+6*UI
MIN:
145ns+10*UITHS-Prepare
MAX:
35ns+4*UI
• Wide range of flexibility
1GB/s: UI=1ns
HS-PREPARE:
MIN: 44ns
MAX: 91ns
HS-ZERO:
MIN: 64ns = 145ns+10*1ns-91ns
MAX:
35ns
MAX:
105ns+n*12*UI
MIN:
MIN: 40ns
max{n*8*UI,
MAX:
60ns+n*4*UI}
55ns+4*UI
n=1 forward direction HS mode
n=4 backward direction HS mode
UI: 1GB/s = 1ns
MIN:
100ns
Enabling MIPI Physical Layer Test
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July, 2008
THS-Prepare
Enabling MIPI Physical Layer Test
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July, 2008
THS-Zero
Enabling MIPI Physical Layer Test
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July, 2008
THS-Trail
Enabling MIPI Physical Layer Test
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July, 2008
Voltage Levels
1300mV
1300mV
1100mV
880mV
880mV
550mV
550mV
450mV
460mV
330mV
200mV
70mV
50mV
-50mV
-40mV
max Differential input high threshold VIDTH = 70mV
min Differential input low threshold VIDTL=-70mV
Enabling MIPI Physical Layer Test
Page 41
July, 2008
VOH-Max >1.2V with 3dB Attenuators
Enabling MIPI Physical Layer Test
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July, 2008
High Speed Offset Example 1: 47mV
Enabling MIPI Physical Layer Test
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July, 2008
High Speed Offset Example 2: 198mV
Enabling MIPI Physical Layer Test
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July, 2008
Transition Details: Low Power Signaling to High
Speed Signaling
Enabling MIPI Physical Layer Test
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July, 2008
Transition Details: High Speed Signaling to Low
Power Signaling
Enabling MIPI Physical Layer Test
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July, 2008
High Speed Signal Details
Enabling MIPI Physical Layer Test
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July, 2008
Spikes During Low Power Mode
MAX: 300
V*ps
MIN:
2*50ns
MIN:
20ns
MIN:
880mV
MAX:
550mV
300V*ps: 0.9V
1V
1.5V
2V
333ps
300ps
200ps
150ps
• Do complete low speed pattern including spikes with high-speed generator
• Max spike level: 1.8V (single ended)
• Spike and low speed data at same amplitude
Enabling MIPI Physical Layer Test
Page 48
July, 2008
Signal With Spikes
Enabling MIPI Physical Layer Test
Page 49
July, 2008
1.8V „1“-Spike
Enabling MIPI Physical Layer Test
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July, 2008
1.8V „0“-Spike
Enabling MIPI Physical Layer Test
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July, 2008