CONTENTS
................................................
1.
INTRODUCTION
1. 1 4280A Applications ...........................................
1.2
4280A Features .............................................
1. 3
C-V Characteristics of MOS Structures and pn Junctions
1.4
Wafer Capacitance Measurements ..................................
Page
1
1
1
...................
2
3
2.
........................
EVALUATION OF C-V/G-V CHARACTERISTICS
2. 1 C-V Measurement ............................................
2. 2
How to Calculate Semiconductor Parameters ..........................
6
6
7
3.
C-t
3. 1
(1)
(2)
3.2
CHARACTERISTICS and ZERBST ANALYSIS ........................
C-t Measurement .............................................
C-t Measurement Using Internal Bias Source ..........................
C-t Measurement Using External Bias Source .........................
Zerbst Analysis ..............................................
9
9
9
10
11
4.
DOPING PROFILE EVALUATION ...................................
4. 1 Doping Profile Measurement .....................................
12
12
( 4280A Technical Information )
l
Internal Bias Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
l
Sampling Mode Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
(Appendixes) ......................................................
I. Evaluation of pn Junction Capacitance Characteristics .......................
lI. Connection Mode (CONN MODE) ....................................
SamplePrograms ................................................
III.
(1) C-V Measurement Program ......................................
(2) C-t Measurement Program ......................................
4280A
IMHz
C METER/C-V
PLOTTER
14
14
15
16
17
21
1. INTRODUCTION
,
1. 1
4280A
ment is only lps, so the C-t characteristics of semiconductors having slow or fast transient properties, can be
obtained easily. C-t measurements can be used in Zerbst
analysis to calculate the minority carrier lifetime and surface generation velocity. Measured C-t values are also used
to calculate deep-level traps.
Applications
The HP model 4280A 1MHz C Meter/C-V Plotter is designed to measure the high-frequency Capacitance-Voltage
(C-V) and Capacitance-time (C-t) characteristics of semiconductor devices and materials. When testing Metal-Oxide
Semiconductors (MOS) or bipolar transistors, the 4280A
provides fully automatic measurements with improved
speed and accuracy. The 4280A is ideally suited for wafer
process evaluation and for development of new semiconductor devices.
n
This Application Note explains how to perform reliable
C-V and C-t characteristics measurements on semiconductor wafers using the 4280A. This note also contains a
procedure for calculating other semiconductor parameters
from measured C-V or C-t characteristics.
1. 2
n
4280A
High Accuracy
Features
The 4280A’s SYNC OUTPUT and EXT TRIGGER are
used to synchronize the 4280A with peripheral equipment, such as bias sources or thermal controllers. A
recorder output is also provided for hard copy analog
plotters. These features make the HP 4280A an ideal element for automatic C-t or B-T (Bias Temperature) systems.
and High Resolution
The 4280A’s CABLE LENGTH CAL capability provides
compensation for residuals of the external cables. ZERO
OPEN provides compensation for parallel capacitance
and conductance in the test fixture. The 4280A’s twoterminal pair measurement method virtually eliminates
the effects of external noise. All of these 4280A features
combine to provide capability for precision C and G
measurements.
C-V and G-V
Semiconductor
Measurement
Applications
Versatility
Covers
Table
4280A
Key Specifications
C-G
c-t
Test Signal
Frequency : 1 MHz f 0.01 %
OSC Level : lOmVrms, 30mVrms *lot
Internal DC
Bias Source
: C,
: c-t,
Function :
output
:
Range
Resolution :
Basic
:
Accuracy
G,
G-t ,
C-G
C . G-t
:,/,A,>,
0 - +lOOV, 3 digits
1 mV (max)
0.1%
Time
*l lo/&- 32s
Sweep Range *2(X number of measurement points)
Automatic swept bias measurements are made by setting
START V, STOP V, and STEP V. To allow the device
under test to reach stability, HOLD TIME and STEP DELAY TIME can also be set. This means that device characteristics are obtained after the device has attained thermal
equilibrium. The 4280A’s measurement accuracy insures
accurate calculation of device parameters such as flat band
voltage (Vfb) and minority carrier lifetime.
Easy-to-Obtain
l-l.
Measurement
Function
Most
The internal DC bias source can be set to from -lOOV to
+lOOV with 1mV (3-digit) resolution and 0.1% accuracy.
Even minute changes in the C-V or G-V characteristics
of a device can be measured accurately.
n
System Applications
Data measured at each bias point during a sweep are
stored in the 4280A’s measurement data buffer. All stored
data are then transfered to the controller at one time
(block-data output) when the sweep ends. Block-data
output reduces measurement time significantly.
The 4280A measures Capacitance (C) and Conductance
(G) with 0.1% accuracy and maximum 4-l/2-digit display
resolution (5l/2-digit resolution with opt. 001). The test
frequency is fiied at 1 MHz.
n
Automatic
Measurements, analysis, and plotting can be performed
automatically using the HP-IB. The 4280A outputs measured values in either of two formats: ASCII, or for fast
dats output, binary code.
Measurement
Range
C
G
: 1fF - 1.9 nF
: 10nS -12mS
Basic Accuracy 0.1 %
4-l/2 digits max.
and Display
(with opt. 001 C : 5-l/2 digits)
Digits
*l : Using an external bias source
** : Max number of measurement points is 9999.
C-t Characteristics
When performing C-t measurements, the 428OA’s measurement time interval (td) can be set from 10~s (with an external bias source) to 32s, with 10~s resolution and 0.02%
accuracy. The response time for a capacitance measureI -
1. 3
C-V Characteristics
and pn Junctions
of MOS Structures
Doping profile, flat band voltage (Vfb), and threshold
voltage (Vth) are essential parameters used for process
monitoring and for new semiconductor device evaluation.
These parameters can be derived from C-V measurements.
Benefits can include improved device quality and increased
production yield.
When high-frequency
carriers are generated
frequency is applied.
decrease even further,
pulsed bias is applied, minority
even more slowly than when high
This causes MOS capacitance to
as shown in Figure l-2 (c).
Semiconductor
n
C-V
Characteristics
of
MOS
Structures
Total capacitance of the MOS structure shown in Figure
l-l consists of oxide-layer capacitance (Cox) and depletion-layer capacitance (Cd). Total capacitance is obtained
from the equation below:
c = Cox * Cd
Cox + Cd
Figure 1-2 shows swept bias C-V characteristics of an ntype MOS structure. Curves (a), (b), and (c) show the
characteristics of the structure at low frequency, high
frequency, and high frequency with pulsed bias.
Figure
Inversion
The carrier distribution in the MOS structure during accumulation, depletion, and inversion is shown in Figure
1-3.
MOS
l-l
Structure
Accumulation
1
U
-.vG
“G
Bias
(1)
Accumulation
When positive voltage is applied to the gate, majority
carriers (electrons) accumulate on the Si-SiOz surface.
In this state, Cd is negligible and MOS capacitance is equal
to Cox, as shown in Figures l-2 and l-3.
(2)
Figure
l-2
T
n-type
Structure
material
I,
(1)
Accumulation
,,,P K”:‘,‘_‘. ..:.,:...:.
_.,,
(3 __------. .. . ... ..
7
Inversion
As the applied gate voltage becomes more negative, the
density of the minority carriers (holes) becomes greater
than the density of electrons at the surface of the depletion layer, forming the inversion layer.
-2
of a MOS
Elec*trons
d
c = Cox - Cd
Cox + Cd
When a state of deep inversion is reached, the width of the
depletion layer becomes constant. Holes in the inversion
layer are supplied by the generation of electron-hole pairs
caused by normal thermal agitation. This electron-hole
generation is relatively slow. At high frequencies, however, holes cannot be generated fast enough, so MOS
capacitance decreases and becomes constant as shown in
Figure 1-2 (b). But at lower frequencies, holes can be
generated fast enough to replenish the inversion layer.
Thus MOS capacitance becomes equal to Cox, as shown
in Figure l-2 for curve (a).
Characteristics
,,,p+2gizg:,”
. . . .:,:,..'.'.'..,,
. . . ..
Depletion
When the applied voltage goes negative, the majority
carriers are repelled from the SiOz surface. Donor ions
remain as fixed charges, forming the depletion layer. In
this state, MOS capacitance consists of Cox and Cd, which
varies with the applied gate voltage. The MOS capacitance
is calculated from this equation:
(3)
C-V
b -L
(2)
Depletion
CdL
_--_-_--. . . . . . . . 1
T
1
(3)
Figure
1-3
Carrier
InZsion
Distribution
of a MOS
Structure
C-V Characteristics
n
k
of pn Junctions
Figure l-4 shows how the depletion layer of a pn junction
is formed by fixed charges (donor and acceptor ions)
which concentrate at the junction of the p and n materials. The depletion layer capacitance, Cd, depends on the
applied bias voltage. Because Cd depends largely on the
impurity concentration of the substrate, the impurity
concentration and the built-in potential can be calculated
by measuring the pn structure’s C-V characteristics. Figure
1-5 shows an example of the C-V characteristics of a pn
junction.
1-4
(I)
Error
Correction
The 4280A has a CABLE LENGTH CALIBRATION
function that corrects errors occurring in cables up to five
meters long. With the test cable connected to the HIGH
terminal (open termination) the 4280A measures the open
admittance of the test cable and stores the measured value
in internal ROM. The stored value is then used to correct
the measured value of the device under test. The corrected value is displayed. CABLE LENGTH CAL doesn’t
need to be performed when the test cable is zero or one
meter.
Next, perform the ZERO OPEN measurement with the
test future and cables open (see Figure l-6). In this case
the 4280A measures stray capacitance/conductance of the
test fixture and stores the measurement in memory.
Depiction layer
Figure
When calculating such parameters as the impurity concentration or oxide layer thickness, precise capacitance measurement results are necessary. These results can be fed
back to control the wafer production process, thereby
increasing production yields, improving device quality,
and reducing test cost.
pn Junction
Last, press the CORRECTION ENABLE key. This causes
the 4280A to calculate error corrections, such as the one
shown below, then display the true value for the DUT.
YT
=
YM{~
1 -ZhYi
+ (RD
+ MYA)
-y
-YM(2Z&YA+R,,+RS)
’
(For floating DUT measurements)
Figure
1.4
1-5
C-V Characteristics
Wafer Capacitance
Where
YM
Yr
YA
Yz
Zo
of a pn Junction
Measurements
It has always been difficult to measure wafer capacitance
accurately when using a wafer prober, because of such inherent measurement errors as these:
l
l
l
l
k
Stray capacitance and conductance of test furture and
probes
Mutual inductance and admittance of test cables
Effects of environmental noise
Transient line noise when performing grounded device
measurements
The HP 4280A, however, virtually eliminates these errors.
The 4280A’s error correction function, two-terminal pair
measurement method, and grounded device measurement
capability enable the user to make accurate measurements
when using a wafer prober.
-3
is the measured value (admittance);
is the true value of the DUT (admittance);
is the open admittance of the test cable;
is the stray admittance of the test fixture;
is the characteristic impedance of the test cable,
a constant (be sure to use the specified cable
(HP No. 8120-4195) otherwise accurate error
correction will be impossible because of incorrect Z,); and
Rs and RD are the residual resistances of the test
signal source (Rs) and the measurement circuit
or I-V convertor (Ro) (also constants).
Stray admittance
\
‘““w
Low
I Wafer
Chuck
Figure
1-6
Open Condition
C-V
428OP
CHARRCTERISTICS
Sample= ME DIODE
Ccr= 43.351pFl
I.a
I
‘3: 8.5
\
CJ
I
,r-----
i
i
center conductor and outer conductor. Consequently the
effects of mutual interference between High and Low conductors cancel. And the outer conductor acts as a shield
to eliminate external noise.
/!
I
.-.-. -... Without
With
correction
correction
1
t
Difference in Measurement
without Error Correction
Results with and
Figure l-7 shows the difference in the results obtained
with and without error correction. It can be seen that the
effect of error correction is substantial.
(2) Two-Terminal
Pair Measurement
Method
Figure l-8 illustrates the two-terminal pair measurement
method. When using a coaxial cable in this method,
currents of equal and opposite direction flow down the
r----I ,
4280A----
duter
(a)
r-----
DUT Measurement
When testing wafers, connect the 4280A to the prober as
shown in Figure 1-9 (a). First cover the prober with a
shield box with dark interior to reduce the effects of
external noise and light. Next, as shown in Figure l-9 (b),
insulate the test cable from the shield box at the connector to avoid mixing noise from the shield box and the
outer conductor of the text cables. Further, as shown in
Figure 1-9 (c), use coaxial lead as close to the probe tip as
possible to decrease stray admittance; and short the outer
conductors of the High and Low cables to prevent errors
that could occur if the two-terminal pair were not formed.
Use of this technique will help insure stable, accurate
measurements.
1
Figure 1-7
(3) Grounded
When the device under test is grounded (for example,
the chuck of a wafer prober), select the “GROUNDED”
CONNECTION MODE. In the grounded mode, the current flowing in the DUT is measured correctly and noise
from ground is eliminated. This improves measurement
accuracy. The grounded measurement is performed as
shown in Figure 1-8 (b).
FLOATING
conductor
MODE
4280A
1
1 HIGH
--------- +
-
(Test
cable)
I-
DUT*
t
-
L---------J
(b)
GROUNDED
MODE
*DUT:
Figure
1-8
Two-Terminal
-4-
Device
Pair Measurement
Under
Method
Test
PTFE
2.
EVALUATION
OF C-V/G-V
CHARACTERISTICS
This chapter explains how to use the C-V characteristics
to calculate other parameters. This analysis is performed
when evaluating the quality of semiconductor processes.
The next example shows how to make a C-V measurement
using the HP-IB system shown in Figure 2-l (a). (Refer
to page 17 for a sample program.)
2. 1
( Example
C-V Measurement
of Measurment
Figure 2-1 shows two examples of C-V/G-V measurement
using the HP 4280A.
START V =
STOP V =
STEP V =
HOLD TIME =
STEP DELAY TIME =
In Figure 2-1 (a), the 4280A is shown controlled by an
HP 9826A Desktop Computer. Using an HP-IB controlled prober, many DUTs on a wafer can be tested automatically.
Figure 2-1 (b) shows a system that enables C-V/G-V
characteristics to be plotted on an X-Y recorder using
RECORDER OUTPUT of the 4280A. Normalized data
can be plotted by measuring the capacitance of the oxide
layer (Cox) before the sweep. Cox is then used as the
normalization constant and the 4280A’s math function
is used to plot C/Cox.
-__
I i! !i\li\
98611A + opt 655
98256A
7470A Plotter
(a) Using HP-IB
Recorder output
1
I
7035B X-Y Recorder
(b) Using X-Y Recorder
The System for C-V Measurement
-6-
-5v
5V
0.05v
10s
1Oms
The C-V characteristics are not accurate for bias from -5
to -2.5V. This is because the measurement was not performed under equilibrium conditions (i.e. the HOLD TIME
of 10s was not long enough). Figure 2-2 (b) shows the
result of a 40s HOLD TIME, performed at equilibrium.
This example shows how the HOLD TIME and STEP DELAY TIME can be chosen to obtain stable measurements.
This test was performed using the connection shown in
Figure 2-3. (Please see page 15 for details.)
--
Figure 2-1
>
Figure 2-2 (a) shows n-type MOS diode C-V characteristics
measured under the following conditions:
C-V
42EIOR
CHARRCTERISTICS
Sample= MO5 DIODE
C&x= 43.551pFl
--------
r-
I
L ______
---
I
A
---4280A
(a)
C-V
HOLD
TIME
Figure
= 10 s
2-3
Connection
(CNIO)
4280R
CHARRCTERISTICS
Sample= MOS DIODE
Cox= 43.55CpFl
2. 2 How to Calculate
(b) HOLD
TIME
Semiconductor
To calculate semiconductor parameters from C-V characteristics, the Cox (oxide layer capacitance) must be measured and the Nsub (impurity concentration of substrate)
obtained from the depletion layer capacitance must be
computed. The reliability of parameters largely depends
on the accuracy and resolution of measured Cox and
depletion layer capacitance. The 4280A can be used to
obtain sufficiently ac,curate parameters for this purpose.
= 40 s
L
J
Figure
2-2
C-V Characteristics
Parameters
of MOS Diode
Internal
Bias Source
The 4280A can provide a step-function ( /
) bias
sweep internally. The range of the bias sweep and the bias
step can be set using START V, STOP V, and STEP V.
Also, the HOLD TIME and STEP DELAY TIME are used
to insure that the DUT is tested under equiribrium conditions.
Therefore the most suitable measurement conditions
for the DUT are obtained.
Four bias sweep modes are available- ,’
, \
,
3%)
and v,
using these modes, the hysteresis of
C-V characteristics can be obtained.
-7-
Features
SWEEP
OV--7
START
STEP
/ HOLD’TIME
’ L
M,easurement
Time
(1) Nsub: impurity concentration of the substrate
Nsub can be calculated accurately from 4280A capacitance measurement data using the following equations, which assume that Nsub is constant in bulk.
Nsub =
4*l@fl
q’E0’ Esi
Using Nsub obtained in (I), we obtain the following:
Csf’b = 9.615X 10-l’ [F]
Cfb = 2.997 X 10-l’ [F]
Therefore Vfb is equal to -0.25 V.
where
(3) Qss/q: Surface charge density
In the oxide layer of a practical MOS device there is
a fixed surface charge. Mobil ions and ionized traps
make up the surface charge, so measured C-V characteristics differ from those of an ideal MOS. Since the
surface charge depends on (i) the semiconductor
orientation, (ii) oxidation, and (iii) annealing conditions, Qss is very important in the evaluation of wafer
processes. The surface charge density is calculated
from following equation:
is the Fermi potential, in Volts;
@f
Csmin is the minimum depletion layer capacitance, in Farads;
A
is the area of the gate (Al), in cm2;
ni
is the intrinsic carrier concentration per
cm3 ;
is the free space permittivity
EO
(8.854 X 10-‘4F/cm);
is the dielectric constant of Si (11.7);
Esi
is the magnitude of electronic charge
q
(1.602 X 10-l’ Coulomb);
k
is the Boltzmann constant
(1.38 X 10-23J/K); and
T
is the absolute temperature, in K.
-
Figure 2-2(b) shows that Csmin = 13.81 X 10-12F.
And by the method of successiveapproximation, we
find Nsub:
Qss _ Cox
-q
I%ls-Vfbl
where @MS is the difference in the work functions of
semiconductor (Si) and metal (Al). In this MOS
diode, the following hold.
@f = -0.3061 V
@MS = -0.6 - @f = -0.2939V
Nsub = 1.406 X 10” [l/cm31
Therefore,
where
A
T
- Qss = 1.193 X 10”
q
= 0.001 cm2, and
= 293 K.
(2) Vfb: flat band voltage
For practical MOS structures, a negative gate voltage
is needed to produce the flat band condition. This is
because there are positive surface charges in the oxide
layer and a difference in the work functions of Semiconductor (Si) and metal (Al). Vfb is obtained from
the gate voltage. Surface charge density and threshold voltage are obtained from Vfb.
Vfb is determined using flat band capacitance, Cfb,
which is calculated from the following equation:
[l/cm31
(4) Vth: threshold voltage
Vth is an important parameter in the analysis of
MOSFET’s Vth is defined by the following equation:
Vth = Vfb + (2#f-$-$)
where Qb is the fixed charge per unit area in the
depletion layer and is defined as follows:
In this MOS diode,
cfb = cox - csfb
cox+ cd-b
Qb = 1.690 X lo-’
where Csfb is the depletion layer capacitance under
flat band condition and is defined by the following
equations:
-8-
Therefore
Vth = -1.25OV
[coulomb/cm’
]
3.
k
C-t
CHARACTERISTICS
and ZERBST
The C-t measurements are sent to the X-Y recorder
through the RECORDER OUTPUT. Using the HP-IB as
shown in Figure 3-2, the C-t measurement and Zerbst
analysis and plotting can be automated. This section
describes C-t measurement as shown in Figure 3-2 (Page
21 shows a sample program.).
This chapter explains how to measure C-t characteristics
of a MOS diode using the 4280A, and how to calculate
rgeff and So from these characteristics.
Tgeff (minority carrier lifetime in semiconductor bulk)
and So (surface generation velocity) are very important
parameters for evaluating the loss that occurs in chargecoupled devices (CCD) during charge transmission.
Measurement of Tgeff and So is essential for the evaluation of Si wafers and for the study of new devices. Since
Tgeff and So are obtained by the Zerbst analysis of the
C-t characteristics, these parameters can be calculated
accurately using C-t data measured by the 4280A.
3. 1
k
ANALYSIS
PULSE
V -~-
3
‘2
C-t Measurement
INT
EXT
th
C-t:
C-t:
lOmsto32s
10 ps to 32 s
o-
C-t characteristics of a MOS structure show the capacitance change after a pulse bias is applied which drives the
structure first into accumulation then into deep inversion.
Since the time constant of minority carrier generation is
relatively long, the MOS structure requires time to reach
equilibrium after the pulse bias is applied. Immediately
after the pulse bias is applied, the depletion layer extends
more widely then the depletion layer becomes narrower the MOS structure approaches equilibrium as more and
more minority carriers are generated. Finally, the depletion layer reaches its equilibrium width. This proves
charge neutrality. The C-t characteristics are obtained
from this change in the depletion layer width (Figure
3-l).
----p--d
MEAS
V,
PULSE
V : 0 to f 100 V
$Time’
1 Measurement
1 time interval:
The HP 4280A offers two C-t measuring methods:
(1) using the 4280A’s internal bias source as the pulse
source (INT C-t), and
(2) using an external bias source (EXT C-t).
--
0 td
I
,,
INT
C-t:
EXT
C-t : 10~s
Time
(t)
2td
Figure 3-1
C-t Measurement
One of these methods is selected in accordance with the
properties of the DUT and the measurement objectives.
(I)
k
C-t Measurement
Using the Internal
In this mode, the measurement
time interval (td) can be set
from 10 ms to 32 s. To set up
the C-t measurement, set the
parameters Pulse V, Meas V, th,
td, and NO OF RDNGS (number of measurements) as shown
in Figure 3-l. When the sweep
starts, PULSE V bias is applied
to the DUT during th, then the
bias changes to MEAS V. This
changing point defines t = 0.
Then measurements are made
at intervals of td until the NO
OF RDNGS is complete. Each
measurement is made in the
middle of the measurement interval.
Bias Source
9826A
Desk-Top
98611A
98256A
-&-.
Computer
+ opt.655
/! i\\\\’
(HP 10833B)
Programmable
Generator
4280A
Pulse*
‘-I
*A pulse generator
is
used for EXT.- C-t.
ii
7470
Plotter
I I
---1
I
I b
L
Prober
Figure 3-2
Example
-9-
System for C-t Measurement
and Zerbst Analysis
lOmsto32s
to 32 s
( Example
of the 4280A as shown in Figure 3-5. Also connect the
pulse generator’s EXT INPUT terminal to the 4280A’s
SYNC OUTPUT terminal.
Match the pulse width of the pulse generator to that of
the 4280A so a pulse bias synchronized with 4280A can
be applied to the DUT. If the -pulse generator has an EXT
WIDTH function, then the pulse bias width can be set
equal to th. (The HP 8112A Programmable Pulse Generator has this function.)
of Measurement)
Figure 3-3 shows C-t characteristics for an n-type MOS
diode measured under the following conditions:
PULSEV = 5V
MEASV
= -5V
NOOF RDNGS = 60
th
= 5s
td
= 1s
*EXT SLOW: td 2 200 /JS
EXT FAST: td& 10~s
The MOS diode is forced into accumulation by applying a
5 V bias for 5 s then the bias is changed to -5 V. 60
measurements are then made at intervals of 1 s.
( Example
Figure 3-4 shows a graph of 100 C-t measurements that
were taken at intervals of 10 ms using the block mode
data output (see page 1).
Data with 4-digit resolution can be obtained with td as
short as 10 ms (with opt. OOl), so minute changes of
capacitance can be resolved for accurate Zerbst analysis.
Parameter
NO OF RDNGS:
th:
td:
l
Figure 3-3
C-t Characteristics
of a MOS Diode
)
. 4280A
Measurement Function:
Measurement Speed:
Connection Mode:
4280R
C-t
CHRRACTERISTICS
Sample= no5 DIODE
Vp”lse.
5.0[“,
“near= -5.BCV1
of Measurement
In this example, an HP 8112A Programmable Pulse
Generator is used as an external pulse bias source for
measuring the C-t characteristics of a MOS diode. Set the
4280A and 8112A as follows:
C-t
MED
CN 13 (EXT FAST C-t)
50
1 ms
lO/ls
8112A
Mode:
Output Levels:
Transition mode:
External width
High=2V
Low=-5V
Fastest transition (fixed)
Figure 3-6 shows C-t measurement results obtained under
these test conditions. Even fast C-t characteristics can be
measured reliably. Figure 3-7 shows the connections for
EXT FAST C-t measurement (see page 15 for details
about connection).
(INT C-t)
-A-----;
4280A (Rear Danel)
L
Figure 3-4
C-t Characteristics
(td = IO ms)
(2) C-t Measurement
using the Block Mode
Using an External
Output of pulse generator
Bias Source
By using a pulse generator with fast rise time, C-t characteristics with td 2 10 ns can be obtained.
*I Match the pulse width of the
pulse generator to th.
Figure 3-5
Connect the OUTPUT terminal of the pulse generator
to the EXT BIAS terminal (EXT SLOW or EXT FAST)*
-
IO
Connecting the 4280A
Bias Source
I
I
w
to an External
t
C-t
Sample=
MOS
"puire=
‘On=
2.0~"1
27.5B[pF1
"mar=
3. 2
428Ofl
CHARACTERISTICS
Zerbst Analysis
Figure 3-8 shows the Zerbst characteristics obtained by
analyzing the C-t characteristics shown in Figure 3-3. The
minority carrier lifetime, rgeff, and the surface generation
velocity, So are calculated from Zerbst characteristics.
-5.0["1
Zerbst characteristics can be obtained by plotting the
following data.
- Cfin C
o.oo”““““““““‘l
Figure 3-6
I
.2
Time
.3
Cmsecl
.4 j “(
1
vS
.5’
(X axis)
Measurement Results for a MOS Diode in
the EXT C-t Mode (td = 10 Jo)
(Y axis)
where
C
is the measured capacitance, in Farads;
Cfin is the final (equilibrium) capacitance, in Farads;
Cox is the capacitance of the oxide layer, in Farads.
First, approximate the middle part of the Zerbst curve as
a straight line and determine the slope (m) and the y-axis
intercept (A). rgeff and So are obtained from the following equations:
Pulse
Generator
(8112A)
I
L-----------l
1
7geff = 2 .nl
.- cox
Nsub
Cfin ‘Y
I
+
4280A
Figure 3-7
Connection
esi - fo ‘A
cox
Mode (CN13)
Sampling
Mode
isI
.A
[ cm/s1
Measurement
High-resolution C-t measurement can be made in the
sampling mode even when the measurement time interval
(td) is as short as IO/B.
most suitable value for each measurement, t (= k-td).
This increases the efficiency of measurement, another advantage of this method.
This figure shows how the 4280A makes repeated measurements with a very short sampling at t = k - td (k = 1,
2 . . ). Usually the sampling time ts is l/5 of k-td. Next
the’ integrator circuit of the dual-slope A/D convertor of
the 4280A is charged repeatedly (at each sample) until
the total of ts reaches the integration time (tm) of an
ordinary measurement method (such as the INT C-t measurement). The C (G). measurement is made with an
resolution of 3 to 4 digits.
The sampling mode permits measurement of even very
fast C-t characteristics, so fast that they couldn’t be measured until now. Even phenomena with very short time
constants can be evaluated by the 4280A.
For example, when the measurement speed is FAST and
tdislO~s,atk=l(t=lO~s),
ts = 2/B
Number of samples = 500
at k = 20 (t = 200 ps) then,
ts = 40/B
Number of samples = 25
th
0 k.td
Number of
1
Measurement
The number of samples decreases as t (= k - td) increases
because the sampling time (ts) can be set larger as t increases. The number of samples is set automatically to the
-II
l-l
0 k.td
2
Measurement
(measurement
-
rL....JL
0 k.td
3
in the Sampling Mode
time t = k- td)
"
where
ni
is the intrinsic carrier concentration, per cm3 ;
Nsub is the impurity concentration in the substrate,
esi is the dielectric constant of Si (equals 11.7);
is the permittivity of free space, (8.854 X
EO
lo-14F/cm) and
A
is the area of the gate, in cm2.
Zerbst
Sample=
CHRRACTERISTICS
MO5 DIODE
"p"lSS=
5.@I",
cox= 43.55CpFl
"Was=
Cf In=
428Ofl
-5.BI",
9.67LpFl
From Figure 3-8 we obtain
m
‘u 2.999, A = 0.2956
Cox = 43.55 pF, Cfin = 9.67 pF,
Nsub = 1.406 X 10” cm3 (See page 8.)
And also
rgeff = 1.625 X IO-’ s
= 6.498 X 10-l cm/s
si
= 293 K, A = 0.001 cm2)
A computer can be used with the HP 4280A to obtain
rgeff and So more easily.
Figure 3-8
4.
DOPING
PROFILE
(g
EVALUATION
In method (2), the pulse bias is generated with the internal bias source in the ( -T ) mode and measurements are
made as shown in Figure 4-l. If the capacitance is measured in pulsed C-V measurement as soon as possible after
pulse bias is applied and before the inversion layer is
formed, then the doping profile can be evaluated deeper
in the substrate. Thus, the shorter the bias settling time
and measurement time are, the better.
The doping profile of a MOS structure can be obtained
from C-V measurement results. The width of the depletion layer and the change in capacitance with applied bias
voltage depend on doping concentration. The doping
profile is calculated from the following equations:
W = A-esi-ee
Zerbst Characteristics
The settling time of the interval bias source (99.9%) for
the 4280A is about (0.05 AV + 1.7) ms (e.g. -5 V + 5 V
takes about 2.2 ms). It takes about 15 ms to measure
capacitance with 3-l/2-digit accuracy, so this measurement is usually made before the inversion layer forms.
- 1)
cox
l
where
C
W
is the measurement capacitance, in Farads; and
is the depth, in cm.
The 4280A’s internal dc bias can be set between -100 V
to +lOOV, so heavily doped substrates can be characterized. Reliability of results are enabled by the 428OA’s
high accuracy (best 0.1%) in measuring capacitance.
4. 1
Doping
Profile
If the inversion layer forms within several ms, method (3)
is the best choice (pulsed C-V measurement in the EXT
C-t mode). Set the parameters for EXT C-t measurement
(refer to 3. 1) as follows:
i) th is the accumulation time (see Figure 4-l.)
ii) td is the wait time (see Figure 4-l.)
iii) NO OF RDNGS is set to 1.
This makes the pulsed C-V measurement possible in the
EXT C-t mode, just as in method (2). The pulse bias level
is set under HP-IB control. Using a pulse generator with
fast rise time, the wait time and the measurement time
can be shortened to 10 /-LSand 2 ps. (See page 11 for the
EXT FAST C-t mode and td = 10 vs.) Therefore doping
concentration can be measured deep in the substrate even
in devices with fast responses.
Measurement
The 4280A can be used in any of three ways to make C-V
measurements. In each method, the doping profile is
computed from C-V data using an HP-IB controller.
(1) C-V measurement using/mode
(2) Pulsed C-V measurement
(Pulse bias is controlled by a computer program.)
(3) Pulse C-V measurement in C-t mode
(Pulse bias is controlled by a computer program.)
Method (1) uses C-V measurement as explained in chapter
2. The pulsed C-V techniques of (2) and (3) extend the
depletion layer more deeply so that doping concentration
is measured deeper in the substrate.
-
Figure 4-2 shows the doping profile for a MOS diode obtained by method (2). In this measurement, the connection shown in Figure 2-3 is used.
I2 -
d
Figure 4-3 shows the doping profile of a MOS diode measured under the following test conditions, using the system
shown in Figure 4-4 and method (3).
I+.! LAccumulation
. 428QA
Measurement Function:
Measurement Speed:
Connection Mode:
time*l
C-t
MED
CN13 (see the page 15)
Parameters
NO OF RDNGS: 1
th:
2 ms
td:
lO/.Js
-L-L I
Bias step
. 8112A
Mode:
Output Level:
External width
Vacc, Vinv, and Bias step are
set by HP-IB control (Figure
4-1 shows the Vacc, Vinv,
and bias step.)
DOPING
Sample=
-r----
I
Figure 4-1
4280R
PROFILE
.
4280R
PROFILE
MOS DIODE
1.0
1.5
DISTRNCE
Cum1
Doping
,kWl$,,
2.0
Profile
8112A Programmable
Pulse Generator
(or 8160A, etc.)
Example
’
0.5
j
’ ’
1.0
’
’
1.5
DISTRNCE
9826A
Desk-Top Computer
Figure 4-4
-8..
Pulsed C-V Measurement
DOPING
,,,,,,,,I,,,,,,,,,
Figure 4-2
*1 : Time during which
accumulation state
is held.
: Bias settling time
Time
MOS DIODE
0.5
--r
-
Figure 4-3
’
S
..~
98611A + opt.655
98256A
-?-
DUT
System for Doping
-
Profile
13 -
Measurement
’
Doping Profile
(EXT C-t Mode)
7470A Plotter
b
j
Cum1
“?qqV
p>““._
m -/. i! \\\\\i
’ ’
2.0
in the EXT C-t Mode
’
2.5
<Appendixes>
I.
Evaluation of pn Junction
Characteristics
Capacitance
ND-NA
A
The pn junction is as important as MOS as a basic IC element. Many pn junction parameters, such as impurity
concentration, and built-in potential, can be obtained
from the C-V characteristics obtained by the HP4280A.
+--DePl&ion---+
layer
QQQQQ;
Q8$Qwn
The following two models are valid for pn junctions.
(I)
Abrupt
Distancex
pn Junctions
An abrupt pn junction is formed when the impurity concentration changes abruptly at the junction from acceptor
impurities (NA) to donor impurities (ND). This is shown
in Figure I-l. Especially, if NA >> ND (or NA << ND),
then a one-sided abrupt junction, p+ -n (or p-n’),
is
obtained.
(2)
Linearly
l
Graded
ND : Donor impurities
NA : Acceptor impurities
Figure I-l
The Abrupt
pn Junction
pn Junctions
A linearly graded pn junction is formed when the impurity concentration changes linearly near the junction
from NA to ND. Figure I-2 shows one example.
ND-NA
t
The abrupt junction is usual for shallow diffused pn junctions, and the linearly graded junction for deep diffused
pn junctions. Also, the metal-semiconductor contact in
a Schottky junction is identical to the one-sided abrupt
junction using the abrupt approximation.
Distancex
Table I-l shows the theoretical equations describing C-V
characteristics of each model and shows how to calculate
parameters.
Abrupt
C
pn Junction
where
C
V
Nsub
per unit area
[
a”
(Vbi+V)
C = [ ,,~;“d~<$]
a&
By graphing V (x-axis) YS l/C* (y-axis)
Vbi
Nsub or a
Nsub =&
[ l/cm3 ]
Vbl =$
[VI
N W) = +
[$$i)]
By graphing V (x-axis) vs l/C3 (y-axis)
12
4
d
q.es* .nl ’ licm ’
-’
m
IV1
where
m LSthe slope, and A IS the intercept
of y-axis.
Cannot be determined from C-V
characteristics.
I l/cm31
W=2c%
where
TableI-
A
1 cm 1
C
is the area of the gate m cm’.
Evaluation
of pn Junction
-
I4 ~
Graded pn Junction
per unit area
=*(Vbi+V)
Vbi =a
where
m 1s the slope, and A is the Intercept
of y-axis.
Doping
Profile
“3
is the capacitance of depletion layer, m Frads;
is the reverse bias, m Volts;
is the impurity concentration of substrate per cm3
(IfN*>>N,,,
thenNsub = N,,.);
is the built-m in potential, in Volts;
is the Impurity gradient, per cm4;
is the semiconductor permittivity, in Frads per cm; and
is the magnitude of electronic charge, in Coulombs.
Vbl
a
6s
q
.zB
.E
Y
ii
2
Y
ti
5
PC
%
,z
“0
2
The Linearly
Linearly Graded pn Junction
(one-sided)
= Jm
or
L-C2 -A
rheoretical Equation
11C-V characteristics
Figure I-2
Capacitance
II.
Connection
Mode
(CONN
MODE)
4280A has 14 connection modes (CONN MODE), which
are selected according to the DUT and measuring system.
(1)
$00”
Connection
Mode for Measurement
of floating
or
grounded DUT using internal or external BiasSource
Figure II-1 (a) and (b) show the CONN MODE for measurement of floating DUT and grounded DUT using the
internal bias source. Also, Figure II-2 shows CONN
MODE for fast measurement of C-t characteristics. (EXT
FAST C-t: measurement time interval, td 2 200 ps) using
an external bias source (pulse generator) for both floating
and grounded DUTs.
(2)
Connection
Mode for more accurate
using External Error Correction
* 4280:
I i---?----J
4280A
(b) CN15
(a) CNlt!
(FLOATING)
Measurement,
Figure II-I
Figure II-3 (a) shows the distribution of the stray admittances and residual impedances (due to probes, etc.) that
exist in most measuring systems. Figure II-3 (b) is the
equivalent circuit of (a). It is possible to measure the
residual impedances using CONN MODE (CN21 to 23)
then to eliminate residuals using a computer.
(GROUNDED)
Connection for Measurements
and Grounded DUTs
on Floating
This will result in a more accurate measurement of the admittance of a DUT.
(3)
b
Connection
Mode for fast Measurement
Characteristics
of C-t
When very fast C-t characteristics are obtained, the measurement time interval td may be as short as 10 /LS(EXT
FAST C-t). In this case, use CONN MODE CN13 (shown in
Figure n-4), which bypassesthe 4280A’s filter circuit. This
allows fast pulse bias to be applied and permits C-t measurement with td as short as 10~s to be performed.
(a) CN12
FigurelI-2
Reference plane
(a) Distribution
CN17
(GROUNDED)
Connection for EXT SLOW C-t Measurement
(td 2 200 /JS)
Reference plane
of Stray Admittance/Residual
Reference plane
(b)
(FLOATING)
.C
1
Impedance
Reference plane
External bias
4280A
(b) The Equivalent Circuit for (a)
Figure II-4
FigureJI-3
Errors in a Measurement
I
----------2
I
I
System
I5 -
Connection
(CN13)
for EXT FAST C-t Measurement
IIL
Sample
Program
These programs must be run using the measurement
SYSterns shown in Figures 2-1 and 3-2 (a pulse generator is
not needed).
Shown below are flow chart (Figure ill-1) and listings of
the two programs that are used in this application
note
(Refer to 2.1 of page 6 and 3.1 (1) of page 9).
(1) Program for C-V characteristics
measurement
(2) Program for C-t characteristics
measurement
(
1: Subroutine
Name (
START
1
4
Initialization
(Parameter
of variables
I
ut of conditions
measurement
- input 1
I
(Measure )
( copy )
(End)
(1)
END
( Measure > of C-V Measurement
1
(2)
(Measure
> of C-t Measurement
r
Measurement
Measurement
4
( Ext _ correction 1
External error
correction
Figure m-1
1
Flow Chart of C-V/C-t
-
16 -
Measurent
Programs
] (Ctmeas)