8M x 18, 4M x 32, 4M x 36 144Mb Sync Burst

Preliminary
GS8128018/32/36GT-400/333/250/200
400 MHz–200 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
8M x 18, 4M x 32, 4M x 36
144Mb Sync Burst SRAMs
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 6/6 RoHS-compliant 100-lead TQFP package
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Functional Description
Applications
The GS8128018/36GT is a 150,994,944-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enables (E1 and E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Core and Interface Voltages
The GS8128018/36GT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Rev: 1.00 9/2015
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-400
2.5
2.5
-333
2.5
3.0
-250
2.5
4.0
-200
3.0
5.0
Unit
ns
ns
650
760
565
660
445
520
380
440
mA
mA
4.0
4.0
4.5
4.5
5.5
5.5
6.5
6.5
ns
ns
445
520
415
485
350
390
305
355
mA
mA
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
A
A
E1
A
NC
NC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A
A
GS8128018 100-Pin TQFP Pinout (Package GT)
NC
NC
NC
VDDQ
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
8M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.00 9/2015
2/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
A
A
E1
A
BD
BC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A
A
GS8128032 100-Pin TQFP Pinout (Package GT)
NU
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NU
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
NU
LBO
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
NU
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
4M x 32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.00 9/2015
3/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
A
A
E1
A
BD
BC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A
A
GS8128036 100-Pin TQFP Pinout (Package GT)
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC3
VSS
VDDQ
DQC
DQC
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
LBO
A
A
A
A
A1
A0
A
A
VSS
VDD
A
A
A
A
A
A
A
A
A
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
4M x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.00 9/2015
4/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
TQFP Pin Description
Symbol
Type
Description
A0, A1
I
Address field LSBs and Address Counter preset Inputs
A
I
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BW
I
Byte Write—Writes all enabled bytes; active low
BA, BB
I
Byte Write Enable for DQA, DQB Data I/Os; active low
BC, BD
I
Byte Write Enable for DQC, DQD Data I/Os; active low
NC
No Connect
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable—Writes all bytes; active low
E1, E3
I
Chip Enable; active low
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
NC
—
No Connect
—
Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may be
left unconnected, tied Low (to VSS), or tied High (to VDDQ or VDD).
NU
Rev: 1.00 9/2015
5/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
GS8128018/32/36 Block Diagram
A0–An
Register
D
Q
A0
A0
D0
A1
Q0
A1
D1
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
D
36
Q
BB
36
4
Register
D
Q
D
Q
D
Q
Register
Register
D
Q
Register
BC
BD
Register
D
Q
Register
E1
D
Q
E3
Register
D
Q
FT
G
ZZ
1
Power Down
Control
DQx1–DQx9
Note: Only x36 version shown for simplicity.
Rev: 1.00 9/2015
6/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Mode Pin Functions
Mode Name
Pin Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
State
Function
L
Linear Burst
H
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.00 9/2015
Note:
The burst counter wraps to initial state on the 5th clock.
7/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Write No Bytes
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.00 9/2015
8/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key
E1
E3
ADSP
ADSC
ADV
W
DQ3
Deselect Cycle, Power Down
None
X
L
H
X
L
X
X
High-Z
Deselect Cycle, Power Down
None
X
L
H
L
X
X
X
High-Z
Deselect Cycle, Power Down
None
X
H
X
X
L
X
X
High-Z
Read Cycle, Begin Burst
External
R
L
L
L
X
X
X
Q
Read Cycle, Begin Burst
External
R
L
L
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
L
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
X
H
H
T
D
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00 9/2015
9/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Simplified State Diagram
X
Deselect
W
R
Simple Burst Synchronous Operation
Simple Synchronous Operation
W
X
R
R
First Write
First Read
CR
CW
W
X
CR
R
R
X
Burst Write
Burst Read
X
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.00 9/2015
10/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Simplified State Diagram with G
X
Deselect
W
R
W
X
R
R
First Write
CR
CW
W
CW
W
X
First Read
X
CR
R
Burst Write
R
CR
CW
W
Burst Read
X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.00 9/2015
11/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to 4.6
V
VI/O
Voltage on I/O Pins
–0.5 to VDD +0.5 ( 4.6 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDD +0.5 ( 4.6 V max.)
V
IIN
Input Current on Any Pin
+/–20
mA
IOUT
Output Current on Any I/O Pin
+/–20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
–55 to 125
oC
TBIAS
Temperature Under Bias
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input High Voltage
VIH
2.0
—
VDD + 0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
VDD3 Range Logic Levels
Note:
VIH (max) must be met for any instantaneous value of VDD.
Rev: 1.00 9/2015
12/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
VDD2 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature (Commercial Range Versions)
TJ
0
25
85
C
Junction Temperature (Industrial Range Versions)*
TJ
–40
25
100
C
Note:
VIH (max) must be met for any instantaneous value of VDD.
Recommended Operating Temperatures
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Thermal Impedance
Package
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
 JA (C°/W)
Airflow = 1 m/s
 JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
 JC (C°/W)
100 TQFP
4-layer
38.28
33.86
32.67
12.74
3.99
Notes:
1. Thermal Impedance data is based on a number of samples from multiple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Note:
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.00 9/2015
13/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
6
7
pF
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
50
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Rev: 1.00 9/2015
14/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IIN1
VDD  VIN  VIH
0 V VIN VIH
–1 uA
–1 uA
1 uA
100 uA
FT Input Current
IIN2
VDD  VIN  VIL
0 V VIN VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current
IOL
Output Disable, VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH2
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
Output High Voltage
VOH3
IOH = –8 mA, VDDQ = 3.135 V
2.4 V
—
Output Low Voltage
VOL
IOL = 8 mA
—
0.4 V
Rev: 1.00 9/2015
15/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Rev: 1.00 9/2015
ZZ VDD – 0.2 V
Operating
Current
Standby
Current
—
—
(x18)
(x32/
x36)
470
50
610
40
420
25
100
100
IDD
IDDQ
IDD
IDDQ
IDD
IDDQ
ISB
ISB
Flow Through
Pipeline
Flow Through
Pipeline
Flow Through
IDD
IDD
Pipeline
Flow Through
140
150
680
80
IDD
IDDQ
Pipeline
0
to
85°C
Symbol
Mode
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Device Deselected;
All other inputs
VIH or  VIL
Device Selected;
All other inputs
VIH or VIL
Output open
Deselect
Current
Test Conditions
Parameter
Operating Currents
-400
160
170
120
120
440
25
630
40
490
50
700
80
–40
to
100°C
130
140
100
100
390
25
530
35
440
45
590
70
0
to
85°C
-333
150
160
120
120
410
25
550
35
460
45
610
70
–40
to
100°C
130
140
100
100
330
20
420
25
350
40
470
50
0
to
85°C
-250
150
160
120
120
350
20
440
25
370
40
490
50
–40
to
100°C
130
130
100
100
290
15
360
20
320
35
400
40
0
to
85°C
-200
150
150
120
120
310
15
380
20
340
35
410
40
–40
to
100°C
mA
mA
mA
mA
mA
mA
mA
mA
Unit
Preliminary
GS8128018/32/36GT-400/333/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
16/23
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Pipeline
Flow
Through
Parameter
Symbol
Clock Cycle Time
-400
-333
-250
-200
Unit
AC Electrical Characteristics
Min
Max
Min
Max
Min
Max
Min
Max
tKC
2.5
—
3.0
—
4.0
—
5.0
—
ns
Clock to Output Valid
tKQ
—
2.5
—
2.5
—
2.5
—
3.0
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ1
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
0.9
—
1.0
—
1.2
—
1.4
—
ns
Hold time
tH
0.1
—
0.1
—
0.2
—
0.4
—
ns
Clock Cycle Time
tKC
4.0
—
4.5
—
5.5
—
6.5
—
ns
Clock to Output Valid
tKQ
—
4.0
—
4.5
—
5.5
—
6.5
ns
Clock to Output Invalid
tKQX
2.0
—
2.0
—
2.0
—
2.0
—
ns
Clock to Output in Low-Z
tLZ1
2.0
—
2.0
—
2.0
—
2.0
—
ns
Setup time
tS
1.2
—
1.3
—
1.5
—
1.5
—
ns
Hold time
tH
0.2
—
0.3
—
0.5
—
0.5
—
ns
Clock HIGH Time
tKH
0.9
—
1.0
—
1.3
—
1.3
—
ns
Clock LOW Time
tKL
1.1
—
1.2
—
1.5
—
1.5
—
ns
Clock to Output in
High-Z
tHZ1
1.5
2.5
1.5
2.5
1.5
2.5
1.5
3.0
ns
G to Output Valid
tOE
—
2.5
—
2.5
—
2.5
—
3.0
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ1
—
2.5
—
2.5
—
2.5
—
3.0
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.00 9/2015
17/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Pipeline Mode Timing (SCD)
Begin
Read A
Cont
Cont
Deselect
Single Read
Write B
Read C
Read C+1
Single Write
Read C+2
Read C+3
Cont
Deselect
Burst Read
tKL
tKH
tKC
CK
ADSP
tS
tH
ADSC initiated read
ADSC
tS
tH
ADV
tS
tH
Ao-An
A
B
C
tS
GW
tS
tH
BW
tH
tS
Ba -Bd
tS
E1 masks ADSP
tH
Deselected with E1
E1
G
tS
tOE
Qa-DQd
Rev: 1.00 9/2015
tOHZ
Q(A)
tKQ
tH
D(B)
tKQX
tLZ
tHZ
Q(C)
Q(C+1)
18/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q(C+2)
Q(C+3)
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Flow Through Mode Timing (SCD)
Begin
Read A
Cont
Cont
Write B
Read C
Read C+1
Read C+2
Read C+3
Read C
Cont
Deselect
tKL
tKH
tKC
CK
ADSP
Fixed High
tS
tS
tH
ADSC initiated read
tH
ADSC
tS
tH
ADV
tS
tH
Ao-An
A
B
C
tS
tH
GW
tS
tH
BW
tS
tH
Ba–Bd
tS
tH
Deselected with E1
E1
G
tS
tOE
DQa–DQd
Rev: 1.00 9/2015
tOHZ
Q(A)
tKQ
tH
tKQX
tLZ
D(B)
tHZ
Q(C)
Q(C+1)
Q(C+2)
19/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q(C+3)
Q(C)
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Rev: 1.00 9/2015
20/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Description
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
—
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
—
0.65
—
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
—
1.00
—
Y
Coplanarity

Lead Angle
e
D
D1
Symbol
Pin 1
TQFP Package Drawing (Package GT)

L
c
L1
Min. Nom. Max
b
A1
A2
0.10
Y
0
—
7
E1
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.00 9/2015
21/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TJ3
8M x 18
GS8128018GT-400
Pipeline/Flow Through
RoHS-compliant TQFP
400/4.0
C
8M x 18
GS8128018GT-333
Pipeline/Flow Through
RoHS-compliant TQFP
333/4.5
C
8M x 18
GS8128018GT-250
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
C
8M x 18
GS8128018GT-200
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
C
4M x 32
GS8128032GT-400
Pipeline/Flow Through
RoHS-compliant TQFP
400/4.0
C
4M x 32
GS8128032GT-333
Pipeline/Flow Through
RoHS-compliant TQFP
333/4.5
C
4M x 32
GS8128032GT-250
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
C
4M x 32
GS8128032GT-200
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
C
4M x 36
GS8128036GT-400
Pipeline/Flow Through
RoHS-compliant TQFP
400/4.0
C
4M x 36
GS8128036GT-333
Pipeline/Flow Through
RoHS-compliant TQFP
333/4.5
C
4M x 36
GS8128036GT-250
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
C
4M x 36
GS8128036GT-200
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
C
8M x 18
GS8128018GT-400I
Pipeline/Flow Through
RoHS-compliant TQFP
400/4.0
I
8M x 18
GS8128018GT-333I
Pipeline/Flow Through
RoHS-compliant TQFP
333/4.5
I
8M x 18
GS8128018GT-250I
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
I
8M x 18
GS8128018GT-200I
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
I
4M x 32
GS8128032GT-400I
Pipeline/Flow Through
RoHS-compliant TQFP
400/4.0
I
4M x 32
GS8128032GT-333I
Pipeline/Flow Through
RoHS-compliant TQFP
333/4.5
I
4M x 32
GS8128032GT-250I
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
I
4M x 32
GS8128032GT-200I
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
I
4M x 36
GS8128036GT-400I
Pipeline/Flow Through
RoHS-compliant TQFP
400/4.0
I
4M x 36
GS8128036GT-333I
Pipeline/Flow Through
RoHS-compliant TQFP
333/4.5
I
4M x 36
GS8128036GT-250I
Pipeline/Flow Through
RoHS-compliant TQFP
250/5.5
I
4M x 36
GS8128036GT-200I
Pipeline/Flow Through
RoHS-compliant TQFP
200/6.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8128018GT-400IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. C = Commercial Temperature Range. I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00 9/2015
22/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
Preliminary
GS8128018/32/36GT-400/333/250/200
144Mb Sync SRAM Datasheet Revision History
File Name
81280xx_r1
Rev: 1.00 9/2015
Types of Changes
Format or Content
Revisions
Creation of new datasheet
23/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology