GS840Z18CGT/GS840Z36CGT 100-Pin TQFP Commercial Temp Industrial Temp 4Mb Pipelined and Flow Through Synchronous NBT SRAMs Features 250 MHz–100 MHz 3.3 V VDD 2.5 V and 3.3 V VDDQ Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. • 256K x 18 and 128K x 36 configurations • User configurable Pipeline and Flow Through mode • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization • Fully pin compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • Pin-compatible with 2Mb, 9Mb and 18Mb devices • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleave Burst mode • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • Clock Control, registered address, data, and control • ZZ Pin for automatic power-down • RoHS-compliant 100-lead TQFP package Functional Description The GS840Z18/36CGT is a 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. The GS840Z18/36CGT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS840Z18/36CGT is implemented with GSI's high performance CMOS technology and is available in a 6/6 RoHS-compliant, JEDEC-standard 100-pin TQFP package. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.01 8/2011 tCycle tKQ IDD tKQ tCycle IDD –250 4.0 ns 2.5 ns TBD 5.5 ns 5.5 ns TBD –200 5.5 ns 3.0 ns TBD 6.5 ns 6.5 ns TBD –166 6.0 ns 3.5 ns TBD 7.0 ns 7.0 ns TBD –150 6.7 ns 3.8 ns TBD 7.5 ns 7.5 ns TBD –100 10 ns 4.5 ns TBD 12 ns 12 ns TBD 1/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT A A E1 E2 NC NC BB BA E3 VDD VSS CK W CKE G ADV NC NC A A GS840Z18CGT Pinout (Package T) NC NC NC VDDQ A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.01 8/2011 2/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT A A E1 E2 BD BC BB BA E3 VDD VSS CK W CKE G ADV NC NC A A GS840Z36CGT Pinout (Package T) DQPC DQC DQC VDDQ DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.01 8/2011 3/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT 100-Pin TQFP Pin Descriptions Symbol Type Description A0, A1 In Burst Address Inputs; preload the burst counter A In Address Inputs CK In Clock Input Signal BA In Byte Write signal for data inputs DQA1-DQA9; active low BB In Byte Write signal for data inputs DQB1-DQB9; active low BC In Byte Write signal for data inputs DQC1-DQC9; active low BD In Byte Write signal for data inputs DQD1-DQD9; active low W In Write Enable; active low E1 In Chip Enable; active low E2 In Chip Enable; active high; for self decoded depth expansion E3 In Chip Enable; active low, for self decoded depth expansion G In Output Enable; active low ADV In Advance / Load—Burst address counter control pin CKE In Clock Input Buffer Enable; active low DQA I/O Byte A Data Input and Output pins DQB I/O Byte B Data Input and Output pins DQC I/O Byte C Data Input and Output pins DQD I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active low LBO In Linear Burst Order; active low VDD In 3.3 V power supply VSS In Ground VDDQ In 3.3 V output power supply for noise reduction NC — No Connect Rev: 1.01 8/2011 4/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Register 1 Register 2 K Write Data Write Data K D Q K FT DQa–DQn GS840Z18/36C NBT SRAM Functional Block Diagram Memory Array Sense Amps FT Register 2 Register 1 Read, Write and Data Coherency Control Logic BC BD 5/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. G CKE CK E3 E2 E1 BA LBO ADV A0– W K K BB Match K Write Address Write Address K K D Q SA1 SA0 Burst Counter SA1’ SA0’ Write Drivers Rev: 1.01 8/2011 © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipelined Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. Function W BA BB BC BD Read H X X X X Write Byte “a” L L H H H Write Byte “b” L H L H H Write Byte “c” L H H L H Write Byte “d” L H H H L Write all Bytes L L L L L Write Abort/NOP L H H H H Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins. Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. Flow through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. Rev: 1.01 8/2011 6/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Synchronous Truth Table Operation Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Read Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10 NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2 Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10 Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3 Write Abort, Begin Burst D None L-H L L L H L H L X L High-Z 1 Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10 Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10 Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z None X X X X X X X X X H High-Z Current L-H H X X X X X X X L - Sleep Mode Clock Edge Ignore, Stall Notes 1 4 Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.01 8/2011 7/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Pipelined and Flow Through Read-Write Control State Diagram D B Deselect R W D D W New Read New Write R R W B B R W R Burst Read W Burst Write B B D Key D Notes Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. ƒ Transition Current State (n) 2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. Next State (n+1) n n+1 n+2 n+3 Clock (CK) Command ƒ Current State ƒ ƒ ƒ Next State Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram Rev: 1.01 8/2011 8/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Pipeline Mode Data I/O State Diagram Intermediate B W R B Intermediate R High Z (Data In) D Data Out (Q Valid) W D Intermediate Intermediate W Intermediate R High Z B D Intermediate Key Notes Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. ƒ Transition Current State (n) Transition Intermediate State (N+1) n Next State (n+2) n+1 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. n+2 n+3 Clock (CK) Command ƒ ƒ ƒ Current State Intermediate State Next State ƒ Current State and Next State Definition for Pipeline Mode Data I/O State Diagram Rev: 1.01 8/2011 9/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Flow Through Mode Data I/O State Diagram B W R B R High Z (Data In) W Data Out (Q Valid) D D W R High Z B D Key Notes Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. ƒ Transition Current State (n) 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. Next State (n+1) n n+1 n+2 n+3 Clock (CK) Command ƒ Current State ƒ ƒ ƒ Next State Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram Rev: 1.01 8/2011 10/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables below for details. Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.01 8/2011 Note: The burst counter wraps to initial state on the 5th clock. 11/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC tKL CK tZZR tZZS tZZH ZZ Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Pin 14. Not all vendors offer this option, however, most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Pin 66, a No Connect (NC) on GSI’s GS840Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked VDD or VDDQ on pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs (GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs. Rev: 1.01 8/2011 12/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 ( 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 ( 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 oC TBIAS Temperature Under Bias –55 to 125 oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Parameter Symbol Min. Typ. Max. Unit Input High Voltage VIH 2.0 — VDD + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V VDD3 Range Logic Levels Note: VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 1.01 8/2011 13/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT VDD2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Input High Voltage VIH 0.6*VDD — VDD + 0.3 V Input Low Voltage VIL –0.3 — 0.3*VDD V Note: VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Junction Temperature (Commercial Range Versions) TJ 0 25 85 C Junction Temperature (Industrial Range Versions)* TJ –40 25 100 C Note: * The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Thermal Impedance Package Test PCB Substrate JA (C°/W) Airflow = 0 m/s JA (C°/W) Airflow = 1 m/s JA (C°/W) Airflow = 2 m/s JB (C°/W) JC (C°/W) 100 TQFP 4-layer 28.3 27.2 25.4 — 7.1 Notes: 1. Thermal Impedance data is based on a number of samples from mulitple lots and should be viewed as a typical number. 2. Please refer to JEDEC standard JESD51-6. 3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to the PCB can result in cooling or heating of the RAM depending on PCB temperature. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Note: Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.01 8/2011 14/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.01 8/2011 15/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH –1 uA –1 uA 1 uA 100 uA FT Input Current IIN2 VDD VIN VIL 0 V VIN VIL –100 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 8 mA — 0.4 V Operating Currents -250 Operating Current Test Conditions Device Selected; All other inputs VIH or VIL Output open (x18) Standby Current ZZ VDD – 0.2 V — Deselect Current Device Deselected; All other inputs VIH or VIL — Rev: 1.01 8/2011 -150 -100 Symbol 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Pipeline IDD IDDQ 195 30 215 30 170 25 190 25 160 25 180 25 140 20 160 20 120 15 140 15 mA Flow Through IDD IDDQ 155 25 175 25 140 20 160 20 135 20 155 20 130 15 150 15 110 15 130 15 mA Pipeline IDD IDDQ 180 15 200 15 155 15 175 15 140 10 160 10 130 10 150 10 110 10 130 10 mA Flow Through IDD IDDQ 145 15 165 15 130 10 150 10 125 15 145 15 120 8 140 8 110 10 130 10 mA Pipeline ISB 25 45 25 45 25 45 25 45 25 45 mA Flow Through ISB 25 45 25 45 25 45 25 45 25 45 mA Pipeline IDD 65 85 65 85 65 85 60 80 60 80 mA Flow Through IDD 65 85 65 85 65 85 60 80 60 80 mA Mode (x32/ x36) -166 16/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Unit Parameter -200 © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Pipeline Flow Through Parameter Symbol Clock Cycle Time -250 -200 -166 -150 -100 Unit AC Electrical Characteristics Min Max Min Max Min Max Min Max Min Max tKC 4.0 — 5.5 — 6.0 — 6.7 — 10 — ns Clock to Output Valid tKQ — 2.5 — 3.0 — 3.5 — 3.8 — 4.5 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 1 tLZ 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Setup time tS 1.2 — 1.4 — 1.5 — 1.5 — 2.0 — ns Hold time tH 0.2 — 0.4 — 0.5 — 0.5 — 0.5 — ns Clock Cycle Time tKC 5.5 — 6.5 — 7.0 — 7.5 — 12.0 — ns Clock to Output Valid tKQ — 5.5 — 6.5 — 7.0 — 7.5 — 12.0 ns Clock to Output Invalid tKQX 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns Clock to Output in Low-Z tLZ1 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 2.0 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.3 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in High-Z 1 tHZ 1.5 2.5 1.5 3.0 1.5 3.0 1.5 3.0 1.5 5 ns G to Output Valid tOE — 2.5 — 3.0 — 3.5 — 3.8 — 5 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.5 — 3.0 — 3.0 — 3.0 — 5 ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns Clock to Output in Low-Z Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.01 8/2011 17/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Pipeline Mode Timing Write A Read B Suspend Read C tKH Write D Write No-op Read E Deselect tKC tKL CK tH tS A A B C D E tH tS CKE tH tS E* tH tS ADV tH tS W tH tH tS tS Bn tH tLZ tKQ tS DQ Rev: 1.01 8/2011 D(A) Q(B) Q(C) D(D) 18/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tHZ tKQX Q(E) © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Flow Through Mode Timing Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G tKL tKH tKC CK tH tS CKE tH tS E tH tS ADV tH tS W tH tS Bn tH tS A0–An A B C D E F G tKQ tH tKQ tLZ tS DQ D(A) D(B) D(B+1) tKQX tHZ Q(C) Q(D) tLZ D(E) tKQX Q(F) D(G) tOLZ tOE tOHZ G *Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1 Rev: 1.01 8/2011 19/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT TQFP Package Drawing (Package T) L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity Lead Angle L1 c D D1 Description Pin 1 Symbol e b A1 A2 0.10 Y 0 — 7 E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. BPR 1999.05.18 Rev: 1.01 8/2011 20/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT Ordering Information—GSI NBT Synchronous SRAMs Org Part Number1 Type Package Speed2 (MHz/ns) TJ3 256K x 18 GS840Z18CGT-250 NBT Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 256K x 18 GS840Z18CGT-200 NBT Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 256K x 18 GS840Z18CGT-166 NBT Pipeline/Flow Through RoHS-compliant TQFP 166/7.0 C 256K x 18 GS840Z18CGT-150 NBT Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 256K x 18 GS840Z18CGT-100 NBT Pipeline/Flow Through RoHS-compliant TQFP 100/12 C 128K x 36 GS840Z36CGT-250 NBT Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 128K x 36 GS840Z36CGT-200 NBT Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 128K x 36 GS840Z36CGT-166 NBT Pipeline/Flow Through RoHS-compliant TQFP 166/7.0 C 128K x 36 GS840Z36CGT-150 NBT Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 128K x 36 GS840Z36CGT-100 NBT Pipeline/Flow Through RoHS-compliant TQFP 100/12 C 256K x 18 GS840Z18CGT-250I NBT Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I 256K x 18 GS840Z18CGT-200I NBT Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I 256K x 18 GS840Z18CGT-166I NBT Pipeline/Flow Through RoHS-compliant TQFP 166/7.0 I 256K x 18 GS840Z18CGT-150I NBT Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I 256K x 18 GS840Z18CGT-100I NBT Pipeline/Flow Through RoHS-compliant TQFP 100/12 I 128K x 36 GS840Z36CGT-250I NBT Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I 128K x 36 GS840Z36CGT-200I NBT Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I 128K x 36 GS840Z36CGT-166I NBT Pipeline/Flow Through RoHS-compliant TQFP 166/7.0 I 128K x 36 GS840Z36CGT-150I NBT Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I 128K x 36 GS840Z36CGT-100I NBT Pipeline/Flow Through RoHS-compliant TQFP 100/12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840Z36CGT-100IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.01 8/2011 21/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS840Z18CGT/GS840Z36CGT 4Mb Synchronous NBT Datasheet Revision History File Name Types of Changes Format or Content • Creation of new datasheet 840ZxxC_r1 840ZxxC_r1_01 Rev: 1.01 8/2011 Revision Content • Updated Operating Currents table 22/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology