GS8322Z18(B/E)/GS8322Z36(B/E) 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 36Mb Pipelined and Flow Through Synchronous NBT SRAM 119 & 165 BGA Commercial Temp Industrial Temp Features ct The GS8322Z18/36 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. De sig Functional Description Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. n— Di sco nt inu ed Pr od u • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • User-configurable Pipeline and Flow Through mode • ZQ mode pin for user-selectable high/low output drive • IEEE 1149.1 JTAG-compatible Boundary Scan • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down • JEDEC-standard 119- or165-Bump BGA package • RoHS-compliant packages available The GS8322Z18/36 is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. me nd ed for Ne w The GS8322Z18/36 is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump or 165-bump BGA package. Parameter Synopsis Re co m Pipeline 3-1-1-1 285 350 6.5 6.5 205 235 265 320 7.0 7.0 195 225 245 295 7.5 7.5 185 210 220 260 8.0 8.0 175 200 210 240 8.5 8.5 165 190 185 215 8.5 8.5 155 175 mA mA ns ns mA mA No t Flow Through 2-1-1-1 tKQ(x18/x36) tCycle Curr (x18) Curr (x36) tKQ tCycle Curr (x18) Curr (x36) -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.5 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns Rev: 1.08 10/2014 1/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u ct GS8322Z18(B/E)/GS8322Z36(B/E) Rev: 1.08 10/2014 2/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) GS8322Z36B Pad Out—119-Bump BGA—Top View (Package B) 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B NC E2 A ADV A E3 NC B C NC A A VDD A A NC C D DQC DQPC VSS ZQ VSS DQPB DQB D E DQC DQC VSS E1 VSS DQB DQB E F VDDQ DQC VSS G VSS DQB VDDQ F G DQC DQC BC A BB DQB DQB G H DQC DQC VSS W VSS DQB DQB H J VDDQ VDD NC VDD NC VDD VDDQ J K DQD DQD VSS CK VSS DQA DQA K L DQD DQD BD NC BA DQA DQA L M VDDQ DQD VSS CKE VSS DQA VDDQ M N DQD DQD VSS A1 VSS DQA DQA N P DQD DQPD VSS A0 VSS DQPA DQA P R NC A LBO VDD FT A NC R T NC NC A A A A ZZ T U VDDQ TMS TDI TCK TDO NC VDDQ U ct n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch No t Re co m A Rev: 1.08 10/2014 3/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) GS8322Z18B Pad Out—119-Bump BGA—Top View (Package B) 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B NC E2 A ADV A E3 NC C NC A A VDD A A NC C D DQB NC VSS ZQ VSS DQPA NC D E NC DQB VSS E1 VSS NC DQA E F VDDQ NC VSS G VSS DQA VDDQ F G NC DQB BB A NC NC DQA G H DQB NC VSS W VSS DQA NC H J VDDQ VDD NC VDD NC VDD VDDQ J K NC DQB VSS CK VSS NC DQA K L DQB NC NC NC BA DQA NC L M VDDQ DQB VSS CKE VSS NC VDDQ M N DQB NC A1 VSS DQA NC N P NC DQPB VSS A0 VSS NC DQA P R NC A LBO VDD FT A NC R T NC A A A A A ZZ T U VDDQ TMS TDI TCK TDO NC VDDQ U ct n— Di sco nt inu ed Pr od u De sig Ne w B 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch No t Re co m me nd ed for VSS A Rev: 1.08 10/2014 4/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) GS8322Z18/36 119-Bump BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD I/O BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I CKE I W I E1 I E3 I E2 I G I ADV I ZZ I FT I LBO I ZQ I TMS I TDI I TDO O TCK I VDD I n— Di sco nt inu ed Pr od u Data Input and Output pins Clock Input Signal; active high Clock Enable; active low Write Enable; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high De sig Output Enable; active low Burst address counter advance enable Sleep mode control; active high Ne w Flow Through or Pipeline mode; active low me nd ed for Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I I/O and Core Ground I Output driver power supply BPR1999.05.18 No t VDDQ Linear Burst Order mode; active low FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Re co m VSS ct Symbol Rev: 1.08 10/2014 5/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 CKE ADV A A A A B NC A E2 NC BA CK W G A A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C D NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D E NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E F NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F G NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G H FT MCH NC VDD VSS VSS VSS VDD NC ZQ ZZ H J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M N DQPB NC P NC NC R LBO A me nd ed for Ne w n— Di sco nt inu ed Pr od u ct 1 De sig 165 Bump BGA—x18 Common I/O—Top View (Package E) VSS NC NC NC VSS VDDQ NC NC N A A TDI A1 TDO A A A NC P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch Rev: 1.08 10/2014 6/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) 165 Bump BGA—x36 Common I/O—Top View (Package E) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 CKE ADV A A NC B NC A E2 BD BA CK W G A A C DQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ D DQC DQC VDDQ VDD VSS VSS VSS VDD E DQC DQC VDDQ VDD VSS VSS VSS F DQC DQC VDDQ VDD VSS VSS G DQC DQC VDDQ VDD VSS H FT MCH NC VDD J DQD DQD VDDQ K DQD DQD L DQD M A B NC DQPB C VDDQ DQB DQB D VDD VDDQ DQB DQB E VSS VDD VDDQ DQB DQB F VSS VSS VDD VDDQ DQB DQB G VSS VSS VSS VDD NC ZQ ZZ H VDD VSS VSS VSS VDD VDDQ DQA DQA J VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N DQPD NC P NC NC R LBO A me nd ed for Ne w n— Di sco nt inu ed Pr od u NC De sig ct 1 VSS NC NC NC VSS VDDQ NC DQPA N A A TDI A1 TDO A A A NC P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch Rev: 1.08 10/2014 7/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) GS8322Z18/36E 165-Bump BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs A18 I Address Input DQA DQB DQC DQD I/O BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I CKE I W I E1 I E3 I E2 I FT I G I ADV I ZQ I FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) ZZ I Sleep mode control; active high LBO I TMS I TDI I TDO O TCK I MCH — n— Di sco nt inu ed Pr od u Clock Input Signal; active high Clock Enable; active low Write Enable; active low Chip Enable; active low Chip Enable; active low De sig Chip Enable; active high Flow Through / Pipeline Mode Control Output Enable; active low me nd ed for Ne w Burst address counter advance enable; active high Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect High I Core power supply I I/O and Core Ground I Output driver power supply No t VSS VDDQ Data Input and Output pins Re co m VDD Rev: 1.08 10/2014 ct Symbol 8/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Functional Details ct Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. W Read H Write Byte “a” L Write Byte “b” L Write Byte “c” L Write Byte “d” L Write all Bytes L De sig Function n— Di sco nt inu ed Pr od u Pipeline Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. Write Abort/NOP L BA BB BC BD X X X X L H H H H L H H H H L H H H H L L L L L H H H H me nd ed for Ne w Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. Re co m Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. No t Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. Rev: 1.08 10/2014 9/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Synchronous Truth Table Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Read Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10 NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2 Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10 Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3 Write Abort, Begin Burst D None L-H L L L H L H L X L High-Z 1 Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10 Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10 Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z None X X X X X X X X X H High-Z Current L-H H X X X X X X X L - Clock Edge Ignore, Stall n— Di sco nt inu ed Pr od u De sig Sleep Mode ct Type Ne w Operation Notes 1 4 No t Re co m me nd ed for Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.08 10/2014 10/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Pipelined and Flow Through Read Write Control State Diagram D n— Di sco nt inu ed Pr od u ct B Deselect R D R D W New Read W B R W R ƒ Transition Current State (n) No t Command Re co m Clock (CK) Ne w 2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. n+1 ƒ Current State D 1. The Hold command (CKE Low) is not shown because it prevents any state change. Next State (n+1) n B Notes me nd ed for Input Command Code W Burst Write De sig Burst Read D Key New Write R B B W n+2 ƒ n+3 ƒ ƒ Next State Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram Rev: 1.08 10/2014 11/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Pipeline Mode Data I/O State Diagram R High Z (Data In) D R B Intermediate Data Out (Q Valid) W D Intermediate Intermediate W Intermediate ct B W n— Di sco nt inu ed Pr od u Intermediate R High Z B D Key Ne w Input Command Code ƒ Transition Transition Intermediate State (N+1) me nd ed for Current State (n) n Next State (n+2) n+1 Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change. 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. n+2 n+3 Command ƒ ƒ ƒ No t Re co m Clock (CK) De sig Intermediate Current State Intermediate State Next State ƒ Current State and Next State Definition for Pipeline Mode Data I/O State Diagram Rev: 1.08 10/2014 12/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Flow Through Mode Data I/O State Diagram R B R High Z (Data In) Data Out (Q Valid) n— Di sco nt inu ed Pr od u W ct B W D D W R High Z B Key Ne w Input Command Code ƒ Transition Current State (n) me nd ed for Re co m Command n+1 ƒ Current State Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change. 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. Next State (n+1) n Clock (CK) De sig D n+2 ƒ n+3 ƒ ƒ Next State No t Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram Rev: 1.08 10/2014 13/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) n— Di sco nt inu ed Pr od u ct Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. FLXDrive™ The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Mode Pin Functions Pin Name Burst Order Control LBO De sig Mode Name Output Register Control me nd ed for FLXDrive Output Impedance Control ZZ Ne w Power Down Control FT ZQ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB L High Drive (Low Impedance) H or NC Low Drive (High Impedance) No t Re co m Note: There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Rev: 1.08 10/2014 14/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 n— Di sco nt inu ed Pr od u 1st address ct A[1:0] A[1:0] A[1:0] A[1:0] Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 De sig Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. me nd ed for Ne w Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC CK tKL tZZR tZZS No t Re co m ZZ tZZH Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not all vendors offer this option, however most mark the pin VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device, the pin will need to be pulled low for correct operation. Rev: 1.08 10/2014 15/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n— Di sco nt inu ed Pr od u Note: ct Symbol V –0.5 to VDDQ +0.5 ( 4.6 V max.) V –0.5 to VDD +0.5 ( 4.6 V max.) V +/–20 mA +/–20 mA 1.5 W –55 to 125 o –55 to 125 oC C De sig Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Symbol Min. Typ. Max. Unit VDD3 3.0 3.3 3.6 V VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V 3.3 V Supply Voltage me nd ed for 2.5 V Supply Voltage Ne w Parameter Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.08 10/2014 16/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1,3 n— Di sco nt inu ed Pr od u Parameter ct VDDQ3 Range Logic Levels Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Parameter Symbol Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage –0.3 — 0.3*VDD V 1,3 De sig Min. Ne w VDDQ2 Range Logic Levels VILQ me nd ed for Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 C 2 Re co m Parameter No t Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.08 10/2014 17/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS n— Di sco nt inu ed Pr od u 50% ct 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF AC Test Conditions Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Output reference level Output load me nd ed for Input reference level Ne w Parameter De sig Note: These parameters are sample tested. VDDQ/2 VDDQ/2 Fig. 1 No t Re co m Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.08 10/2014 18/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) DC Electrical Characteristics Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH FT, SCD, ZQ Input Current IIN2 Output Leakage Current (x36/x72) IOL Output Leakage Current (x18) IOL Output High Voltage VOH2 Output High Voltage VOH3 Output Low Voltage VOL ct Parameter 1 uA 100 uA VDD VIN VIL 0 V VIN VIL –100 uA –1 uA 1 uA 1 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA IOH = –8 mA, VDDQ = 2.375 V 1.7 V — IOH = –8 mA, VDDQ = 3.135 V 2.4 V — IOL = 8 mA — 0.4 V No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u –1 uA –1 uA Rev: 1.08 10/2014 19/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology Rev: 1.08 10/2014 — Device Deselected; All other inputs VIH or VIL Deselect Current Flow Through IDD 85 IDD Pipeline 100 115 100 ISB ISB Flow Through 60 80 85 90 60 60 170 15 225 20 190 20 255 40 0 to 70°C 105 80 80 180 15 245 20 200 20 275 40 –40 to 85°C -200 85 60 60 160 15 200 20 180 20 225 35 0 to 70°C 100 80 80 170 15 220 20 190 20 245 35 –40 to 85°C -166 85 60 60 150 15 190 20 170 20 210 30 0 to 70°C 100 80 80 160 15 210 20 180 20 230 30 –40 to 85°C -150 80 60 60 140 15 170 15 160 15 190 25 0 to 70°C 85 95 80 80 150 15 190 15 170 15 210 25 –40 to 85°C -133 n 80 95 80 95 75 90 70 100 — Di sco nt inu ed Pr od uc t D60 e 80 95 s110 ig 60 190 15 180 15 200 15 Ne80 w 60 80 Pipeline 260 25 DDQ DD DDQ DD Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. — IL ZZ VDD – 0.2 V IH DDQ 210 25 240 25 200 25 220 25 DD DDQ 295 45 –40 to 85°C 280 25 275 45 IDD 320 50 No t 0 to 70°C Re (x36) Pipeline I 30050 co Flow I 210 Device Selected; mThrough I 25 All other inputs m V or V e I 260 Pipelinen Output open 25 deI (x18) Id Flow fo19015r I Through Symbol -225 –40 to 85°C Mode -250 0 to 70°C Test Conditions Standby Current Operating Current Parameter Operating Currents mA mA mA mA mA mA mA mA Unit GS8322Z18(B/E)/GS8322Z36(B/E) Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 20/37 © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) AC Electrical Characteristics Clock Cycle Time -250 -225 -200 -166 -150 -133 Unit Min Max Min Max Min Max Min Max Min Max Min Max tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns Clock to Output Valid tKQ — 2.5 — 2.7 — 3.0 — 3.5 ct Symbol 3.8 — 4.0 ns Clock to Output Invalid tKQX 1.5 — 1.5 Clock to Output in Low-Z tLZ1 1.5 — 1.5 Setup time tS 1.2 — 1.3 Hold Time tH 0.2 — 0.3 Clock Cycle Time tKC 6.5 — 7.0 Clock to Output Valid tKQ — 6.5 — tKQX 3.0 — 3.0 tLZ1 3.0 — 3.0 Setup time tS 1.5 — 1.5 Hold time tH 0.5 — 0.5 Clock HIGH Time tKH 1.3 — 1.3 Clock LOW Time tKL 1.5 — 1.5 Clock to Output in High-Z tHZ1 1.5 2.5 G to Output Valid tOE — 2.5 G to output in Low-Z tOLZ1 0 G to output in High-Z tOHZ1 — ZZ setup time tZZS2 5 tZZH2 tZZR ZZ hold time ZZ recovery n— Di sco nt inu ed Pr od u — 1.5 — 1.5 — 1.5 — 1.5 — ns — 1.5 — 1.5 — 1.5 — 1.5 — ns — 1.4 — 1.5 — 1.5 — 1.5 — ns — 0.4 — 0.5 — 0.5 — 0.5 — ns — 7.5 — 8.0 — 8.5 — 8.5 — ns 7.0 — 7.5 — 8.0 — 8.5 — 8.5 ns — 3.0 — 3.0 — 3.0 — 3.0 — ns — 3.0 — 3.0 — 3.0 — 3.0 — ns — 1.5 — 1.5 — 1.5 — 1.5 — ns — 0.5 — 0.5 — 0.5 — 0.5 — ns — 1.3 — 1.3 — 1.5 — 1.7 — ns — 1.5 — 1.5 — 1.7 — 2 — ns De sig — 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns — 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns — 0 — 0 — 0 — 0 — 0 — ns 2.5 — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 ns — 5 — 5 — 5 — 5 — 5 — ns 1 — 1 — 1 — 1 — 1 — 1 — ns 20 — 20 — 20 — 20 — 20 — 20 — ns me nd ed for Clock to Output Invalid Flow Through Clock to Output in Low-Z Ne w Pipeline Parameter No t Re co m Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.08 10/2014 21/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Pipeline Mode Timing (NBT) Write A Read B Suspend Read C tKH Write D Write No-op Read E Deselect tKC tKL ct CK tH A A B n— Di sco nt inu ed Pr od u tS C D tH tS CKE tH tS E* tH tS ADV tH tS W tH E tH tS Bn De sig tS tH tS DQ Q(B) Q(C) D(D) tHZ tKQX Q(E) No t Re co m me nd ed for Ne w D(A) tLZ tKQ Rev: 1.08 10/2014 22/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Flow Through Mode Timing (NBT) Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G tKL tKH tKC ct CK n— Di sco nt inu ed Pr od u tH tS CKE tH tS E tH tS ADV tH tS W tH tS tH tS A B C tH tS D(A) D(B) D(B+1) me nd ed for DQ G D E F G tKQ tKQ tLZ Ne w A0–An De sig Bn tKQX tHZ Q(C) Q(D) tLZ D(E) tKQX Q(F) D(G) tOLZ tOE tOHZ Re co m *Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1 JTAG Port Operation No t Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.08 10/2014 23/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) JTAG Pin Descriptions Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. Test Data In TDO Test Data Out n— Di sco nt inu ed Pr od u TDI ct Pin Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. De sig JTAG Port Registers Ne w Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. me nd ed for Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. No t Re co m Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.08 10/2014 24/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) · · · · Boundary Scan Register · · · · 1 · 0 Bypass Register 2 1 0 0 108 · n— Di sco nt inu ed Pr od u · ct JTAG TAP Block Diagram Instruction Register TDI TDO ID Code Register · · ·· 2 1 0 De sig 31 30 29 Control Signals TMS Test Access Port (TAP) Controller Ne w TCK No t Re co m me nd ed for Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.08 10/2014 25/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) GSI Technology JEDEC Vendor ID Code I/O Configuration n— Di sco nt inu ed Pr od u Not Used ct Die Revision Code Presence Register ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 X X X X 0 0 0 0 0 0 0 0 0 0 x36 X X X X 0 0 0 X 1 0 0 1 0 0 x32 X X X X 0 0 0 0 0 0 0 0 0 0 x18 X X X X 0 0 0 X 1 0 0 1 0 0 x16 X X X X 0 0 0 0 0 0 0 0 0 0 Tap Controller Instruction Set 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 De sig Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. No t Re co m me nd ed for Ne w When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.08 10/2014 26/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) JTAG Tap Controller State Diagram Test Logic Reset 1 0 Run Test Idle 1 Select DR 1 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 ct 0 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR De sig 1 Update DR 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Ne w 1 1 Select IR n— Di sco nt inu ed Pr od u 0 me nd ed for Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. No t Re co m SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 1.08 10/2014 27/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) n— Di sco nt inu ed Pr od u ct Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. De sig JTAG TAP Instruction Set Summary Code Description EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 Places Bypass Register between TDI and TDO. 1 me nd ed for Re co m BYPASS 111 Notes Ne w Instruction No t Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.08 10/2014 28/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) JTAG Port Recommended Operating Conditions and DC Characteristics Symbol Min. Max. Unit Notes 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 VILJ2 –0.3 0.3 * VDD2 V 1 IINHJ –300 1 uA 2 IINLJ –1 100 uA 3 IOLJ –1 1 uA 4 VOHJ 1.7 — V 5, 6 VOLJ — 0.4 V 5, 7 VOHJC VDDQ – 100 mV — V 5, 8 VOLJC — 100 mV V 5, 9 n— Di sco nt inu ed Pr od u ct Parameter 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low me nd ed for Ne w De sig Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOLJC = +100 uA JTAG Port AC Test Conditions Parameter Input high level Re co m Input low level Conditions VDD – 0.2 V DQ 0.2 V Input slew rate 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 No t JTAG Port AC Test Load 50 30pF* VDDQ/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.08 10/2014 29/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TMS tTKQ TDO tTH tTS JTAG Port AC Electrical Characteristics De sig Parallel SRAM input n— Di sco nt inu ed Pr od u TDI ct tTH tTS Symbol Min TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns tTKL 20 — ns tTS 10 — ns tTH 10 — ns TDI & TMS Set Up Time TDI & TMS Hold Time me nd ed for TCK Low Pulse Width Max Ne w Parameter Unit No t Re co m Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: [email protected]. Rev: 1.08 10/2014 30/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Package Dimensions—119-Bump FPBGA (Package B, Variation 2) TOP VIEW 2 3 4 5 6 7 7 6 5 4 3 2 1 20.32 De sig 22±0.10 1.27 A B C D E F G H J K L M N P R T U ct 1 BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) n— Di sco nt inu ed Pr od u A1 A B C D E F G H J K L M N P R T U 1.27 7.62 A 0.20(4x) 14±0.10 SEATING PLANE No t Re co m C 0.50~0.70 1.86.±0.13 me nd ed for 0.15 C Ne w B Rev: 1.08 10/2014 31/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 1.0 14.0 A B C D E F G H J K L M N P R 1.0 10.0 15±0.05 0.20(4x) 0.36~0.46 1.50 MAX. SEATING PLANE BPR 1999.05.18 No t Re co m C B 1.0 me nd ed for 0.15 C Ne w A De sig 17±0.05 1.0 A B C D E F G H J K L M N P R n— Di sco nt inu ed Pr od u ct 11 10 9 8 7 6 5 4 3 2 1 Rev: 1.08 10/2014 32/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Ordering Information for GSI Synchronous Burst RAMs Part Number1 Type Package Speed2 (MHz/ns) TA3 2M x 18 GS8322Z18B-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 C 2M x 18 GS8322Z18B-225 NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 C 2M x 18 GS8322Z18B-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 C 2M x 18 GS8322Z18B-166 NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 C 2M x 18 GS8322Z18B-150 NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 C 2M x 18 GS8322Z18B-133 NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 C 2M x 18 GS8322Z18E-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 C 2M x 18 GS8322Z18E-225 NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 C 2M x 18 GS8322Z18E-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 C 2M x 18 GS8322Z18E-166 NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 C 2M x 18 GS8322Z18E-150 NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 C 2M x 18 GS8322Z18E-133 NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 C 1M x 36 GS8322Z36B-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 C 1M x 36 GS8322Z36B-225 NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 C 1M x 36 GS8322Z36B-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 C 1M x 36 GS8322Z36B-166 NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 C 1M x 36 GS8322Z36B-150 NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 C 1M x 36 GS8322Z36B-133 NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 C 1M x 36 GS8322Z36E-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 C 1M x 36 GS8322Z36E-225 NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 C 1M x 36 GS8322Z36E-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 C 1M x 36 GS8322Z36E-166 NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 C 1M x 36 GS8322Z36E-150 NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 C 1M x 36 GS8322Z36E-133 NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 C 2M x 18 GS8322Z18B-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 I 2M x 18 GS8322Z18B-225I NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 I 2M x 18 GS8322Z18B-200I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 I 2M x 18 GS8322Z18B-166I NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 I 2M x 18 GS8322Z18B-150I NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 I 2M x 18 GS8322Z18B-133I NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 I n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for No t Re co m ct Org 2M x 18 GS8322Z18E-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.08 10/2014 33/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Ordering Information for GSI Synchronous Burst RAMs (Cont.) Part Number1 Type Package Speed2 (MHz/ns) TA3 2M x 18 GS8322Z18E-225I NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 I 2M x 18 GS8322Z18E-200I NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 I 2M x 18 GS8322Z18E-166I NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 I 2M x 18 GS8322Z18E-150I NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 I 2M x 18 GS8322Z18E-133I NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 I 1M x 36 GS8322Z36B-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 I 1M x 36 GS8322Z36B-225I NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 I 1M x 36 GS8322Z36B-200I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 I 1M x 36 GS8322Z36B-166I NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 I 1M x 36 GS8322Z36B-150I NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 I 1M x 36 GS8322Z36B-133I NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 I 1M x 36 GS8322Z36E-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 I 1M x 36 GS8322Z36E-225I NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 I 1M x 36 GS8322Z36E-200I NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 I 1M x 36 GS8322Z36E-166I NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 I 1M x 36 GS8322Z36E-150I NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 I 1M x 36 GS8322Z36E-133I NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 I 512K x 72 GS8322Z72C-250I NBT Pipeline/Flow Through 209 BGA 250/6.5 I 512K x 72 GS8322Z72C-225I NBT Pipeline/Flow Through 209 BGA 225/7 I 512K x 72 GS8322Z72C-200I NBT Pipeline/Flow Through 209 BGA 200/7.5 I 512K x 72 GS8322Z72C-166I NBT Pipeline/Flow Through 209 BGA 166/8 I 512K x 72 GS8322Z72C-150I NBT Pipeline/Flow Through 209 BGA 150/8.5 I 512K x 72 GS8322Z72C-133I NBT Pipeline/Flow Through 209 BGA 133/8.5 I 2M x 18 GS8322Z18GB-250 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 250/6.5 C 2M x 18 GS8322Z18GB-225 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 225/7 C 2M x 18 GS8322Z18GB-200 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 200/7.5 C 2M x 18 GS8322Z18GB-166 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 166/8 C 2M x 18 GS8322Z18GB-150 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 150/8.5 C 2M x 18 GS8322Z18GB-133 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 133/8.5 C 2M x 18 GS8322Z18GE-250 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 250/6.5 C n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for Re co m ct Org No t 2M x 18 GS8322Z18GE-225 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 225/7 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.08 10/2014 34/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Ordering Information for GSI Synchronous Burst RAMs (Cont.) Part Number1 Type Package Speed2 (MHz/ns) TA3 2M x 18 GS8322Z18GE-200 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 200/7.5 C 2M x 18 GS8322Z18GE-166 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 166/8 C 2M x 18 GS8322Z18GE-150 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 150/8.5 C 2M x 18 GS8322Z18GE-133 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 133/8.5 C 1M x 36 GS8322Z36GB-250 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 250/6.5 C 1M x 36 GS8322Z36GB-225 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 225/7 C 1M x 36 GS8322Z36GB-200 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 200/7.5 C 1M x 36 GS8322Z36GB-166 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 166/8 C 1M x 36 GS8322Z36GB-150 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 150/8.5 C 1M x 36 GS8322Z36GB-133 NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 133/8.5 C 1M x 36 GS8322Z36GE-250 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 250/6.5 C 1M x 36 GS8322Z36GE-225 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 225/7 C 1M x 36 GS8322Z36GE-200 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 200/7.5 C 1M x 36 GS8322Z36GE-166 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 166/8 C 1M x 36 GS8322Z36GE-150 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 150/8.5 C 1M x 36 GS8322Z36GE-133 NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 133/8.5 C 2M x 18 GS8322Z18GB-250I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 250/6.5 I 2M x 18 GS8322Z18GB-225I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 225/7 I 2M x 18 GS8322Z18GB-200I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 200/7.5 I 2M x 18 GS8322Z18GB-166I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 166/8 I 2M x 18 GS8322Z18GB-150I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 150/8.5 I 2M x 18 GS8322Z18GB-133I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 133/8.5 I 2M x 18 GS8322Z18GE-250I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 250/6.5 I 2M x 18 GS8322Z18GE-225I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 225/7 I 2M x 18 GS8322Z18GE-200I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 200/7.5 I 2M x 18 GS8322Z18GE-166I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 166/8 I 2M x 18 GS8322Z18GE-150I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 150/8.5 I 2M x 18 GS8322Z18GE-133I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 133/8.5 I 1M x 36 GS8322Z36GB-250I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 250/6.5 I n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for Re co m ct Org No t 1M x 36 GS8322Z36GB-225I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 225/7 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.08 10/2014 35/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) Ordering Information for GSI Synchronous Burst RAMs (Cont.) Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 36 GS8322Z36GB-200I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 200/7.5 I 1M x 36 GS8322Z36GB-166I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 166/8 I 1M x 36 GS8322Z36GB-150I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 150/8.5 I 1M x 36 GS8322Z36GB-133I NBT Pipeline/Flow Through RoHS-compliant 119 BGA (var. 2) 133/8.5 I 1M x 36 GS8322Z36GE-250I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 250/6.5 I 1M x 36 GS8322Z36GE-225I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 225/7 I 1M x 36 GS8322Z36GE-200I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 200/7.5 I 1M x 36 GS8322Z36GE-166I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 166/8 I 1M x 36 GS8322Z36GE-150I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 150/8.5 I n— Di sco nt inu ed Pr od u ct Org No t Re co m me nd ed for Ne w De sig 1M x 36 GS8322Z36GE-133I NBT Pipeline/Flow Through RoHS-compliant 165 BGA (var. 1) 133/8.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.08 10/2014 36/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology GS8322Z18(B/E)/GS8322Z36(B/E) 36Mb Sync SRAM Datasheet Revision History New Types of Changes Page;Revisions;Reason Format or Content • Creation of new datasheet 8322Z18_r1 ct DS/DateRev. Code: Old; C • Add 165 BGA 8322Z18_r1.02 C • Fix missing address at B9 and ZQ at H10 in 165 pinouts n— Di sco nt inu ed Pr od u 8322Z18_r1.01 • Added 165-BGA package • Updated all power numbers on page 1 and page 26 • Updated AC Characteristics table • Removed all references to parity • Updated tables on page 23 • Updated FT power numbers • Updated Absolute Maximum Ratings table • Corrected Capacitance table • Updated tKQ (PL) numbers in table on page 1 • Updated DC Electrical Characteristics table • Removed Output Load 2 diagram on page 15 • Updated standby current numbers in Operating Current table • Updated timing diagrams 8322Z18_r1_03 Content 8322Z18_r1_04 Format/Content 8322Z18_r1_05 Content 8322Z18_r1_06 Content • Corrected AC Electrical Characteristics Table • Rev1.06a: updated coplanarity for 119, 165 BGA mechanical, removed Status column from Ordering Information table. 8322Z18_r1_07 Content • Updated Synchronous Truth Table (pg. 12) • ((Rev.1.07a) Corrected formating on title page Content • Removed x72 due to NRND status of x18 and x36 me nd ed for De sig Ne w • RoHS-compliant information added No t Re co m 8322Z18_r1_08 • Updated format • Added variation information to package mechanicals Rev: 1.08 10/2014 37/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2002, GSI Technology