CoreFFT v6.4 Release Notes These release notes accompany the production release of the CoreFFT IP core version 6.4. This document provides details about the features and enhancements, system requirements, supported families, implementations, and known issues and workarounds. Key Features CoreFFT v6.4 has the following features: • Highly configurable DirectCore register transfer level (RTL) generator • Choice of Radix-2 In-place architecture or Radix-2 Streaming Fast Fourier Transform (FFT) 2 • Forward and inverse complex FFT • Transform sizes: 32-, 64-, 128-, 256-, 512-, 1,024-, 2,048-, 4,096-, and 8,192-point (in-place architecture), 16-, 32-, 64-, 128-, 256-, 512-, and 1,024-point (streaming architecture) • 8- to 32-bits I/O real and imaginary data and twiddle coefficients • Two’s complementary I/O data • Natural input and output sample order • Selection of conditional or unconditional block floating point scaling (in-place architecture), pre-defined scaling schedule (streaming architecture) • Embedded RAM-block based twiddle look-up table (LUT) • Built-in memory buffers • Handshake signals to facilitate easy interface to the user circuitry Supported Interfaces No standard interface available. Delivery Types CoreFFT is licensed as RTL. A complete hardware description language (HDL) source code is provided for the core and testbenches. Supported Families • SmartFusion 2 ® • IGLOO 2 ® • RTG4™ Supported Tool Flows • CoreFFT v6.4 requires Libero System-on-Chip (SoC) software v11.3 or later. ® • Supports Windows and Linux operating systems ® February 2015 CoreFFT v6.4 Release Notes Installation Instructions The CoreFFT CPZ file must be installed into Libero SoC software. This is done automatically through the Catalog update function in Libero SoC, or the CPZ file can be manually added using the Add Core catalog feature. Once installed in the Libero SoC Catalog, the core can be instantiated and configured. Refer to the Libero SoC online help for further instructions on core installation, licensing, and general use. Documentation The release contains the CoreFFT Handbook. The handbook describes the core functionality and gives step-by-step instructions on how to simulate, synthesize, and place-and-route this core, and implementation suggestions. For more information about Intellectual Property, visit: http://www.microsemi.com/products/fpga-soc/designresources/ip-cores. For updates and additional information about software, FPGAs, and hardware, visit: http://www.microsemi.com. Supported Test Environments The following test environments are supported: • VHDL user testbench • Verilog user testbench Release History Table 1 shows the release history for CoreFFT v6.4. Table 1. Release History Version Date Changes 6.4 February 2015 Support for RTG4 family is added. 6.3 September 2013 Support for Linux and new devices is added. 6.2 June 2013 Support for IGLOO2 family is added. 6.1 March 2013 Support for SmartFusion2 family is added. 5.0 May 2011 Streaming FFT architecture is added. The v5.0 release supports RTAX-DSP family only. 4.0 May 2010 As listed in the Table 7 below. The v4.0 release supports RTAX-DSP family only. 3.0 May 2007 Configurable 8- to 16-bit data precision. 2.0 September 2005 Initial release. 2 Resolved Issues in v6.4 Release Resolved Issues in v6.4 Release Table 2 shows the software action requests (SARs) resolved in the v6.4 release of CoreFFT. Table 2. Resolved SARs in CoreFFT v6.4 SAR No. Description 43888 Provide support for all devices of supported families. 47549 Indicate device type used for utilization and performance data of the handbook. 59864 Fix VHDL code causing synthesis failure. 62324 Add RTG4 support. Resolved Issues in v6.3 Release Table 3 shows the SARs resolved in the v6.3 release of CoreFFT. Table 3. Resolved SARs in CoreFFT v6.3 SAR No. Description 50390 Eliminate REN signal toggling on RTAX-DSP devices. 50391 Improve Streaming FFT performance. Resolved Issues in v6.2 Release Table 4 shows the SARs resolved in the v6.2 release of CoreFFT. Table 4. Resolved SARs in CoreFFT v6.2 SAR No. 48056 Description Support for IGLOO2 family. Resolved Issues in v6.1 Release Table 5 shows the SARs resolved in the v6.1 release of CoreFFT. Table 5. Resolved SARs in CoreFFT v6.1 SAR No. Description 38287 Support for SmartFusion2 family. 29129 Support for multiple FFT instances. Resolved Issues in v5.0 Release Table 6 shows the SARs resolved in the v5.0 release of CoreFFT. Table 6. Resolved SARs in CoreFFT v5.0 SAR No. 32053 Description Add streaming architecture. 3 CoreFFT v6.4 Release Notes Resolved Issues in v4.0 Release Table 7 shows the SARs resolved in the v4.0 release of CoreFFT. Table 7. Resolved SARs in CoreFFT v4.0 SAR No. Description 11570 Eliminate module names reserved by Libero IDE for other purposes. 11732 Resolve the core installation issues. 13857 Indicate in documentation the core output latency. Discontinued Features and Devices CoreFFT v6.4 does not support RTAX-DSP (RTAX2000D, RTAX4000D) devices. These devices are supported in CoreFFT v6.3 or earlier versions. Known Limitations and Workarounds There are no known issues or workarounds for CoreFFT v6.4 release. 4 Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. 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