M13S2561616A (2S)

ESMT
M13S2561616A (2S)
DDR SDRAM
4M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features

Double-data-rate architecture, two data transfers per clock cycle

Bi-directional data strobe (DQS)

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Four bank operation

CAS Latency : 2.5, 3, 4

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock (CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READs; center-aligned with data for WRITEs

Data mask (DM) for write masking only

VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V

7.8us refresh interval

Auto & Self refresh

2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
M13S2561616A -5TG2S
Max Freq.
VDD
Package
Comments
200MHz (DDR400)
66 pin TSOPII
M13S2561616A -6TG2S
166MHz (DDR333)
M13S2561616A -5BG2S
200MHz (DDR400)
2.5V
Pb-free
60 Ball BGA
M13S2561616A -6BG2S
166MHz (DDR333)
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2014
Revision : 1.0
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ESMT
M13S2561616A (2S)
Functional Block Diagram
Clock
Generator
Bank D
Bank C
Bank B
Address, BA
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
CLK
CLK
CKE
Bank A
DQS
DM
WE
Column Decoder
Data Control Circuit
CLK, CLK
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Input & Output
Buffer
CAS
Column
Address
Buffer
&
Refresh
Counter
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Sense Amplifier
DQ
DLL
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ESMT
M13S2561616A (2S)
PIN CONFIGURATION (TOP VIEW)
BALL CONFIGURATION (TOP VIEW)
(TSOPII 66L, 400milX875mil Body, 0.65mm Pin Pitch)
(BGA60, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch)
1
2
3
7
8
9
VSSQ
DQ15
VSS
VDD
DQ0
VDDQ
B DQ14
VDDQ
DQ13
DQ2
VSSQ
DQ1
C
DQ12
VSSQ
DQ11
DQ4
VDDQ
DQ3
D
DQ10
VDDQ
DQ9
DQ6
VSSQ
DQ5
E
DQ8
VSSQ
UDQS
LDQS
VDDQ
DQ7
F
VREF
VSS
UDM
LDM
VDD
NC
G
CLK
CLK
WE
CAS
H
A12
CKE
RAS
CS
J
A11
A9
BA1
BA0
K
A8
A7
A0
A10/AP
L
A6
A5
A2
A1
M
A4
VSS
VDD
A3
A
Pin Description
Pin Name
A0~A12,
BA0, BA1
DQ0~DQ15
Function
Pin Name
Function
Address inputs
- Row address A0~A12
- Column address A0~A8
A10/AP: AUTO Precharge
BA0, BA1: Bank selects (4 Banks)
LDM, UDM
DM is an input mask signal for write data.
LDM corresponds to the data on DQ0~DQ7;
UDM correspond to the data on DQ8~DQ15.
Data-in/Data-out
CLK, CLK
Clock input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
VDDQ
Supply Voltage for DQ
VSS
Ground
VSSQ
Ground for DQ
VDD
Power
VREF
Reference Voltage for SSTL_2
NC
No connection
Bi-directional Data Strobe.
LDQS, UDQS LDQS corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on DQ8~DQ15.
Elite Semiconductor Memory Technology Inc.
CKE
CS
Clock enable
Chip select
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ESMT
M13S2561616A (2S)
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
VDD, VDDQ
-1.0 ~ 3.6
V
VINPUT
-1.0 ~ 3.6
V
Voltage on I/O pins relative to VSS
VIO
-0.5 ~ VDDQ+0.5
V
Operating ambient temperature
TA
0 ~ +70
°C
TSTG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Voltage on VDD & VDDQ supply relative to VSS
Voltage on inputs relative to VSS
Storage temperature
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Conditions & Specifications
DC Operation Conditions
Recommended operating conditions (Voltage reference to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Supply voltage
VDD
2.3
2.7
V
I/O Supply voltage
VDDQ
2.3
2.7
V
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage (system)
VTT
VREF - 0.04
VREF + 0.04
V
2
Input logic high voltage
VIH (DC)
VREF + 0.15
VDDQ + 0.3
V
Input logic low voltage
VIL (DC)
-0.3
VREF - 0.15
V
Input Voltage Level, CLK and CLK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Differential Voltage, CLK and CLK inputs
VID (DC)
0.36
VDDQ + 0.6
V
3
V–I Matching: Pullup to Pulldown Current Ratio
VI (Ratio)
0.71
1.4
-
4
Input leakage current: Any input 0V  VIN  VDD
(All other pins not tested under = 0V)
IL
-2
2
A
Output leakage current
(DQs are disable; 0V  VOUT  VDDQ)
IOZ
-5
5
A
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Note
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ESMT
M13S2561616A (2S)
DC Operation Conditions - continued
Parameter
Symbol
Min
Output High Current (Full strength driver – Normal)
(VOUT =VDDQ-0.373V, min VREF, min VTT)
IOH
Output Low Current (Full strength driver – Normal)
(VOUT = 0.373V, max VREF, max VTT)
Max
Unit
Note
-15
mA
5, 7
IOL
+15
mA
5, 7
Output High Current (Reduced strength driver –Weak)
(VOUT = VDDQ-0.763V, min VREF, min VTT)
IOH
-9
mA
6
Output Low Current (Reduced strength driver – Weak)
(VOUT = 0.763V, max VREF, max VTT)
IOL
+9
mA
6
Output High Current (Reduced strength driver –
Matched impedance)
(VOUT = VDDQ-1.056V, min VREF, min VTT)
IOH
-4.5
mA
6
Output Low Current (Reduced strength driver –
Matched impedance)
(VOUT = 1.056V, max VREF, max VTT)
IOL
+4.5
mA
6
Notes:
1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25 V to 1.0 V. For a given output, it represents
the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
5. VOH = 1.95V, VOL =0.35V.
6. VOH = 1.9V, VOL =0.4V.
7. The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V.
The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.
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ESMT
M13S2561616A (2S)
IDD Parameters and Test Conditions
Test Condition
Symbol
Operating Current (one bank Active - Precharge):
tRC = tRC (min); tCK = tCK (min); DQ, DM, and DQS inputs changing once per clock cycle;
Note
IDD0
Address and control inputs changing once every two clock cycles; CS = high between valid commands.
Operating Current (one bank Active - Read - Precharge):
One bank open; BL = 4; tRC = tRC (min); tCK = tCK (min); IOUT = 0mA;
IDD1
2
Address and control inputs changing once per deselect cycle; CS = high between valid commands
Precharge Power-down Standby Current:
All banks idle; Power-down mode; tCK = tCK (min); CKE  VIL(max); VIN = VREF for DQ, DQS and DM.
IDD2P
Precharge Floating Standby Current:
CS  VIH(min); All banks idle; CKE  VIH(min); tCK = tCK (min);
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM.
Precharge Quiet Standby Current:
IDD2F
CS  VIH(min); All banks idle; CKE  VIH(min); tCK = tCK (min);
Address and other control inputs stable at  VIH(min) or  VIL(max); VIN = VREF for DQ, DQS, and DM.
IDD2Q
Active Power-down Standby Current:
One bank active; Power-down mode; CKE  VIL(max); tCK = tCK (min); VIN = VREF for DQ, DQS, and DM.
IDD3P
Active Standby Current:
CS  VIH(min); CKE  VIH(min); One bank active; tRC = tRAS (max); tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle.
IDD3N
Operating Current (burst read):
BL = 2; Continuous burst reads; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min); IOUT = 0mA;
50% of data changing on every transfer.
IDD4R
Operating Current (burst write):
BL = 2; Continuous burst writes; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle; 50% of input data changing at every transfer.
IDD4W
Auto Refresh Current:
tRC = tRFC(min)
IDD5
Self Refresh Current:
CKE  0.2V; external clock on; tCK = tCK (min)
Operating Current (Four bank operation):
Four-bank interleaving READs (burst = 4) with auto precharge; tRC = tRC (min); tCK = tCK (min);
Address and control inputs change only during ACTIVE, READ, or WRITE commands; IOUT = 0mA.
IDD6
1
IDD7
2
Notes:
1. Enable on-chip refresh and address counters.
2. Random address is changing; 50% of data is changing at every transfer.
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Publication Date : Apr. 2014
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ESMT
M13S2561616A (2S)
IDD Specifications
Version
Symbol
Unit
-5
-6
IDD0
80
70
mA
IDD1
110
100
mA
IDD2P
4
4
mA
IDD2F
30
30
mA
IDD2Q
30
30
mA
IDD3P
25
20
mA
IDD3N
55
50
mA
IDD4R
130
120
mA
IDD4W
130
120
mA
IDD5
140
130
mA
IDD6
3
3
mA
IDD7
220
210
mA
Input / Output Capacitance
Parameter
Package
Input capacitance (A0~A12, BA0~BA1,
TSOP
CKE, CS , RAS , CAS , WE )
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
Symbol
CIN1
CIN2
COUT
CIN3
Min
Max
2
5
TBD
TBD
2
4
TBD
TBD
1
4
TBD
TBD
1
4
TBD
TBD
Delta Cap
(max)
0.5
0.25
0.5
0.5
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Note
1,4
1,4
1,2,3,4
1,2,3,4
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. VDDQ = 2.5V ± 0.2V, VDD = 2.5V ± 0.2V. f=100MHz, TA =25°C, VOUT(DC) = VDDQ/2, VOUT
(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to
facilitate trace matching at the board level).
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M13S2561616A (2S)
AC Operation Conditions & Timing Specifications
AC Operation Conditions
Parameter
Symbol
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CLK and CLK inputs
VID(AC)
Input Crossing Point Voltage, CLK and CLK inputs
VIX(AC)
Unit
Note
V
VREF - 0.31
V
0.7
VDDQ+0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Notes:
1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of
the same.
AC Overshoot / Undershoot Specification
Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
Maximum undershoot area below VSS
Elite Semiconductor Memory Technology Inc.
Pin
Value
-5 / -6
Unit
Address, Control
1.5
V
Data, Strobe, Mask
1.2
V
Address, Control
1.5
V
Data, Strobe, Mask
1.2
V
Address, Control
4.5
V-ns
Data, Strobe, Mask
2.4
V-ns
Address, Control
4.5
V-ns
Data, Strobe, Mask
2.4
V-ns
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M13S2561616A (2S)
AC Timing Parameter & Specifications (Note: 1~6, 9~10)
Parameter
Symbol
CL2.5
Clock period
CL3
tCK
CL4
-5
-6
min
max
min
max
5
12
6
12
5
12
6
12
5
12
6
12
Unit
Note
ns
DQ output access time from CLK/ CLK
tAC
-0.7
+0.7
-0.7
+0.7
ns
CLK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
tDQSCK
-0.6
+0.6
-0.6
+0.6
ns
Clock to first rising edge of DQS delay
tDQSS
0.72
1.25
0.72
1.25
tCK
DQ and DM input setup time (to DQS)
tDS
0.4
0.4
ns
DQ and DM input hold time (to DQS)
tDH
0.4
0.4
ns
tDIPW
1.75
1.75
ns
18
Address and Control input setup time
(fast)
tIS
0.6
0.6
ns
15,
17~19
Address and Control input hold time
(fast)
tIH
0.6
0.6
ns
15,
17~19
Address and Control input setup time
(slow)
tIS
0.8
0.8
ns
16~19
Address and Control input hold time
(slow)
tIH
0.8
0.8
ns
16~19
tIPW
2.2
2.2
ns
18
DQS input high pulse width
tDQSH
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
tCK
DQS falling edge to CLK setup time
tDSS
0.2
0.2
tCK
DQS falling edge hold time from CLK
tDSH
0.2
0.2
tCK
Data strobe edge to output data edge
tDQSQ
0.4
0.4
ns
22
tHZ
+0.7
+0.7
ns
11
+0.7
ns
11
DQS output access time from
CLK/ CLK
DQ and DM input pulse width (for each
input)
Control and Address input pulse width
(for each input)
Data-out high-impedance time from
CLK/ CLK
Data-out low-impedance time from
tLZ
-0.7
Clock half period
tHP
tCLmin
or
tCHmin
tCLmin
or
tCHmin
ns
20,21
DQ/DQS output hold time from DQS
tQH
tHP- tQHS
tHP- tQHS
ns
21
Data hold skew factor
tQHS
CLK/ CLK
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+0.7
0.5
-0.7
0.5
ns
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M13S2561616A (2S)
AC Timing Parameter & Specifications – continued
Parameter
Symbol
-5
-6
min
max
min
max
70K
42
70K
Unit
Active to Precharge command
tRAS
40
Active to Active / Auto Refresh
command period
tRC
55
60
ns
Auto Refresh to Active / Auto Refresh
command period
tRFC
70
72
ns
Active to Read, Write delay
tRCD
15
18
ns
Precharge command period
tRP
15
18
ns
Active to Read with Auto Precharge
command
tRAP
15
18
ns
Active bank A to Active bank B
command
tRRD
10
12
ns
Write recovery time
tWR
15
15
ns
Write data in to Read command delay
tWTR
2
2
tCK
Average periodic refresh interval
tREFI
Write preamble
tWPRE
0.25
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Clock to DQS write preamble setup time
tWPRES
0
0
ns
Mode Register Set command cycle time
tMRD
2
2
tCK
Exit self refresh to Read command
tXSRD
200
200
tCK
Exit self refresh to non-Read command
tXSNR
75
75
ns
Auto Precharge write
recovery+precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
Notes:
1.
2.
3.
7.8
7.8
0.25
Note
ns
us
14
tCK
12
13
23
All voltages referenced to VSS.
Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
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4.
M13S2561616A (2S)
AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still
7.
8.
referenced to VREF (or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the
range between VIL(AC) and VIH(AC).
The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively
switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤
0.2VDDQ is recognized as LOW.
Enables on-chip refresh and address counters.
IDD specifications are tested after the device is properly initialized.
9.
The CLK/ CLK input reference level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross;
5.
6.
the input reference level for signals other than CLK/ CLK , is VREF.
10. The output timing reference voltage level is VTT.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level but specify when the device output is no longer driving (tHZ), or begins driving
(tLZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending
on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
17. For CLK & CLK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
19. Slew Rate is measured between VOH(AC) and VOL(AC).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are =
50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to
crosstalk (tJIT(crosstalk)) into the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts
for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition
followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
22. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers
for any given cycle.
23. For each of the terms above, if not already an integer, round to the next highest integer.
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M13S2561616A (2S)
Command Truth Table
COMMAND
CKEn-1 CKEn CS
RAS
CAS
WE
DM
BA0,
BA1
A10/AP
A12~A11,
Note
A9~A0
Register
Extended MRS
H
X
L
L
L
L
X
OP CODE
1,2
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
Auto Refresh
Refresh
Entry
Self Refresh
Exit
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
V
V
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Entry
H
L
H
X
X
X
L
H
H
H
Exit
L
H
Auto Precharge Disable
Write &
Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Terminate
Bank Selection
All Banks
Precharge Power Down
Mode
Deselect (NOP)
No Operation (NOP)
L
H
Bank Active & Row Addr.
Active Power Down Mode
H
L
Read &
Column
Address
Precharge
H
Entry
H
L
Exit
L
H
H
X
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
3
3
3
Row Address
L
H
L
X
3
H
Column
Address
(A0~A8)
Column
Address
(A0~A8)
X
V
L
X
H
4
4
4,8
4,6,8
7
X
5
X
X
X
X
X
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Notes:
1. OP Code: Operand Code. A0~A12 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst Terminate command is valid at every burst length.
8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding
and coincident DM is “High”. (Write DM latency is 0).
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ESMT
M13S2561616A (2S)
Basic Functionality
Power-Up and Initialization Sequence
DDR SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified
may result in undefined operation. No power sequencing is specified during power up and power down given the following
criteria:

VDD and VDDQ are driven from a single power converter output, AND

VTT is limited to 1.35 V, AND

VREF tracks VDDQ /2
OR, the following relationships must be followed:

VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V, AND

VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V, AND

VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V.
At least one of these two conditions must be met.
Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an
LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee
that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read
access).
After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 μs delay prior
to applying an executable command. Once the 200 μs delay has been satisfied, a DESELECT or NOP command should be
applied, and CKE should be brought HIGH.
Following the NOP command, a PRECHARGE ALL command should be applied. Next a MODE REGISTER SET command
should be issued for the Extended Mode Register, to enable the DLL, and then a MODE REGISTER SET command should be
issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required
between the DLL reset and any executable command. A PRECHARGE ALL command should be applied, placing the device in
the ”all banks idle” state.
Once in the idle state, two AUTO refresh cycles must be performed. Additionally, a MODE REGISTER SET command for the
Mode Register, with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) must be
performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
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ESMT
M13S2561616A (2S)
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the register is not defined, therefore the mode register must be written after
EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE
and BA0~BA1 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register).
The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the
mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle
state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing
mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL
reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing
modes and CAS latencies.
BA1
BA0
0
0
A12
A11
A10
A9
RFU
A8
A7
A6
A5
A4
A3
DLL
TM
CAS Latency
BT
A2
A1
A0
Burst Length
A8
DLL Reset
A7
Mode
A3
Burst Type
0
No
0
Normal
0
Sequential
1
Yes
1
Test
1
Interleave
Address Bus
Mode Register
Burst Length
CAS Latency
BA1
0
0
BA0
0
1
Operating Mode
MRS Cycle
EMRS Cycle
A6
0
0
0
0
1
1
1
A5
0
0
1
1
0
1
1
A4
0
1
0
1
0
0
1
Latency
Reserved
Reserved
Reserved
3
4
2.5
Reserved
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Length
Sequential Interleave
Reserved Reserved
2
2
4
4
8
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Note: RFU (Reserved for future use) must stay “0” during MRS cycle.
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ESMT
M13S2561616A (2S)
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL, and selecting output drive strength. The default value of
the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or
disabling DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of
address pins A0~A12 and BA0~BA1 in the same cycle as CS , RAS , CAS and WE going low is written in the extended
mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle
state. A0 is used for DLL enable or disable. A1 and A6 are used for selecting output drive strength. “High” on BA0 is used for
EMRS. All the other address pins except A0~A1, A6 and BA0 must be set to low for proper EMRS operation. Refer to the table
for specific codes.
BA1 BA0 A12 A11 A10
0
1
A9
A8
RFU
BA1
BA0
Operating Mode
0
0
MRS Cycle
0
1
EMRS Cycle
A7
A6
A5
DS
A4
A3
A2
RFU
A1
A0
DS DLL
Address Bus
Extended Mode Register
A6
A1
Drive Strength
A0
DLL Enable
0
0
Normal
0
Enable
0
1
Weak
1
Disable
1
0
RFU
1
1
Matched impedance
Note: RFU (Reserved for future use) must stay “0” during EMRS cycle.
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ESMT
M13S2561616A (2S)
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address (A2, A1, A0)
Sequential Mode
Interleave Mode
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
2
4
8
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning
to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode,
the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command
can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support reduced drive
strength options, intended for lighter load and/or point-to-point environments.
Mode Register
0
1
2
3
4
5
6
7
CLK
CLK
*1
Precharge
All Banks
CO MMAND
tC K
Any
Command
MRS / EMRS
t R P* 2
tMRD
*1: MRS/EMRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS/EMRS command.
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ESMT
M13S2561616A (2S)
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min) must be satisfied until the precharge command can be
issued. After tRP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by bank address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
No Operation & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect
and NOP the device should finish the current operation when this command is issued.
Bank / Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock (CLK). The DDR SDRAM has four independent banks, so Bank Select addresses (BA0, BA1) are required. The Bank
Activation command must be applied before any Read or Write operation is executed. The Bank Activation command to the first
Read or Write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been
activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time
interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD
min).
Bank Activation Command Cycle ( CAS Latency = 3)
0
1
2
3
Tn
Tn+1
Tn+2
CLK
CLK
Address
Bank A
Row Addr.
Bank A
Col . Ad dr.
RAS-CAS delay (tRCD)
Command
Bank A
Activate
NOP
NOP
Bank A
Row. Ad dr.
Bank B
Row Addr.
RAS-RAS delay (tRRD)
Write A
with AP
Bank B
Activate
NOP
Bank A
Activate
ROW Cycle Time (tRC)
: Don't Care
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ESMT
M13S2561616A (2S)
Read
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , RAS , CAS , and deasserting WE at the same clock rising edge as described in the command truth table. The
length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , RAS , CAS , and WE at the same clock rising edge as describe in the command truth table. The length of the
burst will be determined by the values programmed during the MRS command.
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD
from the bank activation. The address inputs determine the starting address for the Burst. The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR
SDRAM until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C LK
CL K
RE A D A
C OM M A N D
N OP
NO P
NO P
NO P
NO P
NOP
t RP S T
tR P RE
D QS
N OP
NOP
C A S L a t e n cy = 3
DOU T0 DOU T1 DOU T2 DOU T3
DQ 's
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for
burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS prior to data strobe edge enabled after
tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on
each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished,
any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
2
*1
3
4
5
6
7
8
CLK
CLK
CO MMAND
NOP
W R ITE A
NOP
tDQSS
NOP
W RITE B
NOP
NOP
NOP
NOP
max
DQS
*1
tW PRES
*1
DQ's
Note * 1: The specific requirement is that DQS be valid (High or Low) on or before this CLK edge. The case shown (DQS going from
High-Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS
could be High at this time, depending on tDQSS.
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ESMT
M13S2561616A (2S)
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this
point the data from the interrupting Read command appears. Read to Read interval is tCCD(min).
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C LK
C LK
t C CD ( m i n )
CO MMA ND
DQ S
DQ 's
RE A D A
RE A D B
NO P
N OP
NO P
NO P
NO P
N OP
NO P
Hi -Z
Hi- Z
D OUT A0 DOUT A1 D OUT B0 D OUT B 1 DOUT B2 D OUT B3
Read Interrupted by a Write & Burst Terminate
To interrupt a burst read with a write command, Burst Terminate command must be asserted to avoid data contention on the I/O
bus by placing the DQ’s (Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the
beginning the write operation, Burt stop command must be applied at least RU(CL) clocks [RU mean round up to the nearest
integer] before the Write command.
<Burst Length = 4, CAS Latency = 3>
CLK
0
1
2
3
4
5
6
7
8
CLK
COMMAND
READ
Burst
Te r m i n a t e
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
DQS
DQ's
D OUT 0 D OUT 1
D IN
0
D IN
1
DI N
2
DI N
3
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate
the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a
Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.
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M13S2561616A (2S)
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
CLK
0
1
2
3
4
5
6
7
8
CLK
1tCK
COMMAND
READ
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ's
DOUT 0 D OUT 1 D OUT 2 D OUT 3 D OUT 4 D OUT 5 DOUT 6 D OUT 7
Interrupted by prec harge
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before
the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read
burst and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on
the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new
Bank Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock
edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once
the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the
same bank after tRP.
3. For a Read with auto precharge command, a new Bank Activate command may be issued to the same bank after tRP
where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS
Latency. During Read with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest
possible external Precharge command would initiate a precharge operation without interrupting the Read burst as
described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles
between a Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the
clock cycle time) with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS (min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with auto precharge commands where tRAS (min) must still be satisfied such that a Read with
auto precharge command has the same timing as a Read command followed by the earliest possible Precharge command
which does not interrupt the burst.
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ESMT
M13S2561616A (2S)
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is
satisfied.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C LK
C LK
1 tCK
CO MMAND
DQ S
DQ 's
N OP
W RIT E A
W R IT E B
N OP
DI N A 0
D IN B0
NO P
NO P
N OP
NO P
NOP
Hi -Z
Hi- Z
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D IN A1
DI N B1
DIN B2
DI N B 3
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ESMT
M13S2561616A (2S)
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is
registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command
(tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command
is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of
that of write command.
<Burst Length = 8, CAS Latency = 3>
0
CLK
1
2
3
4
5
6
7
8
CLK
COMMAND
NOP
NOP
W RITE
NOP
NOP
NOP
NOP
NOP
tWTR
tDQSS(max)
DQS
READ
Hi-Z
*5
tWPRES
DQ's
DIN0
H i- Z
DIN1
DIN2
DIN3
DIN4 DIN5
DIN6
DIN7
D O UT 0 D OUT 1
DM
tWTR
tDQSS(min)
DQS
Hi-Z
*5
tWPRES
DQ's
Hi-Z
DIN0
DIN1
DIN2
DIN3
DIN4 DIN5
DIN6
DIN7
D O UT0 D OUT1
DM
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into
the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the DDR SDRAM.
5. Refer to “Burst write operation”
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M13S2561616A (2S)
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column
access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command
is asserted, any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
0
CLK
1
2
3
4
5
6
7
Precharge A
W RITE B
8
CLK
CO MMAND
W RITE A
NOP
NOP
NOP
NOP
Hi-Z
DQ's
Hi-Z
tWPRES
NOP
tWR
tDQSS(max)
DQS
NOP
*5
D INA0 D INA1
D INA2 D INA3
D INA4 D IN A5 D INA6 D INA7
D IN B0
DM
tWR
tDQSS(min)
DQS
Hi-Z
tWPRES
DQ's
Hi-Z
*5
D INA0 D INA1
D INA2 D INA3
D I NA4 D INA5 D INA6 D INA7
D INB0 D INB1
DM
Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the time required by a
DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used
to indicate the required of time between the last valid write operation and a Precharge command to the same bank.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge
that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the
time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the
DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
3. For a Write with auto precharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where
tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
Bank Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same time as the
earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with auto precharge commands where tRAS(min) must still be satisfied such that a Write with auto
precharge command has the same timing as a Write command followed by the earliest possible Precharge command which does
not interrupt the burst.
5. Refer to “Burst write operation”
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M13S2561616A (2S)
Burst Terminate
The burst terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the
clock (CLK). The burst terminate command has the fewest restrictions making it the easiest method to use when terminating a
burst read operation before it has been completed. When the burst terminate command is issued during a burst read cycle, the
pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the
mode register. The burst terminate command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
0
1
2
3
4
5
6
7
8
CLK
CLK
CO MMAND
READ A
Burst
Terminate
NOP
NOP
NOP
NOP
NOP
NOP
NOP
The burst read ends after a deley equal to the CAS lantency.
DQS
Hi-Z
DQ's
Hi-Z
DOUT 0 DOUT 1
The Burst Terminate command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with auto precharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to
data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
CLK
0
1
2
3
4
5
6
7
8
CLK
CO MMA ND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSS
DQS
DQ's
Hi-Z
DIN
0
DIN
1
DIN
2
DIN
3
DIN
4
DIN
5
DIN
6
DIN
7
Hi-Z
DM
tDS tDH
masked by DM=H
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M13S2561616A (2S)
Read With Auto Precharge
If a read with auto precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto precharge command when tRAS (min) is satisfied. If not, the start point of precharge operation will be
delayed until tRAS (min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied.
<Burst Length = 4, CAS Latency = 2.5>
0
CLK
CLK
COMMAND
1
Bank A
ACTIVE
2
NOP
NOP
tRAS
3
4
Read A
Auto Precharge
NOP
5
NOP
6
7
NOP
NOP
8
Hi-Z
DQ's
Hi-Z
NOP
NOP
(min)
* Bank can be reactivated at
completion of precharge
tRP
DQS
9
CAS Latency = 2.5
DOUT 0 DOUT 1 DOUT 2 DOUT 3
Auto-Precharge starts
When the Read with Auto Precharge command is issued, new command can be asserted at 4, 5 and 6 respectively as follow.
Asserted
Command
For the same bank
For the different bank
4
5
6
4
5
6
READ
Illegal
Illegal
Legal
Legal
Legal
READ with AP
Illegal
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Legal
Legal
Legal
Precharge
Legal
Legal
Illegal
Legal
Legal
Legal
READ
READ with AP*1
Note 1: AP = Auto Precharge
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M13S2561616A (2S)
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of
the CLK with the tWR delay after the last data-in.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
CLK
CLK
COMMAND
Bank A
ACTIVE
NOP
Write A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
DQS
*Bank can be reactivated
at completion of t RP
DQ's
D IN
0
D IN
1
D IN
D IN
2
3
tWR
tRP
Internal precharge start
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Asserted
Command
For the same bank
For the different bank
4
5
6
7
8
4
5
6
7
8
WRITE
WRITE
WRITE
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
WRITE with AP*1
WRITE
with AP
WRITE
with AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
READ
Illegal
READ +
*2
DM
READ+
DM
READ
Illegal
Illegal
Illegal
Illegal
Legal
Legal
READ with AP
Illegal
READ
with AP+
DM
READ
with AP+
DM
READ
with AP
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Active
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Precharge
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Note: 1. AP = Auto Precharge
2. DM: Refer to “Write Interrupted by a Read & DM“
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M13S2561616A (2S)
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of
the clock (CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of
the external address pins is requires once this cycle has started because of the internal address counter. When the refresh
cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate
command or subsequent auto refresh command must be greater than or equal to the tRFC(min).
A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given DDR SDRAM
meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 8 x tREFI .
CLK
CLK
CO MMA ND
Auto
Refr esh
PRE
CMD
CKE = High
tRFC
tRP
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During
the self refresh operation, all inputs except CKE are ignored. Since CKE is an SSTL_2 input, VREF must be maintained during
self refresh. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited
by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high
for longer than tXSRD for locking of DLL.
CLK
CLK
CO MMAND
NOP
Sel f
Ref resh
NOP
NOP
NOP
NOP
A uto
Ref resh
NOP
tXSNR(m in)
CKE
tIS
tIS
Note: After self refresh exit, input an auto refresh command immediately.
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M13S2561616A (2S)
Power down
Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode
is referred to as active power-down.
Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low
must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is at least 1 tCK + tIS.
However, power down duration is limited by the refresh requirements of the device.
The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A
valid command may be applied 1 tCK + tIS after exit from power down.
CLK
CLK
tRP
CKE
tIS
tIS
CO MMAND
Precharge
tIS
tIS
Active
E n t e r P re c h a rg e
p o w e r- d o wn
mode
Exit Precharge
p o we r -d o wn
mo de
Read
E n t e r Ac ti v e
p o w e r- d o wn
mode
E x it A c t i v e
p o we r -d o w n
mo de
Functional Truth Table
Truth Table – CKE [Note 1~4, 6]
CKE n-1
CKE n
Current State
COMMAND n
ACTION n
L
L
Power Down
X
Maintain Power Down
L
L
Self Refresh
X
Maintain Self Refresh
L
H
Power Down
NOP or DESELECT
Exit Power Down
L
H
Self Refresh
NOP or DESELECT
Exit Self Refresh
H
L
All Banks Idle
NOP or DESELECT
Precharge Power Down Entry
H
L
Bank(s) Active
NOP or DESELECT
Active Power Down Entry
H
L
All Banks Idle
AUTO REFRESH
H
H
NOTE
7
5, 7
Self Refresh Entry
See the Truth Tables as follow
Notes:
1.
2.
3.
4.
5.
CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of DDR SDRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n.
All states and sequences not shown are illegal or reserved.
DESELECT and NOP DESELECT or NOP commands should be issued on any clock edges occurring during the tXSNR or
tXSRD period. A minimum of 200 clock cycles is needed before applying any executable command, for the DLL to lock.
6. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the
DRAM must be powered down and then restarted through the specified initialization sequence before normal operation
can continue.
7. VREF must be maintained during Self Refresh operation.
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M13S2561616A (2S)
Truth Table – Current State Bank n
Current State
CS
RAS
CAS
WE
COMMAND / ACTION
NOTE
Command to Bank n [Note 1~6,13]
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
H
X
X
X
DESELECT (NOP / continue previous operation)
L
H
H
H
No Operation (NOP / continue previous operation)
L
L
H
H
ACTIVE (select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
MODE REGISTER SET
7
L
H
L
H
READ (select column & start read burst)
10
L
H
L
L
WRITE (select column & start write burst)
10
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
8
L
H
L
H
READ (select column & start new read burst)
10
L
H
L
L
WRITE (select column & start write burst)
10, 12
L
L
H
L
PRECHARGE (truncate read burst, start precharge)
8
L
H
H
L
BURST TERMINATE
9
L
H
L
H
READ (select column & start read burst)
10, 11
L
H
L
L
WRITE (select column & start new write burst)
10
L
L
H
L
PRECHARGE (truncate write burst, start precharge)
8, 11
DESELECT (NOP / continue previous operation)
Command to Bank m
Any
Idle
Row Activating,
Active, or
Precharging
Read
(Auto Precharge
disabled)
Write
(Auto Precharge
disabled)
Read with
Auto Precharge
Write with
Auto Precharge
[Note 1~3, 6,13~15]
H
X
X
X
L
H
H
H
No Operation (NOP / continue previous operation)
X
X
X
X
Any command allowed to bank m
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start read burst)
10
10
L
H
L
L
WRITE (select column & start write burst)
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start new read burst)
10
L
H
L
L
WRITE (select column & start write burst)
10, 12
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start read burst)
10, 11
L
H
L
L
WRITE (select column & start new write burst)
10
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start new read burst)
3a, 10
L
H
L
L
WRITE (select column & start write burst)
3a, 10, 12
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column & start read burst)
3a, 10
L
H
L
L
WRITE (select column & start new write burst)
3a, 10
L
L
H
L
PRECHARGE
Notes:
1.
This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSNR or tXSRD has been met (if the previous
state was self refresh).
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ESMT
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
M13S2561616A (2S)
This table is bank - specific, except where noted, i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read / Write: A READ / WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet
terminated or been terminated.
Read / Write with Auto Precharge Enabled: See following text, notes 3a, 3b:
3a. For devices which do not support the optional “concurrent auto precharge” feature, the Read with Auto
Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined
as if the same burst was executed with Auto Precharge disabled and then followed with the earliest
possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto
Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was
disabled. The access period starts with registration of the command and ends where the precharge
period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write
with Auto Precharge Enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other
bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other
bank may be applied. In either case, all other related limitations apply (e.g., contention between READ
data and WRITE data must be avoided).
3b. For devices which do support the optional “concurrent auto precharge” feature, a read with auto precharge
enabled, or a write with auto precharge enabled, may be followed by any command to the other banks,
as long as that command does not interrupt the read or write data transfer, and all other related
limitations apply (e.g., contention between READ data and WRITE data must be avoided.)
The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands,
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and Truth Table.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the
bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the
bank will be in the ”row active” state.
Read/ Write with Auto Precharge Enabled: Starts with registration of a READ / WRITE command with AUTO PRECHARGE enabled
and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
The following states must not be interrupted by any executable command; DESELECT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRFC is met, the DDR SDRAM will be in the ”all banks idle” state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD
has been met. Once tMRD is met, the DDR SDRAM will be in the ”all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank - specific; requires that all banks are idle and no bursts are in progress.
May or may not be bank - specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
Not bank - specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
Reads or Writes listed in the Command/Action column include Reads or Writes with AUTO PRECHARGE enabled and
Reads or Writes with AUTO PRECHARGE disabled.
Requires appropriate DM masking.
A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst Terminate must be
used to end the READ prior to asserting a WRITE command,
Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the
DRAM must be powered down and then restarted through the specified initialization sequence before normal operation
can continue.
AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
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M13S2561616A (2S)
Timing Diagram
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
tCH tCL
tCK
tCH tCL
tC K
HIGH
CKE
tIS
CS
tIH
RAS
CAS
BA0,BA1
BAa
A10/AP
Ra
ADDR
(A0~An)
Ra
BAa
BAb
Ca
Cb
WE
tD QSC K
tRPRE
DQS
tDQSCK
tDQSS
tRPST
tDQSL
tWPST
Hi-Z
tDQSH
tDQSQ
tLZ
Qa0
DQ
Qa1
tAC
Qa2
tWPRES
tHZ
Qa3
tWPRE
tDS tDH tDS tDH
Hi-Z
Db0
Db1
Db2
Db3
Hi-Z
tQH
DM
CO MMA ND
ACTIVE
READ
WRITE
: Don’t care
10122B16R.B1
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M13S2561616A (2S)
Multi Bank Interleaving READ (@ BL=4, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
Ra
Rb
ADDR
(A0~An)
Ra
Rb
BAa
BAb
Ca
Cb
WE
DQS
DQ
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
DM
tCCD
tRCD
CO MMAND
ACTIVE
tRRD
ACTIVE
READ
READ
: Don’t care
10122B16R.B1
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M13S2561616A (2S)
Multi Bank Interleaving WRITE (@ BL=4)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BAa
BAb
A10/AP
Ra
Rb
ADDR
(A0~An)
Ra
Rb
BA0,BA1
BAa
BAb
Ca
Cb
WE
DQS
DQ
Da0
Da1
Da 2
Da3
Db0
Db 1
Db2
Db3
DM
tRCD
CO MMA ND
tCCD
ACTIVE
ACTIVE
tRRD
WRITE
WRITE
tRCD
: D on’t care
10122B16R.B
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M13S2561616A (2S)
Read with Auto Precharge (@ BL=8)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAa
Ca
Ra
A10/AP
A DDR
(A0~An)
WE
Auto prechar ge start
tRP
Note1
DQS(CL=2.5)
D Q(CL=2.5)
Qa0
Qa1
Qa2
Qa3
Qa4
Qa 5
Qa 6
Qa7
Qa0
Qa1
Qa2
Qa3
Qa 4
Qa5
Qa6
DQS(C L=3)
DQ(CL=3)
Qa7
DM
COMMAND
READ
ACTIVE
: Don’t care
10122B16R.B1
Note: 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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M13S2561616A (2S)
Write with Auto Precharge (@ BL=8)
CLK
0
1
2
3
4
5
6
7
8
9
10
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAa
Ca
Ra
A10 /AP
ADDR
(A0~An)
WE
tWR
tDAL
Auto prechar ge start
Note1
tRP
DQS
DQ
Da 0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
DM
CO MMA ND
ACTIVE
WRITE
: Don’t care
10122B16R.B
Note: 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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ESMT
M13S2561616A (2S)
Write followed by Precharge (@ BL=4)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAa
A10/AP
ADDR
(A0~An)
Ca
WE
tWR
DQS
Da0
DQ
Da1
Da2
Da3
DM
COMMAND
WRITE
PRE
CHARGE
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
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ESMT
M13S2561616A (2S)
Write Interrupted by Precharge & DM (@ BL=8)
0
1
2
3
4
0
1
2
3
4
5
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAa
BAb
BAc
Cb
Cc
A10/AP
ADDR
(A0~An)
Ca
WE
DQS
Da0
DQ
Da1
Da2
D a3
Da4
Da5
Da6
Da7
Db0
Db1
Dc0
Dc1
Dc2
Dc3
DM
tCCD
CO MMAND
WRITE
PRE
CHARGE
WRITE
WRITE
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
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ESMT
M13S2561616A (2S)
Write Interrupted by a Read (@ BL=8, CL= 3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
Ca
Cb
A10/AP
ADDR
(A0~An)
WE
DQS
Da0
DQ
Da1
Da2
Da3
Da4
Da5
Qb0
Qb1
Qb2
Qb 3
Qb4
Qb5
DM
tWTR
CO MMAND
WRITE
READ
: Don’t care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
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ESMT
M13S2561616A (2S)
Read Interrupted by Precharge (@ BL=8)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR
(A0~An)
Ca
WE
DQS(CL=2.5)
2.5 tCK Valid
Qa0
DQ(C L=2.5)
Qa1
Qa2
Qa 3
Qa4
Qa5
DQS(CL=3)
3 tCK Valid
Qa0
DQ(CL=3)
Qa1
Qa2
Qa3
Qa4
Qa5
DM
COMMAND
READ
PRE
CHARGE
: Don’t care
10122B16R.B1
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the
Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst
and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on
the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS Precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock
edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the
last data word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same
bank after tRP.
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ESMT
M13S2561616A (2S)
Read Interrupted by a Write & Burst Terminate (@ BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
Ca
Cb
A10/AP
ADDR
(A0~An)
WE
DQS
DQ
Qa0
Qa1
Db0
Db1
Db2
Db3
Db4
db5
Db 6
Db7
DM
CO MMA ND
READ
Burst
Terminate
WRITE
: Don’t car e
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
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ESMT
M13S2561616A (2S)
Read Interrupted by a Read (@ BL=8, CL=3)
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
BAb
Ca
Cb
A10 /AP
ADDR
(A0~An)
WE
DQS
Qa0
DQ
Qa1
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb6
Qb7
DM
tCCD
CO MMA ND
READ
READ
: Don’t care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
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ESMT
M13S2561616A (2S)
DM Function (@ BL=8) only for write
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
CS
RAS
CAS
BA0,BA1
BAa
A10/AP
ADDR
(A0~An)
Ca
WE
DQS
Da0
DQ
Da1
Da2
Da3
Da4
Da5
Da6
Da7
DM
COMMAND
WRITE
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
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ESMT
M13S2561616A (2S)
Power up & Initialization Sequence (based on DDR400)
VDD
VDDQ
tVDT >=0
VTT
(system*)
V REF
tCH
tCK
tCL
CLK
CLK
tIS tIH
CKE
LV C O M S L O W L E V E L
tIS tIH
NOP
COMMAND
PRE
EMRS
AR
PRE
MRS
AR
MRS
ACT
CODE
RA
CODE
RA
BA0=L,
BA1=L
BA
DM
tIS tIH
A 0-A9
A 11 - A n
CODE
CODE
tIS tIH
tIS tIH
tIS tIH
CODE
CODE
A10
ALL BANKS
BA0, BA1
ALL BANKS
tIH tIS
BA0=L,
BA1=L
BA0=H,
BA1=L
DQS
High-Z
DQ
High -Z
T=200us
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
200 cycles of CLK**
Power-up:
VDD and
CLK stable
Extended
Mode
Registe r
Set
Load
Mode
Register
Reset DLL
(with A8=H)
Load
Mode
Register
(with A8=L)
: Don’t care
10122B16R.B
Notes:
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CLK are required before an executable
command can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the
second PRECHARGE ALL command.
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ESMT
M13S2561616A (2S)
Mode Register Set
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
HIGH
CKE
tMRD
CS
RAS
CAS
WE
BA0,BA1
A10/AP
ADDRESS KEY
ADDR
(A0~An)
DS
DQ
DQS
tRP
High-Z
High-Z
Pre ch a rge
Command
All Bank
Mod e R egist er S et
C om m a nd
Any
Command
: Don’t care
10122B16R.B
Note: Power & Clock must be stable for 200us before precharge all banks.
Elite Semiconductor Memory Technology Inc.
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ESMT
M13S2561616A (2S)
Simplified State Diagram
Power
Applied
Power
On
Precharge
PREALL
Self
Refresh
REFS
REFSX
MRS
MRS
EMRS
REFA
Idle
Auto
Refresh
CKEL
CKEH
Active
Power
Down
Precharge
Power
Down
ACT
CKEH
CKEL
Burst Stop
Bank
Active
Write
Read
Write
Write A
Read A
Read
Read
Write
Read
Read A
Write A
Read A
Write
A
PRE
PRE
PRE
PRE
Read
A
Precharge
PREALL
Automatic Sequence
0911R.A
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
Elite Semiconductor Memory Technology Inc.
Command Sequence
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
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ESMT
M13S2561616A (2S)
PACKING
DIMENSIONS
66-LEAD
TSOP(II)
DDR DRAM(400mil)
Symbol
A
A1
A2
b
b1
c
c1
D
ZD
E
E1
e
L
L1

1
Dimension in inch
Min
Norm
Max
0.047
0.002
0.004
0.006
0.037
0.039
0.041
0.009
0.015
0.009
0.012
0.013
0.005
0.008
0.0047
0.005
0.006
0.875 BSC
0.028 REF
0.455
0.463
0.471
0.400 BSC
0.026 BSC
0.016
0.02
0.024
0.031 REF
0
10
Elite Semiconductor Memory Technology Inc.
15
Dimension in mm
Min
Norm
Max
1.2
0.05
0.1
0.15
0.95
1
1.05
0.22
0.38
0.22
0.3
0.33
0.12
0.21
0.12
0.127
0.16
22.22 BSC
0.71 REF
11.56
11.76
11.96
10.16 BSC
0.65 BSC
0.4
0.5
0.6
0.80 REF
8
0
20
10
8
15
20
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ESMT
M13S2561616A (2S)
PACKING
DIMENSIONS
60-BALL
DDR SDRAM
( 8x13 mm )
Symbol
Dimension in mm
Min
Norm
Max
A
1.00
A1
0.20
0.25
0.30
A2
0.71
Φb
0.30
0.35
0.40
D
7.90
8.00
8.10
E
12.90
13.00
13.10
D1
6.40
E1
11.0
e
0.80
e1
1.00
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min
Norm
Max
0.039
0.008
0.010
0.012
0.028
0.012
0.014
0.016
0.311
0.315
0.319
0.508
0.512
0.516
0.252
0.433
0.031
0.039
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ESMT
M13S2561616A (2S)
Revision History
Revision
Date
0.1
2012.12.26
0.2
2013.11.27
1.0
2014.04.29
Elite Semiconductor Memory Technology Inc.
Description
Original
1. Delete CAS Latency: 2
2. Modify the figure of burst write operation
1. Delete "Preliminary"
2. Modify Input / Output Capacitance of TSOP package
3. Delete speed grade -4
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ESMT
M13S2561616A (2S)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time
of publication. ESMT assumes no responsibility for any error in this document,
and reserves the right to change the products or specification in this document
without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but
not limited to, life support devices or system, where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage. If
products described here are to be used for such kinds of application, purchaser
must do its own quality assurance testing appropriate to such applications.
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