M14D128168A

ESMT
DDR II SDRAM
M14D128168A (2M)
2M x 16 Bit x 4 Banks
DDR II SDRAM
Features
z
JEDEC Standard
z
VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
z
Internal pipelined double-data-rate architecture; two data access per clock cycle
z
Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
z
On-chip DLL
z
Differential clock inputs (CLK and CLK )
z
DLL aligns DQ and DQS transition with CLK transition
z
1KB page size
-
Row address: A0 to A11
-
Column address: A0 to A8
z
Quad bank operation
z
CAS Latency : 3, 4, 5, 6, 7
z
Additive Latency: 0, 1, 2, 3, 4, 5
z
Burst Type : Sequential and Interleave
z
Burst Length : 4, 8
z
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z
Data I/O transitions on both edges of data strobe (DQS)
z
DQS is edge-aligned with data for READ; center-aligned with data for WRITE
z
Data mask (DM) for write masking only
z
On-Die-Termination for better signal quality
z
Special function support
-
50/ 75/ 150 ohm ODT
-
High Temperature Self refresh rate enable
-
DCC (Duty Cycle Corrector)
z
Auto & Self refresh
z
Refresh cycle :
z
-
4096 cycles/64ms (15.6μs refresh interval) at 0 ℃ ≦ TC ≦ +85 ℃
-
4096 cycles/32ms (7.8μs refresh interval) at +85 ℃ ＜ TC ≦ +95 ℃
SSTL_18 interface
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
1/59
ESMT
M14D128168A (2M)
Ordering Information:
Max Freq.
VDD
Data Rate
(CL-tRCD-tRP)
Package
M14D128168A - 1.8BG2M
533MHz
1.8V
DDR2-1066 (7-7-7)
84 ball FBGA
(Window BGA)
M14D128168A - 2.5BG2M
400MHz
1.8V
DDR2-800 (5-5-5)
A (max) = 1.2mm
M14D128168A - 1.8BVG2M
533MHz
1.8V
DDR2-1066 (7-7-7)
84 ball VFBGA
M14D128168A - 2.5BVG2M
400MHz
1.8V
DDR2-800 (5-5-5)
A (max) = 1.2mm
M14D128168A - 1.8BBG2M
533MHz
1.8V
DDR2-1066 (7-7-7)
84 ball FBGA
(Window BGA)
M14D128168A - 2.5BBG2M
400MHz
1.8V
DDR2-800 (5-5-5)
A (max) = 1.0mm
M14D128168A - 1.8BBVG2M
533MHz
1.8V
DDR2-1066 (7-7-7)
84 ball VFBGA
M14D128168A - 2.5BBVG2M
400MHz
1.8V
DDR2-800 (5-5-5)
A (max) = 1.0mm
Product ID
Comments
Pb-free
Functional Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
2/59
ESMT
M14D128168A (2M)
Ball Configuration (Top View)
(FBGA / VFBGA 84, 8mmX12.5mmX1.2mm Body, 0.8mm Ball Pitch)
(FBGA / VFBGA 84, 8mmX12.5mmX1.0mm Body, 0.8mm Ball Pitch)
1
2
3
7
8
9
A
VDD
NC
VSS
VSSQ
UDQS
VDDQ
B
DQ14
VSSQ
UDM
UDQS
VSSQ
DQ15
C
VDDQ
DQ9
VDDQ
VDDQ
DQ8
VDDQ
D
DQ12
VSSQ
DQ11
DQ10
VSSQ
DQ13
E
VDD
NC
VSS
VSSQ
LDQS
VDDQ
F
DQ6
VSSQ
LDM
LDQS
VSSQ
DQ7
G
VDDQ
DQ1
VDDQ
VDDQ
DQ0
VDDQ
H
DQ4
VSSQ
DQ3
DQ2
VSSQ
DQ5
J
VDDL
VREF
VSS
VSSDL
CLK
VDD
CKE
WE
RAS
CLK
ODT
BA0
BA1
CAS
CS
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
A12
NC
NC
NC
K
L
NC
M
N
VSS
P
R
VDD
VDD
VSS
Note: A12 (ball R2) is used for MRS/EMRS.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
3/59
ESMT
M14D128168A (2M)
Ball Description
Pin Name
Pin Name
Function
Address inputs
- Row address A0~A11
- Column address A0~A8
A12: use for MRS/EMRS
A10/AP : Auto Precharge
BA0, BA1 : Bank selects (4 Banks)
DM
(LDM, UDM)
DM is an input mask signal for write data.
LDM is DM for DQ0~DQ7 and UDM is DM
for DQ8~DQ15.
DQ0~DQ15
Data-in/Data-out
CLK, CLK
Differential clock input
RAS
Command input
CKE
CAS
Command input
CS
WE
Command input
VDDQ
Supply Voltage for DQ
VSS
Ground
VSSQ
Ground for DQ
VDD
Power
VREF
Reference Voltage
Bi-directional differential Data Strobe.
LDQS and /LDQS are DQS for DQ0~DQ7;
UDQS and /UDQS are DQS for DQ8~DQ15.
VDDL
Supply Voltage for DLL
VSSDL
Ground for DLL
A0~A12,
BA0,BA1
DQS, DQS
(LDQS, LDQS
Function
Clock enable
Chip select
UDQS, UDQS )
ODT
NC
On-Die-Termination.
ODT is only applied to DQ0~DQ15, DM, DQS
and /DQS.
No connection
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 2.3
V
Voltage on VDD supply relative to VSS
VDD
-1.0 ~ 2.3
V
Voltage on VDDL supply relative to VSS
VDDL
-0.5 ~ 2.3
V
Voltage on VDDQ supply relative to VSS
VDDQ
-0.5 ~ 2.3
V
Storage temperature
TSTG
-55 ~ +100
°C ( Note *)
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Note *: Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
4/59
ESMT
M14D128168A (2M)
Operation Temperature Condition
Parameter
Symbol
Value
Unit
TC
0 ~ +95
°C
Operation temperature
Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0 to +85℃ with full AC and DC specifications.
Supporting 0 to + 85℃ and being able to extend to + 95 ℃ with doubling auto-refresh commands in frequency to a
32ms period ( tREFI = 7.9μs ) and higher temperature Self-Refresh entry via A7 “1” on EMRS(2).
DC Operation Condition & Specifications
DC Operation Condition
(Recommended DC operating conditions)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Note
Supply voltage
VDD
1.7
1.8
1.9
V
4,7
Supply voltage for DLL
VDDL
1.7
1.8
1.9
V
4,7
Supply voltage for output
VDDQ
1.7
1.8
1.9
V
4,7
Input reference voltage
VREF
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
1,2,7
Termination voltage (system)
VTT
VREF - 0.04
VREF
VREF + 0.04
V
3,7
Input logic high voltage
VIH (DC)
VREF + 0.125
-
VDDQ + 0.3
V
Input logic low voltage
VIL (DC)
-0.3
-
VREF - 0.125
V
(All voltages referenced to VSS)
Parameter
Output minimum source DC current ( VDDQ(min); VOUT
=1.42V )
Output minimum sink DC current ( VDDQ(min); VOUT =
0.28V )
Symbol
Value
Unit
Note
I OH
-13.4
mA
5,6
I OL
+13.4
mA
5,6
Note:
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of
VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ and VDDL track VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together.
5. The DC value of VREF applied to the receiving device is expected to be set to VTT.
6. TC = 25℃, VDD = VDDQ = 1.8V.
7. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, under all conditions
VDDQ must be less than or equal to VDD.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
5/59
ESMT
M14D128168A (2M)
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
-2.5
85
75
mA
100
95
mA
IDD2P
All banks idle;
tCK = tCK (IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
12
12
mA
IDD2Q
All banks idle;
tCK = tCK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
55
50
mA
55
50
mA
45
40
IDD0
Operating Current
(Active - Read Precharge)
IDD1
Precharge Quiet
Standby Current
Unit
-1.8
Operating Current
(Active - Precharge)
Precharge
Power-Down
Standby Current
Version
Test Condition
Idle Standby Current IDD2N
One bank;
tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min;
CKE is High, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS (IDD)min, tRCD = tRCD (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
All banks idle;
tCK = tCK (IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active Power-down
Standby Current
Active Standby
Current
Operation Current
(Read)
IDD3P
IDD3N
IDD4R
All banks open;
tCK = tCK (IDD); CKE is LOW;
Other control and address bus inputs
are STABLE;
Data bus input are FLOATING
Fast PDN Exit
MRS(12) = 0
mA
Slow PDN Exit
MRS(12) = 1
18
18
All banks open;
tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
80
70
mA
210
170
mA
200
160
mA
All banks open, continuous burst Reads, IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
Operation Current
(Write)
IDD4W
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
6/59
ESMT
Parameter
M14D128168A (2M)
Symbol
Burst Refresh Current
IDD5
Self Refresh Current
IDD6
Operating Current
(Bank interleaving)
IDD7
Version
Test Condition
tCK = tCK (IDD);
Refresh command every tRFC (IDD) interval;
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
CLK and CLK at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
All bank interleaving Reads, IOUT = 0mA;
BL = 4, CL= CL (IDD), AL = tRCD (IDD) – 1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (IDD), tRCD = 1 × tCK (IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during Deslects;
Data pattern is the same as IDD4W;
Unit
-1.8
-2.5
100
95
mA
4
4
mA
220
180
mA
Note:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and /DQS, IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD:
LOW is defined as VIN ≤ VIL (AC) (max.).
HIGH is defined as VIN ≥ VIH (AC) (min.).
STABLE is defined as inputs stable at a HIGH or LOW level.
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
Address and control signal Inputs are changed between HIGH and LOW every other clock cycle (once per two clocks),
and
DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer (once per
clock).
6. When TC ≧ +85 ℃, IDD6 must be derated by 80%.
IDD6 will increase by this amount if TC ≧ +85 ℃ and double refresh option is still enabled.
7. AC Timing for IDD test conditions
For purposes of IDD testing, the following parameters are to be utilized.
-1.8
Parameter
CL (IDD)
tRCD (IDD)
tRC (IDD)
tRRD (IDD)-1KB
tFAW (IDD)-1KB
tCK (IDD)
tRAS (IDD) min.
tRAS (IDD) max.
tRP (IDD)
tRFC (IDD)
-2.5
DDR2-1066
(7-7-7)
7
13.125
53.125
7.5
35
1.875
40
Elite Semiconductor Memory Technology Inc.
DDR2-800 (5-5-5)
5
12.5
57.5
7.5
35
2.5
45
70000
13.125
75
12.5
75
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
Publication Date : Mar. 2013
Revision : 1.4
7/59
ESMT
M14D128168A (2M)
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
-1.8
Symbol
Input High (Logic 1) Voltage
VIH(AC)
Input Low (Logic 0) Voltage
VIL(AC)
Input Differential Voltage
VID(AC)
Input Crossing Point Voltage
VIX(AC)
Output Crossing Point Voltage VOX(AC)
Min.
-2.5
Max.
VREF + 0.2
Min.
Unit
Max.
VREF + 0.2
Note
V
VREF - 0.2
VREF - 0.2
V
0.5
VDDQ + 0.6
0.5
VDDQ
V
0.5 x VDDQ 0.175
0.5 x VDDQ +
0.175
0.5 x VDDQ 0.175
0.5 x VDDQ +
0.175
V
0.5 x VDDQ 0.125
0.5 x VDDQ +
0.125
0.5 x VDDQ 0.125
0.5 x VDDQ +
0.125
V
1
2
2
Note:
1. VID(AC) specifies the input differential voltage |VTR – VCP| required for switching, where VTR is the true input signal (such
as CLK,DQS) and VCP is the complementary input signal (such as CLK , DQS ). The minimum value is equal to VIH(AC) –
VIL(AC).
2. The typical value of VIX / VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX / VOX(AC) is
expected to track variations in VDDQ. VIX / VOX(AC) indicates the voltage at which differential input / output signals must
cross.
Input / Output Capacitance
Parameter
Symbol
Min.
Max.
Unit Note
CIN1
0.5
1.5
pF
1
Input capacitance (CLK, CLK )
CIN2
0.5
1.0
pF
1
DQS, DQS & Data input/output capacitance
CI / O
1.5
3.5
pF
2
Input capacitance (DM)
CIN3
0.5
1.5
pF
2
Input capacitance
(A0~A12, BA0~BA1, CKE, CS , RAS , CAS , WE , ODT)
Note: 1. Maximum capacitance delta is 0.25 pF.
2. Maximum capacitance delta is 0.5 pF.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
M14D128168A (2M)
AC Overshoot / Undershoot Specification
Parameter
Pin
Value
-1.8
-2.5
Unit
Maximum peak amplitude
allowed for overshoot
Address, CKE, CS , RAS , CAS , WE , ODT,
Maximum peak amplitude
allowed for undershoot
Address, CKE, CS , RAS , CAS , WE , ODT,
Maximum overshoot area
above VDD
Address, CKE, CS , RAS , CAS , WE , ODT,
0.5
0.66
V-ns
CLK, CLK , DQ, DQS, DQS , DM
0.19
0.23
V-ns
0.5
0.66
V-ns
0.19
0.23
V-ns
CLK, CLK , DQ, DQS, DQS , DM
CLK, CLK , DQ, DQS, DQS , DM
Maximum undershoot area Address, CKE, CS , RAS , CAS , WE , ODT,
below VSS
CLK, CLK , DQ, DQS, DQS , DM
Elite Semiconductor Memory Technology Inc.
0.5
V
0.5
V
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
M14D128168A (2M)
AC Operating Test Conditions
Parameter
Value
Unit
Note
0.5 x VDDQ
V
1
Input signal maximum peak swing ( VSWING(max.) )
1.0
V
1
Input signal minimum slew rate (SLEW)
1.0
V/ns
2,3
VIH / VIL
V
VREF
V
0.5 x VDDQ
V
Input reference voltage ( VREF )
Input level
Input timing measurement reference level
Output timing measurement reference level (VOTR)
4
Note:
1. Input waveform timing is referenced to the input signal crossing through the VIH / VIL (AC) level applied to the device under
test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH (AC) (min.) for rising edges and the
range from VREF to VIL (AC)(max.) for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL (AC) to VIH (AC) on the positive transitions and VIH (AC) to
VIL (AC) on the negative transitions.
4. The VDDQ of the device under test is reference.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
10/59
ESMT
M14D128168A (2M)
AC Timing Parameter & Specifications
-1.8
-2.5
Unit
Note
ps
12
+400
ps
9
0.48
0.52
tCK (avg)
12
0.52
0.48
0.52
tCK (avg)
12
-325
+325
-350
+350
ps
9
tDQSS
-0.25
+0.25
-0.25
+0.25
tCK (avg)
tDS
0
50
ps
3
75
125
ps
4
tDIPW
0.35
0.35
tCK (avg)
Address and Control Input setup time
tIS (base)
125
175
ps
3
Address and Control Input hold time
tIH (base)
200
250
ps
4
tIPW
0.6
0.6
tCK (avg)
DQS input high pulse width
tDQSH
0.35
0.35
tCK (avg)
DQS input low pulse width
tDQSL
0.35
0.35
tCK (avg)
DQS falling edge to CLK rising setup
time
tDSS
0.2
0.2
tCK (avg)
DQS falling edge from CLK rising hold
time
tDSH
0.2
0.2
tCK (avg)
Data strobe edge to output data edge
tDQSQ
175
200
ps
tHZ
tAC(max.)
tAC(max.)
ps
9
Parameter
Symbol
Min.
Max.
Min.
Max.
1875
7500
-
-
2500
7500
-
-
CL=5
3000
7500
2500
8000
CL=4
3750
7500
3750
8000
tAC
-350
+350
-400
CLK high-level width
tCH (avg)
0.48
0.52
CLK low-level width
tCL (avg)
0.48
tDQSCK
CL=7
Clock period
CL=6
DQ output access time from
CLK/ CLK
DQS output access time from
CLK/ CLK
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width
(for each input)
Control and Address input pulse width
Data-out high-impedance window from
CLK/ CLK
Data-out low-impedance window from
CLK/ CLK
DQ low-impedance window from
CLK/ CLK
tCK (avg)
(base)
tDH
(base)
tLZ
(DQS)
tLZ
(DQ)
tAC(min.)
tAC(max.)
tAC(min.)
tAC(max.)
ps
9
2 x tAC(min.)
tAC(max.)
2 x tAC(min.)
tAC(max.)
ps
9
5, 12
Half clock period
tHP
Min (tCL, tCH)
Min (tCL, tCH)
ps
DQ/DQS output hold time from DQS
tQH
tHP-tQHS
tHP-tQHS
ps
DQ hold skew factor
tQHS
Elite Semiconductor Memory Technology Inc.
250
300
ps
Publication Date : Mar. 2013
Revision : 1.4
11/59
ESMT
M14D128168A (2M)
AC Timing Parameter & Specifications - Continued
Parameter
Symbol
-1.8
-2.5
Min.
Max.
Min.
Max.
70K
45
70K
Unit
Note
Active to Precharge command
tRAS
40
Active to Active command
(same bank)
tRC
53.125
57.5
ns
Auto Refresh row cycle time
tRFC
75
75
ns
Active to Read, Write delay
tRCD
13.125
12.5
ns
Precharge command period
tRP
13.125
12.5
ns
Active bank A to Active bank B
command (1KB page size)
tRRD
7.5
7.5
ns
Four activate window (1KB page size)
tFAW
35
35
ns
Write recovery time
tWR
15
15
ns
Write data in to Read command delay
tWTR
7.5
7.5
ns
Col. address to Col. address delay
tCCD
2
2
tCK
Average periodic Refresh interval
( 0℃ ≦TC ≦ +85℃ )
tREFI
15.6
15.6
μs
Average periodic Refresh interval
(+85℃ ＜TC ≦ +95℃)
tREFI
7.8
7.8
μs
Write preamble
tWPRE
0.35
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK (avg)
DQS Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK (avg)
10
DQS Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK (avg)
11
Load Mode Register / Extended Mode
Register cycle time
tMRD
2
2
tCK
Auto Precharge write recovery +
Precharge time
tDAL
WR + tnRP
WR + tnRP
tCK
Internal Read to Precharge command
delay
tRTP
7.5
7.5
ns
Exit Self Refresh to Read command
tXSRD
200
200
tCK
Exit Self Refresh to non-Read
command
tXSNR
tRFC + 10
tRFC + 10
ns
tXP
3
2
tCK
tXARD
3
2
tCK
2
tXARDS
10 - AL
8 - AL
tCK
1,2
tCKE
3
3
tCK
tDELAY
tIS +
tCK(avg)+tIH
tIS +
tCK(avg)+tIH
ns
Exit Precharge Power-Down to any
non-Read command
Exit Active Power-Down to Read
command
Exit active power-down to Read
command
(slow exit / low power mode)
CKE minimum pulse width
(high and low pulse width)
Minimum time clocks remains ON
after CKE asynchronously drops low
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0.35
ns
tCK (avg)
18
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M14D128168A (2M)
AC Timing Parameter & Specifications - Continued
Parameter
Symbol
-1.8
-2.5
Min.
Max.
Min.
Max.
Unit
Output impedance test driver delay
tOIT
0
12
0
12
ns
MRS command to ODT update delay
tMOD
0
12
0
12
ns
ODT turn-on delay
tAOND
2
2
2
2
tCK
tAC(min.)
tAC(max.) +0.7
ns
tAC(min.) + 2
2 x tCK (avg)
+tAC(max.) + 1
ns
ODT turn-on
tAON
tAC(max.)
tAC(min.)
+2.575
3 x tCK (avg)
tAC(min.) + 2
+tAC(max.) + 1
ODT turn-on (Power-Down mode)
tAONPD
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(min.)
tAC(max.) +0.6
tAC(min.)
tAC(max.) +0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min.) + 2
2.5 x tCK (avg)
+tAC(max.) + 1
tAC(min.) + 2
2.5 x tCK (avg)
+tAC(max.) + 1
ns
ODT to Power-Down entry latency
tANPD
4
3
tCK
ODT Power-Down exit latency
tAXPD
11
8
tCK
Note
13,15
14,
16,17
Note:
1. AL: Additive Latency.
2. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
3. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a
rising signal and VIL (AC) for a falling signal applied to the device under test.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
5.
6.
7.
tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input
specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for
tQH calculation is determined by the following equation;
tHP = Min ( tCH (abs), tCL (abs) ), where:
tCH (abs) is the minimum of the actual instantaneous clock HIGH time;
tCL (abs) is the minimum of the actual instantaneous clock LOW time;
tQHS accounts for:
a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and
b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,
both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to
n-channel variation of the output drivers.
tQH = tHP - tQHS, where:
tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max
column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
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8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
M14D128168A (2M)
Examples:
a. If the system provides tHP of 1200 ps into a DDR2-800 SDRAM, the DRAM provides tQH of 900 ps minimum.
b. If the system provides tHP of 1300 ps into a DDR2-800 SDRAM, the DRAM provides tQH of 1000 ps minimum.
RU stands for round up. WR refers to the tWR parameter stored in the MRS.
When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tERR (6-10per) of the
input clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has tERR (6-10per)(min.) = - 272 ps and tERR (6-10per)(max.) =
+ 293 ps, then tDQSCK (min.)(derated) = tDQSCK (min.) - tERR (6-10per)(max.) = -350 ps - 293 ps = -643 ps and tDQSCK (max.)
(derated) = tDQSCK (max.) - tERR (6-10per)(min.) = 350 ps + 272 ps = +622 ps. Similarly, tLZ (DQ) for DDR2-800 de-rates to
tLZ (DQ)(min.)(derated) = -800 ps - 293 ps = -1093 ps and tLZ (DQ)(max.)(derated) = 400 ps + 272 ps = +672 ps.
When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tJIT (per) of the input
clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has tJIT (per)(min.) = - 72 ps and tJIT (per)(max.) = + 93 ps,
then tRPRE (min.)(derated) = tRPRE (min.) + tJIT (per)(min.) = 0.9 x tCK (avg) - 72 ps = + 2178 ps and tRPRE (max.)(derated) =
tRPRE (max.) + tJIT (per)(max.) = 1.1 x tCK (avg) + 93 ps = + 2843 ps.
When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tJIT (duty) of the input
clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has tJIT (duty)(min.) = - 72 ps and tJIT (duty)(max.) = + 93 ps,
then tRPST (min.)(derated) = tRPST (min.) + tJIT (duty)(min.) = 0.4 x tCK (avg) - 72 ps = + 928 ps and tRPST (max.)(derated) =
tRPST (max.) + tJIT (duty)(max.) = 0.6 x tCK (avg) + 93 ps = + 1593 ps.
Refer to the Clock Jitter table.
ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tERR (6-10per) of the
input clock. (output de-ratings are relative to the SDRAM input clock.)
When the device is operated with input clock jitter, this parameter needs to be derated by { - tJIT (duty)(max.) - tERR
(6-10per)(max.) } and { - tJIT (duty)(min.) - tERR (6-10per)(min.) } of the actual input clock. (output deratings are relative to
the SDRAM input clock.)
For example, if the measured jitter into a DDR2-800 SDRAM has tERR (6-10per)(min.) = - 272 ps, tERR (6- 10per)(max.) = +
293 ps, tJIT (duty)(min.) = -96 ps and tJIT (duty)(max.) = + 94 ps, then tAOF(min.)(derated) = tAOF(min.) + { - tJIT (duty)(max.) tERR (6-10per)(max.) } = -400 ps + { - 94 ps - 293 ps} = -787 ps and tAOF(max.)(derated) = tAOF(max.) + { - tJIT (duty)(min.) tERR (6-10per)(min.) } = 1000 ps + { 96 ps + 272 ps } = +1368 ps.
For tAOFD of DDR2-800/1066, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH (avg), average input clock HIGH pulse width
of 0.5 relative to tCK (avg). tAOF (min.) and tAOF (max.) should each be derated by the same amount as the actual amount of
tCH (avg) offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case tCH (avg) of 0.48, the tAOF (min.) should be derated by subtracting 0.02 x tCK
(avg) from it, whereas if an input clock has a worst case tCH (avg) of 0.52, the tAOF (max.) should be derated by adding 0.02
x tCK (avg) to it. Therefore, we have;
tAOF (min.)(derated) = tAC (min.) - [0.5 - Min(0.5, tCH (avg)(min.))] x tCK (avg)
tAOF (max.)(derated) = tAC (max.) + 0.6 + [Max(0.5, tCH (avg)(max.)) - 0.5] x tCK (avg)
or
tAOF (min.)(derated) = Min(tAC (min.), tAC (min.) - [0.5 - tCH (avg)(min.)] x tCK (avg))
tAOF (max.)(derated) = 0.6 + Max(tAC (max.), tAC (max.) + [tCH (avg)(max.) - 0.5] x tCK (avg)), where:
tCH (avg)(min.) and tCH (avg)(max.) are the minimum and maximum of tCH (avg) actually measured at the DRAM input balls.
tDAL [nCLK] = WR [nCLK] + tnRP [nCLK] = WR + RU {tRP [ps] / tCK (avg) [ps] }, where WR is the value programmed in the
mode register set.
tDAL = WR + RU{ tRP[ns] / tCK [ns] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application
clock period.
Example: For DDR2-800 (5-5-5) at tCK =2.5ns with WR programmed to 6 clocks.
tDAL = 6 + (12.5 ns / 2.5 ns) clocks = 6 + 5 clocks = 11 clocks.
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M14D128168A (2M)
ODT DC Electrical Characteristics
Parameter
Rtt effective impedance value for 75Ω setting
EMRS(1) [A6, A2] = 0, 1
Rtt effective impedance value for 150Ω setting
EMRS(1) [A6, A2) = 1, 0
Rtt effective impedance value for 50Ω setting
EMRS(1) [A6, A2] = 1, 1
Deviation of VM with respect to VDDQ /2
Symbol
Min.
Typ.
Max.
Unit
Rtt1(eff)
60
75
90
Ω
Rtt2(eff)
120
150
180
Ω
Rtt3(eff)
40
50
60
Ω
△VM
-6
-
+6
%
Note:
Measurement Definition for Rtt(eff) :
Rtt(eff) is determined by separately applying VIH(AC) and VIL(AC) to test pin, and then measuring current I(VIH(AC)) and
I(VIL(AC)) respectively.
Measurement Definition for △VM :
Measure voltage (VM) at test pin with no load.
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M14D128168A (2M)
Clock Jitter [ DDR2- 1066, 800]
Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters' and these parameters apply to DDR2-1066 and DDR2-800 only. The jitter specified is a random jitter meeting a
Gaussian distribution.
Parameter
Symbol
-1.8
Min.
-90
-2.5
Max.
90
Min.
-100
Clock period jitter
tJIT (per)
Clock period jitter during
tJIT (per,lck)
-80
80
-80
DLL locking period
Cycle to cycle period jitter
tJIT (cc)
-180
180
-200
Cycle to cycle clock period jitter
tJIT (cc, lck)
-160
160
-160
During DLL locking period
Cumulative error across 2 cycles
tERR (2per)
-132
132
-150
Cumulative error across 3 cycles
tERR (3per)
-157
157
-175
Cumulative error across 4 cycles
tERR (4per)
-175
175
-200
Cumulative error across 5 cycles
tERR (5per)
-188
188
-200
Cumulative error across
tERR (6-10per)
-250
250
-300
n=6,7,8,9,10 cycles
Cumulative error across
tERR (11-50per)
-425
425
-450
n=11,12,….49,50 cycles
Duty cycle jitter
tJIT (duty)
-75
75
-100
Note:
1. tCK (avg) is calculated as the average clock period across any consecutive 200 cycle window.
Max.
100
Unit
Note
ps
5
80
ps
5
200
ps
6
160
ps
6
150
175
200
200
ps
ps
ps
ps
7
7
7
7
300
ps
7
450
ps
7
100
ps
4
2.
tCH (avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
3.
tCL (avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
4.
tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH
(avg). tCL jitter is the largest deviation of any single tCL from tCL (avg).
tJIT (duty) is not subject to production test.
tJIT (duty) = Min./Max. of { tJIT (CH), tJIT (CL)}, where:
tJIT (CH) = { tCH j - tCH (avg) where j =1 to 200}
tJIT (CL) = {tCL j - tCL (avg) where j =1 to 200}
5.
tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg).
tJIT (per) = Min./Max. of { tCK j - tCK (avg) where j =1 to 200}
tJIT (per) defines the single period jitter when the DLL is already locked.
tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT (per) and tJIT (per, lck) are not subject to production testing.
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M14D128168A (2M)
6.
tJIT (cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT (cc) = Max. of | tCK i +1 - tCK i|
tJIT (cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT (cc, lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT (cc) and tJIT (cc, lck) are not subject to production testing.
7.
tERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg).
tERR (nper) is not subject to production testing.
8.
These parameters are specified per their average values, however it is understood that the following relationship between
the average timing and the absolute instantaneous timing holds at all times. (Min. and max. of SPEC values are to be used
for calculations in the table below.)
Parameter
Symbol
Min.
Max.
Absolute clock period
tCK (abs)
tCK (avg)(min.) + tJIT (per)(min.)
tCK (avg)(max.) + tJIT (per)(max.)
tCH (avg)(min.) x tCK (avg)(min.)
Absolute clock high pulse
tCH (avg)(max.) x tCK (avg)(max.)
tCH (abs)
width
+ tJIT (duty)(min.)
+ tJIT (duty)(max.)
tCL (avg)(min.) x tCK (avg)(min.)
Absolute clock low pulse
tCL (avg)(max.) x tCK (avg)(max.)
tCL (abs)
width
+ tJIT (duty)(min.)
+ tJIT (duty)(max.)
Example: For DDR2-800, tCH (abs)(min.) = (0.48 x 2500ps) – 100 ps = 1100 ps
Unit
ps
ps
ps
Input Slew Rate De-rating
For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS
(base) and tIH (base), tDH (base) value to the ΔtIS, ΔtDS and ΔtIH, ΔtDH de-rating value respectively.
Example: tDS (total setup time) = tDS (base) + ΔtDS.
Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF (DC) and the first
crossing of VIH (AC)(min.). Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF (DC) and the first crossing of VIL (AC)(max.). If the actual signal is always earlier than the nominal slew rate line between
shaded ‘VREF (DC) to AC region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for de-rating value (see the figure of Slew Rate Definition
Tangent).
Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC)(max.) and the
first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH (DC)(min.) and the first crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line between
shaded ‘DC level to VREF (DC) region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’, the slew rate of a
tangent line to the actual signal from the DC level to VREF (DC) level is used for de-rating value (see the figure of Slew Rate
Definition Tangent).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH / VIL (AC) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH / VIL (AC).
For slew rates in between the values listed in the tables below, the de-rating values may be obtained by linear interpolation. These
values are typically not subject to production test. They are verified by design and characterization.
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M14D128168A (2M)
DQ slew rate (V/ns)
De-rating Value of tDS/tDH with Differential DQS (DDR2-800, 1066)
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
DQS, DQS differential slew rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
Unit
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
+100 +45 +100 +45 +100 +45
ps
+67
+21
+67
+21
+67
+21
+79
+33
ps
0
0
0
0
0
0
+12
+12
+24
+24
ps
-5
-14
-5
-14
+7
-2
+19
+10
+31
+22
ps
-13
-31
-1
-19
+11
-7
+23
+5
+35
+17
ps
-10
-42
+2
-30
+14
-18
+26
-6
+38
+6
ps
-10
-59
+2
-47
+14
-35
+26
-23
+38
-11
ps
-24
-89
-12
-77
0
-65
+12
-53
ps
-52
-140
-40
-128
-28
-116
ps
De-rating Value of tIS/tIH (DDR2-800, 1066)
Command / Address slew rate (V/ns)
2.0 V/ns
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ΔtIS
ΔtIH
+150
+143
+133
+120
+100
+67
0
-5
-13
-22
-34
-60
-100
-168
-200
-325
-517
-1000
+94
+89
+83
+75
+45
+21
0
-14
-31
-54
-83
-125
-188
-292
-375
-500
-708
-1125
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CLK, CLK differential slew rate
1.5 V/ns
1.0 V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
-4
-30
-70
-138
-170
-295
-487
-970
+124
+119
+113
+105
+75
+51
+30
+16
-1
-24
-53
-95
-158
-262
-345
-470
-678
-1095
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
0
-40
-108
-140
-265
-457
-940
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
-23
-65
-128
-232
-315
-440
-648
-1065
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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M14D128168A (2M)
Slew Rate Definition Nominal
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M14D128168A (2M)
Slew Rate Definition Tangent
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M14D128168A (2M)
Command Truth Table
Note 7
COMMAND
(Extended) Mode Register Set
Auto Refresh
Refresh
Entry
Self
Refresh
Note 7
H
H
Exit
Bank Active
H
H
L
BA0,1
CAS
WE
DM
L
L
L
L
X
OP Code (included A12)
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
H
L
L
H
H
X
V
H
H
L
H
L
H
X
V
Auto Precharge Disable
Read
H
Auto Precharge Disable
L
H
H
L
H
L
L
X
V
Auto Precharge Enable
Precharge
Bank Selection
All Banks
Entry
H
H
H
H
L
Active Power-Down
Exit
L
H
Entry
H
L
Precharge Power-Down
Exit
L
L
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
L
H
DM
H
H
Device Deselect
H
X
H
X
X
No Operation
H
X
L
H
H
X
X
A9~A0
Note
1,2
10,12
6,9, 12
Row Address
L
Auto Precharge Enable
Write
A10/AP
A11,
RAS
CKE(n-1) CKE(n) CS
V
L
X
H
Column
Address
(A8~A0)
1,3
Column
Address
(A8~A0)
1,3
X
4,11,
12,14
X
X
X
4,8,
12,14
X
4,11,
12,14
X
4,8,
12,14
X
V
X
X
X
X
H
X
X
15
(OP Code = Operand Code, V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note:
1. BA during a MRS/EMRS command selects which mode register is programmed.
2. MRS/EMRS can be issued only at all bank Precharge state.
3. Burst Reads or Writes at BL = 4 cannot be terminated or interrupted.
4. The Power-Down mode does not perform any Refresh operations. The duration of Power-Down is limited by the Refresh
requirements. Need one clock delay to entry and exit mode.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. Self Refresh Exit is asynchronous.
7. CKE (n) is the logic state of CKE at clock edge n; CKE (n–1) was the state of CKE at the previous clock edge.
8. All states not shown are illegal or reserved unless explicitly described elsewhere in this document.
9. On Self Refresh, Exit Deselect or NOP commands must be issued on every clock edge occurring during the tXSNR period.
Read commands may be issued only after tXSRD is satisfied.
10. Self Refresh mode can only be entered from all banks idle state.
11. Power-Down and Self Refresh can not be entered while Read or Write operations, MRS/EMRS operations or Precharge
operations are in progress.
12. Minimum CKE HIGH / LOW time is tCKE (min).
13. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
14. ODT must be driven HIGH or LOW in Power-Down if the ODT function is enabled.
15. Used to mask write data, provided coincident with the corresponding data.
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M14D128168A (2M)
Power On and Initialization
DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified
may result in undefined operation.
Power-Up and Initialization Sequence
The following sequence is required for Power-Up and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 x VDDQ and ODT (*1) at a low state (all other inputs may be undefined).
- VDD(*2), VDDL(*2) and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95V max, AND
- VREF tracks VDDQ /2.
or
- Apply VDD(*2) before or at the same time as VDDL.
- Apply VDDL(*2) before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT and VREF.
at least one of these two sets of conditions must be met.
2.
Start clock and maintain stable condition.
3.
4.
For the minimum of 200us after stable power and clock (CLK, CLK ), then apply NOP or Deselect and take CKE High.
Waiting minimum of 400ns then issue Precharge commands for all banks of the device. NOP or Deselect applied during
400ns period.
Issue EMRS(2) command. (To issue EMRS(2) command, provide “LOW” to BA0, “HIGH” to BA1.)
Issue EMRS(3) command. (To issue EMRS(3) command, provide “HIGH” to BA0 and BA1.)
Issue EMRS(1) to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and "LOW" to
BA1.)
Issue a Mode Register Set command for “DLL reset” (*3).
(To issue DLL reset command, provide “HIGH” to A8 and “LOW” to BA0-1)
Issue Precharge commands for all banks of the device.
Issue 2 or more Auto Refresh commands.
Issue a Mode Register Set command with LOW to A8 to initialize device operation. (To program operation parameters
without resetting the DLL.)
At least 200 clocks after step 8, execute EMRS(1) OCD default command (A9=A8= A7=1) followed by EMRS(1) OCD exit
command (A9=A8=A7=0) must be issued with other operating parameters of EMRS(1).
The DDR2 SDRAM is now ready for normal operation.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Note:
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
*2) If DC voltage level of VDDL or VDD is intentionally changed during normal operation, (for example, for the purpose of VDD
corner test, or power saving) “DLL Reset” must be executed.
*3) Every “DLL enable” command resets DLL. Therefore sequence 8 can be skipped during power up. Instead of it, the
additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Initialization Sequence after Power-Up
tCH tCL
CLK
CLK
tIS
CKE
Command
NOP
PA L L
400ns
EMR S(2)
tRP
EMRS(3)
tMRD
MR S
E MRS (1 )
tMRD
Precharge
All
tMRD
PA L L
tMRD
REF
REF
tRP
tRFC
DLL enable
MRS
tR FC
tMR D
OCD default
DLL R eset
Any
Comma nd
EMRS(1)
EMRS(1)
tMRD
tOIT
OCD exit
200 Cycle (min.)
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M14D128168A (2M)
Mode Register Definition
Mode Register Set [MRS]
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst
length, burst type, test mode, DLL reset, WR and various vendor specific options to make the device useful for variety of different
applications. The default value of the mode register is not defined, therefore the mode register must be written after Power-Up for
proper operation. The mode register is written by asserting LOW on CS , RAS , CAS , WE , BA0 and BA1 (The device should
be in all bank Precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A12 in the
same cycle as CS , RAS , CAS , WE , BA0 and BA1 going LOW are written in the mode register.
The tMRD time is required to complete the write operation to the mode register. The mode register contents can be changed using
the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on functionality. The burst length is defined by A0 ~ A2. Burst address sequence
type is defined by A3, CAS latency (read latency from column address) is defined by A4 ~ A6. The DDR2 doesn’t support half
clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write
recovery time WR is defined by A9 ~ A11. Refer to the table for specific codes.
BA1
BA0
A12
0
0
PD
A11
A10
A9
WR
A8
A7
DLL
TM
Active Power down exit timing
A12
PD
0
1
Fast Exit (normal)
Slow Exit (low power)
BA1 BA0
0
0
1
1
0
1
0
1
Mode Register
MRS
EMRS(1)
EMRS(2)
EMRS(3) : Reserved
0
1
0
1
0
1
0
1
CAS Latency
BT
A2
A1
A0
Address Bus
Mode Register
Burst Length
A7
Mode
A3
Burst Type
0
1
No
Yes
0
1
Sequential
Interleave
A2
A1
A0
Burst Length
No
Yes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
CAS Latency
*1
Reserved
2
3
4
5
6
7
8
A3
DLL reset
DDR2-1066
0
0
1
1
0
0
1
1
WR(cycles)
A4
0
1
DDR2-800
0
0
0
0
1
1
1
1
A9
A5
A8
Write recovery for Auto Precharge
A11 A10
A6
A6
A5
A4
Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
4
5
6
7
Note:
1. WR(min.) (write recovery for Auto Precharge) is determined by tCK (max.) and WR(max.) is determined by tCK (min.)
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next
integer ( WR[cycles] = tWR (ns)/ tCK (ns)). The mode register must be programmed to this value. This is also used with
tRP to determine tDAL.
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M14D128168A (2M)
Burst Address Ordering for Burst Length
Burst
Length
4
8
Starting Column Address
(A2, A1,A0)
000
001
010
011
000
001
010
011
100
101
110
111
Sequential Mode
Interleave Mode
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Mode Register Set
0
1
2
3
4
5
6
7
8
CLK
CLK
*1
tC K
Any
Command
Mode
Register Set
Precharge
All Banks
CO MMA ND
t R P* 2
tMRD
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having the DLL disabled for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL
is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Impedance Control
The normal drive strength for all outputs is specified to be SSTL_18. The device also supports a reduced drive strength option,
intended for lighter load and/or point-to-point environments.
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M14D128168A (2M)
Extended Mode Register Set-1 [EMRS(1)]
The EMRS(1) stores the data for enabling or disabling DLL, output driver impedance control, additive latency, ODT, disable DQS ,
OCD program. The default value of the EMRS(1) is not defined, therefore EMRS(1) must be written after power up for proper
operation. The EMRS(1) is written by asserting LOW on CS , RAS , CAS , WE , BA1 and HIGH on BA0 (The device should be
in all bank Precharge with CKE already high prior to writing into EMRS(1)). The state of address pins A0~A12 in the same cycle
as CS , RAS , CAS , WE and BA1 going LOW and BA0 going HIGH are written in the EMRS(1).
The tMRD time is required to complete the write operation to the EMRS(1). The EMRS(1) contents can be changed using the same
command and clock cycle requirements during normal operation as long as all banks are in the idle state. A0 is used for DLL
enable or disable. A1 is used for reducing output driver impedance control. The additive latency is defined by A3~A5. A7~A9 are
used for OCD control. A10 is used for DQS disable. ODT setting is defined by A2 and A6.
BA1
BA0
A12
A11
A10
0
1
Qoff
0*1
DQS
A12
0
1
BA1 BA0
0
0
1
1
0
1
0
1
A9
A7
OCD program
A10
DQS Enable
0
1
Enable
Disable
Qoff
A8
A6
A5
A3
A2
Rtt
Additive Latency
Rtt
A6
A2
Rtt (nominal)
0
0
1
1
0
1
0
1
Disable
75 Ω
150 Ω
50 Ω
MRS
EMRS(1)
EMRS(2)
EMRS(3): Reserved
A1
A0
D.I.C DLL
A0
DLL Enable
0
1
Enable
Disable
Output Driver
Impedance Control
Full strength
Reduced strength
A1
0
1
*3
Additive Latency
Output buffer enable
Output buffer disable
Mode Register
A4
*2
A9
A8
A7
OCD operation
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD exit
Reversed
Reversed
Reversed
Enable OCD default
A5
A4
A3
Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
Reversed
Note:
1. A11 is reserved for future use and must be set to 0.
2. As detailed in the Initialization section notes, during initialization of the OCD operation, all three bits must be set to
“1” for the OCD default state, then set to “0” before initialization finished.
3.
Output disabled - DQs, DQSs, DQS s. This feature is used in conjunction with DIMM IDD measurements when IDDQ is
not desired to be included.
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M14D128168A (2M)
Extended Mode Register Set-2 [EMRS(2)]
The EMRS(2) controls refresh related features. The default value of the EMRS(2) is not defined, therefore EMRS(2) must be
written after power up for proper operation. The EMRS(2) is written by asserting LOW on CS , RAS , CAS , WE , BA0 and
HIGH on BA1 (The device should be in all bank Precharge with CKE already high prior to writing into EMRS(2)). The state of
address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going LOW and BA1 going HIGH are written in the
EMRS(2).
The tMRD time is required to complete the write operation to the EMRS(2). The EMRS(2) contents can be changed using the same
command and clock cycle requirements during normal operation as long as all banks are in the idle state. A7 is used for high
temperature self refresh rate enable or disable. A3 is used for DCC enable or disable.
BA1
BA0
1
0
BA1 BA0
0
0
1
1
0
1
0
1
A12
A11
A10
A9
0*1
A8
A7
A6
SRF
Mode Register
MRS
EMRS(1)
EMRS(2)
EMRS(3): Reserved
A7
0
1
A5
0*1
A4
A3
A2
DCC*2
A3
DCC Enable
0
1
Disable
Enable
A1
A0
0*1
High Temperature
Self Refresh rate
Disable
Enable
Note:
1. A0~A2, A4~A6 and A8~A12 are reserved for future use and must be set to 0.
2. User may enable or disable the DCC (Duty Cycle Corrector) by programming A3 bit accordingly.
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M14D128168A (2M)
Extended Mode Register Set-3 [EMRS(3)]
BA1
BA0
1
1
BA1 BA0
0
0
1
1
0
1
0
1
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
Mode Register
MRS
EMRS(1)
EMRS(2)
EMRS(3): Reserved
Note:
EMRS(3) is reserved for future. All bits except BA0 and BA1 are reserved for future use and must be set to 0 when
setting to mode register during initialization.
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M14D128168A (2M)
Off-Chip Driver (OCD) Impedance Adjustment
The Off-Chip Driver function is an optional DDR2 JEDEC feature not supported by ESMT and thereby must be set to the default
state. Enabling OCD beyond the default settings will alter the I/O drive characteristics and the timing and output I/O specifications
will no longer be valid (see Initialization for proper setting of OCD defaults).
ODT (On Die Termination)
On Die Termination (ODT) is a feature that allows a DDR2 SDRAM to turn on/off termination resistance for each DQ, all
DQS/ DQS , and all DM signals via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory
channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all devices.
The ODT function is supported for Active and Standby modes. ODT is turned off and not supported in Self Refresh mode.
Timing for ODT Update Delay
CLK
CLK
Command
EMRS(1)
NOP
tAOFD
tIS
ODT
tMOD(max.)
tMOD(min.)
Internal
Rtt Setting
Old setting
Updating
New Setting
Note: tAOFD must be met before issuing EMRS(1) command. ODT must remain low for the entire duration of tMOD
window.
ODT Timing for Active and Standby Mode
T1
T0
T3
T2
T4
T5
T6
CLK
CLK
CKE
tIS
tIS
ODT
tAOFD
tAOND
Internal
Term Res.
Rtt
tAON(min.)
tAON(max.)
tAOF(min.)
tAOF(max.)
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M14D128168A (2M)
ODT Timing for Power-Down Mode
T1
T0
T3
T2
T4
T5
T6
CLK
CLK
CKE
tIS
tIS
ODT
tAOFPD(max.)
Internal
Term Res.
tAOFPD(min.)
Rtt
tAONPD(min.)
tAONPD(max.)
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M14D128168A (2M)
ODT Timing Mode Switch at Entering Power-Down Mode
T-5
T-4
T-3
T-2
T-1
T1
T0
T2
T3
CLK
CLK
tANPD
CKE
tIS
Entering slow exit Active Power-Down mode
or Precharge Power-Down mode.
tIS
ODT
Internal
Term Res.
tAOFD
Active and Standby
mode timings to
be applied.
tAOFPD(max.)
Power-Down
mode timings to
be applied.
Rtt
tIS
ODT
Internal
Term Res.
Rtt
tIS
ODT
tAOND
Internal
Term Res.
Active and Standby
mode timings to
be applied.
Rtt
tIS
ODT
tAONPD(max.)
Internal
Term Res.
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Rtt
Power-Down
mode timings to
be applied.
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M14D128168A (2M)
ODT Timing Mode Switch at Exiting Power-Down Mode
T0
T1
T5
T4
T6
T7
T8
T9
T10
T11
CLK
CLK
CKE
tAXPD
tIS
Exiting from slow Active Power-Down mode
or Precharge Power-Down mode.
tIS
ODT
Active and Standby
mode timings to
be applied.
tAOFD
Internal
Term Res.
Rtt
tIS
ODT
Power-Down
mode timings to
be applied.
tAOFPD(max.)
Internal
Term Res.
Rtt
tIS
ODT
Active and Standby
mode timings to
be applied.
tAOND
Internal
Term Res.
Rtt
tIS
ODT
Power-Down
mode timings to
be applied.
tAONPD(max.)
Internal
Term Res.
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M14D128168A (2M)
Precharge
The Precharge command is used to precharge or close a bank that has activated. The command is issued when CS , RAS and
WE are LOW and CAS is HIGH at the rising edge of the clock. The Precharge command can be used to precharge each bank
respectively or all banks simultaneously. The bank select addresses (BA0, BA1) and A10 are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the Precharge command can be
issued. After tRP from the precharge, a Bank Active command to the same bank can be initiated.
Bank Selection for Precharge by Address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
1
0
Bank B Only
0
0
1
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, DDR2 SDRAM would ignore all the control inputs.
The DDR2 SDRAM are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect
and NOP, the device should finish the current operation when this command is issued.
Bank Active
The Bank Active command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock
(CLK). The DDR2 SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Active
command to the first Read or Write command must meet or exceed the minimum of RAS to CAS delay time (tRCD(min.)). Once
a bank has been activated, it must be precharged before another Bank Active command can be applied to the same bank. The
minimum time interval between interleaved Bank Active command (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (tRRD min).
Bank Active Command Cycle
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
CLK
Command
Address
ACT
Posted
READ
Bank A
Row Addr.
Bank A
Col. Addr.
ACT
Posted
READ
Bank B
Row Addr.
Bank B
Col. Addr.
tCCD
tRCD=1
tRRD
Additive latency (AL)
PRE
PRE
ACT
Bank A
Bank B
Bank A
Row Addr.
Bank A Read begins
tRP
tRAS
tRC
Bank A
Active
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Active
Bank A
Precharge
Bank B
Precharge
Bank A
Active
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M14D128168A (2M)
Read Bank
This command is used after the Bank Active command to initiate the burst read of data. The Read command is initiated by
activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the Bank Active command to initiate the burst write of data. The Write command is initiated by
activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
Posted
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In
this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the Bank Active command (or
any time during the tRRD period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device.
The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W
command before the tRCD(min), then AL (greater than 0) must be written into the EMRS(1). The Write Latency (WL) is always
defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL).
Read or Write operations using AL allow seamless bursts.
Read followed by a Write to the Same Bank
< AL= 2; CL= 3 ; BL = 4>
-1
0
1
3
2
4
5
6
7
8
9
10
11
12
CLK
CLK
Active
Bank A
CMD
Read
Bank A
Write
Bank A
WL = RL -1 =4
CL = 3
AL = 2
DQS/DQS
>= tRCD
RL = AL + CL = 5
Dout0 Dout1 Dout2 Dout3
DQ
Din0 Din1 Din2 Din3
< AL= 0; CL= 3; BL = 4 >
-1
0
1
2
3
4
5
6
7
9
8
10
11
12
CLK
CLK
AL = 0
CMD
Read
Bank A
Active
Bank A
Write
Bank A
CL = 3
WL = RL -1 = 2
DQS/DQS
>= tRCD
RL = AL + CL = 3
DQ
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Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2 Din3
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M14D128168A (2M)
Essential Functionality for DDR2 SDRAM
Burst Read Operation
The Burst Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of
the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to
when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The DQS is driven LOW 1
clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of DQS.
Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the MRS and the AL is defined by the
EMRS(1).
Read (Data Output) Timing
tCH
tCL
CLK
CLK
DQS
DQS
tRPST
tRPRE
DQ
Dout0
Dout1
tDQSQ(max.)
Dout2
Dout3
tDQSQ(max.)
tQH
tQH
Burst Read
< RL= 5 (AL= 2; CL= 3); BL= 4 >
T0
T1
T2
T4
T3
T6
T5
T7
T8
CLK
CLK
CMD
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
=< tDQSCK
DQS,DQS
AL = 2
CL = 3
RL = 5
DQs
DoutA0 DoutA1 DoutA2 DoutA3
< RL= 3 (AL= 0; CL= 3); BL= 8 >
T0
T1
T2
T4
T3
T5
T6
T7
T8
CLK
CLK
CMD
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
=< tDQSCK
DQS,DQS
CL = 3
RL = 3
DQs
Elite Semiconductor Memory Technology Inc.
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
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ESMT
M14D128168A (2M)
Burst Read followed by Burst Write
< RL= 5; WL= (RL-1) = 4; BL= 4 >
T0
Tn-1
T1
Tn+1
Tn
Tn+2
Tn+3
Tn+4
Tn+5
CLK
CLK
Posted CAS
READ A
CMD
Posted CAS
NOP
NOP
WRITE A
tRTW (Read to Write-turn around-time)
NOP
NOP
NOP
NOP
NOP
DQS,DQS
RL = 5
WL = RL-1 = 4
DQs
DoutA0 DoutA1 DoutA2 DoutA3
DinA0 DinA1
DinA2 DinA3
Note: The minimum time from the Burst Read command to the Burst Write command is defined by a read to
write-turn around-time(tRTW), which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8
operation.
Seamless Burst Read
< RL= 5; AL= 2; CL= 3; BL = 4 >
T0
T1
T2
T4
T3
T6
T5
T7
T8
CLK
CLK
Posted CAS
READ A
CMD
NOP
Posted CAS
READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
AL = 2
DQs
CL = 3
RL = 5
DoutA0 DoutA1 DoutA2 DoutA3 DoutB0 DoutB1 DoutB2
Note: The seamless burst read operation is supported by enabling a Read command at every other clock for BL =
4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or
different banks as long as the banks are activated.
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ESMT
M14D128168A (2M)
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE LOW while holding RAS HIGH at the rising edge of the
clock (CLK). The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL)
minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is
registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven low (preamble) one
clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS
following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge
during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed,
which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal
is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the
write recovery time (tWR).
Write (Data Input) Timing
tDQSL
tDQSH
DQS
DQS
DQS
DQS
tWPST
tWPRE
DQ
tDS
Din3
Din2
Din1
Din0
tDH
tDS
tDH
DM
Burst Write
< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >
T0
T1
T2
T4
T3
T5
T6
T7
Tn
CLK
CLK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
Case1 : with tDQSS(max)
DQS,DQS
tDQSS
WL = RL -1 = 4
DQs
tDSS
DinA0
tDQSS
Case2 : with tDQSS(min)
>= tWR
DinA1 DinA2 DinA3
tDSH
DQS,DQS
WL = RL -1 = 4
>= tWR
DQs
DinA0
DinA1 DinA2 DinA3
< RL= 3 (AL= 0; CL= 3); WL= 2; BL= 4 >
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CLK
CLK
CMD
WRITE A
NOP
NOP
NOP
NOP
NOP
Precharge
NOP
Bank A
Active
tDQSS
DQS,DQS
WL = RL -1 = 2
DQs
Elite Semiconductor Memory Technology Inc.
tWR
DinA0
>= tRP
DinA1 DinA2 DinA3
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ESMT
M14D128168A (2M)
Burst Write followed by Burst Read
< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >
T0
T1
T2
T4
T3
T6
T5
T7
T9
T8
CLK
CLK
Write to Read = CL -1+BL/2+tWTR
NOP
CMD
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQS,DQS
DQS
AL = 2
WL = RL -1 = 4
CL = 3
RL = 5
> = tWTR
DQ
DinA0
DoutA0
DinA1 DinA2 DinA3
Note: The minimum number of clock from the Burst Write command to the Burst Read command is [CL - 1 + BL/2
+ tWTR]. This tWTR is not a write recovery time (WR) but the time required to transfer the 4 bit write data from
the input buffer into sense amplifiers in the array.
Seamless Burst Write
< RL= 5; WL= 4; BL= 4 >
T0
T1
T2
T3
T4
T6
T5
T7
T8
CLK
CLK
CMD
Posted CAS
WRITE A
NOP
Posted CAS
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
WL = RL-1 = 4
DQs
DinA0 DinA1 DinA2 DinA3 DinB0 DinB1 DinB2 DinB3
Note: The seamless burst write operation is supported by enabling a Write command at every other clock for BL =
4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or
different banks as long as the banks are activated.
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ESMT
M14D128168A (2M)
Read Interrupted by a Read
Burst Read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed.
< CL= 3; AL= 0; RL= 3; BL= 8 >
CLK
CLK
READ A
CMD
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
A0
DQs
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Note:
1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write
command or Precharge command is prohibited.
3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst
interrupt timings are prohibited.
4. Read burst interruption is allowed to any bank inside DRAM.
5. Read burst with Auto Precharge enabled is not allowed to interrupt.
6. Read burst interruption is allowed by another Read with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length
set in the MRS and not the actual burst (which is shorter because of interrupt).
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ESMT
M14D128168A (2M)
Write Interrupted by a Write
Burst Wirte can only be interrupted by another Write with 4 bit burst boundary. Any other case of Write interrupt is not allowed.
< CL= 3; AL= 0; RL= 3; WL= 2; BL= 8 >
T0
T1
T2
T4
T3
T5
T6
T7
T8
CLK
CLK
CMD
NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
A0
DQs
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Note:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read
command or Precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst
interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the MRS. They are not referenced to actual
burst. For example, minimum Write to Precharge timing is WL+BL/2+ tWR where tWR starts with the rising
clock after the un-interrupted burst end and not from the end of actual burst end.
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ESMT
M14D128168A (2M)
Burst Read Followed by Precharge
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(tRTP, 2) - 2 clocks.
For the earliest possible Precharge, the Precharge command may be issued on the rising edge which is “Additive latency (AL) +
BL/2 clocks” after a Read command. A new Bank Active command may be issued to the same bank after the Precharge time (tRP).
A Precharge command cannot be issued until tRAS is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the
last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4, this is the time from
the actual read (AL after the Read command) to Precharge command. For BL = 8, this is the time from AL + 2 clocks after the Read
to the Precharge command.
< RL= 4 (AL= 1; CL= 3) >
T0
T1
T2
T4
T3
T5
T6
T7
T8
CLK
CLK
Posted CAS
READ A
CMD
BL = 4
NOP
NOP
AL + BL/2 clks
Bank A
Active
NOP
NOP
NOP
Precharge
NOP
DQS,DQS
>= tRP
CL = 3
AL = 1
RL = 4
DQs
DoutA0 DoutA1 DoutA2 DoutA3
>= tRAS
>= tRTP
Posted CAS
READ A
CMD
CL = 3
NOP
NOP
AL + BL/2 clks
NOP
NOP
NOP
NOP
Precharge A
NOP
DQS,DQS
BL = 8
CL = 3
AL = 1
RL = 4
DQs
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
>= tRTP
< RL= 5 (AL= 2; CL= 3); BL= 4 >
T0
T1
T2
T4
T3
T6
T5
T7
T8
CLK
CLK
CMD
Posted CAS
READ A
NOP
NOP
AL + BL/2 clks
NOP
Precharge A
Bank A
Active
NOP
NOP
NOP
>= tRP
DQS,DQS
AL = 2
RL = 5
DQs
CL = 3
DoutA0 DoutA1 DoutA2 DoutA3
>= tRAS
CL = 3
>= tRTP
< RL= 6 (AL= 2; CL= 4); BL= 4 >
T0
T1
T2
T4
T3
T6
T5
T7
T8
CLK
CLK
CMD
Posted CAS
READ A
NOP
NOP
AL + BL/2 clks
NOP
Precharge A
NOP
NOP
Bank A
Active
NOP
>= tRP
DQS,DQS
AL = 2
CL = 4
RL = 6
DQs
DoutA0 DoutA1 DoutA2 DoutA3
>= tRAS
>= tRTP
Elite Semiconductor Memory Technology Inc.
CL = 4
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ESMT
M14D128168A (2M)
< RL= 4 (AL= 0; CL= 4); BL=8 >
T0
T1
T2
T4
T3
T5
T6
T7
T8
CLK
CLK
Posted CAS
WRITE A
CMD
NOP
NOP
NOP
NOP
NOP
Precharg A
AL+2 clks + max(tRTP;2)
NOP
Bank A
Active
> = tRP
DQS,DQS
CL = 4
AL = 0
RL = 4
DQs
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
>= tRAS
Burst Write Followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 clocks + tWR.
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be
issued. This delay is known as a write recovery time (tWR) referenced from the completion of the Burst Write to the Precharge
command. No Precharge command should be issued prior to the tWR delay.
< WL= (RL-1) = 3; BL=4>
T0
T1
T2
T4
T3
T5
T6
T7
T8
CLK
CLK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharg A
> = tWR
DQS,DQS
WL = 3
DinA0
DQs
DinA1 DinA2
DinA3
< WL= (RL-1) = 4; BL=4 >
T0
T1
T2
T3
T4
T5
T6
T7
T9
CLK
CLK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharg A
> = tWR
DQS,DQS
WL = 4
DQs
Elite Semiconductor Memory Technology Inc.
DinA0
DinA1 DinA2
DinA3
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ESMT
M14D128168A (2M)
Write data mask by DM
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM, Consistent with the implementation
on DDR2 SDRAM. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is
internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.
Data Mask Timing
T1
T2
T3
T4
Din
Din
T5
Tn
DQS
DQS
Din
DQ
Din
Din
Din
Din
Din
Din
DM
Write mask Iatency = 0
Example: < WL= 3; AL= 0; BL= 4 >
T0
T1
T2
T4
T3
T5
T6
T7
T8
CLK
CLK
tWR
Command
NOP
WRIT
[tDQSS(min.)]
WL
tDQSS
DQS,DQS
DQ
Din0
Din2
DM
[tDQSS(max.)]
WL
tDQSS
DQS,DQS
DQ
Din0
Din2
DM
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ESMT
M14D128168A (2M)
Read with Auto Precharge
If A10 is HIGH when a Read command is issued, the Read with Auto Precharge function is engaged. The device starts an Auto
Precharge operation on the rising edge which is (AL + BL/2) cycles later than the Read with AP command if tRAS (min) and tRTP(min)
are satisfied.
If tRAS(min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRAS(min) is satisfied.
If tRTP (min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRTP (min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next
rising clock edge after this event). So for BL = 4, the minimum time from Read_AP to the next Bank Active command becomes AL
+ (tRTP + tRP)*. For BL = 8, the time from Read_AP to the next Bank Active command is AL + 2 + (tRTP + tRP)*. (Note: “*” means
“rouded up to the next integer”).
< RL= 4 (AL= 1; CL= 3) >
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
CMD
BL = 8
t RTP <= 2 clocks
Posted CAS
READ A
Autoprecharge
NOP
NOP
AL+BL/2 clks
NOP
NOP
NOP
NOP
NOP
Bank A
Active
> = tRP
DQS,DQS
AL = 1
CL = 3
RL = 4
DQs
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
>= tRTP
tRTP
Precharge begins here
CMD
BL = 4
t RTP > 2 clocks
Posted CAS
READ A
Autoprecharge
NOP
NOP
>=AL+tRTP+tRP
NOP
NOP
NOP
NOP
Bank A
Active
NOP
DQS,DQS
AL = 1
DQs
CL = 3
RL = 4
DoutA0 DoutA1 DoutA2 DoutA3
tRTP
tRP
Precharge begins here
A new Bank Active command may be issued to the same bank if the following two conditions are satisfied simultaneously.
(1) The Precharge time (tRP) has been satisfied from the clock at which the Auto Precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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ESMT
M14D128168A (2M)
< RL= 5 (AL= 2; CL= 3); BL= 4; tRCD = 3 clocks; tRTP <= 2 clocks >
T0
T1
T2
T4
T3
T5
T6
T7
T8
CLK
CLK
CMD
Posted CAS
READ A
Autoprecharge
NOP
NOP
>= tRAS(min)
tRC Limit
NOP
NOP
NOP
Bank A
Active
Bank A
Active
NOP
NOP
NOP
Autoprecharge begins
DQS,DQS
CL = 3
AL = 2
>= tRP
RL = 5
DQs
DoutA0 DoutA1 DoutA2 DoutA3
>= tRC
CLK
CLK
CMD
Posted CAS
READ A
Autoprecharge
NOP
NOP
>= tRAS(min)
tRP Limit
NOP
NOP
NOP
NOP
Autoprecharge begins
DQS,DQS
CL = 3
AL = 2
>= tRP
RL = 5
DQs
DoutA0 DoutA1 DoutA2 DoutA3
>= tRC
Write with Auto Precharge
If A10 is HIGH when a Write command is issued, the Write with Auto Precharge function is engaged. The device automatically
begins precharge operation after the completion of the burst write plus write recovery time (tWR). The Bank Active command
undergoing Auto Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied.
(1) The data-in to bank activate delay time (tWR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
< WR = 2; BL= 4; tRP = 3 clocks >
T0
T1
T2
T3
T4
T5
T6
T7
Tm
CLK
CLK
CMD
Posted CAS
WRITE A
Autoprecharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank A
Active
Auto Precharge begins
tRC Limit
DQS,DQS
>= tWR
WL = RL-1 = 2
>= tRP
DinA0 DinA1 DinA2 DinA3
DQs
>= tRC
T0
T3
T4
T5
T6
T7
T8
T9
T12
CLK
CLK
CMD
Posted CAS
WRITE A
Autoprecharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank A
Active
Auto Precharge begins
tWR + tRP
DQS,DQS
WL = RL-1 = 4
DQs
>= tWR
>= tRP
DinA0 DinA1 DinA2 DinA3
>= tRC
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ESMT
M14D128168A (2M)
Auto Refresh & Self Refresh
Auto Refresh
An Auto Refresh command is issued by having CS , RAS and CAS held LOW with CKE and WE HIGH at the rising edge of the
clock(CLK). All banks must be precharged and idle for tRP(min) before the Auto Refresh command is applied. An address counter,
internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once
this cycle has started. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh
command and the next Bank Active command or subsequent Auto Refresh command must be greater than or equal to the
tRFC(min).To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight Refresh commands can be posted, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x tREFI.
CLK
CLK
COMMAND
Au t o
Refresh
PRE
CMD
CKE = High
tRP
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tRFC
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ESMT
M14D128168A (2M)
Self Refresh
A Self Refresh command is defined by having CS , RAS , CAS and CKE held LOW with WE HIGH at the rising edge of the
clock (CLK). ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1)
command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the device has
entered Self Refresh mode, all of the external signals except CKE, are “don’t care”.
For proper Self Refresh operation all power supply pins (VDD, VDDQ, VDDL and VREF) must be at valid levels. The device initiates a
minimum of one refresh command internally within tCKE period once it enters Self Refresh mode. The clock is internally disabled
during Self Refresh operation to save power. Self Refresh mode must be remained tCKE (min).
The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered,
however, the clock must be restarted and stable before the device can exit Self Refresh operation. The procedure for exiting Self
Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit
is registered, a delay of tXSRD(min) must be satisfied before a valid command can be issued to the device to allow for any internal
refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSRD for proper operation except for Self
Refresh re-entry. Upon exit from Self Refresh, the device can be put back into Self Refresh mode after waiting tXSNR(min) and
issuing one Refresh command. NOP or deselect commands must be registered on each positive clock edge during the Self
Refresh exit interval tXSNR. ODT should be turned off during tXSRD. The use of Self Refresh mode introduces the possibility that an
internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the
device requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
T0
T1
T2
T3
T4
T6
T5
Tn
Tm
tCK
tCH
tCL
CLK
CLK
>= tXSNR
>= tXSRD
tRP
CKE
tAOFD
tIS
tIS
ODT
tIS
tIS
tIH
Command
Note:
1. Device must be in the “All banks idle” state prior to entering Self Refresh mode.
2. ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD
timing is satisfied.
3. tXSRD is applied for a Read or a Read with Auto Precharge command.
4. tXSNR is applied for any command except a Read or a Read with Auto Precharge command.
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ESMT
M14D128168A (2M)
Power-Down
Power-Down is synchronously entered when CKE is registered LOW (no accesses can be in progress). CKE is not allowed to go
LOW while MRS or EMRS command time, or read or write operation is in progress. CKE is allowed to go LOW while any of other
operations such as Bank Active, Precharge or Auto Precharge, or Auto Refresh is in progress. The DLL should be in a locked state
when Power-Down is entered. Otherwise DLL should be reset after exiting Power-Down mode for proper read operation.
If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power-Down occurs when
there is a Bank Active command in any bank, this mode is referred to as Active Power-Down. Entering Power-Down deactivates
the input and output buffers, excluding CLK, CLK , ODT and CKE. Also the DLL is disabled upon entering Precharge Power-Down
or slow exit Active Power-Down, but the DLL is kept enabled during fast exit Active Power-Down. In Power-Down mode, CKE LOW
and a stable clock signal must be maintained at the inputs of the device, and ODT should be in a valid state but all other input
signals are “Don’t Care”. CKE LOW must be maintained until tCKE has been satisfied. Power-Down duration is limited by 9 times
tREFI of the device.
The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). CKE
HIGH must be maintained until tCKE has been satisfied. A valid, executable command can be applied with Power-Down exit latency,
tXP, tXARD, or tXARDS, after CKE goes HIGH.
CLK
CLK
tIS tIH
tIS tIH
VALID
NOP
tIH
tIH
tIS
CKE
Command
NOP
tCKE
VALID
VALID
VALID
tCKE
tXP, tXARD,
tXARDS
tCKE
Exit power-down mode
Enter power-down mode
: Don’t care
Read to Power-Down Entry
T0
T1
T2
Tx+1
Tx
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CLK
CLK
CKE should be kept high until the end of burst operation
Command
READ
High
CKE
BL = 4
DQS
DQS
AL + CL
DoutA0 DoutA1 DoutA2 DoutA3
DQ
T0
T1
T2
Tx+1
Tx
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CLK
CLK
Command
READ
CKE should be kept high until the end of burst operation
High
CKE
BL = 8
DQS
DQS
AL + CL
DQ
Elite Semiconductor Memory Technology Inc.
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
M14D128168A (2M)
Read with Auto Precharge to Power-Down Entry
T0
T1
T2
Tx+1
Tx
Tx+2
Tx+3
Tx+5
Tx+4
Tx+6
Tx+7
Tx+8
Tx+9
CLK
CLK
Command
READ
PRE
AL+BL/2
with tRTP =7.5ns
and tRAS(min.) satisfied
CKE should be kept high until the end of burst operation
CKE
DQS
DQS
BL = 4
AL + CL
DoutA0 DoutA1 DoutA2 DoutA3
DQ
T0
T1
T2
Tx+1
Tx
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CLK
CLK
Start internal precharge
Command
PRE
READ
CKE should be kept high until the end of burst operation
AL+BL/2
with tRTP = 7.5ns
and tRAS(min.) satisfied
CKE
BL = 8
DQS
DQS
AL + CL
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
DQ
Write to Power-Down Entry
T0
T1
Tm
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Ty
Ty+1
Ty+2
Ty+3
Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
CLK
CLK
Command
WRITE
CKE
tWTR
BL = 4
DQS
DQS
WL
DinA0 DinA1 DinA2 DinA3
DQ
T0
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
CLK
CLK
Command
WRITE
CKE
tWTR
BL = 8
DQS
DQS
WL
DQ
DinA0 DinA1 DinA2 DinA3 DinA4 DinA5 DinA6 DinA7
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ESMT
M14D128168A (2M)
Write with Auto Precharge to Power-Down Entry
T0
T1
Tm
Tm+1
Tm+3
Tm+2
Tx+1
Tx
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx
Tx+1
Tx+2
Tx+3
Tx+4
CLK
CLK
Command
PRE
WRITE A
CKE
tWR
BL = 4
DQS
DQS
WL
DinA0 DinA1 DinA2 DinA3
DQ
T0
T1
Tm
Tm+3
Tm+2
Tm+1
Tm+5
Tm+4
CLK
CLK
Command
PRE
WRITE A
CKE
tWR
BL = 8
DQS
DQS
WL
DinA0 DinA1 DinA2 DinA3 DinA4 DinA5 DinA6 DinA7
DQ
Auto Refresh/ Bank Active/ Precharge to Power-Down Entry
T0
T1
T2
T3
T8
T7
T6
T5
T4
T9
T10
T11
CLK
CLK
Command
CMD
CKE can go to low one clock after a command
CKE
Note: CMD could be Auto Refresh/ Bank Active/ Precharge command.
MRS/EMRS to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
CLK
Command
MRS/
EMRS
CKE
tMRD
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
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ESMT
M14D128168A (2M)
Asynchronous CKE Low event
DDR2 SDRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously
drops “LOW” during any valid operation, the device is not guaranteed to preserve the contents of array. If this event occurs,
memory controller must satisfy tDELAY before turning off the clocks. Stable clocks must exist at the input of device before CKE is
raised “HIGH” again. The device must be fully re-initialized (steps 4 ~ 13) as described in initialization sequence. The device is
ready for normal operation after the initialization sequence.
Stable clocks
tCK
CLK
CLK
tDELAY
CKE
CKE asynchronously
drops low
Clocks can be turned off
after this point
Clock Frequency change in Precharge Power-Down mode
DDR2 SDRAM input clock frequency can be changed under following condition:
The device is in Precharge Power-Down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2
clocks must be waited after CKE goes LOW before clock frequency may change. The device input clock frequency is allowed to
change only between tCK (min) and tCK (max). During input clock frequency change, ODT and CKE must be held at stable LOW
levels. Once input clock frequency is changed, stable new clocks must be provided before Precharge Power-Down may be exited
and DLL must be RESET via MRS after Precharge Power-Down exit. Depending on new clock frequency an additional MRS
command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After the
DLL lock time, the device is ready to operate with new clock frequency.
T0
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
NOP
NOP
DLL
Reset
Tz
CLK
CLK
command
NOP NOP
NOP
Vaild
CKE
ODT
200 clocks
Frequency change
occurs here
tRP
txP
tAOFD
Minimum 2 clocks required
before changing frequency
Elite Semiconductor Memory Technology Inc.
Stable new clock
before power down exit
ODT is off
during DLL RESET
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
M14D128168A (2M)
Functional Truth Table
Current State
IDLE
BANK ACTIVE
READ
WRITE
Address
Command
Action
CS
RAS
CAS
WE
H
X
X
X
X
DESEL
NOP or Power-Down
L
H
H
H
X
NOP
NOP or Power-Down
L
H
L
X
BA, CA, A10
READ / READA /
ILLEGAL (*1)
WRITE / WRITEA
L
L
H
H
BA, RA
Active
Bank Active, Latch RA
L
L
H
L
BA, A10 / A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
Refresh
Refresh (*2)
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
Mode Register setting / Extended
Mode Register setting (*2)
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
L
H
BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto Precharge
L
H
L
L
BA, CA, A10
WRITE / WRITEA
Begin Write, Latch CA,
Determine Auto Precharge
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 /A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin New Read,
Determine Auto Precharge (*1, 4)
L
H
L
L
BA, CA, A10
WRITE / WRITEA
ILLEGAL (*1)
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to end)
L
H
H
H
X
NOP
NOP (Continue Burst to end)
L
H
L
H
BA, CA, A10
READ / READA
ILLEGAL (*1)
L
H
L
L
BA, CA, A10
WRITE / WRITEA
Terminate Burst, Latch CA,
Begin new Write,
Determine Auto-Precharge (*1, 4)
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
Current State
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
PRE-CHARGIN
G
ROW
ACTIVATING
M14D128168A (2M)
Address
Command
Action
CS
RAS
CAS
WE
H
X
X
X
X
DESEL
NOP (Continue Burst to end)
L
H
H
H
X
NOP
NOP (Continue Burst to end)
L
H
L
H
BA, CA, A10
READ / READA
ILLEGAL (*1)
L
H
L
L
BA, CA, A10
WRITE / WRITEA
ILLEGAL (*1)
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
L
H
BA, CA, A10
READ / READA
ILLEGAL (*1)
L
H
L
L
BA, CA, A10
WRITE / WRITEA
ILLEGAL (*1)
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
L
X
BA, CA, A10
READ / READA /
ILLEGAL (*1)
WRITE / WRITEA
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 / A10
PRE / PREA
NOP (Idle after tRP)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Bank Active after tRCD)
L
H
H
H
X
NOP
NOP (Bank Active after tRCD)
L
H
L
X
BA, CA, A10
READ / READA /
ILLEGAL (*1, 5)
WRITE / WRITEA
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
Current State
WRITE
RECOVERING
WRITE
RECOVERING
with
AUTO
PRECHARGE
REFRESH
(Extended)
MODE
REGISTER
SETTING
M14D128168A (2M)
Address
Command
Action
CS
RAS
CAS
WE
H
X
X
X
X
DESEL
NOP (Bank Active after tWR)
L
H
H
H
X
NOP
NOP (Bank Active after tWR)
L
H
L
H
BA, CA, A10
READ / READA
ILLEGAL (*1, 6)
L
H
L
L
BA, CA, A10
WRITE / WRITEA
WRITE / WRITEA
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Bank Active after tWR)
L
H
H
H
X
NOP
NOP (Bank Active after tWR)
L
H
L
X
BA, CA, A10
READ / READA /
ILLEGAL (*1)
WRITE / WRITEA
L
L
H
H
BA, RA
Active
ILLEGAL (*1)
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRFC)
L
H
H
H
X
NOP
NOP (Idle after tRFC)
L
H
L
X
BA, CA, A10
READ / READA /
ILLEGAL
WRITE / WRITEA
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tMRD)
L
H
H
H
X
NOP
NOP (Idle after tMRD)
L
H
L
X
BA, CA, A10
READ / READA /
ILLEGAL
WRITE / WRITEA
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10 / A10
PRE / PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code Mode-Add
MRS / EMRS
ILLEGAL
H = High Level, L = Low level, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
ILLEGAL = Device operation and / or data integrity are not guaranteed.
Note :
1.
2.
3.
4.
5.
6.
This command may be issued for other banks, depending on the state of the banks.
All banks must be in “IDLE”.
All AC timing specs must be met.
Only allowed at the boundary of 4 bits burst. Burst interruption at other timings is illegal.
Available in case tRCD is satisfied by AL setting.
Available in case tWTR is satisfied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
M14D128168A (2M)
Simplified States Diagram
CKEL = CKE LOW
CKEH = CKE HIGH
ACT = Activate
WR(A) = Write (with Auto Precharge)
RD(A) = Read (with Auto Precharge)
PR(A) = Precharge (All)
(E)MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Auto Refresh
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
PACKING
M14D128168A (2M)
DIMENSIONS
84-BALL FBGA (Window BGA) / VFBGA DDRII SDRAM ( 8x12.5x1.2 mm )
Symbol
Dimension in mm
Min
Norm
Max
A
1.00
1.15
1.20
A1
0.25
0.35
0.40
Φb
0.37
0.45
0.50
D
7.90
8.00
8.10
E
12.40
12.50
12.60
D1
6.40 BSC
E1
11.20 BSC
e
0.80 BSC
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min
Norm
Max
0.039
0.045
0.047
0.010
0.014
0.016
0.015
0.018
0.020
0.311
0.315
0.319
0.488
0.492
0.496
0.252 BSC
0.441 BSC
0.031 BSC
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
PACKING
M14D128168A (2M)
DIMENSIONS
84-BALL FBGA (Window BGA)
Symbol
DDRII SDRAM
Dimension in mm
Min
Norm
Max
A
0.87
0.93
1.00
A1
0.25
0.32
0.37
Φb
0.37
0.42
0.50
D
7.90
8.00
8.10
E
12.40
12.50
12.60
D1
6.40 BSC
E1
11.20 BSC
e
0.80 BSC
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
( 8x12.5x1.0 mm )
Dimension in inch
Min
Norm
Max
0.034
0.037
0.039
0.010
0.013
0.015
0.015
0.017
0.020
0.311
0.315
0.319
0.488
0.492
0.496
0.252 BSC
0.441 BSC
0.031 BSC
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
PACKING
84-BALL
M14D128168A (2M)
DIMENSIONS
VFBGA DDRII SDRAM
Symbol
( 8x12.5x1.0 mm )
Dimension in mm
Min
Norm
Max
A
0.87
0.94
1.00
A1
0.25
0.35
0.40
Φb
0.37
0.45
0.50
D
7.90
8.00
8.10
E
12.40
12.50
12.60
D1
6.40 BSC
E1
11.20 BSC
e
0.80 BSC
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min
Norm
Max
0.034
0.037
0.039
0.010
0.014
0.016
0.015
0.018
0.020
0.311
0.315
0.319
0.488
0.492
0.496
0.252 BSC
0.441 BSC
0.031 BSC
Publication Date : Mar. 2013
Revision : 1.4
57/59
ESMT
M14D128168A (2M)
Revision History
Revision
Date
0.1
2012.05.22
Original
1.0
2012.05.30
Delete "Preliminary"
1.1
2012.08.23
Add BGA package for A(max) = 1.0mm
1.2
2012.09.18
Modify the specification of IDD0, IDD1 for speed grade
-2.5 and IDD5
1.3
2013.03.11
1. Change BGA to VFBGA (Window BGA)
2. Add VFBGA package for A(max) = 1.2mm and 1.0mm
3. Add packing dimension of VFBGA (Window BGA:
8x12.5x1.0mm)
4. Modify the value of A and A1 in packing dimension
( 8x12.5x1.2mm & VFBGA: 8x12.5x1.0mm )
5. Modify Input / Output Capacitance
1.4
2013.03.29
Modify VFBGA (Window BGA) to FBGA (Window BGA)
Elite Semiconductor Memory Technology Inc.
Description
Publication Date : Mar. 2013
Revision : 1.4
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ESMT
M14D128168A (2M)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time
of publication. ESMT assumes no responsibility for any error in this document,
and reserves the right to change the products or specification in this document
without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express, implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but
not limited to, life support devices or system, where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage. If
products described here are to be used for such kinds of application, purchaser
must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
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Revision : 1.4
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