BCM1255 Product Brief

BCM1255
®
DUAL-CORE 64-BIT MIPS® PROCESSOR
SUMMARY OF BENEFITS
FEATURES
•
Two 64-bit MIPS® CPUs, scalable from 800 MHz–1.2 GHz
• Quad issue in-order pipeline with dual-execute and dual-memory pipes
• Enhanced skew pipeline enables a zero load-to-use penalty
• 32-KB instruction cache and 32-KB data cache (ECC protected)
•
Fast on-chip multiprocessor bus
• Connects the CPUs, L2 cache, memory controller, and I/O bridges
• Runs at half the CPU core frequency and is 256 bits wide
•
On-chip L2 cache
• 512 KB shared by two CPUs and I/O agents
• Eight-way associative, ECC protected
• Any way can be programmed as fast on-chip RAM
•
DDR memory controller
• Memory bandwidth as high as 100 Gbps
• Configurable as 2 x 64-bit or 4 x 32-bit wide channels
• Runs up to 400-MHz clock rate, 800-MHz data rate
• Support for DDR1 and DDR2
•
Integrated network and system I/O
• Four Gigabit Ethernet MACs configurable as packet FIFO interfaces
• 64-bit PCI-X® interface at 133 MHz
• Generic I/O for direct connect to boot ROM, flash memory
• Two SMBus serial configuration interfaces
• PCMCIA control interface and up to 16 interrupts
• Four UART interfaces
On-chip debug capability
• EJTAG
• Bus trace unit (internal logic analyzer)
Support for leading operating systems, including VxWorks®, Linux®,
and QNX®
•
Industry-leading performance
• 2.5 Dhrystone MIPS/MHz per CPU
• 10 million packets per second of L3 forwarding
• 128 Gbps on-chip bus bandwidth, with 100 Gbps memory bandwidth
and 31 Gbps 1/0 bandwidth
•
•
•
Low-power dissipation of 13W @ 1 GHz
•
•
Software-compatible with the BCM1250 and BCM112X
High functional integration, reducing overall system cost
Programming ease and flexibility based on MIPS64® instruction set
architecture (ISA)
Broad tools and system software support
APPLICATIONS
•
Because of its world-class performance, power efficiency, and
integration, the BCM1255 processor is ideal for a broad variety of
applications, including:
• Enterprise-class routers and switches
• Multifunction security platforms (VPN/SSL/IDS)
• Compact NAS platforms
• SAN routers/gateways/switches
• Video servers and systems
Evaluation board platform available with samples (includes tools,
firmware, and software drivers)
BCM1255 Applications
VPN/Firewall Application
Storage System or Video Server
DRAM
DRAM
SATA Disk Drives
GMII
Control Path
GMII
BCM1255
GMII
PCI-X ServerWorks
SATA Bridge
BCM1255
Data Path
FIFO
4xGMII
BCM5841
2 Gbps Full-Duplex IPSec
JTAG
OVERVIEW
Debug/ Bus
Trace
SB_1
Core
SB_1
Core
512K
L2 Cache
DDR
Memory
Controller
100 Gbps
256 Bits
Serial
Interfaces
ZBBus
Data
Mover
1/2 core clock; 128 Gbps @ 1 GHz
Dual
SMBus
DMA
DMA
DMA
DMA
10/100/
1000
MAC
10/100/
1000
MAC
10/100/
1000
MAC
10/100/
1000
MAC
GPIO/
Interrupt/
PCMCIA
I/O Bridge
Generic Bus
& Flash I/O
64 Bit PCI-X
8 Gbps
4xGMII
(and/or Packet FIFO)
1 Gbps
BCM1255 Block Diagram
The BCM1255 device is a MIPS64 processor core-based system-on-a-chip (SOC)
that offers industry-leading performance, high functional integration, and low
power levels required by next-generation computing, storage, and networking
applications.
The BCM1255 is a chip multiprocessor (CMP) system consisting of two
Broadcom SB-1 high-performance MIPS64 CPUs, a shared 512-KB L2 cache, a
DDR memory controller, and an integrated I/O. All major blocks of the processor
are connected together via the ZBbus™, a high-speed, split-transaction
multiprocessor bus.
functions assist both hardware and software designers in debugging and tuning
the system. The system can be run in either big-endian or little-endian mode.
Implementation of MIPS64 ISA
The SB-1 CPU core is a high-performance implementation of the standard
MIPS64 ISA that incorporates the MIPS-3D and MIPS-MDMX applicationspecific extensions (ASEs). The core supports a four-issue enhanced skew
pipeline and can dispatch up to two memory and two ALU (integer, floating point,
MDMX, or MIPS-3D) instructions per cycle.
The bus implements the standard MESI protocol to ensure coherency between the
two CPUs, L2 cache, I/O agents, and memory. Four Gigabit Ethernet (GbE)
MACs (10/100/1000) enable easy interfacing to LANs or control backplanes. To
enable higher data rates (or in cases where Ethernet protocol processing is not
required), the GbE MACs can be configured as 8-bit and/or 16-bit packet FIFOs.
The BCM1255 also integrates a 64-bit 133-MHz PCI-X local bus for direct
connection to I/O devices. Four serial ports are available for use as UARTs for
console ports.
Next-Generation Broadband Processors
# of CPUs
L2 Cache
DDR2 Support
# of MACs
PCI-X
# of SPI-4/HT Ports
BCM1255 BCM1280 BCM1455 BCM1480
2
2
4
4
512 KB
1 MB
1 MB
1 MB
Yes
Yes
Yes
Yes
4 GMII
4 GMII
4 GMII
4 GMII
1 x 64-bit 1 x 64-bit 1 x 64-bit 1 x 64-bit
0
3
0
3
To enable low-chip count systems, the BCM1255 also includes a configurable
generic bus that allows glueless connection of a boot ROM or flash memory and
simple I/O peripherals. On-chip debug, trace, and performance monitoring
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among
the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries
and/or the EU. Any other trademarks or trade names mentioned are the property of their respective
owners.
®
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2006 by BROADCOM CORPORATION. All rights reserved.
1255-PB04-R
05/12/06
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: [email protected]
Web: www.broadcom.com