IS61LPS25632A

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
256K x 36, 256K x 32, 512K x 18
9 Mb SYNCHRONOUS PIPELINED,
Single CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for BGA package
• Power Supply
LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5%
• JEDEC 100-Pin QFP, 119-ball BGA, and 165ball BGA packages
• Lead-free available
JUNE 2015
DESCRIPTION
The ISSI IS61LPS/VPS25636A, IS61LPS25632A,
IS64LPS25636A and IS61LPS/VPS51218A are highspeed, low-power synchronous static RAMs designed
to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/
VPS25636A and IS64LPS25636A are organized as
262,144 words by 36 bits. The IS61LPS25632A is
organized as 262,144 words by 32 bits. The IS61LPS/
VPS51218A is organized as 524,288 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH
or left floating.
FAST ACCESS TIME
Symbol
tkq
tkc
Parameter
Clock Access Time
Cycle Time
Frequency
250200166
2.6
3.1
3.5
4
5
6
250
200
166
Units
ns
ns
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
1
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
BLOCK DIAGRAM
MODE
CLK
Q0
CLK
A0
BINARY
COUNTER
ADV
ADSC
ADSP
A
Q1
CE
A1
A0'
A1'
256Kx32;
256Kx36;
512Kx18
MEMORY ARRAY
CLR
18/19
D
Q
16/17
18/19
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
D
GW
BWE
BW(a-d)
x18: a,b
x32/x36: a-d
32, 36,
or 18
Q
DQ(a-d)
BYTE WRITE
REGISTERS
CLK
CE
2/4/8
CE2
D
Q
ENABLE
REGISTER
CE2
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32, 36,
or 18
DQa - DQd
OE
CE
CLK
D
ZZ
POWER
DOWN
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165-pin BGA
119-pin BGA
165-Ball, 13x15 mm BGA
119-Ball, 14x22 mm BGA
Bottom view
Bottom View
Integrated Silicon Solution, Inc.
Rev. 05/25/2015
3
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION-256K x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC
CE2
A
ADSC
A
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQPc
Vss
NC
Vss
DQPb
DQb E
DQc
DQc
Vss
CE
Vss
DQb
DQb
F
VDDQ
DQc
Vss
OE
Vss
DQb
VDDQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
Vss
GW
Vss
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
Vss
CLK
Vss
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
Vss
BWE
Vss
DQa
VDDQ
N
DQd
DQd
Vss
A1*
Vss
DQa
DQa
P
DQd
DQPd
Vss
A0*
Vss
DQPa
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
OE
Pin Name
Output Enable
A0, A1
ADV
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
ADSP
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
TCK, TDO
JTAG Pins
ADSC
GW
Address Status Controller
Global Write Enable
CLK
CE, CE2
Synchronous Clock
Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Controls
BWE
4
Byte Write Enable
TMS, TDI
NC
No Connect
DQa-DQd
Data Inputs/Outputs
DQPa-Pd
Output Power Supply
Vdd
Power Supply
Vddq
Output Power Supply
Vss
Ground
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION
512Kx18 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC
CE2
A
ADSC
A
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQb
NC
Vss
NC
Vss
DQPa
NC
E
NC
DQb
Vss
CE
Vss
NC
DQa
F
VDDQ
NC
Vss
OE
Vss
DQa
VDDQ
G
NC
DQb
BWb
ADV
Vss
NC
DQa
H
DQb
NC
Vss
GW
Vss
DQa
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQb
Vss
CLK
Vss
NC
DQa
L
DQb
NC
Vss
NC
BWa
DQa
NC
M
VDDQ
DQb
Vss
BWE
Vss
NC
VDDQ
N
DQb
NC
Vss
A 1*
Vss
DQa
NC
P
NC
DQPb
Vss
A 0*
Vss
NC
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
OE
Pin Name
Output Enable
A0, A1
ADV
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
ADSP
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
TCK, TDO
JTAG Pins
ADSC
GW
Address Status Controller
Global Write Enable
NC
No Connect
CLK
CE, CE2
Synchronous Clock
Synchronous Chip Select
DQa-DQb
Data Inputs/Outputs
DQPa-Pb
Output Power Supply
Vdd
Power Supply
Vddq
Output Power Supply
Vss
Ground
BWx (x=a,b) Synchronous Byte Write Controls
BWE
Byte Write Enable
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
TMS, TDI
5
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BGA PACKAGE PIN CONFIGURATION
256K x 36 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWc
BWb
CE2
BWE
ADSC
ADV
A
NC
B
NC
A
CE2
BWd
BWa
CLK
GW
OE
ADSP
A
NC
C
DQPc
NC
Vddq
Vss
Vss
Vss
Vss
Vss
Vddq
NC
DQPb
D
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
DQb
E
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
F
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
G
DQc
DQc
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQb
DQb
H
NC
Vss
NC
Vdd
Vss
Vss
Vss
Vdd
NC
NC
ZZ
J
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
K
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
L
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
M
DQd
DQd
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
DQa
N
DQPd
NC
Vddq
Vss
NC
NC
NC
Vss
Vddq
NC
DQPa
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
Pin Name
BWE
Byte Write Enable
A0, A1
ADV
OE
Output Enable
ZZ
Power Sleep Mode
ADSP
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
MODE
Burst Sequence Selection
ADSC
GW
Address Status Controller
Global Write Enable
JTAG Pins
CLK
CE, CE2, CE2
Synchronous Clock
Synchronous Chip Select
TCK, TDO
TMS, TDI
NC
DQx
DQPx
Vdd
Vddq
BWx (x=a,b,c,d) Synchronous Byte Write
Controls
Vss
6
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply 3.3V/2.5V
Ground
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BGA PACKAGE PIN CONFIGURATION
512K x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWb
NC
CE2
BWE
ADSC
ADV
A
A
B
NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP
A
NC
C
NC
NC
Vddq
Vss
Vss
Vss
Vss
Vss
Vddq
NC
DQPa
D
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
E
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
F
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
G
NC
DQb
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
NC
DQa
H
NC
Vss
NC
Vdd
Vss
Vss
Vss
Vdd
NC
NC
ZZ
J
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
K
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
L
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
M
DQb
NC
Vddq
Vdd
Vss
Vss
Vss
Vdd
Vddq
DQa
NC
N
DQPb
NC
Vddq
Vss
NC
NC
NC
Vss
Vddq
NC
NC
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
Symbol
BWE
Byte Write Enable
A0, A1
ADV
OE
Output Enable
ZZ
Power Sleep Mode
ADSP
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
MODE
Burst Sequence Selection
ADSC
GW
Address Status Controller
Global Write Enable
JTAG Pins
CLK
CE, CE2, CE2
Synchronous Clock
Synchronous Chip Select
BWx (x=a,b)
Synchronous Byte Write
Controls
TCK, TDO
TMS, TDI
NC
DQx
DQPx
Vdd
Vddq
Vss
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
Pin Name
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply 3.3V/2.5V
Ground
7
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PIN CONFIGURATION
DQPc
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin QFP (256K x 36)
(2 Chip-Enable option)
(3 Chip-Enable option)
PIN DESCRIPTIONS
A0, A1
A
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
8
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Parity Data Input/Output
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
Vdd
3.3V/2.5V Power Supply
Vddq
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
Vss
ZZ
Synchronous Clock
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PIN CONFIGURATION
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin QFP (256K x 32)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
(3 Chip-Enable option)
PIN DESCRIPTIONS
A0, A1
A
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
DQa-DQd
Synchronous Data Input/Output
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
Vdd
3.3V/2.5V Power Supply
Vddq
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
Vss
ZZ
CE, CE2, CE2 Synchronous Chip Enable
CLK
Synchronous Clock
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
9
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PIN CONFIGURATION
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
A
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin QFP (512K x 18)
(3 Chip-Enable Option)
(2 Chip-Enable Option)
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQb
Synchronous Data Input/Output
10
DQPa-DQPb
Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
GW
MODE
Synchronous Global Write Enable
Burst Sequence Mode Selection
OE
Vdd
Vddq
Output Enable
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
Vss
ZZ
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TRUTH TABLE(1-8)
OPERATION
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Deselect Cycle, Power-Down
Snooze Mode, Power-Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
ADDRESS
CE CE2 CE2ZZADSP ADSC ADV
None
H
X
X
L
X
L
X
None
L
X
L
L
L
X
X
None
L
H
X
L
L
X
X
None
L
X
L
L
H
L
X
None
L
H
X
L
H
L
X
None
X
X
X
H
X
X
X
External
L
L
H
L
L
X
X
External
L
L
H
L
L
X
X
External
L
L
H
L
H
L
X
External
L
L
H
L
H
L
X
External
L
L
H
L
H
L
X
Next
X
X
X
L
H
H
L
Next
X
X
X
L
H
H
L
H
X
X
L
X
H
L
Next
H
X
X
L
X
H
L
Next
X
X
X
L
H
H
L
Next
H
X
X
L
X
H
L
Next
X
X
L
H
H
H
Current
X
X
X
L
H
H
H
Current
X
X
X
L
X
H
H
Current
H
X
X
L
X
H
H
Current
H
X
X
L
H
H
H
Current
X
X
X
L
X
H
H
Current
H
WRITE OECLK DQ
X
X
L-H
High-Z
X
X
L-H
High-Z
X
X
L-H
High-Z
X
X
L-H
High-Z
X
X
L-H
High-Z
X
X
X
High-Z
X
L
L-H
Q
X
H
L-H
High-Z
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
High-Z
H
L
L-H
Q
H
H
L-H
High-Z
H
L
L-H
Q
H
H
L-H
High-Z
L
X
L-H
D
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
High-Z
H
L
L-H
Q
H
H
L-H
High-Z
L
X
L-H
D
L
X
L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function
GW BWEBWaBWbBWcBWd
Read
HHXXXX
Read
HLHHHH
Write Byte 1
H
L
L
H
H
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
11
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = Vss)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
SymbolParameter
Tstg
Storage Temperature
Pd
Power Dissipation
Iout
Output Current (per I/O)
Vin, Vout Voltage Relative to Vss for I/O Pins
Vin
Voltage Relative to Vss for for Address and Control Inputs
Vdd
Voltage on Vdd Supply Relative to Vss
Value
Unit
–55 to +150
°C
1.6
W
100
mA
–0.5 to Vddq + 0.5 V
–0.5 to Vdd + 0.5
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
12
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
OPERATING RANGE (IS61LPSXXXXX)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
Vdd
3.3V + 5%
Vddq
3.3V / 2.5V + 5%
–40°C to +85°C
3.3V + 5%
3.3V / 2.5V + 5%
Ambient Temperature
0°C to +70°C
Vdd
2.5V + 5%
Vddq
2.5V + 5%
–40°C to +85°C
2.5V + 5%
2.5V + 5%
Vdd
3.3V + 5%
Vddq
3.3V / 2.5V + 5%
OPERATING RANGE (IS61VPSXXXXX)
Range
Commercial
Industrial
OPERATING RANGE (IS64LPSXXXXX)
Range
Automotive
Ambient Temperature
–40°C to +125°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Voh
Output HIGH Voltage
Test Conditions
Ioh = –4.0 mA (3.3V)
Ioh = –1.0 mA (2.5V)
Iol = 8.0 mA (3.3V)
Iol = 1.0 mA (2.5V)
Vol
Output LOW Voltage
Vih
Vil
Ili
Ilo
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current Vss ≤ Vin ≤ Vdd(1)
Output Leakage Current Vss ≤ Vout ≤ Vddq,
OE = Vih
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
3.3V
Min.
Max.
2.4
—
—
0.4
2.0
-0.3
-5
-5
Vdd + 0.3
0.8
5
5
2.5V
Min.
Max.
2.0
—
—
0.4
1.7 Vdd + 0.3
-0.3
0.7
-5
5
-5
5
Unit
V
V
V
V
µA
µA
13
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Icc
AC Operating
Supply Current
Isb
Standby Current
TTL Input
Isbi
Standby Current
CMOS Input
Test Conditions
Device Selected, OE = Vih, ZZ ≤ Vil,
All Inputs ≤ 0.2V or
≥ Vdd – 0.2V,
Cycle Time ≥ tkc min.
Device Deselected, Vdd = Max.,
All Inputs ≤ Vil or ≥ Vih,
ZZ ≤ Vil, f = Max.
Device Deselected,
Vdd = Max.,
Vin ≤ Vss + 0.2V or
≥Vdd – 0.2V
f=0
-250
-200
-166
MAX MAXMAX
Temp. range x18
x36
x18
x36
x18
x36
Com.
275 275
250 250
225 225
Ind.
300 300
275 275
250 250
Auto.
300 300
Unit
mA
Com.
Ind.
Auto.
150 150
150 150
150 150
150 150
150 150
150 150
200 200
mA
Com.
Ind.
Auto.
100 100
105 105
100 100
105 105
100100
105 105
130 130
mA
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤
Vss + 0.2V or ≥ Vdd – 0.2V.
14
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Refe rence Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
Output
50Ω
1.5V
Figure 1
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
OUTPUT
5 pF
Including
jig and
scope
351 Ω
Figure 2
15
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
2.5V
ZO = 50Ω
Output
50Ω
1.25V
Figure 3
16
OUTPUT
5 pF
Including
jig and
scope
1,538 Ω
Figure 4
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
fmax
tkc
tkh
tkl
tkq
tkqx(2)
tkqlz(2,3)
tkqhz(2,3)
toeq
toelz(2,3)
toehz(2,3)
Parameter
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
tas
tws
tces
tavs
Output Disable to Output High-Z
Address Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Status SetupTime
tds
tah
twh
tceh
tavh
tSH
DataSetupTime
Address Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
tdh
tpds
tpus
-250-200-166
Min.Max.
Min.Max.
Min. Max.
—
250
—
200
—
166
4.0
—
5
—
6
—
1.7
—
2
—
2.4
—
1.7
—
2
—
2.3
—
—
2.6
—
3.1
—
3.8
0.8
—
1.5
—
1.5
—
0.8
—
1
—
1.5
—
—
2.6
—
3.0
3.5
—
—
2.6
—
3.1
3.5
—
0
—
0
—
0
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
1.2
1.2
1.2
1.2
1.2
2.6
—
—
—
—
—
—
1.4
1.4
1.4
1.4
1.4
3.0
—
—
—
—
—
3.5
1.7
1.7
1.7
1.7
1.7
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Address Status HoldTime
1.2
0.3
0.3
0.3
0.3
0.3
—
—
—
—
—
—
1.4
0.4
0.4
0.4
0.4
0.4
—
—
—
—
—
—
1.7
0.7
0.7
0.7
0.7
0.7
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
DataHoldTime
ZZ High to Power Down
ZZ Low to Power Down
0.3
—
—
—
2
2
0.4
—
—
—
2
2
0.7
—
—
—
2
2
ns
cyc
cyc
Note:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
17
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
G
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate read
ADSC
tSS
tSH
tAVH
tAVS
Suspend Burst
ADV
tAS
Address
tAH
RD1
RD3
RD2
tWS
tWH
tWS
tWH
GW
BWE
BWx
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
tOEHZ
tOEQ
OE
tKQX
tOELZ
DATAOUT
High-Z
1a
2a
2b
2c
2d
tKQLZ
tKQHZ
tKQ
DATAIN
High-Z
Pipelined Read
Single Read
18
Burst Read
Unselected
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
ADSC initiate Write
tSH
ADSC
ADV must be inactive for ADSP Write tAVS
tAVH
ADV
tAS
Address
tAH
WR1
WR3
WR2
tWS
tWH
tWS
tWH
tWS
tWH
GW
BWE
WR1
BWx
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
tDH
1a
Single Write
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
BW4-BW1 only are applied to first cycle of WR2
2a
2b
2c
2d
Burst Write
3a
Write
Unselected
19
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Isb2
Current during SNOOZE MODE
tpds
tpus
tzzi
trzzi
Conditions
ZZ ≥ Vih
Temperature
Range
Com.
Ind.
Auto.
Min. Max.
—
—
—
—
2
—
0
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
50
60
75
2
—
2
—
Unit
mA
cycle
cycle
cycle
ns
SNOOZE MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
20
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Access Port (TAP) - Test Clock
The IS61LPS/VPSxxxxxx products have a serial boundary
scan Test Access Port (TAP) in the BGA package only.
(The QFP package not available.) This port operates in
accordance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
Disabling the JTAG Feature
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to Vdd through a pull-up resistor.
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
Test Mode Select (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The pin
is internally pulled up, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB)
on any register.
tap controller block diagram
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
31 30 29
. . .
Selection Circuitry
2
1
0
2
1
0
TDO
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
21
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB)
of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (Vdd) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass reg-
ister is set LOW (Vss) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Register
Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
(x18)
3
1
32
75
Bit Size
(x36)
3
1
32
75
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
22
Description
Reserved for version number.
Defines depth of SRAM. 256K or 512K
Defines width of the SRAM. x36 or x18
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
256K x 36
xxxx
00111
00100
xxxxx
00011010101
1
512K x 18
xxxx
01000
00011
xxxxx
00011010101
1
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP Instruction Set
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM
is not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; instead it performs a capture of the Inputs and
Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted from
the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant. When the
SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock
runs more than an order of magnitude faster. Because of
the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition (metastable state).The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up
plus hold times (tcs and tch). To insure that the SRAM clock
input is captured correctly, designs need a way to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction.
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK captured
in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When an
EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST
places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
Bypass
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state,
the bypass register is placed between the TDI and TDO
pins. The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
SAMPLE-Z
Reserved
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also places
all SRAM outputs into a High-Z state.
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
23
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Instruction Codes
Code InstructionDescription
000
EXTEST
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
010
SAMPLE-Z
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
011
RESERVED
Do Not Use: This instruction is reserved for future use.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101
RESERVED
Do Not Use: This instruction is reserved for future use.
110
111
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
Run Test/Idle
1
Select DR
0
0
1
1
1
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
Exit1 IR
0
Pause DR
0
1
0
1
24
Exit2 DR
1
Update DR
0
Capture IR
0
Shift IR
1
0
Pause IR
1
0
1
1
0
1
0
Exit2 IR
1
Update IR
0
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
Voh1
Voh2
Vol1
Vol2
Vih
Vil
Ix
Notes:
Parameter
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Test Conditions
Ioh = –2.0 mA
Ioh = –100 µA
Iol = 2.0 mA
Iol = 100 µA
Vss ≤ V I ≤ Vddq
Min.
1.7
2.1
—
—
1.7
–0.3
–10
Max.
—
—
0.7
0.2
Vdd +0.3
0.7
10
Units
V
V
V
V
V
V
µA
1. All Voltage referenced to Ground.
2. Overshoot: Vih (AC) ≤ Vdd +1.5V for t ≤ ttcyc/2,
Undershoot: Vil (AC) ≥ -1.5V for t ≤ ttcyc/2,
Power-up: Vih < 2.6V and Vdd < 2.4V and Vddq < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (Over Operating Range)
SymbolParameter Min.
Max.
Unit
ttcyc
TCK Clock cycle time
100
—
ns
ftf
TCK Clock frequency
—
10
MHz
tth
TCK Clock HIGH
40
—
ns
ttl
TCK Clock LOW
40
—
ns
ttmss
TMS setup to TCK Clock Rise
10
—
ns
ttdis
TDI setup to TCK Clock Rise
10
—
ns
tcs
Capture setup to TCK Rise10
—
ns
ttmsh
TMS hold after TCK Clock Rise 10
—
ns
ttdih
TDI Hold after Clock Rise
10
—
ns
tch
Capture hold after Clock Rise
10
—
ns
ttdov
TCK LOW to TDO valid
—
20
ns
ttdox
TCK LOW to TDO invalid
0
—
ns
Notes:
1. Both tcs and tch refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns.
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
25
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TAP AC TEST CONDITIONS (2.5V/3.3V)
TAP Output Load Equivalent
Input pulse levels
0 to 2.5V/0 to 3.0V
Input rise and fall times
1ns
Input timing reference levels
1.25V/1.5V
Output reference levels
1.25V/1.5V
Test load termination supply voltage
1.25V/1.5V
Vtrig
1.25V/1.5V
50Ω
Vtrig
TDO
Z0 = 50Ω
20 pF
GND
Tap timing
1
2
tTHTH
3
4
5
6
tTLTH
TCK
tTHTL
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLOV
TDO
tTLOX
DON'T CARE
UNDEFINED
26
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA Boundary Scan Order (256K X 36)
SignalBump
Bit # Name ID
1
A
2R
2
A
3T
3
A
4T
4
A
5T
5
A
6R
6
A
3B
7
A
5B
8
DQa
6P
9
DQa
7N
10
DQa
6M
11
DQa
7L
12
DQa
6K
13
DQa
7P
14
DQa
6N
15
DQa
6L
16
DQa
7K
17
ZZ
7T
18
DQb
6H
SignalBump SignalBump
Bit # Name ID
Bit # Name ID
19
DQb
7G
37
BWa
5L
20
DQb
6F
38
BWb
5G
21
DQb
7E
39
BWc
3G
22
DQb
7D
40
BWd
3L
23
DQb
7H
41
CE2
2B
24
DQb
6G
42
CE
4E
25
DQb
6E
43
A
3A
26
DQb
6D
44
A
2A
27
A
6A
45
DQc
2D
28
A
5A
46
DQc
1E
29
ADV
4G
47
DQc
2F
30 ADSP 4A
48
DQc
1G
31 ADSC 4B
49
DQc
2H
32
OE
4F
50
DQc
1D
33
BWE 4M
51
DQc
2E
34
GW
4H
52
DQc
2G
35
CLK
4K
53
DQc
1H
36
A
6B
54
NC
5R
SignalBump
Bit # Name ID
55
DQd
2K
56
DQd
1L
57
DQd
2M
58
DQd
1N
59
DQd
1P
60
DQd
1K
61
DQd
2L
62
DQd
2N
63
DQd
2P
64 MODE 3R
65
A
2C
66
A
3C
67
A
5C
68
A
6C
69
A1
4N
70
A0
4P
119 BGA Boundary Scan Order (512k X 18)
SignalBump
Bit # Name ID
1
A
2R
2
A
2T
3
A
3T
4
A
5T
5
A
6R
6
A
3B
7
A
5B
8
DQa
7P
9
DQa
6N
10
DQa
6L
11
DQa
7K
12
ZZ
7T
13
DQa
6H
SignalBump SignalBump
Bit # Name ID
Bit # Name ID
14
DQa
7G
27
CLK
4K
15
DQa
6F
28
A
6B
16
DQa
7E
29
BWa
5L
17
DQa
6D
30
BWb
3G
18
A
6T
31
CE2
2B
19
A
6A
32
CE
4E
20
A
5A
33
A
3A
21
ADV
4G
34
A
2A
22 ADSP 4A
35
DQb
1D
23 ADSC 4B
36
DQb
2E
24
OE
4F
37
DQb
2G
25
BWE 4M
38
DQb
1H
26
GW
4H
39
NC
5R
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
SignalBump
Bit # Name ID
40
DQb
2K
41
DQb
1L
42
DQb
2M
43
DQb
1N
44
DQb
2P
45 MODE 3R
46
A
2C
47
A
3C
48
A
5C
49
A
6C
50
A1
4N
51
A0
4P
27
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BGA Boundary Scan Order (x 36)
SignalBump
Bit # Name ID
1
MODE 1R
2
NC
6N
3
A
11P
4
A
8P
5
A
8R
6
A
9R
7
A
9P
8
A
10P
9
A
10R
10
A
11R
11
ZZ
11H
12
DQa 11N
13
DQa 11M
14
DQa 11L
15
DQa 11K
16
DQa 11J
17
DQa 10M
18
DQa 10L
19
DQa 10K
20
DQa 10J
28
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SignalBump
Name
ID
DQb
11G
DQb
11F
DQb
11E
DQb
11D
DQb
10G
DQb
10F
DQb
10E
DQb
10D
DQb
11C
NC
11A
A
10A
A
10B
ADV
9A
ADSP
9B
ADSC
8A
OE
8B
BWE
7A
GW
7B
CLK
6B
NC
11B
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Signal Bump
Name
ID
NC
1A
CE2
6A
BWa
5B
BWb
5A
BWc
4A
BWd
4B
CE2
3B
CE
3A
A
2A
A
2B
NC
1B
DQc
1C
DQc
1D
DQc
1E
DQc
1F
DQc
1G
DQc
2D
DQc
2E
DQc
2F
DQc
2G
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SignalBump
Name
ID
DQd
1J
DQd
1K
DQd
1L
DQd
1M
DQd
2J
DQd
2K
DQd
2L
DQd
2M
DQd
1N
A
3P
A
3R
A
4R
A
4P
A1
6P
A0
6R
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 BGA Boundary Scan Order (x 18)
SignalBump
Bit # Name ID
1
MODE 1R
2
NC
6N
3
A
11P
4
A
8P
5
A
8R
6
A
9R
7
A
9P
8
A
10P
9
A
10R
10
A
11R
11
ZZ
11H
12
NC
11N
13
NC
11M
14
NC
11L
15
NC
11K
16
NC
11J
17
DQa 10M
18
DQa 10L
19
DQa 10K
20
DQa 10J
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Integrated Silicon Solution, Inc.
Rev. N
05/25/25
SignalBump
Name
ID
DQa
11G
DQa
11F
DQa
11E
DQa
11D
DQa
11C
NC
10F
NC
10E
NC
10D
NC
10G
A
11A
A
10A
A
10B
ADV
9A
ADSP
9B
ADSC
8A
OE
8B
BWE
7A
GW
7B
CLK
6B
NC
11B
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Signal Bump
Name
ID
NC
1A
CE2
6A
BWa
5B
NC
5A
BWb
4A
NC
4B
CE2
3B
CE
3A
A
2A
A
2B
NC
1B
NC
1C
NC
1D
NC
1E
NC
1F
NC
1G
DQb
2D
DQb
2E
DQb
2F
DQb
2G
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SignalBump
Name
ID
DQb
1J
DQb
1K
DQb
1L
DQb
1M
DQb
1N
NC
2K
NC
2L
NC
2M
NC
2J
A
3P
A
3R
A
4R
A
4P
A1
6P
A0
6R
29
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Range: 0°C to +70°C
Configuration
Frequency
Order Part Number
Package(1)
250
IS61LPS25636A-250TQ
100 QFP, 3CE
IS61LPS25636A-250B2
119 BGA
IS61LPS25636A-250B3
165 BGA
IS61LPS25636A-200TQ
100 QFP, 3CE
IS61LPS25636A-200B2
119 BGA
IS61LPS25636A-200B3
165 BGA
IS61LPS25636A-166TQ
100 QFP, 3CE
IS61LPS25636A-166TQL
100 QFP, 3CE, Lead-free
IS61LPS51218A-250TQ
100 QFP, 3CE
IS61LPS51218A-250B2
119 BGA
IS61LPS51218A-250B3
165 BGA
IS61LPS51218A-200TQ
100 QFP, 3CE
IS61LPS51218A-200B2
119 BGA
IS61LPS51218A-200B3
165 BGA
256Kx36
200
166
512Kx18
250
200
30
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Industrial Range: -40°C to +85°C
Configuration
Frequency
OrderPartNumber
Package(1)
200
IS61LPS25632A-200TQLI
100 QFP,3CE,Lead-free
250
IS61LPS25636A-250TQI
100 QFP,3CE
IS61LPS25636A-250TQLI
100 QFP,3CE,Lead-free
IS61LPS25636A-250B2I
119 BGA
IS61LPS25636A-250B3I
165 BGA
IS61LPS25636A-200TQI
100 QFP,3CE
IS61LPS25636A-200TQ2LI
100 QFP,2CE,Lead-free
IS61LPS25636A-200TQ2I
100 QFP,2CE
IS61LPS25636A-200TQLI
100 QFP,3CE,Lead-free
IS61LPS25636A-200B2I
119 BGA
IS61LPS25636A-200B2LI
119 BGA,Lead-free
IS61LPS25636A-200B3I
165 BGA
166
IS61LPS25636A-200B3LI
165 BGA,Lead-free
250
IS61LPS51218A-250TQI
100 QFP,3CE
IS61LPS51218A-250B2I
119 BGA
IS61LPS51218A-250B3I
165 BGA
IS61LPS51218A-200TQI
100 QFP,3CE
IS61LPS51218A-200TQ2LI
100 QFP,2CE,Lead-free
IS61LPS51218A-200TQ2I
100 QFP,2CE
IS61LPS51218A-200TQLI
100 QFP,3CE,Lead-free
IS61LPS51218A-200B2I
119 BGA
IS61LPS51218A-200B3I
165 BGA
256Kx32
256Kx36
200
512Kx18
200
Note:
1. For 100 QFP, 2CE option contact SRAM Marketing at [email protected]
Automotive Range: -40°C to +125°C
Configuration
256Kx36
Frequency
166
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
Order Part Number
Package
IS64LPS25636A-166TQLA3
100 QFP, 3CE
31
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0°C to +70°C
Configuration
256Kx36
Frequency
250
200
Order Part Number
Package(1)
IS61VPS25636A-250TQ
IS61VPS25636A-250B2
IS61VPS25636A-250B3
IS61VPS25636A-200TQ
IS61VPS25636A-200B2
IS61VPS25636A-200B3
100 QFP, 3CE
119 BGA
165 BGA
100 QFP, 3CE
119 BGA
165 BGA
IS61VPS51218A-250TQ
IS61VPS51218A-250B2
IS61VPS51218A-250B3
IS61VPS51218A-200TQ
IS61VPS51218A-200B2
IS61VPS51218A-200B3
100 QFP, 3CE
119 BGA
165 BGA
100 QFP, 3CE
119 BGA
165 BGA
512Kx18
250
200
Industrial Range: -40°C to +85°C
Configuration
256Kx36
Frequency
250
200
Order Part Number
Package(1)
IS61VPS25636A-250TQI
IS61VPS25636A-250B2I
IS61VPS25636A-250B3I
IS61VPS25636A-200TQI
IS61VPS25636A-200TQ2I
IS61VPS25636A-200TQLI
IS61VPS25636A-200B2I
IS61VPS25636A-200B3I
100 QFP, 3CE
119 BGA
165 BGA
100 QFP, 3CE 100 QFP, 2CE 100 QFP, 3CE, Lead-free
119 BGA
165 BGA
IS61VPS51218A-250TQI
IS61VPS51218A-250B2I
IS61VPS51218A-250B3I
IS61VPS51218A-200TQI
IS61VPS51218A-200TQ2I
IS61VPS51218A-200B2I
IS61VPS51218A-200B3I
100 QFP, 3CE
119 BGA
165 BGA
100 QFP, 3CE
100 QFP, 2CE
119 BGA
165 BGA
512Kx18
250
200
Note:
1. For 100 QFP, 2CE option contact SRAM Marketing at [email protected]
32
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
33
34
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MS-028
NOTE :
Package Outline
10/02/2008
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
Integrated Silicon Solution, Inc.
Rev. N
05/25/2015
Package Outline
1. CONTROLLING DIMENSION : MM .
NOTE :
08/28/2008
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
35