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IS61DDB41M18A
IS61DDB451236A
1Mx18, 512Kx36
18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
FEATURES
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512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid
window.
Common I/O read and write ports.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and
write input ports.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two input clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5V to1.8V VDDQ,
used with 0.75V to 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
OCTOBER 2014
DESCRIPTION
The 18Mb IS61DDB451236A and IS61DDB41M18A are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have a common I/O
bus. The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed. Refer to
the Timing Reference Diagram for Truth Table for a
description of the basic operations of these DDR-II (Burst of
4) CIO SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate.
The following are registered internally on the rising edge of
the K clock:

Read/write address

Read enable

Write enable

Byte writes for burst addresses first and third

Data-in for burst addresses first and third
The following are registered on the rising edge of the K#
clock:

Byte writes for burst addresses second and fourth

Data-in for burst addresses second and fourth
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the
second and third rising edges of the C# clock (starting on and
half cycles later after read command). The data-outs from the
second and fourth bursts are updated with the third and
fourth rising edges of the C clock. The K and K# clocks are
used to time the data-outs whenever the C and C# clocks are
tied high. Two full clock cycles are required to complete a
read operation.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
10/02/2014
1
IS61DDB41M18A
IS61DDB451236A
Package Ballout and description
x36 FBGA Ball Configuration (Top View)
A
1
CQ#
2
1
NC/SA
3
1
NC/SA
4
R/W#
5
BW 2#
6
K#
7
BW 1#
8
LD#
9
SA
10
1
NC/SA
11
CQ
B
NC
DQ27
DQ18
SA
BW 3#
K
BW 0#
SA
NC
NC
DQ8
C
NC
NC
DQ28
VSS
SA
SA0
SA1
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
Doff#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
P
R
NC
NC
TDO
DQ35
NC
TCK
DQ25
DQ26
SA
VSS
SA
SA
SA
SA
SA
SA
C
C#
SA
SA
SA
VSS
SA
SA
NC
NC
SA
NC
DQ9
TMS
DQ10
DQ0
TDI
8
LD#
9
SA
10
1
NC/SA
11
CQ
Notes:
1. The following balls are reserved for higher densities: 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.
x18 FBGA Ball Configuration (Top View)
A
1
CQ#
2
1
NC/SA
3
SA
4
R/W#
5
BW 1#
B
NC
DQ9
NC
SA
NC/SA
C
NC
NC
NC
VSS
SA
D
NC
NC
DQ10
VSS
VSS
VSS
E
NC
NC
DQ11
VDDQ
VSS
VSS
1
6
K#
7
1
NC/SA
K
BW 0#
SA
NC
NC
DQ8
SA0
SA1
VSS
NC
DQ7
NC
VSS
VSS
NC
NC
NC
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
P
R
NC
NC
TDO
NC
NC
TCK
DQ16
DQ17
SA
VSS
SA
SA
SA
SA
SA
SA
C
C#
SA
SA
SA
VSS
SA
SA
NC
NC
SA
NC
NC
TMS
NC
DQ0
TDI
Notes:
1.
The following balls are reserved for higher densities: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb and 5B for 288Mb.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
10/02/2014
2
IS61DDB41M18A
IS61DDB451236A
Ball Description
Symbol
Type
K, K#
Input
C, C#
Input
CQ, CQ#
Output
Doff#
Input
SA
Input
DQ0 - DQn
Bidir
R/W#
Input
LD#
Input
BW x#
Input
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
These balls cannot remain VREF level.
Input clock for output data. C and C# are used to clock out the READ data. They can be used
together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals are free running
clocks and do not stop when Q tri-states.
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Data input and output signals. Input data must meet setup and hold times around the rising edges of
K and K# during WRITE operations. These pins drive out the requested data when the read
operation is active. Valid output data is synchronized to the respective C and C#, or to the
respective K and K# if C and /C are tied to high. When read access is deselected, DQ0 - DQn are
automatically tri-stated.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.
The x36 device uses DQ0~DQ35.
Synchronous Read or Write input. When LD# is low, this input designates the access type (read
when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times
around edge of K.
Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition
includes address and read/write direction.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
VDD
Input
reference
Power
VDDQ
Power
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
VSS
Ground
Ground of the device
ZQ
Input
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. DQ and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
TMS, TDI,
TCK
Input
IEEE1149.1 input pins for JTAG.
TDO
Output
IEEE1149.1 output pins for JTAG.
NC
N/A
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
VREF
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Rev. A
10/02/2014
3
IS61DDB41M18A
IS61DDB451236A
SRAM Features description
Block Diagram
36(18)
Data
RegisterBurst4
36x4 (18x4)
36x4 (18x4)
Write
Driver
LD#
R/W#
4 (2)
Control
Logic
512K x 36
(1M x 18)
Memory Array
36x4
(18x4)
144
(72)
Output
Reg
36
(18)
Input/Output Driver
SA0,SA1
19 (20)
Sense Amplifiers
2
Add Reg &
Burst
Control
Output Select
17 (18)
Address Decoder
Addresses :
SA
36 (18)
DQ(Data-out
&Data-In)
CQ, CQ#
(Echo Clocks)
BWx#
K
K#
C
C#
Clock
Generator
Select Output Control
/Doff
Note: Numerical values in parentheses refer to the x18 device configuration.
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R/W# in active high
state at the rising edge of the K clock. R/W# can be activated every other cycle because two full cycles are required to
complete the burst-of-four read in DDR mode. A second set of clocks, C and C#, are used to control the timing to the
outputs. A set of free-running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs.
The echo clocks can be used as data capture clocks by the receiver device.
When the C and C# clocks are connected high, the K and K# clocks assume the function of those clocks. In this case,
the data corresponding to the first address is clocked one and half cycles later by the rising edge of the K# clock. The
data corresponding to the second burst is clocked two cycles later by the following rising edge of the K clock. The third
data-out is clocked by the subsequent rising edge of the K# clock, and the fourth data-out is clocked by the
subsequent rising edge of the K clock.
Whenever LD# is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD# is high)
does not terminate the previous read. The output drivers disable automatically to a high state.
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IS61DDB451236A
Write Operations
Write operations can also be initiated at every other rising edge of the K clock whenever R/W# is low. The write
address is also registered at that time. When the address needs to change, LD# needs to be low simultaneously to be
registered by the rising edge of K. Again, the write always occurs in bursts of four.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#. The third data-out is clocked by the subsequent rising
edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of the K# clock.
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array
on the third write cycle. A read cycle to the last two write address produces data from the write buffers. The SRAM
maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written (see
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).
Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ should not be
connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
values. The final impedance value is achieved within 1024clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock mode to
minimize power and requires only 1024 cycles to restart. No clocks can be issued until V DD reaches its allowable
operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up
and must never change. Under this condition, K and K# control the output timings. Either clock pair must have both
polarities switching and must never connect to VREF, as they are not differential clocks.
Delay Locked Loop (DLL)
Delay Lock Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to enhance
the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match the clock
frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy
QUAD mode.
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Rev. A
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IS61DDB41M18A
IS61DDB451236A
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
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Rev. A
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IS61DDB41M18A
IS61DDB451236A
Power-Up and Power-Down Sequences
1)
2)
The recommendation of voltage apply sequence is : VDD → VDDQ →VREF → VIN
Notes:
VDDQ can be applied concurrently with VDD.
VREF can be applied concurrently with VDDQ.
After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKClock cycle period, device initializes internal logics and locks DLL. Depending on /Doff status, locking DLL will be
skipped. The following timing pictures are possible examples of power up sequence.
Sequence1. /Doff is fixed low
After tKC-lock cycle of stable clock, device is ready for normal operation.
Power On stage
Unstable Clock Period
Stable Clock period
Read to use
K
K#
VDD
>tKC-lock for device initialization
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
Sequence2. /Doff is controlled and goes high after clock being stable.
Power On stage
Unstable Clock Period
Stable Clock period
Read to use
K
K#
Doff#
>tKC-lock for device initialization
VDD
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
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IS61DDB41M18A
IS61DDB451236A
Sequence3. /Doff is controlled but goes high before clock being stable.
Because DLL has a risk to be locked with the unstable clock, DLL needs to be reset and locked with the stable input.
a) K-stop to reset. If K or K# stays at VIH or VIL for more than 30nS, DLL will be reset and ready to re-lock. In tKCLock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that.
Power On stage
Unstable Clock Period
K-Stop
Stable Clock period
Read to use
K
K#
Doff#
>30nS
>tKC-lock for device initialization
VDD
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
a) /Doff Low to reset. If /Doff toggled low to high, DLL will be reset and ready to re-lock. In tKC-Lock period, DLL will
be locked with a new stable value. Device can be ready for normal operation after that.
Power On stage
Unstable Clock Period
Doff reset DLL
Stable Clock period
Read to use
K
K#
Doff#
>tDoffLowToReset
>tKC-lock for device
initialization
VDD
VDDQ
VREF
VIN
Note) Applying DLL reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off.
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
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IS61DDB41M18A
IS61DDB451236A
Application Example
The following figure depicts an implementation of four 2M x 18 DDR-II SRAMs with common I/Os. In this application
example, the second pair of C and C# clocks is delayed such that the return data meets the data setup and hold times
at the bus master.
Vt
R
Address
SA
Read&Write Control
R/W#
New Address Control
LD#
BWx# SRAM #1
Byte Write Control
Source CLK
K/K#
Return CLK
R
Memory
Controller
Vt
Vt
C/C#
R
Data-In&Data Out
SRAM #1 CQ Input
DQ
CQ/CQ#
ZQ
RQ = 250Ω
SRAM #4 CQ Input
SA
R = 50Ω
Vt = V REF
R/W#
LD#
BWx# SRAM #4
K/K#
C/C#
DQ
CQ/CQ#
ZQ
RQ = 250Ω
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IS61DDB41M18A
IS61DDB451236A
State Diagram
Power-Up
/LOAD
NOP
Load
/LOAD
D count = 2
Load New Read Address
D count = 0
Read
Load
Write
DDR-II Read
D count =
D count +1
Read
D count = 1
/LOAD
D count = 2
Load
DDR-II Write
D count =
D count +1
Write
D count = 1
Always
Increment Read
Address
Always
Increment Write
Address
Notes:
1.
Internal burst counter is fixed as four-bit linear; that is when first address is A0+0, next internal burst addresses are A0+1, A0+2, and A0+3
2.
Read refers to read active status with R/W# = High.
3.
Write refers to write active status with R/W# = LOW.
4.
Load refers to read new address active status with LD# = low.
5.
Load is read new address inactive status with LD = high.
Linear Burst Sequence Table
Case1
Burst Sequence
Case2
Case3
Case4
SA1
SA0
SA1
SA0
SA1
SA0
SA1
SA0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address
1
1
0
0
0
1
1
0
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IS61DDB41M18A
IS61DDB451236A
Timing Reference Diagram for Truth Table
The Timing Reference Diagram for Truth Table is helpful in understanding the Clock and Write Truth Tables, as it
shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued
at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”.
Cycle
t
t+1
t+2
t+3
t+4
t+5
K# Clock
K Clock
LD#
R/W#
BWx#
A
Address
B
tCHQV
DataIn/Out(DQ)
tCHQX
QA
QA+1
QA+2
QA+3
DB
DB+1
DB+2
DB+3
C# Clock
C Clock
CQ
CQ#
Clock Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Clock
Controls
Data Out / Data In
Mode
K
LD#
R/W#
DB
DB+1
DB+2
DB+3
Stop Clock
Stop
X
X
Previous State
Previous State
Previous State
Previous State
No
Operation
(NOP)
L→H
H
X
High-Z
High-Z
High-Z
High-Z
Read A
L→H
L
H
DOUT at C# (t+1.5) ↑
DOUT at C (t+2.0) ↑
DOUT at C# (t+2.5) ↑
DOUT at C (t+3.0) ↑
Write B
L→H
L
L
DIN at K (t+4.0) ↑
DIN at K# (t+4.5) ↑
DIN at K (t+5.0) ↑
DIN at K# (t+5.5) ↑
Notes:
1. X = “don’t care”; H = logic “1”; L = logic “0”.
2. A read operation is started when control signal R/W# is active high.
3. A write operation is started when control signal R/W# is active low.
4. Before entering into stop clock, all pending read and write commands must be completed.
5. For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with
respect to switching clocks K,K#,C, and C#.
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IS61DDB41M18A
IS61DDB451236A
x18 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t+1.0)
BW 0
BW 1
DB
Write Byte 0
L→H
L
H
D0-8 (t+4.0)
Write Byte 1
L→H
H
L
D9-17 (t+4.0)
Write All Bytes
L→H
L
L
D0-17 (t+4.0)
Abort Write
L→H
H
H
Don't Care
K (t+1.5)
K (t+2.0)
K (t+2.5)
DB+1
Write Byte 0
L→H
L
H
D0-8 (t+4.5)
Write Byte 1
L→H
H
L
D9-17 (t+4.5)
Write All Bytes
L→H
L
L
D0-17 (t+4.5)
Abort Write
L→H
H
H
Don't Care
DB+2
Write Byte 0
L→H
L
H
D0-8 (t+5.0)
Write Byte 1
L→H
H
L
D9-17 (t+5.0)
Write All Bytes
L→H
L
L
D0-17 (t+5.0)
Abort Write
L→H
H
H
Don't Care
DB+3
Write Byte 0
L→H
L
H
D0-8 (t+5.5)
Write Byte 1
L→H
H
L
D9-17 (t+5.5)
Write All Bytes
L→H
L
L
D0-17 (t+5.5)
Abort Write
L→H
H
H
Don't Care
Notes:
1. For all cases, R/W# needs to be active low during the rising edge of K occurring at time t.
2.
For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
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IS61DDB41M18A
IS61DDB451236A
x36 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t+1.0)
BW 0
BW 1
BW 2
BW 3
DB
Write Byte 0
L→H
L
H
H
H
D0-8 (t+4.0)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+4.0)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+4.0)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+4.0)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+4.0)
Abort Write
L→H
H
H
H
H
Don't Care
K (t+1.5)
K (t+2.0)
K (t+2.5)
DB+1
Write Byte 0
L→H
L
H
H
H
D0-8 (t+4.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+4.5)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+4.5)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+4.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+4.5)
Abort Write
L→H
H
H
H
H
Don't Care
DB+2
Write Byte 0
L→H
L
H
H
H
D0-8 (t+5.0)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+5.0)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+5.0)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+5.0)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+5.0)
Abort Write
L→H
Don't Care
DB+3
H
H
H
H
Write Byte 0
L→H
L
H
H
H
D0-8 (t+5.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+5.5)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+5.5)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+5.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+5.5)
Abort Write
L→H
H
H
H
H
Don't Care
Notes:
1. For all cases, R/W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
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IS61DDB41M18A
IS61DDB451236A
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
VDD
0.5
2.9
V
I/O Power Supply Voltage
VDDQ
0.5
2.9
V
DC Input Voltage
VIN
0.5
VDD+0.3
V
Data Out Voltage
VDOUT
0.5
2.6
V
Junction Temperature
TJ
-
110
°C
Storage Temperature
TSTG
55
+125
°C
Note:
Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Operating Temperature Range
Temperature Range
Symbol
Min
Max
Units
Commercial
TA
0
+70
°C
Industrial
TA
40
+85
°C
DC Electrical Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%)
Parameter
Symbol
Min
Max
Units
Notes
x36 Average Power Supply Operating Current
(IOUT=0, VIN=VIH or VIL )
IDD30
IDD33
IDD40

620
580
550
mA
1,2
x18 Average Power Supply Operating Current
(IOUT=0, VIN=VIH or VIL )
IDD30
IDD33
IDD40

570
530
500
mA
1,2
Power Supply Standby Current
(R=VIH, W=VIH. All other inputs=VIH or VIL, IIH=0)
ISB30
ISB33
ISB40

310
295
280
mA
1,2
ILI
2
+2
µA
3
ILO
2
+2
µA
Output “high” level voltage (IOH=100uA, Nominal ZQ)
VOH
VDDQ0.2
VDDQ
V
Output “low” level voltage (IOL= 100uA, Nominal ZQ)
VOL
VSS
VSS+0.2
V
Input leakage current
( 0 ≤VIN≤VDDQ for all input balls except VREF, ZQ, TCK,
TMS, TDI ball)
Output leakage current
(0 ≤VOUT ≤VDDQ for all output balls except TDO ball;
Output must be disabled.)
Notes:
1.
IOUT = chip output current.
2.
The numeric suffix indicates the part operating at speed, as indicated in AC Timing Characteristics table (that is, IDD25 indicates 2.5ns cycle
time).
3.
DOFF# Ball does not follow this spec, ILI = ±5uA
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IS61DDB41M18A
IS61DDB451236A
Recommended DC Operating Conditions
(Over the Operating Temperature Range)
Parameter
Symbol
Min
Typical
Max
Units
Notes
Supply Voltage
VDD
1.8–5%
1.8
1.8+5%
V
1
Output Driver Supply Voltage
VDDQ
1.4
1.5
VDD
V
1
Input High Voltage
VIH
VREF+0.1
-
VDDQ+0.2
V
1, 2
Input Low Voltage
VIL
–0.2
-
VREF –0.1
V
1, 3
VREF
0.68
0.75
0.95
V
1, 5
VIN-CLK
–0.2
-
VDDQ+0.2
V
1, 4
Input Reference Voltage
Clock Signal Voltage
Notes:
1.
All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.
2.
VIH(max) AC = See 0vershoot and Undershoot Timings.
3.
VIL(min) AC = See 0vershoot and Undershoot Timings.
4.
VIN-CLK specifies the maximum allowable DC excursions of each clock (K,K#,C and C#).
5.
Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
Overshoot and Undershoot Timings
20% Min Cycle Time
20% Min Cycle Time
VDDQ + 0.6V
GND
VDDQ
GND - 0.6V
VIH(max) AC Overshoot Timing
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IS61DDB41M18A
IS61DDB451236A
Typical AC Input Characteristics
Parameter
Symbol
Min
AC Input Logic HIGH
VIH (AC)
VREF+0.2
AC Input Logic LOW
VREF–0.2
VIL (AC)
Clock Input Logic HIGH
VIH-CLK (AC)
Clock Input Logic LOW
VIL-CLK (AC)
Max
VREF+0.2
VREF–0.2
Units
Notes
V
1, 2, 3, 4
V
1, 2, 3, 4
V
1, 2, 3
V
1, 2, 3
Notes:
1.
The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2.
Performance is a function of VIH and VIL levels to clock inputs.
3.
See the AC Input Definition diagram.
4.
See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past
VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.
AC Input Definition
K#
VREF
K
VRAIL
VIH(AC)
Setup Time
Hold Time
VREF
VIL(AC)
V-RAIL
PBGA Thermal Characteristics
Parameter
Symbol
13x15 BGA
15x17 BGA
Units
Thermal resistance (junction to ambient at airflow = 1m/s)
RθJA
19.6
18.0
°C/W
Thermal resistance (junction to pins)
RθJB
4.02
3.30
°C/W
Thermal resistance (junction to case)
RθJC
4.53
4.20
°C/W
Note: these parameters are guaranteed by design and tested by a sample basis only.
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IS61DDB41M18A
IS61DDB451236A
Pin Capacitance
Parameter
Symbol
Input or output capacitance except DQ pins
CIN ,CO
DQ capacitance (DQ0–DQx)
CDQ
Clocks Capacitance (K, K, C, C)
CCLK
Test Condition
°
Max
Units
5
pF
6
pF
4
pF
Note: these parameters are guaranteed by design and tested by a sample basis only.
Programmable Impedance Output Driver DC Electrical Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter
Symbol
Min
Max
Units
Notes
Output Logic HIGH Voltage
VOH
VDDQ /2 -0.12
VDDQ /2 + 0.12
V
1, 3
Output Logic LOW Voltage
VOL
VDDQ /2 -0.12
VDDQ /2 + 0.12
V
2, 3
Notes:
1.
 VDDQ 


2 
| IOH | 
 RQ 


 5 
2.
 VDDQ 


2 
| IOL | 
 RQ 


 5 
3.
Parameter Tested with RQ=250Ω and VDDQ=1.5V
AC Test Conditions
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter
Symbol
Conditions
Units
VDDQ
1.5/1.8
V
Input Logic HIGH Voltage
VIH
VREF+0.5
V
Input Logic LOW Voltage
VIL
VREF–0.5
V
Input Reference Voltage
VREF
0.75/0.9
V
Input Rise Time
TR
2.0
V/ns
Input Fall Time
TF
Output Drive Power Supply Voltage
2.0
V/ns
Output Timing Reference Level
VREF
V
Clock Reference Level
VREF
V
Output Load Conditions
Notes
1, 2
Notes:
1.
See AC Test Loading.
2.
Parameter Tested with RQ=250Ω and VDDQ=1.5V
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IS61DDB41M18A
IS61DDB451236A
AC TEST LOADING
(a) Unless otherwise noted, AC test loading assume this condition.
VREF
50Ω
50Ω
Output
Test Comparator
VREF
(b) tCHQZ and tCHQX1 are specified with 5pF load capacitance and measured when transition occurs ±100mV from
the steady state voltage.
VREF
50Ω
Output
5pF
Test Comparator
VREF ± 100mV
(c)TDO
VREF
50Ω
50Ω
Output
20pF
Test Comparator
VREF
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IS61DDB41M18A
IS61DDB451236A
AC Timing Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter
Symbol
30 (333MHz)
33 (300MHz)
40 (250MHz)
Min
Max
Min
Max
Min
Max
3.00
8.4
3.33
8.4
4.00
8.4
unit
notes
Clock
Clock Cycle Time (K, K#,C,C#)
tKHKH
Clock Phase Jitter (K, K#,C,C#)
tKC var
Clock High Time (K, K#,C,C#)
tKHKL
0.4
0.4
0.4
cycle
Clock Low Time (K, K#,C,C#)
tKLKH
0.4
0.4
0.4
cycle
Clock to Clock (KH→ K#H, CH→ C#H)
tKHK#H
1.35
1.50
1.80
ns
Clock to Data Clock (K > C, K# > C#)
tKHCH
0
tKC lock
1024
1024
tDoffLowToReset
5
30
5
30
DLL Lock Time (K,C)
Doff Low period to DLL reset
K static to DLL reset
tKCreset
0.3
1.35
0.3
0
1.48
0.3
ns
ns
4
ns
5
1024
cycles
5
5
30
ns
0
1.8
ns
Output Times
C,C# High to Output Valid
tCHQV
C,C# High to Output Hold
tCHQX
C,C# High to Echo Clock Valid
tCHCQV
C,C# High to Echo Clock Hold
tCHCQX
CQ, CQ# High to Output Valid
tCQHQV
CQ, CQ# High to Output Hold
tCQHQX
0.45
-0.45
0.45
-0.45
0.45
-0.45
-0.45
0.45
-0.45
0.30
-0.30
0.45
0.45
-0.45
0.30
-0.30
0.30
-0.30
ns
1,3
ns
1,3
ns
1
ns
1
ns
1,3
ns
1,3
ns
1,3
1,3
C,C# High to Output High-Z
tCHQZ
C,C# High to Output Low-Z
tCHQX1
-0.45
-0.45
-0.45
ns
Address valid to K rising edge
tAVKH
0.40
0.40
0.40
ns
2
LD#,R/L# control inputs valid to K rising edge
tIVKH
0.40
0.40
0.40
ns
2
BWx# control inputs valid to K rising edge
tIVKH2
0.30
0.30
0.30
ns
2
Data-in valid to K, K# rising edge
tDVKH
0.30
0.30
0.30
ns
2
tKHAX
0.40
0.40
0.40
ns
2
K rising edge to LD#,R/L# control inputs hold
tKHIX
0.40
0.40
0.40
ns
2
K rising edge to BWx# control inputs hold
tKHIX2
0.30
0.30
0.30
ns
2
0.45
0.45
0.45
Setup Times
Hold Times
K rising edge to address hold
K, K# rising edge to data-in hold
tKHDX
0.30
0.30
0.30
ns
2
Notes:
1.
All address inputs must meet the specified setup and hold times for all latching clock edges.
2.
During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
3.
If C, C are tied high, then K, K become the references for C, C timing parameters.
4.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5.
VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V DD and input clock are stable.
6.
The data sheet parameters reflect tester guard bands and test setup variations.
7.
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
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IS61DDB41M18A
IS61DDB451236A
Read, Write, and NOP Timing Diagram
Read
1 tKHKH
Read
3
2
4
NOP
5
NOP3
6
Write
7
Read
9
8
10
11
12
tKHKL tKLKH
K
tKHK#H
K#
tAVKH
Address
(SA+SA1
+SA0)
A1
tIVKH
tKHAX
A2
A3
A4
tKHIX
LD#
R/W#
tKHCH
C
tKHK#H
C#
tCHQX1
DQs
1.5 Cycle Read
Latency
tCHQV
tCHQV
tCHQX
tCHQZ
tDVKH
Q1-0 Q1-1 Q1-2 Q1-3 Q2-0 Q2-1 Q2-2 Q2-3
tCQHQX
tCHQV
tKHDX
D3-0 D3-1 D3-2 D3-3
Q4-0 Q4-1 Q4-2
tCQHQX
tCQHQV
tCHCQV
tCQHQV
CQ
tCHCQV
tCHCQX
CQ#
tCHCQX
Undefined
Notes: 1. Q1-0 refers to the output from address A1. Q1-1 refers to the output from the next burst address following A1.
2. Outputs are disabled (high impedance) one clock cycle after a NOP.
3. The NOP cycle is not necessary for correct device operation, however, at high clock frequencies, it might be required to prevent bus contention.
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IS61DDB41M18A
IS61DDB451236A
IEEE 1149.1 Serial Boundary Scan of JTAG
These SRAMs incorporate a serial boundary scan Test Access Port (TAP) controller in 165 FBGA package. That is
fully compliant with IEEE Standard 1149.1-2001. The TAP controller operates using standard 1.8 V interface logic
levels.
Disabling the JTAG feature
These SRAMs operate without using the JTAG feature. To disable the TAP controller, TCK must be tied Low (VSS) to
prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively
be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the device.
Test Access Port Signal List:
Test Clock (TCK)
The test clock is to operate only TAP controller. All inputs are captured on the rising edge of TCK. All outputs are
driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is to set commands of the TAP controller and is sampled on the rising edge of TCK. This pin can be left
unconnected at SRAM operation. The pin is pulled up internally to keep logic high level.
Test Data-In (TDI)
The TDI pin is to receive serially input information into the instruction and data registers. It can be connected to the
input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the
TAP instruction register. For information on loading the instruction register (Refer to the TAP Controller State
Diagram). TDI is internally pulled up and can be unconnected at SRAM. TDI is connected to the most significant bit
(MSB) on any register.
Test Data-Out (TDO)
The TDO pin is to drive serially clock data out from the JTAG registers. The output is active, depending upon the
current state of the TAP state machine (Refer to instruction codes). The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register.
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IS61DDB41M18A
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TAP Controller State and Block Diagram
...
Boundary Scan Register (109 bits)
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
TDO
Instruction Register (3 bits)
Control Signals
TMS
TAP Controller
TCK
TAP Controller State Machine
1
Test Logic
Reset
0
Run Test
Idle
1
Select DR
1
Select IR
0
1
0
0
1
1
Capture
DR
0
Capture
IR
0
0
Shift DR
1
1
1
1
Exit1 DR
Exit1 IR
0
0
0
Pause DR
0
Pause IR
1
1
Exit2 DR
0
Exit2 IR
1
0
1
Update
DR
1
0
Shift IR
Update IR
0
1
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IS61DDB41M18A
IS61DDB451236A
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the
operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to
ensure that TDO comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the
TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
Instruction Register
This register is loaded during the update-IR state of the TAP controller. Three-bit instructions can be serially loaded into the
instruction register. At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP
controller is in the capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault isolation of the
board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. It is to skip certain chips
without serial boundary scan. This allows data to be shifted through the SRAM with minimal delay. The bypass register
is set LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and output balls on the SRAM. Several No Connected(NC)
balls are also included in the scan register to reserve other product options. The boundary scan register is loaded with
the contents of the SRAM input and output ring when the TAP controller is in the capture-DR state and is then placed
between the TDI and TDO balls when the controller is moved to the shift-DR state. The EXTEST, SAMPLE/PRELOAD,
and SAMPLE Z instructions can be used to capture the contents of the input and output ring. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command
is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP
controller is in the shift-DR state. The ID register has a vendor ID code and other information
TAP Instruction Set
TAP Instruction Set is available to set eight instructions with the three bit instruction register and all combinations are
listed in the TAP Instruction Code Table. Three of listed instructions on this table are reserved and must not be used.
Instructions are loaded serially into the TAP controller during the Shift-IR state when the instruction register is placed
between TDI and TDO. To execute an instruction once it is shifted in, the TAP controller must be moved into the
Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places
the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when
the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon powerup or whenever the TAP controller is given a test logic reset state.
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IS61DDB41M18A
IS61DDB451236A
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next
command is supplied during the Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a IEEE 1149.1 basic instruction which connects the boundary scan register between the TDI and TDO pins
when the TAP controller is in a Shift-DR state.. A snapshot of data on the inputs and output balls is captured in the
boundary scan register when the TAP controller is in a Shift-DR state. The user must be aware that the TAP controller
clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates significantly faster. Because there
is a large difference between the clock frequencies, it is possible that during the capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a signal while in transition. This will not harm the device, but
there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To ensure that the
boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to
meet the TAP controller’s capture setup plus hold time. The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan
register. Once the data is captured, it is possible to shift out the data by putting the TAP into the shift-DR state. This
places the boundary scan register between the TDI and TDO balls.
PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of
another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when
required, that is, while the data captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass
register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a board.
PRIVATE
Do not use these instructions. They are reserved for future use and engineering mode.
EXTEST
The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects
the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. IEEE Standard
1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan
register has a special bit located at bit #109. When this scan cell, called the “EXTEST output bus tri-state,” is latched
into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Qbus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive
the output bus. When LOW, this bit places the output bus into a High Z condition. This bit can be set by entering the
SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell during the Shift-DR state.
During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST
instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.
JTAG DC Operating Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%)
Parameter
Symbol
JTAG Input High Voltage
VIH1
JTAG Input Low Voltage
VIL1
JTAG Output High Voltage
VOH1
JTAG Output Low Voltage
VOL1
JTAG Output High Voltage
VOH2
JTAG Output Low Voltage
VOL2
JTAG Input Leakage Current
ILIJTAG
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Rev. A
10/02/2014
Min
1.3
–0.3
1.4
1.6
-100
Max
VDD+0.3
0.5
0.4
0.2
+100
Units
V
V
V
V
V
V
uA
Notes
|IOH1|=2mA
IOL1=2mA
|IOH2|=100uA
IOL2=100uA
0 ≤ Vin ≤ VDD
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IS61DDB41M18A
IS61DDB451236A
JTAG Output Leakage Current
ILOJTAG
-5
+5
uA
0 ≤ Vout ≤ VDD
Notes:
1.
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
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Rev. A
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IS61DDB41M18A
IS61DDB451236A
JTAG AC Test Conditions
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter
Symbol
Input Pulse High Level
VIH1
Input Pulse Low Level
VIL1
Input Rise Time
TR1
Input Fall Time
TF1
Input and Output Timing Reference Level
Conditions
1.3
0.5
1.0
1.0
0.9
Units
V
V
ns
ns
V
JTAG AC Characteristics
(Over the Operating Temperature Range, VDD=1.8V±5%, VDDQ=1.5V/1.8V)
Parameter
Symbol
Min
TCK cycle time
tTHTH
50
TCK high pulse width
tTHTL
20
TCK low pulse width
tTLTH
20
TMS Setup
tMVTH
5
TMS Hold
tTHMX
5
TDI Setup
tDVTH
5
TDI Hold
tTHDX
5
Capture Setup
tCVTH
5
Capture Hold
tTHCX
5
TCK Low to Valid Data*
tTLOV
–
TCK Low to Invalid Data*
tTLQX
0
Max
–
–
–
–
–
–
–
–
–
10
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: See AC Test Loading(c)
JTAG Timing Diagram
tTHTL
tTHTH
tTLTH
TCK
tMVTH
tTHMX
tDVTH
tTHDX
TMS
TDI
tTLOX
tTLOV
TDO
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Rev. A
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IS61DDB41M18A
IS61DDB451236A
Instruction Set
Code
Instruction
TDO Output
000
EXTEST
Boundary Scan Register
001
IDCODE
32-bit Identification Register
010
SAMPLE-Z
Boundary Scan Register
011
PRIVATE
Do Not Use
100
SAMPLE(/PRELOAD)
Boundary Scan Register
101
PRIVATE
Do Not Use
110
PRIVATE
Do Not Use
111
BYPASS
Bypass Register
ID Register Definition
Revision Number (31:29)
Part Configuration (28:12)
Vendor ID Code (11:1)
Start Bit (0)
000
0TDEF0WX01PQLBTS0
00011010101
1
Part Configuration Definition:
1. DEF = 001 for 18Mb, 010 for 36Mb, 011 for 72Mb
2. WX = 11 for x36, 10 for x18
3. P = 1 for II+(QUAD-P/DDR-IIP), 0 for II(QUAD/DDR-II)
4. Q = 1 for QUAD, 0 for DDR-II
5. L = 1 for RL=2.5, 0 for RL≠2.5
6. B = 1 for burst of 4, 0 for burst of 2
7. S = 1 for Separate I/O, 0 for Common I/O
8. T = 1 for ODT option, 0 for No ODT option
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Rev. A
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IS61DDB41M18A
IS61DDB451236A
Boundary Scan Exit Order
ORDER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin ID
6R
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin ID
10D
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
10A
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
ORDER
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
Pin ID
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Internal
Notes:
1. NC pins as defined on the FBGA Ball Assignments are read as ”don’t cares”.
2. State of internal pin (#109) is loaded via JTAG
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Rev. A
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IS61DDB41M18A
IS61DDB451236A
Ordering Information
Commercial Range: 0°C to +70°C
Speed
333 MHz
300 MHz
250 MHz
Order Part No.
IS61DDB451236A-333M3
IS61DDB451236A-333M3L
IS61DDB41M18A-333M3
IS61DDB41M18A-333M3L
IS61DDB451236A-300M3
IS61DDB451236A-300M3L
IS61DDB41M18A-300M3
IS61DDB41M18A-300M3L
IS61DDB451236A-250M3
IS61DDB451236A-250M3L
IS61DDB41M18A-250M3
IS61DDB41M18A-250M3L
Organization
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
Package
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
166 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
Organization
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
Package
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
166 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
Commercial Range: 0°C to +70°C
Speed
333 MHz
300 MHz
250 MHz
Order Part No.
IS61DDB451236A-333B4
IS61DDB451236A-333B4L
IS61DDB41M18A-333B4
IS61DDB41M18A-333B4L
IS61DDB451236A-300B4
IS61DDB451236A-300B4L
IS61DDB41M18A-300B4
IS61DDB41M18A-300B4L
IS61DDB451236A-250B4
IS61DDB451236A-250B4L
IS61DDB41M18A-250B4
IS61DDB41M18A-250B4L
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Rev. A
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IS61DDB41M18A
IS61DDB451236A
Industrial Range: -40°C to +85°C
Speed
333 MHz
300 MHz
250 MHz
Order Part No.
IS61DDB451236A-333M3I
IS61DDB451236A-333M3LI
IS61DDB41M18A-333M3I
IS61DDB41M18A-333M3LI
IS61DDB451236A-300M3I
IS61DDB451236A-300M3LI
IS61DDB41M18A-300M3I
IS61DDB41M18A-300M3LI
IS61DDB451236A-250M3I
IS61DDB451236A-250M3LI
IS61DDB41M18A-250M3I
IS61DDB41M18A-250M3LI
Organization
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
Package
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
165 FBGA (15x17 mm)
165 FBGA (15x17 mm), lead free
Organization
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
512Kx36
512Kx36
1Mx18
1Mx18
Package
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
165 FBGA (13x15 mm)
165 FBGA (13x15 mm), lead free
Industrial Range: -40°C to +85°C
Speed
333 MHz
300 MHz
250 MHz
Order Part No.
IS61DDB451236A-333B4I
IS61DDB451236A-333B4LI
IS61DDB41M18A-333B4I
IS61DDB41M18A-333B4LI
IS61DDB451236A-300B4I
IS61DDB451236A-300B4LI
IS61DDB41M18A-300B4I
IS61DDB41M18A-300B4LI
IS61DDB451236A-250B4I
IS61DDB451236A-250B4LI
IS61DDB41M18A-250B4I
IS61DDB41M18A-250B4LI
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Rev. A
10/02/2014
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IS61DDB41M18A
IS61DDB451236A
Package drawing – 15x17x1.4 BGA
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Rev. A
10/02/2014
31
IS61DDB41M18A
IS61DDB451236A
Package drawing – 13x15x1.4 BGA
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Rev. A
10/02/2014
32