D o c u m en t a ti o n A d d en d u m , V 1 . 2, Au g . 2 0 0 7 TC1796 3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r Delta BD-to-BE Step M i c r o c o n t r o l l e rs Edition 2007-08 Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D o c u m en t a ti o n A d d en d u m , V 1 . 2, Au g . 2 0 0 7 TC1796 3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r Delta BD-to-BE Step M i c r o c o n t r o l l e rs TC1796 Delta BD-to-BE Step, Documentation Addendum Revision History: V1.2 2007-08 Previous Versions: V1.1, V1.0 Page Subjects (major changes since last revision) 2 References to actual documents updated. Trademarks TriCore® is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] TC1796 Delta BD-to-BE Step Table of Contents Table of Contents 1 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Improvements/DIfferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Scan Chain Mode (SSCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Documentation Addendum 1 2 2 2 2 2 3 5 5 5 V1.2, 2007-08 TC1796 Delta BD-to-BE Step Introduction 1 Introduction This document describes functional differences and improvements of the TC1796 BEStep in comparison to the previous B-Steps, especially the BD-Step. The referenced documents to this addendum are located at the Internet page: • • • • www.infineon.com/tc1796 TC1796 System Units User’s Manual (Vol.1), V2.0, July 2007 TC1796 Peripheral Units User’s Manual (Vol.2), V2.0, July 2007 TC1796 Data Sheet V0.7, March 2006 1.1 Functional Improvements/DIfferences This section summarizes the functional differences and improvements of the TC1796 BE-Step. 1.1.1 RTID Register In the TC1796 BE-Step the reset value of register RTID = 0000 0300H. 1.1.2 PCP The erratum PCP_TC.029 “Possible corruption of CPPN value when a nested channel is restarted” has been fixed in the BE-Step. 1.1.3 Pads This section summarizes all pad related changes and improvements. • • • • • The ESD strength based on human body model of the BD-Step will be improved in the BE-Step. Detailed parameters are defined in the Data Sheet for the BE-Step. The erratum PWR_TC.P009 “Power up behavior” with the problem: “High cross current at OCDS L2 ports during power up” is fixed in the BE-Step. Therefore, also the constraints for the power up sequence as defined in the data sheet can be relaxed concerning the OCDS trace pins. Up to the BD-Step, the input pads with spike filter functionality PORST, HDRST, and NMI have no hysteresis. In the BE-Step these three input pads have a built-in hysteresis. The JTAG module clock input TCLK and the JTAG module reset/enable input TRST have a weak pull-down device active during reset (PORST = 0). Caused by this change, the pad test feature for pins TCLK and TRST (bits SCU_PTDAT2.TRST and SCU_PTDAT2.TCK) is no more supported. This means, the two bits 3 and 4 in register SCU_PTDAT2 are “rh” bits. In the BE-Step, the eight LVDS MSC Clock and Data output pads of the BE-Step are set into a high-impedance state if they are disabled by SCU_CON.LCDEN = 0. Documentation Addendum 2 V1.2, 2007-08 TC1796 Delta BD-to-BE Step Introduction • In the BE-Step, the driver strength of class A1 and A2 pads have been improved. This especially affects the test conditions for the output low voltage VOLA and output high voltage VOHA. The detailed test condition values for IOL and IOH are defined in the Data Sheet for the BE-Step. 1.1.4 SCU Control Register In the TC1796 BE-Step it is possible that fOSC remains connected to the PLL even if a PLL loss-of-lock failure is detected. This feature is controlled by the new bit OSCDISCDIS in the SCU_CON register. Figure 1-1 shows the changes of the CGU of the BE-Step (in the red circle). The changes in registers SCU_CON and PLL_CLC are also documented on the next pages. XTAL1 Clock Generation Unit (CGU) fOSC Phase Detect. fSYS KDivider SYSFS KDIV BYPPIN VCOBYP LOCK VCO fVCO M U X fCPU NDivider PLL & PDIV ORDRES OSCR MOSC fP fN PLL Lock Detect. Osc. Run Detect. OGC ≥1 VCOSEL PDivider NDIV XTAL2 Clock Output Control OSCDISC Main Osc. Circuit OSCDISCDIS BYPASS Oscillator Control Register OSC_CON PLL Clock Control and Status Register PLL_CLC System Control Unit (SCU) P5.3 / TXD1A Figure 1-1 SCU Control Register SCU_CON MCB05600a PLL Block Diagram Documentation Addendum 3 V1.2, 2007-08 TC1796 Delta BD-to-BE Step Introduction SCU_CON SCU Control Register 31 15 30 29 14 13 28 (F0000050H) 27 26 25 24 23 Reset Value: FF00 0002H 22 ONE ZERO rw rw 12 11 10 RPA LD RAV EN 0 r rw rw 9 8 7 DTS ON 0 rw r 21 20 OSC DISC DIS rw 6 5 4 19 18 16 SSC SLS 0 PDR PDR rw rw GIN1S rw 3 17 2 1 0 AN7 NMI EPU CS CS CS FIEN TM EN D GEN OEN EEN rw rws rw rw rw rw rw Field Bits Type Description OSCDISCDIS 20 rw Oscillator Disconnect Disable This bit is used to disable the control of PLL_CLC.OCSDISC in a PLL loss-of-lock case. 0 In case of a PLL loss-of-lock the oscillator clock fOSC is controlled by bit PLL_CLC.OCSDISC (default after reset) 1 In case of a PLL loss-of-lock the oscillator clock fOSC is always connected to the PLL even in a PLL loss-of-lock case. ZERO [23:21] rw Spare 0 Control Bits Documentation Addendum 4 V1.2, 2007-08 TC1796 Delta BD-to-BE Step Introduction PLL_CLC PLL Clock Control Register 31 30 29 28 27 (F0000040H) 26 25 24 23 Reset Values: see 22 21 20 19 0 BYP PIN 0 OSC DISC 0 NDIV r rh r rwh r rw 8 7 15 14 13 12 11 10 9 5 4 3 PDIV 0 KDIV VCOSEL VCO BYP 0 rw r rw rw rw r Field Bits Type Description OSCDISC 24 rwh 1.1.5 6 18 17 16 2 1 0 SYS RES LO FS LD CK rw rwh rh Oscillator Disconnect This bit is used to disconnect the divided fOSC clock from the PLL in order to avoid unstable operation due to noise or sporadic clock pulses coming from the oscillator circuit while the PLL is still trying to lock to invalid clock pulses. The functionality of this bit can be disabled by setting SCU_CON.OSCDISCDIS to 1. 0 Oscillator clock fOSC is connected to the PLL. 1 Oscillator clock fOSC is disconnected from the PLL (default after reset) This bit is set by hardware if a PLL loss-of-lock failure is detected. EBU The erratum EBU_TC.019 “Burst Mode signals delayed longer than specified” has been fixed in the BE-Step. 1.1.6 ADC The erratum ADC_TC.033 “Wrong CHCON register might be used by inserted conversion” has been fixed in the BE-Step. 1.1.7 Single Scan Chain Mode (SSCM) The SSCM is a test mode which is especially implemented in the BE-Step for analysis purposes. In SSCM, all device internal scan chains are concatenated to one single Documentation Addendum 5 V1.2, 2007-08 TC1796 Delta BD-to-BE Step Introduction chain. This configuration allows to access the scan chains with a minimum number of external pins. This section describes the hardware requirements for a system that allows use of the SSCM for in-system diagnostics. Entering Single Scan Chain Mode The SSCM is entered if the following signals are applied during the rising edge of PORST. • • • • • NMI = 0 TMS = 0 BYPASS = 1 TESTMODE = 0 P10.[3:0] / HWCFG[3:0] = 0100B Note that the pins TESTMODE, BYPASS, and NMI are forced to their non-default states. All the pins mentioned in the list above must be permanently driven when the SSCM is active.This must be regarded during board design. Device State in Single Scan Chain Mode When the TC1796 is in SSCM, the pins/modules are in the following states: • • • • • • • • • • • P0 to P9 I/O pins: high impedance state EBU pins: high impedance state Trace pins: high impedance state LVDS pins: switched off Dedicated SSC pins: high impedance state BRKIN, BRKOUT: high impedance state TSTRES: high impedance input HDRST: drives 0 XTAL1: drive through mode, not used during SSCM Analog inputs AN[43:0]: not selected CPU & Peripheral modules: logic connected together in single scan chain Pins used to control the SSCM The following device pins of the TC1796 must be accessible during SSCM for in-system diagnostics. • • • • • TRST: JTAG reset input TDI: Scan chain enable TCK: Scan chain clock, used for shift and capture TMS: Scan chain input TDO: Scan chain output Documentation Addendum 6 V1.2, 2007-08 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG