RENESAS M306H1SFP

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
1. Description
The M306H1SFP is single-chip microcomputer using the high-performance silicon gate CMOS process
using a M16C/60 Series CPU core and is packaged in a 144-pin plastic molded QFP. This single-chip
microcomputer operates using sophisticated instructions featuring a high level of instruction efficiency.
With 1M bytes of address space, this is capable of executing instructions at high speed. This also features
a built-in OSD display function and data slicer, making this correspondence to Teletext broadcasting service.
This microcomputer is ROM less article, it can be used only at microprocessor mode.
1.1 Features
• Memory capacity ..................................<ROM>ROM less
<RAM>5K bytes
• Shortest instruction execution time ...... 100 ns (f(XIN)=10 MHz)
• Supply voltage ..................................... 4.75 V to 5.25V(at f(XIN)=10 MHz)
• Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels (Including key input interrupt)
• Multifunction 16-bit timer...................... 5 output timers + 6 input timers
• Serial I/O .............................................. 5 channels
UART/clock synchronous: 3
Clock synchronous: 2
• DMAC .................................................. 2 channels (trigger: 24 sources)
• A-D converter ....................................... 8 bits X 8 channels (Expandable up to 10 channels)
• D-A converter ....................................... 8 bits X 2 channels
• CRC calculation circuit ......................... 1 circuit
• Watchdog timer ....................................1 line
• Programmable I/O ............................... 50 lines
_______
• Input port.............................................. 1 port (P85 shared with NMI pin)
• Chip select output ................................ 3 lines
• Clock generating circuit ....................... 2 built-in circuits
(built-in feedback resistor, and external ceramic or crystal oscillator)
• OSD function ....................................... Screen composition
40 characters X 25 lines
Characters available
Font RAM : 256 characters, SYRAM : 15 characters
• Data slicer ............................................ For PDC, VPS and VBI
• Encoder ............................................... For VBI
1.2 Applications
VCR, etc
Rev. 1.1
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table of contents
1. Description ............................................................. 1
1.1 Features .......................................................... 1
1.2 Applications .................................................... 1
1.3 Pin Configuration ............................................ 3
1.4 Block Diagram ................................................ 4
1.5 Performance Outline ....................................... 5
2. Operation of Functional Blocks .............................. 9
2.1 Memory ........................................................... 9
2.2 CPU ................................................................ 13
2.3 Reset .............................................................. 16
2.4 Processor Mode .............................................. 20
2.5 Clock Generating Circuit ................................. 31
2.6 Protection ........................................................ 40
2.7 Interrupt .......................................................... 41
2.8 Watchdog Timer ............................................. 61
2.9 DMAC ............................................................. 63
2.10 Timer ............................................................. 73
2.11 Serial I/O ....................................................... 91
2.12 A-D Converter ............................................... 132
2.13 D-A Converter ............................................... 142
2.14 CRC Calculation Circuit ................................ 144
2.15 Expansion Function ...................................... 146
2.16 Programmable I/O ........................................ 207
3. Usage Precaution .................................................. 217
4. Electrical Characteristic ......................................... 222
5. Marking Figure ....................................................... 239
6. Package Outline..................................................... 240
Rev. 1.0
2
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
1.3 Pin Configuration
NC
NC
NC
P42/A18
P43/A19
P40/A16
P41/A17
P35/A13
P36/A14
P37/A15
P34/A12
VCC
P31/A9
P32/A10
P33/A11
VSS
P30/A8(/-/D7)
P23/A3(/D3/D2)
P24/A4(/D4/D3)
P25/A5(/D5/D4)
P26/A6(/D6/D5)
P27/A7(/D7/D6)
P22/A2(/D2/D1)
P17 /D15/INT5
P20/A0(/D0/-)
P21/A1(/D1/D0)
P14 /D12
P15 /D13/INT3
P16 /D14/INT4
P12 /D10
P13 /D11
P11/D9
NC
P10/D8
NC
NC
Figures 1.3.1 shows the pin configuration (top view).
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P07/D7
109
72
NC
P06/D6
110
71
NC
P05/D5
P04/D4
111
70
NC
112
69
P44 /CS0
P03/D3
P02/D2
113
68
114
67
P4 5
P46/CS2
P01/D1
P00/D0
115
66
116
65
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
117
64
118
63
119
62
P51/WRH/BHE
P52 /RD
P53/BCLK
120
61
P54/HLDA
121
60
P55/HOLD
P102/AN2
P101/AN1
AVSS
122
59
123
58
P56/ALE
P57/RDY
124
57
P100/AN0
125
56
VREF
126
M306H1SFP
55
P47 /CS3
P50/WRL/WR
P60/CTS0/RTS0
P61/CLK0
P62/RXD0
AVCC
127
P97/ADTRG/SIN4
VDD1
VSS1
128
53
129
52
P63/TXD0
P64/CTS1/RTS1/CLKS1
P65/CLK1
130
51
P66/RXD1
VERT
LP3
131
50
132
49
P67/TXD1
NC
LP4
133
48
VDD1
LP1
134
47
LP2
135
46
P110/EDO2
P111/EDO1
54
139
42
140
41
CVIDEO1
141
40
P115/G
P116/R
P117/GRAY
VDD2
VSS3
142
39
P118/SLICEON
143
38
VDD3
144
37
VSS1
NC
P112/CSYN
P113/BLNK
P70/TXD2/SDA/TA0OUT
P74/TA2OUT
P73/CTS2/RTS2/TA1IN
P75/TA2IN
P77/TA3IN
P76/TA3OUT
P80/TA4OUT
P83/INT1
P72/CLK2/T A1OUT
P71/RXD2/SCL/TA0IN/TB5IN
144P6Q-A
P82/INT0
P81/TA4IN
Vcc
P85/NMI
P84/INT2
XIN
Vss
XOUT
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
RESET
8
P86/XCOUT
7
P87/XCIN
6
CNVss
5
P90/TB0IN/CLK3
BYTE
4
P93/DA0/TB3IN
3
P92/TB2IN/SOUT3
P91/TB1IN/SIN3
2
P94/DA1/TB4IN
1
P96/ANEX1/SOUT4
P95/ANEX0/CLK4
P114/B
SVREF
Vss2
VSS3
43
CVIDEO2
138
CVIN2
44
NC
SYNCIN/HOR
45
137
CVIN1
136
SECAMIN
NC
FSCIN
Figure 1.3.1 Pin configuration (top view)
Rev. 1.0
3
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
1.4 Block Diagram
Figure 1.4.1 is a block diagram of the M306H1SFP.
8
I/O ports
Port P0
8
8
Port P1
8
Port P2
8
Port P3
8
8
Port P4
Port P5
Port P6
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Expandable up to 10 channels)
XIN-XOUT
XCIN-XCOUT
UART/clock synchronous SI/O
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Encoder
M16C/60 series16-bit CPU core
(8 bits X 2 channels)
SB
PC
Stack pointer
ISP
USP
Memory
RAM
(5K bytes)
Vector table
INTB
Flag register
FLG
Multiplier
8
R0H
R0L
R0H
R0L
R1H
R1L
R1H
R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
Program counter
8
D-A converter
Slicer
Port P10
(2 channels)
OSD
Port P9
DMAC
(8 bits X 2 channels)
Port P85
(15 bits)
Clock synchronous SI/O
(8 bits X 3 channels)
Registers
Watchdog timer
AAAAAA
AA
AA
AA
AAAAAAAA
AA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAA
AAAA
7
System clock generator
( 8 bits X 8 channels
Port P8
A-D converter
Timer
8
Port P7
Internal peripheral functions
9
Port P11
Figure 1.4.1 Block diagram of M306H1SFP
Rev. 1.0
4
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
1.5 Performance Outline
Table 1.5.1 is a performance outline of M306H1SFP.
Table 1.5.1 Performance outline of M306H1SFP
Item
Number of basic instructions
Shortest instruction execution time
Memory
ROM
capacity
RAM
I/O port
P0 to P10 (except P85)
Input port
P85
Output port P11
Multifunction TA0, TA1, TA2, TA3, TA4
timer
TB0, TB1, TB2, TB3, TB4, TB5
Serial I/O
UART0, UART1, UART2
SI/O3, SI/O4
A-D converter
D-A converter
DMAC
CRC calculation circuit
Watchdog timer
Interrupt
Clock generating circuit
Performance
91 instructions
100ns (f(XIN)=10MHZ )
—
5K bytes
8 bits x 10, 7 bits x 1
1 bit x 1
9 bit x 1
16 bits x 5
16 bits x 6
(UART or clock synchronous) x 3
(Clock synchronous) x 2
8 bits x (8 + 2) channels
8 bits x 2 channels
2 channels (trigger: 24 sources)
CRC-CCITT
15 bits x 1 (with prescaler)
25 internal and 8 external sources, 4 software sources, 7 levels
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or crystal oscillator)
Supply voltage
4.75 to 5.25V (f(XIN)=10MHZ)
Device configuration
CMOS high performance silicon gate
Package
144-pin plastic mold QFP
OSD function OSD display RAM
2.75K Bytes (25 x 40 x 22-bit)
Font RAM
3.84K Bytes (12 x 10 x 256-bit)
SYRAM
260 Bytes (13 x 10 x 16-bit)
Screen composition
40 characters x 25 lines
Character composition
12 x 10 dots matrix
Character coloring
8 colors choices per character
Character Background coloring 8 colors choices per character
Background coloring
8 colors choices per screen
SYRAM color
8 colors choices per character
Character Background coloring 8 colors choices per character
Synchronous signal
PAL
Video signal
PAL
Data slicer
Slice RAM
864 Bytes (48 x 18 x 8-bit)
VBIRAM
95 Bytes ((5 + 5 x 18) x 8-bit)
Data slicer
for PDC, VPS and VBI
Encoder
for VBI
Rev. 1.0
5
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 1.5.2 Pin Description
Pin name
Signal name
I/O type
Function
VCC, VSS
Power supply
input
CNVSS
CNVSS
Input
This pin switches between processor modes. Connect it to the VCC pin
when in microprocessor mode.
RESET
Reset input
Input
A “L” on this input resets the microcomputer.
XIN
Clock input
Input
XOUT
Clock output
Output
These pins are provided for the main clock generating circuit. Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
XOUT pin open.
BYTE
External data
bus width
select input
Input
AVCC
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
VREF
Reference
voltage input
Input
This pin is a reference voltage input for the A-D converter.
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually.
Input/output
When set as a separate bus, these pins input and output data (D0–D7).
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as external interrupt pins as selected by software.
Input/output
When set as a separate bus, these pins input and output data (D8–D15).
Input/output
This is an 8-bit I/O port equivalent to P0.
A0 to A7
Output
These pins output 8 low-order address bits (A0–A7).
A0/D0 to
A7/D7
Input/output
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D0–D7) and output 8 low-order address bits
(A0–A7) separated in time by multiplexing.
A0, A1/D0
to A7/D6
Output
Input/output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D0–D6) and output address (A1–A7) separated
in time by multiplexing. They also output address (A0).
Input/output
This is an 8-bit I/O port equivalent to P0.
A8 to A15
Output
These pins output 8 middle-order address bits (A8–A15).
A8/D7,
A9 to A15
Input/output
Output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D7) and output address (A8) separated in time
by multiplexing. They also output address (A9–A15).
Input/output
This is an 8-bit I/O port equivalent to P0.
Output
Output
These pins output CS0,CS2,CS3 signals and A16–A19. CS0,CS2,CS3 are
chip select signals used to specify an access space. A16–A19 are 4
high- order address bits.
D0 to D7
P10 to P17
I/O port P1
D8 to D15
P20 to P27
P30 to P37
P40 to P47
CS0,CS2,CS3,
A16 to A19
I/O port P2
I/O port P3
I/O port P4
Supply 4.75 to 5.25 V to the Vcc pin. Supply 0 V to the Vss pin.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”.
Rev. 1.0
6
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 1.5.3 Pin Description
Pin name
Signal name
I/O type
Function
Input/output
This is an 8-bit I/O port equivalent to P0.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
Output
Output
Output
Output
Output
Input
ALE,
RDY
Output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
P50 to P57
I/O port P5
P60 to P67
I/O port P6
Input/output
This is an 8-bit I/O port equivalent to P0. The port can be set to have or
not have a pull-up resistor in units of four bits by software. Pins in this
port also function as UART0 and UART1 I/O pins as selected by
software.
P70 to P77
I/O port P7
Input/output
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel
open-drain output). Pins in this port also function as timer A0–A3,
timer B5 or UART2 I/O pins as selected by software.
P80 to P84,
P86,
I/O port P8
Input/output
Input/output
P80 to P84, P86, and P87 are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P86 and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
P87,
Input/output
P85
I/O port P85
Input
P90 to P97
I/O port P9
Input/output
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as SI/O3, 4 I/O pins, Timer B0–B4 input pins, D-A converter output pins,
A-D converter extended input pins, or A-D trigger input pins as selected
by software.
P100 to P107
I/O port P10
Input/output
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P104–P107 also function as
input pins for the key input interrupt function.
VDD1
Power supply
input
Digital power supply pin. Connect to +5 V.
VDD2
Power supply
input
Analog power supply pin. Connect to +5 V.
VDD3
Power supply
input
Analog power supply pin. Connect to +5 V.
CVIDEO1
Composite
video output 1
Output
This is composite video signal output pin. Output 2 Vp-p composite
video signal. In superimpose mode, this pin's signal consists of CVIN1
signal of the display range combined with the character output signal.
Rev. 1.0
7
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 1.5.4 Pin Description
Pin name
Signal name
I/O type
Output
Function
CVIDEO2
Composite
video output 2
This is composite video signal output pin. Output 2 Vp-p composite
video signal. This pin's signal consists of CVIN2 signal of vertical
blanking erase interval combined with the VBI output signal.
SVREF
Synchronous
Input
slice level input
When slice the vertical synchronous signal, input slice power.
CVIN1
Composite
video signal
input 1
Input
This pin inputs the external composite video signal. In superimpose
mode, this pin's signal consists of it's composite video signal combined
with the character output signal. Data slices this signal internally by
setting.
SECAMIN
SECAM input
Input
Carrier input pin for SECAM.
CVIN2
Composite
video signal
input 2
Input
This pin inputs the external composite video signal. In VBI encode, this
pin's signal consists of it's composite video signal combined with the
VBI output signal. Data slices this signal internally by setting.
SYNCIN
Composite
video signal
input 3
Input
This pin inputs the external composite video signal. Synchronous
devides this signal internally.
Input digital horizontal synchronous signal (5 V).
HOR
LP1
Filter output 1
Output
This is filter output pin 1 (for display).
LP2
Filter output 2
Output
This is filter output pin 2 (for synchronous).
LP3
Filter output 3
Output
This is filter output pin 3 (for VBI, VPS).
LP4
Filter output 4
Output
This is filter output pin 4 (for PDC).
FSCIN
fsc input pin for Input
synchronous
signal
generation
Sub-carrier (fsc) input pin for synchronous signal generation.
VERT
Vertical
synchronous
signal input
Digital vertical synchronous signal input (5 V).
Input
P110 to P118 Output port P11 Output
This is a 9-bit output-only port. Pins in this port also function as EDO2,
EDO1,CSYN,BLNK,B,G,R,GRAY,SLICEON output pins as selected by
software.
Rev. 1.0
8
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2. Operation of Functional Blocks
The M306H0SFP accommodates certain units in a single chip. These units include RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included
are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, OSD circuit, Data slicer circuit, Data encode circuit and I/O ports.
The following explains each unit.
2.1 Memory
Figure 2.1.1 is a memory map of the M306H0SFP. The address space extends the 1M bytes from address 0000016 to FFFFF16. From address FFFFF16 down is ROM. In the M306H0SFP, can use from
address from
0400016 to FFFFF16 as external ROM area. The vector table for fixed interrupts such as the
_______
reset and NMI are mapped to from address FFFDC16 to FFFFF16. The starting address of the interrupt
routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired
using the internal register (INTB). See the section on interrupts for details.
5K bytes of internal RAM is mapped to from address 0040016 to 017FF16. In addition to storing data, the
RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to from address 0000016 to 003FF 16. This area accommodates the control
registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 2.1.2
to 2.1.4 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is
reserved and cannot be used for other purposes.
The special page vector table is mapped to from address FFE0016 to FFFDB 16. If the starting addresses
of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and
jump instructions can be used as 2-byte instructions, reducing the number of program steps.
Address 0180016 to 03FFF16 and address 2800016 to 2FFFF16 are reserved and cannot be used.
0000016
003FF16
0040016
SFR area
For details, see Figures
2.1.2 to 2.1.4
FFE0016
Internal RAM area
017FF16
0180016
03FFF16
0400016
Special page
vector table
Internal reserved
area
External area
FFFDC16
Undefined instruction
FFFFF16
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
Overflow
2800016
Internal reserved
area
3000016
External area
FFFFF16
Figure 2.1.1 Memory map
Rev. 1.0
9
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
000016
004416
000116
004516
000216
004616
000316
000416
000516
000616
000716
000816
000916
000A16
004716
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
004816
004916
004A16
Bus collision detection interrupt control register (BCNIC)
004B16
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
004C16
000B16
004D16
000C16
004E16
000D16
000E16
000F16
004F16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
001016
001116
005016
005116
005216
Address match interrupt register 0 (RMAD0)
005316
001216
005416
001316
005516
001416
005616
001516
Address match interrupt register 1 (RMAD1)
INT3 interrupt control register(INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
SI/O4 interrupt control register (S4IC)
INT5 interrupt control register(INT5IC)
SI/O3 interrupt control register (S3IC)
INT4 interrupt control register(INT4IC)
005716
001616
005816
001716
005916
001816
005A16
001916
005B16
001A16
005C16
001B16
005D16
001C16
005E16
001D16
005F16
001E16
006016
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
001F16
002016
002116
DMA0 source pointer (SAR0)
020016
002216
020116
002316
020216
002416
002516
020316
DMA0 destination pointer (DAR0)
020416
002616
020516
002716
020616
002816
002916
DMA0 transfer counter (TCR0)
002A16
020816
020916
002B16
002C16
020716
020A16
DMA0 control register (DM0CON)
020C16
002E16
020D16
002F16
020E16
003016
020F16
DMA1 source pointer (SAR1)
021016
003216
021116
003316
021216
003416
021316
003516
DMA1 destination pointer (DAR1)
021416
003616
021516
003716
021616
003816
003916
DMA1 transfer counter (TCR1)
021716
021816
003A16
021916
003B16
021A16
003C16
DMA1 control register (DM1CON)
Display RAM data control register
Font RAM address control register
Font RAM data control register
SYRAM address control register
020B16
002D16
003116
Display RAM address control register
SYRAM data control register
Slice RAM address control register
Slice RAM data control register
VBIRAM address control register
VBIRAM data control register
Address control register for expansion register
Data control register for expansion register
Humming 8/4 register
021B16
003D16
021C16
003E16
021D16
003F16
021E16
004016
021F16
004116
022016
Humming 24/18 register 0
Humming 24/18 register 1
004216
004316
033F16
Figure 2.1.2 Location of peripheral unit control registers (1)
Rev. 1.0
10
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
034016
Timer B3, 4, 5 count start flag (TBSR)
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
038016
038116
034116
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Timer A4-1 register (TA41)
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
034E16
038E16
034F16
038F16
035016
039016
035116
035216
035316
035416
035516
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
039116
039216
039316
039416
039516
035616
039616
035716
039716
035816
039816
035916
039916
039A16
035A16
035B16
035C16
035D16
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
036016
Interrupt cause select register (IFSR)
SI/O3 transmit/receive register (S3TRR)
036116
036216
036316
036416
SI/O3 control register (S3C)
SI/O3 bit rate generator (S3BRG)
SI/O4 transmit/receive register (S4TRR)
036716
039C16
039D16
Timer A1 (TA1)
Timer A2 (TA2)
Timer A3 (TA3)
Timer A4 (TA4)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
039F16
03A016
UART0 transmit/receive mode register (U0MR)
03A116
UART0 bit rate generator (U0BRG)
03A216
03A316
03A416
03A516
036516
036616
039B16
Timer A0 (TA0)
039E16
035E16
035F16
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
SI/O4 control register (S4C)
SI/O4 bit rate generator (S4BRG)
03A616
03A716
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
036816
03A816
UART1 transmit/receive mode register (U1MR)
036916
03A916
UART1 bit rate generator (U1BRG)
036A16
03AA16
036B16
03AB16
036C16
03AC16
036D16
03AD16
036E16
03AE16
036F16
03AF16
037016
03B016
037116
03B116
037216
03B216
037316
03B316
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
03B416
037416
037516
UART1 transmit buffer register (U1TB)
UART2 special mode register 3(U2SMR3)
UART2 special mode register 2(U2SMR2)
UART2 special mode register (U2SMR)
03B516
UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
03B816
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1)
UART2 receive buffer register (U2RB)
03B616
03B716
DMA0 request cause select register (DM0SL)
03B916
03BA16
DMA1 request cause select register (DM1SL)
03BB16
03BC16
03BD16
03BE16
CRC data register (CRCD)
CRC input register (CRCIN)
03BF16
Figure 2.1.3 Location of peripheral unit control registers (2)
Rev. 1.0
11
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
A-D register 0 (AD0)
Reserved register
A-D register 1 (AD1)
Reserved register
A-D register 2 (AD2)
Reserved register
A-D register 3 (AD3)
Reserved register
A-D register 4 (AD4)
Reserved register
A-D register 5 (AD5)
Reserved register
A-D register 6 (AD6)
Reserved register
A-D register 7 (AD7)
Reserved register
03D016
03D116
03D216
03D316
03D416
A-D control register 2 (ADCON2)
03D516
03D616
03D716
03D816
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
03D916
03DA16
D-A register 1 (DA1)
03DB16
03DC16
D-A control register (DACON)
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
03F516
03F616
Port P10 direction register (PD10)
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
Figure 2.1.4 Location of peripheral unit control registers (3)
Rev. 1.0
12
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.2 Central Processing Unit (CPU)
The CPU has 13 registers shown in Figure 2.2.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and
FB) come in two sets; therefore, these have two register banks.
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
b15
R0(Note)
b8 b7
b15
R1(Note)
R2(Note)
b15
A0(Note)
Program counter
Data
registers
b0
b19
INTB
b0
b15
b0
Interrupt table
register
L
H
b0
User stack pointer
USP
b15
b0
b0
Interrupt stack
pointer
ISP
b0
Address
registers
b15
b0
SB
b15
FB(Note)
b0
PC
AAAAAAA
AAAAAAA
AAAAAAA
A
AA
AA
AAAAAAAA
A
AA
AA
AA
A
AAA
AAAAAAAAAAAAA
AA
AA
A
b15
A1(Note)
b19
b0
L
AAAAAAA
AAAAAAA
AAAAAAA
b15
R3(Note)
b8 b7
H
b15
b0
L
H
b15
b0
Frame base
registers
IPL
Static base
register
b0
FLG
Flag register
U I O B S Z D C
Note: These registers consist of two register banks.
Figure 2.2.1 Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev. 1.0
13
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 2.2.2 shows the flag
.register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
Rev. 1.0
14
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
AA
AAA
AAAAAAAAA
AA
AA
AA
A
AA
AAAAAAAAAAAAAAAA
AA
AA
A
AA
b15
b0
IPL
U
I
O B S Z D C
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 2.2.2 Flag register (FLG)
Rev. 1.0
15
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.3 Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 2.3.1 shows the example reset circuit. Figure 2.3.2 shows the reset sequence.
5V
4.0V
VCC
RESET
VCC
0V
5V
RESET
0.8V
0V
Example when VCC = 5V.
Figure 2.3.1 Example reset circuit
XIN
More than 20 cycles are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
24cycles
BCLK
Content of reset vector
Address
FFFFC 16
FFFFD 16
FFFFE16
RD
WR
CS0
Microprocessor
mode BYTE = “L”
Address
Content of reset vector
FFFFC 16
FFFFE 16
RD
WR
CS0
Figure 2.3.2 Reset sequence
Rev. 1.0
16
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
____________
Table 2.3.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 2.3.3 and 2.3.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 2.3.1 Pin status when RESET pin level is “L”
Status
CNVSS = VCC
Pin name
BYTE = VSS
BYTE = VCC
P0
Data input (floating)
Data input (floating)
P1
Data input (floating)
Input port (floating)
P2, P3, P40 to P43 Address output (undefined)
Address output (undefined)
P44
CS0 output (“H” level is output)
CS0 output (“H” level is output)
P45 to P47
Input port (floating)
(pull-up resistor is on)
Input port (floating)
(pull-up resistor is on)
P50
WR output (“H” level is output)
WR output (“H” level is output)
P51
BHE output (undefined)
BHE output (undefined)
P52
RD output (“H” level is output)
RD output (“H” level is output)
P53
BCLK output
BCLK output
HLDA output (The output value HLDA output (The output value
depends on the input to the
depends on the input to the
HOLD pin)
HOLD pin)
P54
P55
HOLD input (floating)
HOLD input (floating)
P56
ALE output (“L” level is output)
ALE output (“L” level is output)
P57
RDY input (floating)
RDY input (floating)
P6, P7, P80 to P84,
Input port (floating)
P86, P87, P9, P10
Input port (floating)
Output port
Output port
CVIDEO1, CVIDEO2 Output port
Output port
P110 to P118
CVIN1, CVIN2,
SECAMIN, SVREF, Input port
SYNCIN, VERT,
FSCIN
LP1, LP2, LP3, LP4
Output port
Input port
Output port
2.3.1 Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of
internal RAM are preserved.
Rev. 1.0
17
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Processor mode register 0 (Note)
Processor mode register 1
System clock control register 0
(020216)···
0016
0
(020316)···
0016
(000616)··· 0 1 0 0 1 0 0 0
(020416)···
0016
(020516)···
0016
(020616)···
0016
(020716)···
0016
(000416)···
0016
(000516)··· 0 0 0 0 0
Display RAM address control register
System clock control register 1
(000716)··· 0 0 1 0 0 0 0 0
Chip select control register
(000816)··· 0 0 0 0 0 0 0 1
Display RAM data control register
Font RAM address control register
Address match interrupt enable register
(000916)···
0 0
Protect register
(000A16)···
0 0 0
(020816)···
0016
Watchdog timer control register
(000F16)··· 0 0 0 ? ? ? ? ?
(020916)···
0016
(001016)···
0016
SYRAM address control register
(020A16)···
0016
(001116)···
0016
(020B16)···
0016
SYRAM data control register
(020C16)···
0016
0016
(020D16)···
0016
0016
(020E16)···
0016
(020F16)···
0016
(021016)···
0016
(003C16)··· 0 0 0 0 0 ? 0 0
(021116)···
0016
(004416)···
(021216)···
0016
(021316)···
0016
(021416)···
0016
? 0 0 0
(021516)···
0016
(004816)···
0 0 ? 0 0 0
(021616)···
0016
SI/O3 interrupt control register
(004916)···
0 0 ? 0 0 0
(021716)···
0016
Bus collision detection interrupt
control register
(004A16)···
? 0 0 0
(021816)···
0016
? 0 0 0
(021916)···
0016
Humming 8/4
(021A16)···
0016
Humming 24/18
Address match interrupt register 0
(001216)···
Address match interrupt register 1
(001416)···
(001516)···
(001616)···
DMA0 control register
DMA1 control register
INT3 interrupt control register
0 0 0 0
0 0 ? 0 0 0
Timer B5 interrupt control register
(004516)···
? 0 0 0
(004616)···
? 0 0 0
SI/O4 interrupt control register
DMA0 interrupt control register
(004716)···
(004B16)···
Slice RAM address control register
0 0 0 0
(002C16)··· 0 0 0 0 0 ? 0 0
Timer B4 interrupt control register
Timer B3 interrupt control register
Font RAM data control register
Slice RAM data control register
VBIRAM address control register
VBIRAM data control register
Address control register for expansion register
Data control register for expansion register
DMA1 interrupt control register
(004C16)···
? 0 0 0
Key input interrupt control register
(004D16)···
? 0 0 0
(021B16)···
0016
? 0 0 0
(021C16)···
0016
A-D conversion interrupt control register
(004E16)···
UART2 transmit interrupt control register
(004F16)···
? 0 0 0
(021D16)···
0016
UART2 receive interrupt control register
(005016)···
? 0 0 0
(021E16)···
0016
? 0 0 0
(021F16)···
0016
UART0 transmit interrupt control register
(005116)···
(034016)··· 0 0 0
UART0 receive interrupt control register
(005216)···
? 0 0 0
Timer B3,4,5 count start flag
UART1 transmit interrupt control register
(005316)···
? 0 0 0
Reserved register
(034816)···
0016
UART1 receive interrupt control register
(005416)···
? 0 0 0
Reserved register
(034916)···
0016
Timer A0 interrupt control register
(005516)···
? 0 0 0
Reserved register
(034A16)···
0016
Timer A1 interrupt control register
(005616)···
? 0 0 0
Reserved register
(034B16)···
0016
Timer A2 interrupt control register
(005716)···
? 0 0 0
Timer B3 mode register
(035B16)··· 0 0 ?
0 0 0 0
Timer A3 interrupt control register
(005816)···
? 0 0 0
Timer B4 mode register
(035C16)··· 0 0 ?
0 0 0 0
Timer A4 interrupt control register
(005916)···
? 0 0 0
Timer B5 mode register
(035D16)··· 0 0 ?
Timer B0 interrupt control register
(005A16)···
? 0 0 0
Interrupt cause select register
(035F16)···
SI/O3 control register
(036216)···
4016
SI/O4 control register
(036616)···
4016
UART2 special mode register 2
(037616)···
0016
UART2 special mode register
(037716)···
0016
UART2 transmit/receive mode register
(037816)···
0016
UART2 transmit/receive control register 0
(037C16)··· 0 0 0 0 1 0 0 0
UART2 transmit/receive control register 1
(037D16)··· 0 0 0 0 0 0 1 0
Timer B1 interrupt control register
(005B16)···
? 0 0 0
Timer B2 interrupt control register
(005C16)···
? 0 0 0
INT0 interrupt control register
(005D16)···
0 0 ? 0 0 0
INT1 interrupt control register
(005E16)···
0 0 ? 0 0 0
INT2 interrupt control register
(005F16)···
0 0 ? 0 0 0
0 0 0 0
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Figure 2.3.3 Device's internal status after a reset is cleared
Rev. 1.0
18
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Count start flag
(038016)···
Clock prescaler reset flag
(038116)··· 0
One-shot start flag
(038216)··· 0 0
Trigger select flag
(038316)···
Up-down flag
(038416)···
Timer A0 mode register
(039616)···
Timer A1 mode register
Timer A2 mode register
0016
D-A control register
(03DC16)···
0016
Port P0 direction register
(03E216)···
0016
0 0 0 0 0
Port P1 direction register
(03E316)···
0016
0016
Port P2 direction register
(03E616)···
0016
0016
Port P3 direction register
(03E716)···
0016
0016
Port P4 direction register
(03EA16)···
0016
(039716)···
0016
Port P5 direction register
(03EB16)···
0016
(039816)···
0016
Port P6 direction register
(03EE16)···
0016
Timer A3 mode register
(039916)···
0016
Port P7 direction register
(03EF16)···
0016
Timer A4 mode register
(039A16)···
0016
Port P8 direction register
(03F216)··· 0 0
0 0 0 0 0
Timer B0 mode register
(039B16)··· 0 0 ?
0 0 0 0
Port P9 direction register
(03F316)···
0016
Timer B1 mode register
(039C16)··· 0 0 ?
0 0 0 0
Port P10 direction register
(03F616)···
0016
Timer B2 mode register
(039D16)··· 0 0 ?
0 0 0 0
Pull-up control register 0
(03FC16)···
0016
UART0 transmit/receive mode register
(03A016)···
Pull-up control register 1(Note)
(03FD16)···
0016
UART0 transmit/receive control register 0
(03A416)··· 0 0 0 0 1 0 0 0
Pull-up control register 2
(03FE16)···
0016
UART0 transmit/receive control register 1
(03A516)··· 0 0 0 0 0 0 1 0
Port control register
(03FF16)···
0016
UART1 transmit/receive mode register
(03A816)···
0016
0016
Data registers (R0/R1/R2/R3)
000016
UART1 transmit/receive control register 0 (03AC16)··· 0 0 0 0 1 0 0 0
Address registers (A0/A1)
000016
UART1 transmit/receive control register 1 (03AD16)··· 0 0 0 0 0 0 1 0
Frame base register (FB)
000016
UART transmit/receive control register 2
Interrupt table register (INTB)
0000016
(03B016)···
0 0 0 0 0 0 0
DMA0 cause select register
(03B816)···
0016
User stack pointer (USP)
000016
DMA1 cause select register
(03BA16)···
0016
Interrupt stack pointer (ISP)
000016
A-D control register 2
(03D416)··· 0 0 0 0
Static base register (SB)
000016
A-D control register 0
(03D616)··· 0 0 0 0 0 ? ? ?
Flag register (FLG)
000016
A-D control register 1
(03D716)···
0
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
Figure 2.3.4 Device's internal status after a reset is cleared
Rev. 1.0
19
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.4 Processor Mode
(1) Types of Processor Mode
Processor mode can be used at microprocessor mode.
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “ 2.4.1 Bus
Settings” for details.)
(2) Setting Microprocessor Mode
Microprocessor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Set the processor mode bits to “112”.
Regardless of the level of the CNVSS pin, the processor mode bits can be changed by software. Therefore, never change the processor mode bits when changing the contents of other bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 2.4.1 shows the processor mode register 0 and 1.
Figure 2.4.2 shows the memory maps applicable for microprocessor mode.
Rev. 1.0
20
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Processor mode register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PM0
Address
000416
Bit symbol
PM00
When reset
0016 (Note 2)
Bit name
Processor mode bit
PM01
Function
b1 b0
0 0: Inhibited
0 1: Inhibited
1 0: Inhibited
1 1: Microprocessor mode
0 : RD,BHE,WR
1 : RD,WRH,WRL
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
AA
A
AA
R W
PM02
R/W mode select bit
PM03
Software reset bit
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
PM04
Multiplexed bus space
select bit
b5 b4
PM06
Port P40 to P43 function
select bit
0 : Address output
1 : Port function
(Address is not output)
PM07
BCLK output disable bit
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
PM05
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Inhibited
1 1 : Inhibited
Notes 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
2: If the VCC voltage is applied to the CNVSS, the value of this register when
reset is 0316. (PM00 and PM01 both are set to “1”.)
Processor mode register 1 (Note)
b7
b6
b5
b4
0
0
0 0
b3
b2
b1
b0
0
Symbol
PM1
Address
000516
Bit symbol
Bit name
When reset
00000XX02
Function
Must always be set to “0”
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
PM17
Wait bit
0 : No wait state
1 : Wait state inserted
AA
A
AAAA
AA
R W
Note : Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Figure 2.4.1 Processor mode registers
Rev. 1.0
21
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
00000 16
SFR area
00400 16
Internal
RAM area
017FF1 6
Internally
reserved area
04000 16
28000 16
External
area
Internally
reserved area
30000 16
External area :
Accessing this area allows the user to
access a device connected externally to
the microcomputer.
External
area
FFFFF 16
Figure 2.4.2 Memory maps applicable for microprosessor mode
Rev. 1.0
22
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.4.1 Bus settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change
the bus settings.Table 2.4.1 shows the factors used to change the bus settings.
Table 2.4.1 Factors for switching bus settings
Bus setting
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
Switching factor
Bit 6 of processor mode register 0
BYTE pin
Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register
0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the
address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode
register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43
become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can
be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The
internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to
“L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode
register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen.
Rev. 1.0
23
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 2.4.2 Pin functions for processor mode
Processor mode
Microprocessor modes
“00”
“01”
Multiplexed bus
space select bit
CS2 is for multiplexed bus
and others are for separate
bus
(separate bus)
8 bits
“H”
16 bits
“L”
8 bits
“H”
16 bits
“L”
P00 to P07
Data bus
Data bus
Data bus
Data bus
P10 to P17
I/O port
Data bus
I/O port
Data bus
Data bus width
BYTE pin level
P20
Address bus
/data bus (Note)
Address bus
Address bus
Address bus
P21 to P27
Address bus
data bus (Note)
Address bus
data bus (Note)
Address bus
Address bus
P30
Address bus
Address bus
data bus (Note)
Address bus
Address bus
P31 to P37
Address bus
Address bus
Address bus
Address bus
P40 to P43
Port P40 to P43
function select bit = 1
I/O port
I/O port
I/O port
I/O port
P40 to P43
Port P40 to P43
function select bit = 0
Address bus
Address bus
Address bus
Address bus
P44 to P47
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
P50 to P53
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
P54
HLDA
HLDA
HLDA
HLDA
P55
HOLD
HOLD
HOLD
HOLD
P56
ALE
ALE
ALE
ALE
P57
RDY
RDY
RDY
RDY
Note : Address bus when in separate bus mode.
Rev. 1.0
24
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.4.2 Bus Control
The following explains the signals required for accessing external devices and software waits.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
(2) Chip select signal
The chip select signal is output using the same pins as P44, P46 and to P47. Bits 0, 2 and 3 of the chip
select control register (address 000816) set each pin to function as a port or to output the chip select
signal.
_______
In microprocessor
mode,
only
CS0 outputs the chip select signal after the reset state has been can______ _______
celled. CS2,CS3 function as input ports. Figure 2.4.3 shows the chip select control register.
The chip select signal can be used to split the external area. Tables 2.4.3 show the external memory
areas specified using the chip select signal.
Table 2.4.3 External areas specified by the chip select signals
Chip select signal
Processor mode
Microprocessor mode
CS0
CS2
CS3
3000016 to
FFFFF16
(832K bytes)
0800016 to
27FFF16
(128K bytes)
0400016 to
07FFF16
(16K bytes)
Note : Address 2800016 to 2FFFF16 are reserved and cannot be used.
Chip select control register
b7
b6
b5
0
b4
b3
b2
b1
0
b0
Symbol
CSR
Address
000816
Bit name
Bit symbol
CS0 output enable bit
CS0
When reset
0116
Function
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
Always set to “0”.
Reserved bit
CS2
CS2 output enable bit
CS3
CS3 output enable bit
CS0W
CS0 wait bit
Reserved bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Always set to “0”.
CS2W
CS2 wait bit
CS3W
CS3 wait bit
0 : Wait state inserted
1 : No wait state
AA
A
A
A
AA
RW
Figure 2.4.3 Chip select control register
Rev. 1.0
25
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) Read/write signals
With a 16-bit data bus
(BYTE pin =“L”),
bit 2 of the_____
processor
mode
register 0 (address 000416) select
_____ ________
______
________
_________
the combinations of RD, BHE, and WR signals
or RD, WRL,
and WRH signals. With an 8-bit data bus
_____ ______
_______
(BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode
register 0 (address 000416) to “0”.) Tables 2.4.4 and
2.4.5 show________
the operation of these signals.
_____ ______
After a reset has been cancelled,
the combination
of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of
the processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the
protect register (address 000A16) to “1”.
_____
________
_________
Table 2.4.4 Operation of RD, WRL, and WRH signals
Data bus width
16-bit
(BYTE = “L”)
RD
L
H
H
H
WRL
H
L
H
L
_____
______
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRH
H
H
L
L
________
Table 2.4.5 Operation of RD, WR, and BHE signals
Data bus width
16-bit
(BYTE = “L”)
8-bit
(BYTE = “H”)
RD
H
L
H
L
H
L
H
L
WR
L
H
L
H
L
H
L
H
BHE
L
L
H
H
L
L
Not used
Not used
A0
H
H
L
L
L
L
H/L
H/L
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when
the ALE signal falls.
When BYTE pin = “L”
When BYTE pin = “H”
ALE
ALE
D0/A0 to D7/A7
A8 to A19
Address
Data (Note)
A0
D0/A1 to D7/A8
Address
Address
Data (Note)
Address
A9 to A19
Address
Note : Floating when reading
Figure 2.4.4 ALE signal and address/data bus
Rev. 1.0
26
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
________
(5)________
The RDY signal
RDY is a signal that facilitates access to an external
device that requires long access time. As shown
________
in Figure 2.4.5, if an “L” is being input
to the RDY at the BCLK falling edge, the bus turns to the wait
________
state. If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state.
Table 2.4.6 shows the state of the
microcomputer with the bus
in the wait state, and Figure 2.4.5
____
________
shows
an example in which the RD signal is prolonged by the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus ________
cycle in which bits 4, 6 and
7 of the chip select control register (address 000816) are set to “0”. The RDY signal is invalid
when
________
setting “1” to all bits 4, 6 and 7 of the chip select control register (address 000816), but the RDY pin
should be treated as properly as in non-using.
Table 2.4.6 Microcomputer status in ready state (Note)
Item
Status
Oscillation
On
___
_____
________
R/W signal, __________
address bus, data bus, CS
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
Maintain status when RDY signal received
On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
AAAA
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
AAAAAA
AAAAAA
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
AA
AA
: Wait using RDY signal
Accept timing of RDY signal
: Wait using software
_____
________
Figure 2.4.5 Example of RD signal extended by RDY signal
Rev. 1.0
27
MITSUBISHI MICROCOMPUTERS
M306H1SFP
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(6) Hold signal
The hold
signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L”
__________
to the HOLD pin places the microcomputer in the
hold state at the end of the current bus
access. This
__________
__________
status is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table
2.4.7 shows the microcomputer status
in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 2.4.6 Bus-using priorities
Table 2.4.7 Microcomputer status in hold state
Item
Status
Oscillation
ON
___
_____
_______
R/W signal, address bus, data bus, CS, BHE
Programmable I/O ports
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Floating
Floating
Maintains status when hold signal is received
__________
HLDA
Internal peripheral circuits
ALE signal
Output “L”
ON (but watchdog timer stops)
Undefined
(7) External bus status when the internal area is accessed
Table 2.4.8 shows the external bus status when the internal area is accessed.
Table 2.4.8 External bus status when the internal area is accessed
Item
SFR accessed
Internal RAM accessed
Address bus
Address output
Maintain status before accessed
address of external area
Data bus
When read
Floating
Floating
When write
Output data
Undefined
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
Output "H"
BHE
BHE output
Maintain status before accessed
status of external area
CS
Output "H"
Output "H"
ALE
Output "L"
Output "L"
Rev. 1.0
28
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the
protectregister (address 000A16) to “1”.
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4, 6 and 7 of the chip select control register (address 000816).
A software wait is inserted in the internal RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK
cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two
or three BCLK cycles), regardless of the contents of bits 4, 6 and 7 of the chip select control register.
Set this bit after referring to the recommended operating conditions (main clock
input oscillation fre________
quency) of the electric characteristics. However, when the user is using the RDY signal, the relevant
bit in the chip select control register’s bits 4, 6 and 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each areas selected using_______
the chip
select_______
signal. Bits 4, 6 and 7 of the chip select control register
______
correspond to chip selects CS0, CS2, and CS3. When one of these bits is set to “1”, the bus cycle is
executed in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles.
These bits default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Also, insert a software wait if using the multiplex bus to access the external memory area.
Table 2.4.9 shows the software wait and bus cycles. Figure 2.4.7 shows example bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the
protect register (address 000A16) to “1”.
Table 2.4.9 Software waits and bus cycles
Area
Wait bit
Bits 4, 6 and 7 of chip select
control register
Invalid
Invalid
2 BCLK cycles
0
Invalid
1 BCLK cycle
1
Invalid
2 BCLK cycles
Separate bus
0
1
1 BCLK cycle
Separate bus
0
0
2 BCLK cycles
Separate bus
1
0 (Note)
2 BCLK cycles
Multiplex bus
0
0
3 BCLK cycles
Multiplex bus
1
0 (Note)
3 BCLK cycles
Bus status
SFR
Internal
RAM
External
memory
area
Bus cycle
Note: When using the RDY signal, always set to “0”.
Rev. 1.0
29
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
< Separate bus (no wait) >
Bus cycle
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
Chip select
< Separate bus (with wait) >
Bus cycle
BCLK
Write signal
Read signal
Input
Output
Data bus
Address bus
Address
Address
Chip select
< Multiplexed bus >
Bus cycle
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Address
Address
Address
Data output
Address
Input
Chip select
Figure 2.4.7 Typical bus timings using software wait
Rev. 1.0
30
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.5 Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 2.5.1 Main clock and sub clock generating circuits
Main clock generating circuit
Sub clock generating circuit
• CPU’s operating clock source
• CPU’s operating clock source
• Internal peripheral units’
• Timer A/B’s count clock
operating clock source
source
Ceramic or crystal oscillator
Crystal oscillator
XIN, XOUT
XCIN, XCOUT
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Use of clock
Usable oscillator
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
2.5.1 Example of oscillator circuit
Figure 2.5.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 2.5.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using
an externally derived clock for input. Circuit constants in Figures 2.5.1 and 2.5.2 vary with each
oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
COUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 2.5.1 Examples of main clock
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 2.5.2 Examples of sub clock
Rev. 1.0
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2.5.2 Clock Control
Figure 2.5.3 shows the block diagram of the clock generating circuit.
XCIN
XCOUT
fC32
1/32
f1
CM04
f1SIO2
fAD
fC
f8SIO2
f8
Sub clock
f32SIO2
CM10 “1”
Write signal
f32
S Q
XIN
XOUT
a
RESET
Software reset
Main clock
CM02
CM05
NMI
Interrupt request
level judgment
output
AAA
AAA
b
R
c
Divider
d
CM07=0
BCLK
fC
CM07=1
S Q
WAIT instruction
R
c
b
a
1/2
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
Details of divider
Figure 2.5.3 Clock generating circuit
Rev. 1.0
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The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616).
Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the
power dissipation.After the oscillation of the main clock oscillation circuit has stabilized, the drive
capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select
bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces
the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to
stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode,
the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the X CIN-X COUT drive capacity select bit (bit 3 at address
000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation.
This bit changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock
by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal
can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416).
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2 , f8SIO2,f32SIO2 ,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral
function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
Rev. 1.0
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Figure 2.5.4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Address
000616
Bit symbol
When reset
4816
Bit name
Function
b1 b0
AAAA
AA
AAA
A
AAAA
AA
A
AAAA
AA
AAA
AAA
RW
Clock output function
select bit
0 0 : I/O port P57
0 1 : Inhibited
1 0 : Inhibited
1 1 : Inhibited
CM02
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
CM03
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
CM04
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM05
Main clock (XIN-XOUT)
stop bit (Notes 3,4,5)
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Division by 8 mode
CM07
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
CM00
CM01
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with XIN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns
pulled up to XOUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included.
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0 0 0 0
b0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
2016
Bit name
All clock stop control bit
(Note4)
Reserved bit
Function
0 : Clock on
1 : All clocks off (stop mode)
Always set to “0”
CM15
XIN-XOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
CM16
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
CM17
AAAA
AAAAA
AAA
RW
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state.
Figure 2.5.4 Clock control registers 0 and 1
Rev. 1.0
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2.5.3 Stop Mode
Writing “1” to the wain clock and sub-clock stop control bit (bit 0 at address 000716) stops oscillation
and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained
provided that VCC remains above 2V.
The internal oscillator circuit of expansion function (OSD function/ data slice function/ data encode
function/ humming function) stops oscillation when expansion register CK_VCO, XTAL_VCO,
PDC_VCO_ON, VPS_VCO_ON = "L".
Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and
timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2)
SI/O3,4 functions provided an external clock is selected. Table 2.5.2 shows the status of the ports in
stop mode.Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to
cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt
routine is executed.When shifting from high-speed/medium-speed mode to stop mode and at a reset,
the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/
low power dissipation mode to stop mode, the value before stop mode is retained.
Table 2.5.2 Port status during stop mode
Pin
_______ ______ _______
Address
bus, data bus, CS0, CS2, CS3
_____ ______ _______ ________ _________
RD,
WR, BHE, WRL, WRH
_________
HLDA, BCLK
ALE
Port
Microprocessor mode
Retains status before stop mode
“H”
“H”
“H”
Retains status before stop mode
Rev. 1.0
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2.5.4 Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode.
In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT
peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to
the internal peripheral functions, allowing power dissipation to be reduced. Table 2.5.3 shows the
status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode,
the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected
when the WAIT instruction was executed.
Table 2.5.3 Port status during wait mode
Pin
_______ ______ _______
Address
bus, data bus, CS0, CS2, CS3
_____ ______ _______ ________ _________
RD,
WR, BHE, WRL, WRH
_________
HLDA, BCLK
ALE
Port
Microprocessor mode
Retains status before stop mode
“H”
“H”
“H”
Retains status before stop mode
Rev. 1.0
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2.5.5 Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source
for BCLK. Table 2.5.4 shows the operating modes corresponding to the settings of system clock
control registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at
address 000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a
reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop
mode is retained. The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized
before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after
the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized
immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note :
Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for the
oscillation to stabilize before switching over the clock.
Table 2.5.4 Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
0
1
Invalid
1
0
Invalid
Invalid
1
0
Invalid
1
0
Invalid
Invalid
0
0
0
0
0
1
1
0
0
1
0
0
Invalid
Invalid
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
1
1
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
Rev. 1.0
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2.5.6 Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates
according to its assigned clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are
those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
The main clock and the sub-clock oscillators stop. The CPU and all built-in peripheral functions stop.
This mode, among the three modes listed here, is the most effective in decreasing power consumption.
Figure 2.5.5 is the state transition diagram of the above modes.
Rev. 1.0
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Transition of stop mode, wait mode
Reset
Main clock is stopped
Sub clock is stopped
CM10 = “1”
Stop mode
Interrupt
Medium-speed mode
(divided-by-8 mode)
Wait mode
Interrupt
Main clock is stopped
Sub clock is stopped Interrupt
Stop mode
CM10 = “1”
Stop mode
Interrupt
CPU operation stopped
WAIT
instruction
High-speed/mediumspeed mode
Wait mode
Interrupt
Main clock is stopped
Sub clock is stopped
CM10 = “1”
CPU operation stopped
WAIT
instruction
CPU operation stopped
WAIT
instruction
Low-speed/low power
dissipation mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
Main clock is oscillating CM04 = “0”
Sub clock is oscillating
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XCIN)
CM07 = “1”
CM07 = “1”
(Note 2)
CM05 = “0”
CM04 = “0”
CM06 = “0”
(Notes 1,3)
Main clock is oscillating
Sub clock is stopped
CM05 = “1”
CM04 = “1”
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
CM07 = “1” (Note 2)
CM05 = “1”
BCLK : f(XCIN)
CM07 = “1”
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 2.5.5 State transition diagram of Power control mode
Rev. 1.0
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2.6 Protection
The protection function is provided so that the values in important registers cannot be changed in the
event that the program runs out of control. Figure 2.6.1 shows the protect register. The values in the
processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock
control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction
register (address 03F316) , SI/O3 control register (address 036216) and SI/O4 control register (address
036616 ) can only be changed when the respective bit in the protect register is set to “1”. Therefore,
important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register and SI/Oi control register
(i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically
reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0
at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically
return to “0” after a value has been written to an address. The program must therefore be written to return
these bits to “0”.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Bit symbol
Address
000A16
Bit name
When reset
XXXXX0002
Function
PRC0
Enables writing to system clock
control registers 0 and 1 (addresses 0 : Write-inhibited
1 : Write-enabled
000616 and 000716)
PRC1
Enables writing to processor mode
0 : Write-inhibited
registers 0 and 1 (addresses 000416
1 : Write-enabled
and 000516)
PRC2
Enables writing to port P9 direction
register (address 03F316) and to
0 : Write-inhibited
SI/Oi control register (i=3,4)
1 : Write-enabled
(addresses 036216 and 036616)(Note)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
AA
A
AA
A
AAA
AAA
R W
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 2.6.1 Protect register
Rev. 1.0
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2.7 Interrupt
2.7.1 Interrupt
Figure 2.7.1 lists the types of interrupts.










Hardware
Special
Peripheral I/O (Note)
















Interrupt
Software
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
NMI
________
DBC
Watchdog timer
Single step
Address matched
_______
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 2.7.1 Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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2.7.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are nonmaskable interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the
stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0”
and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning
from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt
request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make
a shift.
Rev. 1.0
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2.7.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset
occurs if an “L” is input to the RESET pin.
_______
• NMI_______
interrupt
_______
An
NMI
interrupt
occurs
if
an
“L”
is
input
to
the
NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated
by the address match interrupt register is executed with the address match interrupt enable bit set to
“1”.
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs. For address match interrupt, see 2.7.10 Address match
Interrupt.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B5 interrupt
These
are interrupts that ________
timer B generates.
________
• INT0
interrupt through INT5 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
Rev. 1.0
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2.7.4 Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt
vector table. Set the first address of the interrupt routine in each vector table. Figure 2.7.2 shows the
format for specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed
and variable vector table in which addresses can be varied by the setting.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
MSB
LSB
Vector address + 0
Low address
Vector address + 1
Mid address
Vector address + 2
0000
High address
Vector address + 3
0000
0000
Figure 2.7.2 Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an
area extending from FFFDC16 to FFFFF16 . One vector table comprises four bytes. Set the first
address of interrupt routine in each vector table. Table 2.7.1 shows the interrupts assigned to the
fixed vector tables and addresses of vector tables.
Table 2.7.1 Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Undefined instruction
Overflow
BRK instruction
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF 16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
Single step (Note)
FFFEC16 to FFFEF16
Watchdog timer
FFFF016 to FFFF3 16
DBC (Note)
FFFF416 to FFFF7 16
Do not use
_______
NMI
FFFF816 to FFFFB16
External interrupt by input to NMI pin
Reset
FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
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• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the
address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 2.7.2
shows the interrupts assigned to the variable vector tables and addresses of vector tables.
Table 2.7.2 Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number
Vector table address
Interrupt source
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note 1)
BRK instruction
Software interrupt number 4
+16 to +19 (Note 1)
INT3
Software interrupt number 5
+20 to +23 (Note 1)
Timer B5
Software interrupt number 6
+24 to +27 (Note 1)
Timer B4
Software interrupt number 7
+28 to +31 (Note 1)
Timer B3
Software interrupt number 8
+32 to +35 (Note 1)
SI/O4/INT5
(Note 2)
(Note 2)
Software interrupt number 9
+36 to +39 (Note 1)
SI/O3/INT4
Software interrupt number 10
+40 to +43 (Note 1)
Bus collision detection
DMA0
Software interrupt number 11
+44 to +47 (Note 1)
Software interrupt number 12
+48 to +51 (Note 1)
DMA1
Software interrupt number 13
+52 to +55 (Note 1)
Key input interrupt
Software interrupt number 14
+56 to +59 (Note 1)
A-D
Software interrupt number 15
+60 to +63 (Note 1)
UART2 transmit/NACK (Note 3)
Software interrupt number 16
+64 to +67 (Note 1)
UART2 receive/ACK (Note 3)
Software interrupt number 17
+68 to +71 (Note 1)
UART0 transmit
Software interrupt number 18
+72 to +75 (Note 1)
UART0 receive
Software interrupt number 19
+76 to +79 (Note 1)
UART1 transmit
Software interrupt number 20
+80 to +83 (Note 1)
UART1 receive
Software interrupt number 21
+84 to +87 (Note 1)
Timer A0
Software interrupt number 22
+88 to +91 (Note 1)
Timer A1
Software interrupt number 23
+92 to +95 (Note 1)
Timer A2
Software interrupt number 24
+96 to +99 (Note 1)
Timer A3
Software interrupt number 25
+100 to +103 (Note 1)
Timer A4
Software interrupt number 26
+104 to +107 (Note 1)
Timer B0
Software interrupt number 27
+108 to +111 (Note 1)
Timer B1
Software interrupt number 28
+112 to +115 (Note 1)
Timer B2
Software interrupt number 29
+116 to +119 (Note 1)
INT0
Software interrupt number 30
+120 to +123 (Note 1)
INT1
Software interrupt number 31
+124 to +127 (Note 1)
INT2
Software interrupt number 32
+128 to +131 (Note 1)
to
Software interrupt number 63
to
+252 to +255 (Note 1)
Software interrupt
Remarks
Cannot be masked I flag
Cannot be masked I flag
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: It is selected by interrupt request cause bit (bit 6, 7 in address 035F16 ).
Note 3: When IIC mode is selected, NACK and ACK interrupts are selected.
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2.7.5 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or
absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level
selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable
flag (I flag) and the IPL are located in the flag register (FLG).
Figure 2.7.3 shows the memory map of the interrupt control registers.
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Interrupt control register
AAA
AA
A
AAA
AA
A
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBiIC(i=3 to 5)
BCNIC
DMiIC(i=0, 1)
KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Bit symbol
ILVL0
Address
004516 to 004716
004A16
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
Bit name
Interrupt priority level
select bit
ILVL2
IR
Function
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
ILVL1
Interrupt request bit
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
R
W
AA
AA
AA
AA
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
Nothing is assigned.
(Note 1)
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be “0”.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
AAA
A
AA
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
Address
INTiIC(i=3)
004416
SiIC/INTjIC (i=4, 3)
004816, 004916
(j=4, 5)
INTiIC(i=0 to 2)
005D16 to 005F16
Bit symbol
ILVL0
ILVL2
POL
XX00X0002
Bit name
Interrupt priority level
select bit
ILVL1
IR
When reset
XX00X0002
XX00X0002
Interrupt request bit
Polarity select bit
Reserved bit
Function
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
Nothing is assigned.
AA
AA
A
A
AA
AA
AA
AA
R
W
(Note 1)
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be “0”.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Figure 2.7.3 Interrupt control registers
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(1) Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting
this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This
flag is set to “0” after reset.
(2) Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware.
The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
(3) Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component
bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is
compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher
than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 2.7.3 shows the settings of interrupt priority levels and Table 2.7.4 shows the interrupt levels
enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL
are independent, and they are not affected by one another.
Table 2.7.3 Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
Table 2.7.4 Interrupt levels enabled according
to the contents of the IPL
Priority
order
b2 b1 b0
IPL
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Level 0 (interrupt disabled)
0
0
1
Level 1
0
1
0
0
1
1
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Interrupt levels 2 and above are enabled
Level 2
0
1
0
Interrupt levels 3 and above are enabled
1
Level 3
0
1
1
Interrupt levels 4 and above are enabled
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
Low
High
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(4) Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register
after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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2.7.6 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to
the instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the
interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 00000 16.
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag
(U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt
numbers 32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
( f) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the
first address of the interrupt routine.
Note: This register cannot be utilized by the user.
(1) Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and
the time required for executing the interrupt sequence (b). Figure 2.7.4 shows the interrupt response
time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
Instruction in
interrupt routine
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 2.7.4 Interrupt response time
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Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 2.7.5
Table 2.7.5 Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Notes 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Notes 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address bus
Address
0000
Interrupt
information
Data bus
R
Indeterminate
Indeterminate
SP-2
SP-2
contents
SP-4
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 2.7.5 Time required for executing the interrupt sequence
(2) Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values
shown in Table 2.7.6 is set in the IPL.
Table 2.7.6 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Value set in the IPL
_______
Watchdog timer, NMI
7
Reset
0
Other
Not changed
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(3) Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits
and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order
bits of the program counter. Figure 2.7.6 shows the state of the stack as it was before the acceptance
of the interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
Stack pointer
value before
interrupt occurs
Flag register
(FLGH)
[SP]
New stack
pointer value
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 2.7.6 State of stack before and after acceptance of interrupt request
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The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits
at a time. Figure 2.7.7 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
Saved simultaneously,
all 8 bits
(1)
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 2.7.7 Operation of saving registers
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(4) Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program
that was being executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
(5) Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest
priority), watchdog timer interrupt, etc. are regulated by hardware.
Figure 2.7.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
_______
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 2.7.8 Hardware interrupts priorities
(6) Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the
highest priority level. Figure 2.7.9 shows the circuit that judges the interrupt priority level.
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Priority level of each interrupt
INT1
Level 0 (initial value)
High
Timer B2
Timer B0
Timer A3
Timer A1
Timer B4
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3
Timer B5
UART1 reception
UART0 reception
Priority of peripheral I/O interrupts
(if priority levels are same)
UART2 reception/ACK
A-D conversion
DMA1
Bus collision detection
Serial I/O4/INT5
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission/NACK
Key input interrupt
DMA0
Serial I/O3/INT4
Processor interrupt priority level (IPL)
Low
Interrupt enable flag (I flag)
Address match
Interrupt
request
accepted
Watchdog timer
DBC
NMI
Reset
Figure 2.7.9 Maskable interrupts priorities (peripheral I/O interrupts)
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______
2.7.7
INT________
Interrupt
________
INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the
polarity select bit.
________
Of interrupt control registers, 004816 is used both as serial I/O4 and external interrupt
INT5 input
________
control register, and 004916 is used both as serial I/O3 and as external interrupt INT4 input control
register. Use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select
register (035F16) - to specify which interrupt request cause to select. After having set an interrupt
request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt.
Either of the interrupt control registers - 004816, 004916 - has the polarity-switching bit. Be sure to set
this bit to “0” to select an serial I/O as the interrupt request cause.
As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling
edge by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select
register (035F16). To select both edges, set the polarity switching bit of the corresponding interrupt
control register to ‘falling edge’ (“0”).
Figure 2.7.10 shows the Interrupt request cause select register.
AA
A
AA
A
AA
AA
AA
Interrupt request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR
Bit symbol
Address
035F16
When reset
0016
Bit name
Fumction
IFSR0
INT0 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR1
INT1 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR2
INT2 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR3
INT3 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR4
INT4 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR5
INT5 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR6
Interrupt request cause
select bit
0 : SIO3
1 : INT4
IFSR7
Interrupt request cause
select bit
0 : SIO4
1 : INT5
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
R W
Figure 2.7.10 Interrupt request cause select register
Rev. 1.0
56
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
______
2.7.8______
NMI Interrupt
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI
interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit
5 at address 03F016).
This pin cannot be used as a normal port input.
2.7.9 Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a
key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for
cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not
use P104 to P107 as A-D input ports. Figure 2.7.11 shows the block diagram of the key input interrupt.
Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins
are not detected as an interrupt.
Port P104-P107 pull-up
select bit
Pull-up
transistor
Key input interrupt control register
Port P107 direction
register
(address 004D16)
Port P107 direction register
P107/KI3
Pull-up
transistor
Port P106 direction
register
Interrupt control circuit
P106/KI2
Pull-up
transistor
Key input interrupt
request
Port P105 direction
register
P105/KI1
Pull-up
transistor
Port P104 direction
register
P104/KI0
Figure 2.7.11 Block diagram of key input interrupt
Rev. 1.0
57
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.7.10 Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents
match the program counter value. Two address match interrupts can be set, each of which can be
enabled and disabled by an address match interrupt enable bit. Address match interrupts are not
affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the
program counter (PC) for an address match interrupt varies depending on the instruction being executed.
Figure 2.7.12 shows the address match interrupt-related registers.
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AA
A
AA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Bit symbol
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
Function
Address setting register for address match interrupt
When reset
X0000016
X0000016
AAA
AAA
Values that can be set R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 2.7.12 Address match interrupt-related registers
Rev. 1.0
58
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.7.11 Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt
written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets
enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway.
Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack
point at the beginning of a program.
Concerning the first instruction immediately after reset, gener_______
ating_______
any interrupts including the NMI interrupt is prohibited.
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor
(pull-up)
if unused. Be sure to work on it.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading
the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
• Do not reset the CPU with the input to the NMI pin being_______
in the “L” state.
• Do not _______
attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input
to the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is
turned down.
_______
• Do not_______
attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input
to the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is
saved. In this instance,
the CPU is returned to the normal state by a later interrupt.
_______
• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the
CPU.
(4) External interrupt
________
• Either an________
“L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
through INT5 regardless________
of the CPU
operation clock.
________
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to
"1". After changing the______
polarity, set the interrupt request bit to "0". Figure 2.7.13 shows the procedure for changing the INT interrupt generate factor.
Rev. 1.0
59
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 2.7.13 Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request
for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control
register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been
generated. This will depend on the instruction. If this creates problems, use the below instructions to
change the register.
Instructions : AND, OR, BCLR, BSET
Rev. 1.0
60
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.8 Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer
is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A
watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is
selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler
division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2
regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's
period can be calculated as given below. The watchdog timer's period is, however, subject to an error due
to the pre-scaler.
With XIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (2) X watchdog timer count (32768)
BCLK
For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and
when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The
count is started by writing to the watchdog timer start register (address 000E16).
Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timerrelated registers.
Prescaler
1/16
BCLK
1/128
“CM07 = 0”
“WDC7 = 0”
“CM07 = 0”
“WDC7 = 1”
Watchdog timer
HOLD
Watchdog timer
interrupt request
“CM07 = 1”
1/2
Write to the watchdog timer
start register
(address 000E16)
Set to
“7FFF16”
RESET
Figure 2.8.1 Block diagram of watchdog timer
Rev. 1.0
61
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
WDC
Bit symbol
Address
000F16
When reset
000XXXXX2
Function
Bit name
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
AA
AA
A
AA
A
AA
A
R W
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
A
R W
Figure 2.8.2 Watchdog timer control and start registers
Rev. 1.0
62
MITSUBISHI MICROCOMPUTERS
M306H1SFP
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.9 DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent
to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word
(16-bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 2.9.1 shows the block
diagram of the DMAC. Table 2.9.1 shows the DMAC specifications. Figures 2.9.2 to 2.9.4 show the
registers used by the DMAC.
AA
AAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAA
AA
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAA
A
AA
A
A
AAA
AA
A
AAA A
AA
AA A AA
AA
AA
AA
A
A
AA
A
AA
AA
A
AAA A
AA
AAAA AA AA
AA
AA
AA
A
A
AA
AA
A
A
A
AA
A
A AA
AA
AA
AA
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003916, 003816)
DMA1 transfer counter TCR1 (16)
DMA latch high-order bits
DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 2.9.1 Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA
transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by
the interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer
request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the
DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with
the number of transfers. For details, see the description of the DMA request bit.
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 2.9.1 DMAC specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [0020 16 to 003F16 ] cannot be accessed)
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________ ________
________
DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
Serial I/O3, 4 interrpt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive
• When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, the
Forward address pointer and
value of one of source pointer and destination pointer - the one specified for the
reload timing for transfer
forward direction - is reloaded to the forward direction address pointer,and the value
counter
of the transfer counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
Rev. 1.0
64
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
DMA0 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0SL
Bit symbol
DSEL0
Address
03B816
When reset
0016
Function
Bit name
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
b3 b2 b1 b0
R
W
AAA
AAA
AAA
AA
A
AAA
0 0 0 0 : Falling edge of INT0 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS=0)
/two edges of INT0 pin (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
Timer B3 (DMS=1)
1 0 0 0 : Timer B1 (DMS=0)
Timer B4 (DMS=1)
1 0 0 1 : Timer B2 (DMS=0)
Timer B5 (DMS=1)
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMS
DMA request cause
expansion bit
0 : Normal
1 : Expanded cause
DSR
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
AAA
AA
A
AAA
Figure 2.9.2 DMAC register (1)
Rev. 1.0
65
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
DMA1 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM1SL
Address
03BA16
Function
Bit name
Bit symbol
DSEL0
When reset
0016
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3(DMS=0)
/serial I/O3 (DMS=1)
0 1 1 0 : Timer A4 (DMS=0)
/serial I/O4 (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMS
DMA request cause
expansion bit
0 : Normal
1 : Expanded cause
DSR
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
AA
A
AA
A
AA
AA
AA
A
A
AA
R
W
DMAi control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMiCON(i=0,1)
Bit symbol
Address
002C16, 003C16
When reset
00000X002
Bit name
Function
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMAS
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
DMAE
DMA enable bit
0 : Disabled
1 : Enabled
DSD
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DAD
Destination address
0 : Fixed
direction select bit (Note 3) 1 : Forward
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
AA
AA
AA
AA
AA
AA
AA
R
W
(Note 2)
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 2.9.3 DMAC register (2)
Rev. 1.0
66
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
DMAi source pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
• Source pointer
Stores the source address
R W
AA
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi destination pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
• Destination pointer
Stores the destination address
AAAA
R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
Function
• Transfer counter
Set a value one less than the transfer count
When reset
Indeterminate
Indeterminate
Transfer count
specification
000016 to FFFF16
AA
R W
Figure 2.9.4 DMAC register (3)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses and,
the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) , the 16 bits of data are sent in
two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for
writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal RAM, and SFR), these areas are accessed using the data size
selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 2.9.5 shows the example of the transfer cycles for a source read. For convenience, the destination
write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In
reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure
2.9.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the
source read cycle and the destination write cycle.
Rev. 1.0
68
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1 Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source + 1 Destination
Source
Dummy
cycle
CPU use
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination Dummy
cycle
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 2.9.5 Example of the transfer cycles for a source read
Rev. 1.0
69
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 2.9.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 2.9.2 No. of DMAC transfer cycles
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Microprocessor mode
Bus width
Access address No. of read No. of write
cycles
cycles
16-bit
Even
1
1
(BYTE= “L”)
Odd
1
1
8-bit
Even
1
1
(BYTE = “H”)
Odd
1
1
16-bit
Even
1
1
(BYTE = “L”)
Odd
2
2
8-bit
Even
2
2
(BYTE = “H”)
Odd
2
2
Coefficient j, k
Internal memory
Internal RAM
Internal RAM
No wait
With wait
1
2
SFR area
2
External memory
Separate bus Separate bus
No wait
With wait
1
2
Multiplex
bus
3
Rev. 1.0
70
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.9.1 DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for
the forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations
given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the
DMA enable bit.
2.9.2 DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors for each channel.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and
software DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.
The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's
state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before
data transfer starts.
In addition, it can be set to "0" by use of a program, but cannot be set to "1".
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor
selection bit is changed.
The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether
the DMAC is active, read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1"
due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control
register to turn to "1" due to several factors.
Turning the DMA request bit to "1" due to an internal factor is timed to be effected immediately before
the transfer starts.
(2) External factors
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends
on which DMAC channel is used).
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input
from these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with
the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data
transfer starts similarly to the state in which an internal factor is selected.
Rev. 1.0
71
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period
from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels
concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start
data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU
finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 2.9.6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
DMA1
CPU
INT0
DMA0
request bit
AAAA
AAAAAAAA
AAAA
AAAAAA
AA
AAAAA
AA
A
Obtainm
ent of the
bus right
INT1
DMA1
request bit
Figure 2.9.6 An example of DMA transfer effected by external factors
Rev. 1.0
72
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.10 Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers
B (six). All these timers function independently.
Figures 2.10.1 and 2.10.2 show the block diagram of timers.
Clock prescaler
f1
XIN
f8
1/8
1/4
f32
1/32
XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
fC32
Reset
f1 f8 f32 fC32
• Timer mode
• One-shot mode
• PWM mode
Timer A0 interrupt
TA0IN
Noise
filter
Timer A0
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
TA1IN
Noise
filter
Timer A1 interrupt
Timer A1
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A2 interrupt
TA2IN
Noise
filter
Timer A2
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A3 interrupt
TA3IN
Noise
filter
Timer A3
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A4 interrupt
TA4IN
Noise
filter
Timer A4
• Event counter mode
Timer B2 overflow
Note 1: The TA0IN pin (P71) is shared with RxD2 and the TB5IN pin, so be careful.
Figure 2.10.1 Timer A block diagram
Rev. 1.0
73
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Clock prescaler
f1
XIN
f8
1/8
1/4
f32
fC32
1/32
XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
Reset
f1 f8 f32 fC32
Timer A
• Timer mode
• Pulse width measuring mode
TB0IN
Timer B0 interrupt
Noise
filter
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB1IN
Noise
filter
Timer B1 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB2IN
Noise
filter
Timer B2 interrupt
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB3IN
Noise
filter
Timer B3 interrupt
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB4IN
Noise
filter
Timer B4 interrupt
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB5IN
Noise
filter
Timer B5 interrupt
Timer B5
• Event counter mode
Note 1: The TB5IN pin (P71) is shared with RxD2 and the TA0IN pin, so be careful.
Figure 2.10.2 Timer B block diagram
Rev. 1.0
74
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.10.1 Timer A
Figure 2.10.3 shows the block diagram of timer A. Figures 2.10.4 to 2.10.6 show the timer A-related
registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai
mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “0000 16”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
AAA
AAA
AA
AA
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1
f8
f32
Low-order
8 bits
• Timer
(gate function)
fC32
High-order
8 bits
Reload register (16)
• Event counter
Counter (16)
Polarity
selection
Up count/down count
Clock selection
TAiIN
(i = 0 to 4)
Always down count except
in event counter mode
Count start flag
(Address 038016)
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Down count
TB2 overflow
External
trigger
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Up/down flag
(Address 038416)
Addresses
038716 038616
038916 038816
038B16 038A16
038D16 038C16
038F16 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Figure 2.10.3 Block diagram of timer A
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
Bit name
Operation mode select bit
TMOD1
MR0
MR1
Address
When reset
039616 to 039A16
0016
Function
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Function varies with each operation mode
MR2
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Figure 2.10.4 Timer A-related registers (1)
AA
A
A
A
AA
A
AA
A
A
A
A
AA
RW
Rev. 1.0
75
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Timer Ai register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Address
038716,0386 16
038916,0388 16
038B16,038A 16
038D16,038C 16
038F16,038E 16
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
Values that can be set
• Timer mode
Counts an internal count source
000016 to FFFF 16
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF 16
• One-shot timer mode
Counts a one shot width
0000 16 to FFFF 16
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE 16
R W
0016 to FE 16
(Both high-order
and low-order
addresses)
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
Note 1: Read and write data in 16-bit units.
Note 2: In the case of using “Event counter mode” as “Free-Run type”, the timer register
contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
0380 16
Bit symbol
When reset
0016
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
R W
0 : Stops counting
1 : Starts counting
Up/down flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UDF
Address
038416
Bit symbol
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
TA2P
Timer A2 two-phase pulse
signal processing select bit
TA3P
Timer A3 two-phase pulse
signal processing select bit
TA4P
Timer A4 two-phase pulse
signal processing select bit
When reset
0016
Function
R W
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Figure 2.10.5 Timer A-related registers (2)
Rev. 1.0
76
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
One-shot start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
ONSF
b0
Address
038216
When reset
00X000002
Bit symbol
Bit name
Function
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
1 : Timer start
When read, the value is “0”
A
A
A
AA
A
AA
A
A
AA
AA
AA
AA
RW
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TA0TGL
Timer A0 event/trigger
select bit
TA0TGH
b7 b6
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
Trigger select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TRGSR
Bit symbol
TA1TGL
Address
038316
Bit name
Timer A1 event/trigger
select bit
TA1TGH
TA2TGL
Timer A2 event/trigger
select bit
TA2TGH
TA3TGL
Timer A3 event/trigger
select bit
TA3TGH
TA4TGL
Timer A4 event/trigger
select bit
TA4TGH
When reset
0016
Function
b1 b0
AA
AA
AA
AA
AA
AA
AA
AA
R W
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
b3 b2
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
b5 b4
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX2
Function
RW
AAAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAAA
AA
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
Figure 2.10.6 Timer A-related registers (3)
Rev. 1.0
77
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 2.10.1) Figure 2.10.7
shows the timer Ai mode register in timer mode.
Table 2.10.1 Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing counting
1/(n+1) n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
When the timer underflows
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode
select bit
Function
b1 b0
0 0 : Timer mode
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
Gate function select bit
b4 b3
AA
AA
AA
AAA
A
AA
AA
AA
AA
RW
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR2
MR3
0 (Must always be fixed to “0” in timer mode)
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Figure 2.10.7 Timer Ai mode register in timer mode
Rev. 1.0
78
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a twophase external signal. Table 2.10.2 lists timer specifications when counting a single-phase external
signal. Figure 2.10.8 shows the timer Ai mode register in event counter mode.
Table 2.10.3 lists timer specifications when counting a two-phase external signal. Figure 2.10.9
shows the timer Ai mode register in event counter mode.
Table 2.10.2 Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
Programmable I/O port or count source input
TAiOUT pin function
Programmable I/O port, pulse output, or up/down count select input
Read from timer
Count value can be read out by reading timer Ai register
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
TAiMR(i = 0, 1)
0 1
Address
039616, 039716
When reset
0016
Function
AAAA
AAA
AA
AAA
A
AAA
A
AAA
A
AAA
AA
A
Bit symbol
Bit name
TMOD0
Operation mode select bit
b1 b0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
MR2
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
0 1 : Event counter mode (Note 1)
TMOD1
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
select bit
TCK1
Invalid in event counter mode
Can be “0” or “1”
0 : Reload type
1 : Free-run type(Note 5)
RW
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Note 5: In the case of using “Event counter mode” as “Free-Run type”, the timer register
contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Figure 2.10.8 Timer Ai mode register in event counter mode
Rev. 1.0
79
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 2.10.3 Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4)
Item
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
Timer overflows or underflows
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
• Normal processing operation
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
count
Down
count
Down
count
Down
count
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges
Count down all edges
Count up all edges
Count down all edges
TAiIN
(i=3,4)
Note: This does not apply when the free-run function is selected.
Rev. 1.0
80
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7
b6
b5
b4
b3
b2
0
b1
b0
0 1
Symbol
Address
When reset
0016
TAiMR(i = 2 to 4) 039816 to 039A16
Bit symbol
TMOD0
Bit name
Operation mode select bit
TMOD1
Function
b1 b0
0 1 : Event counter mode
AA
A
AA
A
AA
AA
AA
AA
AA
AA
R W
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
MR2
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
MR3
0 : (Must always be “0” in event counter mode)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type(Note 6)
TCK1
Two-phase pulse signal
processing operation
select bit (Note 4)(Note 5)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Note 6: In the case of using “Event counter mode” as “Free-Run type”, the timer register
contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Timer Ai mode register
(When using two-phase pulse signal processing)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 0 0 0 1
Symbol
Address
When reset
TAiMR(i = 2 to 4) 039816 to 039A16
0016
Bit symbol
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
MR1
Function
b1 b0
0 1 : Event counter mode
0 (Must always be “0” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
1 (Must always be “1” when using two-phase pulse signal
processing)
MR3
0 (Must always be “0” when using two-phase pulse signal
processing)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type(Note 3)
TCK1
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
RW
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Note 3: In the case of using “Event counter mode” as “Free-Run type”, the timer register
contents may be unkown when counting begins.(Refer 3. Usage Precaution.)
Figure 2.10.9 Timer Ai mode register in event counter mode
Rev. 1.0
81
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 2.10.4) When a trigger occurs, the timer starts
up and continues operating for a given period. Figure 2.10.10 shows the timer Ai mode register in
one-shot timer mode.
Table 2.10.4 Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : Set value
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
The count reaches 000016
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
1 0
Symbol
Address
When reset
TAiMR(i = 0 to 4) 039616 to 039A16
0016
Bit symbol
Bit name
TMOD0
Operation mode select bit
b1 b0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAiIN pin's input signal (Note 3)
MR2
Trigger select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
MR3
0 (Must always be “0” in one-shot timer mode)
TCK0
Count source select bit
TMOD1
TCK1
Function
1 0 : One-shot timer mode
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
AA
AA
AA
AA
A
RW
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Figure 2.10.10 Timer Ai mode register in one-shot timer mode
Rev. 1.0
82
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 2.10.5) In this mode,
the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator.
Figure 2.10.11 shows the timer Ai mode register in pulse width modulation mode. Figure 2.10.12
shows the example of how a 16-bit pulse width modulator operates. Figure 2.10.13 shows the example of how an 8-bit pulse width modulator operates.
Table 2.10.5 Timer specifications in pulse width modulation mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• High level width
n / fi n : Set value
• Cycle time
(216-1) / fi fixed
• High level width n (m+1) / fi
n : values set to timer Ai register’s high-order address
• Cycle time
(28 -1) (m+1) / fi
m : values set to timer Ai register’s low-order address
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
PWM pulse goes “L”
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 1
1
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode
select bit
Function
b1 b0
1 1 : PWM mode
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
MR0
1 (Must always be “1” in PWM mode)
MR1
External trigger select
bit (Note 1)
0: Falling edge of TAiIN pin's input signal (Note 2)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
Trigger select bit
0: Count start flag is valid
1: Selected by event/trigger select register
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
TCK1
R W
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0”.
Figure 2.10.11 Timer Ai mode register in pulse width modulation mode
Rev. 1.0
83
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Condition : Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X (2 16 – 1)
Count source
“H”
TAiIN pin
input signal
“L”
Trigger is not generated by this signal
1 / fi X n
PWM pulse output
from TAiOUT pin
“H”
Timer Ai interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16.
Figure 2.10.12 Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (2 8 – 1)
Count source (Note1)
TAiIN pin input signal
“H”
“L”
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fi X (m + 1) X n
PWM pulse output
from TAiOUT pin
“H”
Timer Ai interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16.
Figure 2.10.13 Example of how an 8-bit pulse width modulator operates
Rev. 1.0
84
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.10.2 Timer B
Figure 2.10.14 shows the block diagram of timer B. Figures 2.10.15 and 2.10.16 show the timer Brelated registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period
or pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f1
• Timer
• Pulse period/pulse width measurement
f8
f32
fC32
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
Reload register (16)
(address 038016)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
TBj overflow
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Address
039116 039016
039316 039216
039516 039416
035116 035016
035316 035216
035516 035416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Figure 2.10.14 Block diagram of timer B
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
TBiMR(i = 0 to 5) 039B16 to 039D16
035B16 to 035D16
Bit symbol
TMOD0
Function
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00XX00002
00XX00002
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
Function varies with each operation mode
MR1
MR2
AAA
AAA
AAA
AAA
A
AA
A
AA
A
AAA
A
AA
AAA
R
W
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 2.10.15 Timer B-related registers (1)
Rev. 1.0
85
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
b0
Address
039116, 039016
039316, 039216
039516, 039416
035116, 035016
035316, 035216
035516, 035416
Function
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Values that can be set
• Timer mode
Counts the timer's period
000016 to FFFF16
• Event counter mode
Counts external pulses input or a timer overflow
000016 to FFFF16
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
A
A
A
RW
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
038016
When reset
0016
A
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
A
Bit name
Bit symbol
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
RW
0 : Stops counting
1 : Starts counting
Timer B3, 4, 5 count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Address
034016
When reset
000XXXXX2
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
A
Bit symbol
Bit name
Function
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be “0”.
TB3S
Timer B3 count start flag
TB4S
Timer B4 count start flag
TB5S
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX2
Function
R W
Nothing is assigned.
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be “0”.
CPSR
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
Figure 2.10.16 Timer B-related registers (2)
Rev. 1.0
86
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 2.10.6) Figure 2.10.17
shows the timer Bi mode register in timer mode.
Table 2.10.6 Timer specifications in timer mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Programmable I/O port
Read from timer
Count value is read out by reading timer Bi register
Write to timer
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
AA
A
AA
A
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
TBiMR(i=0 to 5)
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode select bit
TMOD1
MR0
MR1
MR2
When reset
00XX00002
00XX00002
Function
b1 b0
0 0 : Timer mode
Invalid in timer mode
Can be “0” or “1”
0 (Fixed to “0” in timer mode ; i = 0, 3)
Nothing is assiigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be indeterminate.
MR3
Invalid in timer mode.
In an attempt to write to this bit, write “0”. The value, if read in
timer mode, turns out to be indeterminate.
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
AAA
AAA
A
AA
A
AAA
AA
AAA
A
A
AAA
AAA
R
W
(Note 1)
(Note 2)
Figure 2.10.17 Timer Bi mode register in timer mode
Rev. 1.0
87
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 2.10.7)
Figure 2.10.18 shows the timer Bi mode register in event counter mode.
Table 2.10.7 Timer specifications in event counter mode
Item
Specification
Count source
• External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Count source input
Read from timer
Count value can be read out by reading timer Bi register
Write to timer
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
AA
AA
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
TBiMR(i=0 to 5)
Address
039B16 to 039D16
035B16 to 035D16
Bit symbol
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
Count polarity select
bit (Note 1)
MR1
MR2
MR3
When reset
00XX00002
00XX00002
Function
b1 b0
0 1 : Event counter mode
b3 b2
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0, 3)
Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read,
turns out to be indeterminate.
Invalid in event counter mode.
In an attempt to write to this bit, write “0”. The value, if read in
event counter mode, turns out to be indeterminate.
TCK0
Invalid in event counter mode.
Can be “0” or “1”.
TCK1
Event clock select
0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
AA
AA
AA
AA
A
A
AA
A
A
AAAA
AA
AA
AAAA
AA
AAAA
AAAA
R
W
(Note 2)
(Note 3)
(j = i – 1; however, j = 2 when i = 0,
j = 5 when i = 3)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding port direction register to “0”.
Figure 2.10.18 Timer Bi mode register in event counter mode
Rev. 1.0
88
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table
2.10.8) Figure 2.10.19 shows the timer Bi mode register in pulse period/pulse width measurement
mode. Figure 2.10.20 shows the operation timing when measuring a pulse period. Figure 2.10.21
shows the operation timing when measuring a pulse width.
Table 2.10.8 Timer specifications in pulse period/pulse width measurement mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Measurement pulse input
Read from timer
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
TBiMR(i=0 to 5)
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode
select bit
Measurement mode
select bit
MR1
MR2
When reset
00XX00002
00XX00002
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0, 3)
Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
MR3
Timer Bi overflow
flag ( Note 1)
TCK0
Count source
select bit
TCK1
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
AAA
A
AAAA
AA
AAAA
A
AA
AAAA
R
W
(Note 2)
(Note 3)
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Figure 2.10.19 Timer Bi mode register in pulse period/pulse width measurement mode
Rev. 1.0
89
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
Count start flag
“0”
Timer Bi interrupt
request bit
“1”
Timer Bi overflow flag
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 2.10.20 Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 2.10.21 Operation timing when measuring a pulse width
Rev. 1.0
90
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.11 Serial I/O
Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4.
2.11.1 UART0 to 2
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 2.11.1 shows the block diagram of UART0, UART1 and UART2. Figures 2.11.2 and 2.11.3
show the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at
addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous
serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have
almost the same functions.
UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O
mode (Note). It also has the bus collision detection function that generates an interrupt request if the
TxD pin and the RxD pin are different in level.
Table 2.11.1 shows the comparison of functions of UART0 through UART2, and Figures 2.11.4 to
2.11.8 show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table 2.11.1 Comparison of functions of UART0 through UART2
Function
UART0
UART1
UART2
CLK polarity selection
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
LSB first / MSB first selection
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 2)
Continuous receive mode selection
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
Transfer clock output from multiple
pins selection
Impossible
Possible
(Note 1)
Impossible
Serial data logic switch
Impossible
Impossible
Sleep mode selection
Possible
TxD, RxD I/O polarity switch
Impossible
Impossible
Possible
TxD, RxD port output format
CMOS output
CMOS output
N-channel open-drain
output
Parity error signal output
Impossible
Impossible
Possible
Bus collision detection
Impossible
Impossible
Possible
(Note 3)
Possible
Possible
(Note 3)
(Note 4)
Impossible
(Note 4)
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
Rev. 1.0
91
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(UART0)
RxD0
TxD0
UART reception
1/16
Clock source selection
Reception
control circuit
Clock synchronous type
Bit rate generator
Internal (address 03A116)
f1
f8
f32
1 / (n0+1)
UART transmission
1/16
Transmission
control circuit
Clock synchronous type
External
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
RTS0
C T S 0 / R T S0
Vcc
CTS/RTS disabled
CTS0
(UART1)
RxD1
TxD1
Clock source selection
Bit rate generator
Internal (address 03A916)
f1
f8
f32
UART reception
1/16
1 / (n1+1)
UART transmission
1/16
CTS1 / RTS1
/ CLKS1
Clock synchronous type
(when internal clock is selected)
Transmit
clock
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
CTS/RTS selected
Clock output pin
select switch
Transmit/
receive
unit
(when internal clock is selected)
1/2
CLK1
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
CLK
polarity
reversing
circuit
Reception
control circuit
Clock synchronous type
Receive
clock
RTS1
VCC
CTS/RTS disabled
CTS1
(UART2)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD2
Clock source selection
f1
f8
f32
Internal
UART reception
1/16
Bit rate generator
(address 037916)
1 / (n2+1)
Clock synchronous type
UART transmission
1/16
Clock synchronous type
External
Reception
control circuit
Transmission
control circuit
Receive
clock
TxD2
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
1/2
CLK2
CLK
polarity
reversing
circuit
(when internal clock is selected)
Clock synchronous type
(when internal clock is selected)
CTS/RTS
selected
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
RTS2
C T S 2 / R T S2
Vcc
CTS/RTS disabled
CTS2
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Figure 2.11.1 Block diagram of UARTi (i = 0 to 2)
Rev. 1.0
92
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Clock
synchronous type
PAR
disabled
1SP
RxDi
SP
SP
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UARTi receive register
UART (7 bits)
PAR
2SP
PAR
enabled
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
UART (9 bits)
2SP
SP
SP
Clock synchronous
type
UART
TxDi
PAR
1SP
UARTi transmit
buffer register
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
PAR
enabled
D0
PAR
disabled
“0”
Clock
synchronous
type
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
Clock synchronous
type
SP: Stop bit
PAR: Parity bit
Figure 2.11.2 Block diagram of UARTi (i = 0, 1) transmit/receive unit
Rev. 1.0
93
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
No reverse
RxD data
reverse circuit
RxD2
Reverse
Clock
synchronous type
PAR
disabled
1SP
SP
SP
Clock
synchronous
type
UART2 receive register
UART(7 bits)
PAR
2SP
PAR
enabled
0
UART
(7 bits)
UART
(8 bits)
0
0
0
UART
0
Clock
synchronous type
UART
(9 bits)
0
0
UART
(8 bits)
UART
(9 bits)
D8
D0
UART2 receive
buffer register
Logic reverse circuit + MSB/LSB conversion circuit
Address 037E16
Address 037F16
D7
D6
D5
D4
D3
D2
D1
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
D0
UART2 transmit
buffer register
Address 037A16
Address 037B16
UART
(8 bits)
UART
(9 bits)
PAR
enabled
2SP
SP
SP
UART
(9 bits)
Clock
synchronous type
UART
PAR
1SP
PAR
disabled
“0”
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
UART2 transmit register
UART(7 bits)
Clock
synchronous type
Error signal output
disable
No reverse
TxD data
reverse circuit
Error signal
output circuit
Error signal output
enable
TxD2
Reverse
SP: Stop bit
PAR: Parity bit
Figure 2.11.3 Block diagram of UART2 transmit/receive unit
Rev. 1.0
94
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
U2TB
Address
03A316, 03A216
03AB16, 03AA16
037B16, 037A16
When reset
Indeterminate
Indeterminate
Indeterminate
Function
AA
R W
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turn out to be indeterminate.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
b0
Bit
symbol
Symbol
U0RB
U1RB
U2RB
Address
03A716, 03A616
03AF16, 03AE16
037F16, 037E16
When reset
Indeterminate
Indeterminate
Indeterminate
Function
(During clock synchronous
serial I/O mode)
Bit name
Receive data
Function
(During UART mode)
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
ABT
Arbitration lost detecting
flag (Note 2)
OER
Overrun error flag (Note 1) 0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag (Note 1)
Invalid
0 : No parity error
1 : Parity error found
SUM
Error sum flag (Note 1)
Invalid
0 : No error
1 : Error found
0 : Not detected
1 : Detected
Invalid
A
AA
AA
AA
A
R W
Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016,
03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out.
Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is
assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value
of this bit is “0”.
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
When reset
Indeterminate
Indeterminate
Indeterminate
Function
Assuming that set value = n, BRGi divides the count source by
n+1
Values that can be set
0016 to FF16
AA
RW
Figure 2.11.4 UARTi I/O-related registers (1)
Rev. 1.0
95
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Bit name
SMD0
Serial I/O mode select bit
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
b2 b1 b0
1 0 0 : Transfer data 7 bits length
1 0 1 : Transfer data 8 bits length
1 1 0 : Transfer data 9 bits length
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
Must always be “0”
0 : Sleep mode deselected
1 : Sleep mode selected
R W
A
A
A
A
AA
A
A
A
A
A
AA
A
AA
AA
AA
UART2 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
U2MR
b0
Address
037816
Bit
symbol
Bit name
SMD0
Serial I/O mode select bit
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : (Note)
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
b2 b1 b0
1 0 0 : Transfer data 7 bits length
1 0 1 : Transfer data 8 bits length
1 1 0 : Transfer data 9 bits length
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
Must always be fixed to “0”
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
Usually set to “0”
0 : No reverse
1 : Reverse
Usually set to “0”
Note: Bit 2 to bit 0 are set to “0102” when I2C mode is used.
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
R W
AA
A
A
A
A
AA
A
A
A
AA
A
AA
A
AA
AA
Figure 2.11.5 UARTil I/O-related registers (2)
Rev. 1.0
96
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
UARTi transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiC0(i=0,1)
Bit
symbol
CLK0
Address
When reset
0816
03A416, 03AC16
Function
(During clock synchronous
serial I/O mode)
Bit name
b1 b0
BRG count source
select bit
CLK1
CRS
TXEPT
CTS/RTS function
select bit
Function
(During UART mode)
b1 b0
AA
AA
AA
A
AA
AA
R W
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
0 : Data present in transmit register
Transmit register empty
register (during transmission)
(during transmission)
flag
1 : No data present in transmit
1 : No data present in transmit
register (transmission
completed)
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
NCH
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL
CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Must always be “0”
AA
AA
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2C0
Bit
symbol
CLK0
Address
037C16
Bit name
BRG count source
select bit
CLK1
CRS
TXEPT
CTS/RTS function
select bit
When reset
0816
Function
(During clock synchronous
serial I/O mode)
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
0 : Data present in transmit register
Transmit register empty
register (during transmission)
(during transmission)
flag
1 : No data present in transmit
1 : No data present in transmit
CTS/RTS disable bit
Nothing is assigned.
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions programmable
I/O port)
0 : TXDi pin is CMOS output
0: TXDi pin is CMOS output
: TXDi
pinvalue,
is N-channel
1: TXDi
is N-channel
In an attempt to write to this bit, write1“0”.
The
if read, turns out
to bepin“0”.
CKPOL
R W
AA
AA
AA
A
AA
AAAA
AA
AA
b1 b0
register (transmission
completed)
CRD
Function
(During UART mode)
CLK polarity select bit
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
(Note 3)
open-drain output
Must always be “0”
0 : LSB first
1 : MSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 2.11.6 UARTi I/O-related registers (3)
Rev. 1.0
97
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
UARTi transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
UiC1(i=0,1)
b0
Bit
symbol
Address
03A516,03AD16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit name
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
R W
A
A
A
A
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
UART2 transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
U2C1
b0
Bit
symbol
Address
037D16
Bit name
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2ERE Error signal output
enable bit
Must be fixed to “0”
0 : Output disabled
1 : Output enabled
U2IRS UART2 transmit interrupt
cause select bit
A
A
A
A
A
A
A
A
A
A
A
R W
Figure 2.11.7 UARTi I/O-related registers (4)
Rev. 1.0
98
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
UART transmit/receive control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UCON
0
Bit
symbol
Address
03B0 16
When reset
X0000000 2
Function
(During clock synchronous
serial I/O mode)
Bit name
U0IRS
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
U1IRS
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
(TXEPT = 1)
Function
(During UART mode)
R W
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Normal mode
Must always be “0”
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Must always be “0”
Reserved bit
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A8 16) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Bit
symbol
Address
037716
Bit name
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
IICM
I2C mode selection bit
0 : Normal mode
1 : I2C mode
Must always be “0”
ABC
Arbitration lost detecting
flag control bit
0 : Update per bit
1 : Update per byte
Must always be “0”
BBS
Bus busy flag
0 : STOP condition detected
1 : START condition detected
Must always be “0”
LSYN
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Must always be “0”
ABSCS
Bus collision detect
sampling
clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
SSS
Transmit start condition
select bit
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
SDDS
SDA digital delay
selection bit
(Notes 2 and 3)
0 : Analog delay output
selection
1 : Digital delay output selection
Must always be “0”
R W
(Note 1)
Notes 1: Nothing but "0" may be written.
2: Do not write "1" except at I 2C mode. Must always be “0” at normal mode.
Bit 7 to bit5 (DL2 to DL0 = SDA digital delay value setting bit) of UART2 special mode
register 3 (U2SMR3/address 0375 16) are initialized and become “000” when this bit is "0", analog
delay circuit is selected. Reading and writing U2SMR are enable when SDDS = "0" .
3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value
when digital delay is selected.
Figure 2.11.8 UARTi I/O-related registers (5)
Rev. 1.0
99
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
UART2 special mode register 2 (I2C bus exclusive register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Bit
symbol
Address
037616
When reset
0016
Bit name
Function
IICM2
I 2C mode selection bit 2
Refer to Table 2.11.11
CSC
Clock-synchronous bit
0 : Disabled
1 : Enabled
SWC
SCL wait output bit
0 : Disabled
1 : Enabled
ALS
SDA output stop bit
0 : Disabled
1 : Enabled
STAC
UART2 initialization bit
0 : Disabled
1 : Enabled
SWC2
SCL wait output bit 2
0: UART2 clock
1: 0 output
SDHI
SDA output disable bit
0: Enabled
1: Disabled (high impedance)
SHTC
Start/stop condition
control bit
Set this bit to "1" in I2C mode
(refer to Table 2.11.12)
AA
A
A
A
A
A
A
AA
AA
AA
AA
AA
R W
UART2 special mode register 3 (I2C bus exclusive register)
Symbol
U2SMR3
b7 b6 b5 b4 b3 b2 b1 b0
Bit
symbol
Address
037516
When reset
Indeterminate
(initializing value is "0016" at SDDS = "1")
Function
(I2C bus exclusive)
Bit name
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
“0” is read out when SDDS = 1.
DL0
SDA digital delay value
setting bit
DL1
DL2
b7 b6 b5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Analog delay
1 : 2 cycle of 1/f (Xin)(Digital delay)
0 : 3 cycle of 1/f (Xin)(Digital delay)
1 : 4 cycle of 1/f (Xin)(Digital delay)
0 : 5 cycle of 1/f (Xin)(Digital delay)
1 : 6 cycle of 1/f (Xin)(Digital delay)
0 : 7 cycle of 1/f (Xin)(Digital delay)
1 : 8 cycle of 1/f (Xin)(Digital delay)
Notes 1: Reading and writing is possible when bit7 (SDDS = SDA digital delay selection
bit) of UART2 special mode register (U2SMR/address 037716) is "1". When
set SDDS = "1" and read out initialized value of UART2 special mode register
3(U2SMR3), this value is "0016".When set SDDS = "1" and write to UART2
special mode register 3(U2SMR3), set "0" to bit 0 to bit 4. When SDDS = "0",
writing is enable. When read out, this value is indeterminate.
2: When SDDS = "0" , this bit is initialized and become "000", selected analog
delay circuit. This bit is become "000" after end reset released, and selected
analog delay circuit. Reading out is possible when only SDDS = "1". when
SDDS = "0", value which was read out is indeterminate.
3: Delaying ; Only analog delay value when analog delay is selected, and only
digital delay value when digital delay is selected.
4: Delay level depends on SCL pin and SDA pin. And, when use external clock,
delay is increase around 100ns. So test first, and use this.
R W
A
A
A
AA
A
AA
AA
Figure 2.11.9 UARTi -related registers (6)
Rev. 1.0
100
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.11.2 Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables
2.11.2 and 2.11.3 list the specifications of the clock synchronous serial I/O mode. Figur 2.11.10 shows
the UARTi transmit/receive mode register.
Table 2.11.2 Specifications of clock synchronous serial I/O mode (1)
Item
Transfer data format
Transfer clock
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “1”) : Input from CLKi pin
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A5 16, 03AD16, 037D16 ) = “0”
_______
_______
_ When CTS function selected, CTS input level = “L”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A5 16, 03AD16, 037D16 ) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
• When transmitting
Interrupt request
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B0 16, bit 4 at
generation timing
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B0 16, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Rev. 1.0
101
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 2.11.3 Specifications of clock synchronous serial I/O mode (2)
Item
Select function
Specification
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
UARTi transmit/receive mode registers
b7
b6
b5
b4
b3
0
b2
b1
b0
0 0 1
Symbol
UiMR(i=0,1)
Bit symbol
SMD0
Address
03A016, 03A816
When reset
0016
Bit name
Serial I/O mode select bit
SMD1
SMD2
Internal/external clock
select bit
CKDIR
Function
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
0 (Must always be “0” in clock synchronous serial I/O mode)
UART2 transmit/receive mode register
b7
0
b6
b5
b4
b3
b2
b1
b0
0 0 1
Symbol
U2MR
Address
037816
Bit symbol
SMD0
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Internal/external clock
select bit
Function
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
Note: Usually set to “0”.
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
0 : No reverse
1 : Reverse
Figure 2.11.10 UARTi transmit/receive mode register in clock synchronous serial I/O mode
Rev. 1.0
103
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 2.11.4 lists the functions of the input/output pins during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the
TxDi pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 2.11.4 Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxDi
Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
CLKi
Transfer clock output
(P61, P65, P72)
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
CTSi/RTSi
CTS input
(P60, P64, P73)
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16,
bit 3 at address 03EF16) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1”
Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
bit 2 at address 03EF16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
Rev. 1.0
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
“1”
“0”
Data is set in UARTi transmit buffer register
“1”
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
TCLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
CLKi
TxDi
D0 D 1 D2 D3 D4 D5 D6 D7
Transmit
register empty
flag (TXEPT)
D0 D 1 D2 D3 D4 D5 D 6 D7
D 0 D1 D2 D 3 D 4 D 5 D6 D7
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
Transmit enable
bit (TE)
“0”
Transmit buffer
empty flag (Tl)
“1”
“0”
“H”
RTSi
Dummy data is set in UARTi transmit buffer register
“1”
Transferred from UARTi transmit buffer register to UARTi transmit register
“L”
1 / fEXT
CLKi
Receive data is taken in
D 0 D1 D 2 D3 D 4 D5 D6 D 7
RxDi
Receive complete “1”
flag (Rl)
“0”
Receive interrupt
request bit (IR)
Transferred from UARTi receive register
to UARTi receive buffer register
D0 D 1 D 2
D3 D4 D5
Read out from UARTi receive buffer register
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 2.11.11 Typical transmit/receive timings in clock synchronous serial I/O mode
Rev. 1.0
105
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(1) Polarity select function
As shown in Figure 2.11.12 the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16)
allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLK pin level when not
transferring data is “H”.
• When CLK polarity select bit = “1”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLK pin level when not
transferring data is “L”.
Figure 2.11.12 Polarity of transfer clock
(2) LSB first/MSB first select function
As shown in Figure 2.11.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,
037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
LSB first
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
D2
D1
D0
• When transfer format select bit = “1”
CLKi
TXDi
D7
D6
D5
D4
D3
MSB first
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
Note: This applies when the CLK polarity select bit = “0”.
Figure 2.11.13 Transfer format
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 2.11.14)
The multiple pins function is valid_______
only _______
when the internal clock is selected for UART1. Note that when
this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 2.11.14 The transfer clock output from the multiple pins function usage
(4) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
(5) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 2.11.15 shows the example of serial
data logic switch timing.
•When LSB first
Transfer clock
“H”
“L”
TxD2
“H”
(no reverse) “L”
TxD2
“H”
(reverse) “L”
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Figure 1.11.15 Serial data logic switch timing
Rev. 1.0
107
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.11.3 Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and
transfer data format. Tables 2.11.5 and 2.11.6 list the specifications of the UART mode. Figure
2.11.16 shows the UARTi transmit/receive mode register.
Table 2.11.5 Specifications of UART Mode (1)
Item
Transfer data format
Transfer clock
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A016 ,03A816 ,037816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016 and 03A8 16 = “1”) :
fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)
_______
_______
_______
_______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
- Transmit
buffer empty flag (bit 1_______
at addresses 03A5 16, 03AD16, 037D 16) = “0”
_______
- When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
- Start bit detection
Interrupt request
• When transmitting
generation timing
- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ‘n’ denotes the value 00 16 to FF 16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
Rev. 1.0
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Table 2.11.6 Specifications of UART Mode (2)
Item
Select function
Specification
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave microcomputers
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TXD, RXD I/O polarity switch (UART2)
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
Rev. 1.0
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UARTi transmit / receive mode registers
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiMR(i=0,1)
Bit symbol
SMD0
Address
03A016, 03A816
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Function
b2 b1 b0
1 0 0 : Transfer data 7 bits length
1 0 1 : Transfer data 8 bits length
1 1 0 : Transfer data 9 bits length
Internal / external clock
select bit
Stop bit length select bit
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
0 : Sleep mode deselected
1 : Sleep mode selected
STPS
AA
AA
AA
A
AA
AA
AA
AA
AA
AA
AA
RW
UART2 transmit / receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2MR
Address
037816
Bit symbol
SMD0
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
STPS
When reset
0016
Internal / external clock
select bit
Stop bit length select bit
Function
b2 b1 b0
1 0 0 : Transfer data 7 bits length
1 0 1 : Transfer data 8 bits length
1 1 0 : Transfer data 9 bits length
Must always be fixed to “0”
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note: Usually set to “0”.
AA
AA
AA
AA
AA
A
AA
A
AA
A
AA
RW
Figure 2.11.16 UARTi transmit/receive mode register in UART mode
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Table 2.11.7 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the
N-channel open-drain is selected, this pin is in floating state.)
Table 2.11.7 Input/output pin functions in UART mode
Pin name
Function
TxDi
Serial data output
(P63, P67, P70)
Method of selection
RxDi
Serial data input
(P62, P66, P71)
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
CLKi
Programmable I/O port
(P61, P65, P72)
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
CTSi/RTSi
CTS input
(P60, P64, P73)
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16,
bit 3 at address 03EF16) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0”
(Do not set external clock for UART2)
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
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• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register.
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
Start
bit
TxDi
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
Stopped pulsing because transmit enable bit = “0”
Stop
bit
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1
SP
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 2.11.17 Typical transmit timings in UART mode(UART0,UART1)
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• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
Data is set in UART2 transmit buffer register
“0”
Note
“0”
Transferred from UART2 transmit buffer register to UARTi transmit register
Parity
bit
Start
bit
TxD2
ST D0 D1
D2 D 3 D4 D 5 D6 D7
P
Stop
bit
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
“1”
Transmit register
empty flag (TXEPT) “0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Figure 2.11.18 Typical transmit timings in UART mode(UART2)
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• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
Receive enable bit
“1”
“0”
Stop bit
Start bit
RxDi
D1
D0
D7
Sampled “L”
Receive data taken in
Transfer clock
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Receive
complete flag
Transferred from UARTi receive register to
UARTi receive buffer register
“0”
“H”
“L”
RTSi
Receive interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Figure 2.11.19 Typical receive timing in UART mode
(1) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
(2) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 2.11.20 shows the example of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
Transfer clock
“H”
“L”
TxD2
“H”
(no reverse)
“L”
TxD2
“H”
(reverse)
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit
P : Even parity
SP : Stop bit
Figure 2.11.20 Timing for switching serial data logic
Rev. 1.0
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(3) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(4) Bus collision detection function (UART2)
This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 2.11.21
shows the example of detection timing of a buss collision (in UART mode).
Transfer clock
“H”
“L”
TxD2
“H”
ST
SP
ST
SP
“L”
RxD2
“H”
“L”
Bus collision detection
interrupt request signal
Bus collision detection
interrupt request bit
“1”
“0”
“1”
“0”
ST : Start bit
SP : Stop bit
Figure 2.11.21 Detection timing of a bus collision (in UART mode)
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2.11.4 Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding
some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 2.11.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the
SIM interface).
Table 2.11.8 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
Specification
Transfer data format
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock
• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32
(Do not set external clock)
_______
_______
Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings
• The sleep mode select function is not available for UART2
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”)
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
Reception start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
Interrupt request
• When transmitting
generation timing
When data transmission from the UART2 transfer register is completed
(bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the T XD2 pin by use of the parity error
signal output function (bit 7 of address 037D 16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RXD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 00 16 to FF 16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
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Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UART2 transmit buffer register
Note
“0”
Transferred from UART2 transmit buffer register to UART2 transmit register
Start
bit
TxD2
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P
SP
P
SP
RxD2
A “L” level returns from TxD2 due to
the occurrence of a parity error.
Signal conductor level
(Note 1)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
The level is
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Tc
Transfer clock
Receive enable
bit (RE)
“1”
“0”
Start
bit
RxD2
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
Stop
bit
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
TxD2
A “L” level returns from TxD2 due to
the occurrence of a parity error.
Signal conductor level
(Note 1)
Receive complete
flag (RI)
“1”
Receive interrupt
request bit (IR)
“1”
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
“0”
Read to receive buffer
Read to receive buffer
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Note: Equal in waveform because TxD2 and RxD2 are connected.
Figure 2.11.22 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
Rev. 1.0
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(1) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L”
level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing
of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure
2.11.23 shows the output timing of the parity error signal.
• LSB first
Transfer
clock
“H”
RxD2
“H”
TxD2
“H”
Receive
complete flag
“1”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“L”
Hi-Z
“L”
“0”
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 2.11.23 Output timing of the parity error signal
(2) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted
and output from TxD2.
Figure 2.11.24 shows the SIM interface format.
Transfer
clcck
TxD2
(direct)
D0
D1
D2
D3
D4
D5
D6
D7
P
TxD2
(inverse)
D7
D6
D5
D4
D3
D2
D1
D0
P
P : Even parity
Figure 2.11.24 SIM interface format
Rev. 1.0
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Figure 2.11.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and
apply pull-up.
Microcomputer
SIM card
TxD2
RxD2
Figure 2.11.25 Connecting the SIM interface
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2.11.5 UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways.
Figure 2.11.26 shows the UART2 special mode register.
In the first place, the control bits related to the I2C bus(simplified I2C bus) interface are explained.
Bit 0 of the UART special mode register (037716) is used as the I2C mode selection bit.
Setting “1” in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus interface effective.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Bit
symbol
Address
037716
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit name
Function
(During UART mode)
IICM
I2 C mode selection bit
0 : Normal mode
1 : I 2C mode
Must always be “0”
ABC
Arbitration lost detecting
flag control bit
0 : Update per bit
1 : Update per byte
Must always be “0”
BBS
Bus busy flag
0 : STOP condition detected
1 : START condition detected
Must always be “0”
LSYN
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Must always be “0”
ABSCS
Bus collision detect
sampling clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
SSS
Transmit start condition
select bit
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
SDDS
SDA digital delay select
bit
(Notes 2 and 3)
0 : Selects analog delay
output
1 : Selects digital delay
output (Must always
be “0” except at I 2C
mode)
Must always be “0”
R W
(Note 1)
Notes 1: Nothing but "0" may be written.
2: Do not write "1" except at I 2C mode. Must always be “0” at normal mode.
Bit 7 to bit5 (DL2 to DL0 = SDA digital delay value setting bit) of UART2 special mode
register 3 (U2SMR3/address 0375 16) are initialized and become “000” when this bit is "0", analog
delay circuit is selected. Reading and writing U2SMR are enable when SDDS = "0" .
3: Delaying ; Only analog delay value when analog delay is selected, and only digital delay value
when digital delay is selected.
UART2 special mode register 3 (I2C bus exclusive register)
Symbol
U2SMR3
b7 b6 b5 b4 b3 b2 b1 b0
Bit
symbol
Address
037516
When reset
Indeterminate
(initializing value is "00 16" at SDDS = "1")
Function
(I2C bus exclusive)
Bit name
R W
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
“0” is read out when SDDS = 1.
DL0
SDA digital delay value
set bit
DL1
DL2
b7 b6 b5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Selects analog delay
1 : 2 cycle of 1/f (Xin)(Digital delay)
0 : 3 cycle of 1/f (Xin)(Digital delay)
1 : 4 cycle of 1/f (Xin)(Digital delay)
0 : 5 cycle of 1/f (Xin)(Digital delay)
1 : 6 cycle of 1/f (Xin)(Digital delay)
0 : 7 cycle of 1/f (Xin)(Digital delay)
1 : 8 cycle of 1/f (Xin)(Digital delay)
Notes 1: Reading and writing is possible when bit7 (SDDS = SDA digital delay selection
bit) of UART2 special mode register (U2SMR/address 0377 16) is "1". When
set SDDS = "1" and read out initialized value of UART2 special mode register
3(U2SMR3), this value is "00 16".When set SDDS = "1" and write to UART2
special mode register 3(U2SMR3), set "0" to bit 0 to bit 4. When SDDS = "0",
writing is enable. When read out, this value is indeterminate.
2: When SDDS = "0" , this bit is initialized and become "000", selected analog
delay circuit. This bit is become "000" after end reset released, and selected
analog delay circuit. Reading out is possible when only SDDS = "1". when
SDDS = "0", value which was read out is indeterminate.
3: Delaying ; Only analog delay value when analog delay is selected, and only
digital delay value when digital delay is selected.
4: Delay level depends on SCL pin and SDA pin. And, when use external clock,
delay is increase around 100ns. So test first, and use this.
Figure 2.11.26 UART2 special mode register
Rev. 1.0
120
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
To DMA0, DMA1
P70/TXD2/SDA
IICM=1(SDDS=0)
or DL=000(SDDS=1)
Timer
Selector
I/O
Analog
delay
UART2
SDDS=0
or DL=000
SDDS=1
and DL=000
D
ALS
To DMA0
Arbitration
Q
T
Noize
Filter
UART2 transmission/
NACK interrupt request
IICM=1
and IICM2=0
IICM=0
or DL=000(SDDS=1)
SDHI
Digital Delay
(Divier)
IICM=0
or IICM2=1
UART2
Transmission
register
IICM=0
or IICM2=1
IICM=1
Reception register
IICM=0
UART2
IICM=1
and IICM2=0
Start condition detection
S
R
Q
UART2 reception/ACK interrupt request
DMA1 request
Bus
busy
Stop condition detection
D
L-synchronous
output enabling bit
Falling edge
detection
P71/RXD2/SCL
D
I/O
R
UART2
IICM=1
IICM=1
Noize
Filter
Noize
Filter
ACK
9th pulse
(Port P71 output data latch)
Selector
Q
T
Data bus
Q
NACK
Q
T
IICM=1
Internal clock
SWC2
External clock
CLK
control
Bus collision
detection
Bus collision/start, stop condition detection
interrupt request
IICM=0
UART2
Falling of 9th pulse
IICM=0
SWC
Port reading
UART2
IICM=0
P72/CLK2
Selector
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7 1 of the direction register.
I/O
Timer
Figure 2.11.27 Functional block diagram for I2C mode
Table 2.11.9 Features in I2C mode
Function
Normal mode
I2C mode (Note 1)
Start condition detection or stop
condition detection
1
Factor of interrupt number 10 (Note 2)
Bus collision detection
2
Factor of interrupt number 15 (Note 2)
UART2 transmission
No acknowledgment detection (NACK)
3
Factor of interrupt number 16 (Note 2)
UART2 reception
Acknowledgment detection (ACK)
4
UART2 transmission output delay
Not delayed
Delayed
5
P70 at the time when UART2 is in use
TxD2 (output)
SDA (input/output) (Note 3)
6
P71 at the time when UART2 is in use
RxD2 (input)
SCL (input/output)
7
P72 at the time when UART2 is in use
CLK2
P72
8
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits
UART2 reception
Acknowledgment detection (ACK)
9
Noise filter width
15ns
50ns
10 Reading P71
Reading the terminal when 0 is
assigned to the direction register
Reading the terminal regardless of the
value of the direction register
11 Initial value of UART2 output
H level (when 0 is assigned to
the CLK polarity select bit)
The value set in latch P70 when the port is
selected
Note 1: Make the settings given below when I2C mode is in use.
Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
Rev. 1.0
121
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M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Figure 2.11.27 hows the functional block diagram for I2C mode. Setting “1” in the I2C mode selection
bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock
input-output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission
output, so the SDA output changes after SCL fully goes to “L”. Can select analog delay or digital delay
by SDA digital delay selection bit (7 bit of address 037716). When select digital delay, can select delay
to 2 cycle to 8 cycle of f1 by UART2 special mode register 3 (address 037516) . Functions changed by
I2C mode selection bit 2 is shown in below.
Table 2.11.10 Delay circuit selection condition
Register value
Contents
Digital delay selection
IICM
SDDS
1
1
DL
001
111
Analog delay selection
No delay
1
000
0
(000)
0
(000)
1
0
When select digital delay, analog delay is not added.
Only digital delay.
When select DL="000" , analog delay is chosen
regardless of the value of SDDS.
When SDDS="0" , DL is initialized and DL="000".
Delay circuit is not selected when IICM="0".
But, must set SDDS="0" when IICM="0".
An attempt to read Port P71 (SCL) results in getting the terminal’s level regardless of the content of the
port direction register. The initial value of SDA transmission output in this mode goes to the value set
in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt,
and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment
non-detection interrupt, and acknowledgment detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the
SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection
interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected
with the SCL terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register)
is set to “1” by the start condition detection, and set to “0” by the stop condition detection.
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal
level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment
detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already
went to “L” at the 9th transmission clock. Also, assigning 1101(UART2 reception) to the DMA1 request
factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment
detection.
Bit 1 of the UART2 special mode register (037716) is used as the arbitration loss detecting flag control
bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA
terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2
reception buffer register (037F16), and “1” is set in this flag when nonconformity is detected. Use the
arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte
by byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the
arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock.
If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit.
Setting this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level
going to “L”.
Rev. 1.0
122
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Some other functions added are explained here. Figure 2.11.28 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit.
The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the
nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit
is set to “0”. If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0
rather than at the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this
bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK
TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK
TxD
Enabling transmission
With "1: falling edge of RxD2" selected
CLK
TxD
RxD
Figure 2.11.28 Some other functions added
Rev. 1.0
123
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.11.6 UART2 Special Mode Register 2
UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure
2.11.29 shows the UART2 special mode register 2.
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Bit
symbol
Address
037616
When reset
0016
Bit name
Function
IICM2
I2 C mode selection bit 2
Refer to Table 2.11.11
CSC
Clock-synchronous bit
0 : Disabled
1 : Enabled
SWC
SCL wait output bit
0 : Disabled
1 : Enabled
ALS
SDA output stop bit
0 : Disabled
1 : Enabled
STAC
UART2 initialization bit
0 : Disabled
1 : Enabled
SWC2
SCL wait output bit 2
0: UART2 clock
1: 0 output
SDHI
SDA output disable bit
0: Enabled
1: Disabled (high impedance)
SHTC
Start/stop condition
control bit
Set this bit to "1" in I2C mode
(refer to Table 2.11.12)
R W
Figure 2.11.29 UART2 special mode register 2
Rev. 1.0
124
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode selection bit 2.
Table 2.11.11 shows the types of control to be changed by I2C mode selection bit 2 when the I2C
mode selection bit is set to "1". Table 2.11.12 shows the timing characteristics of detecting the start
condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode
register 2) to "1" in I2C mode.
Table 2.11.11 Functions changed by I2C mode selection bit 2
IICM2 = 0
IICM2 = 1
1 Factor of interrupt number 15
No acknowledgment detection (NACK)
UART2 transmission (the rising edge
of the final bit of the clock)
2 Factor of interrupt number 16
Acknowledgment detection (ACK)
UART2 reception (the falling edge
of the final bit of the clock)
Function
3 DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK)
is assigned to the DMA request
factor selection bits
UART2 reception (the falling edge of
the final bit of the clock)
4 Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
5 Timing for generating a UART2
reception/ACK interrupt request
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
Table 2.11.12 Timing characteristics of detecting the start condition and the stop condition(Note1)
3 to 6 cycles < duration for setting-up (Note2)
3 to 6 cycles < duration for holding (Note2)
Note 1 : When the start/stop condition count bit is "1" .
Note 2 : "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock.
Duration for
setting up
Duration for
holding
SCL
SDA
(Start condition)
SDA
(Stop condition)
Rev. 1.0
125
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
To DMA0, DMA1
P70/TXD2/SDA
IICM=1(SDDS=0)
or DL=000(SDDS=1)
Timer
Selector
I/O
Analog
delay
UART2
SDDS=0
or DL=000
Digital Delay
(Divier)
SDHI
D
UART2
Transmission
register
ALS
To DMA0
Arbitration
Q
T
Noize
Filter
UART2 transmission/
NACK interrupt request
IICM=1
and IICM2=0
IICM=0
or DL=000(SDDS=1)
SDDS=1
and DL=000
IICM=0
or IICM2=1
IICM=0
or IICM2=1
IICM=1
Reception register
IICM=0
UART2
IICM=1
and IICM2=0
Start condition detection
S
R
Q
UART2 reception/ACK interrupt request
DMA1 request
Bus
busy
Stop condition detection
D
L-synchronous
output enabling bit
Falling edge
detection
P71/RXD2/SCL
D
I/O
Selector
R
Q
IICM=1
Noize
Filter
Noize
Filter
Q
T
Data bus
ACK
9th pulse
(Port P71 output data latch)
UART2
IICM=1
NACK
Q
T
IICM=1
Internal clock
SWC2
External clock
CLK
control
Bus collision
detection
Bus collision/start, stop condition detection
interrupt request
IICM=0
UART2
Falling of 9th pulse
IICM=0
SWC
Port reading
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7 1 of the direction register.
UART2
IICM=0
P72/CLK2
Selector
I/O
Timer
Figure 2.11.30 Functional block diagram for I2C mode
Functions available in I2C mode are shown in Figure 2.11.30— a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit.
Setting this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance
state the instant when the arbitration loss detection flag is set to "1".
Bit 1 of the UART2 special mode register 2 (address 036716) is used as the clock synchronization bit.
With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start
counting within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to
"L", stops counting the baud rate generator, and starts counting it again when the SCL pin turns to "H".
Due to this function, the UART2 transmission-reception clock becomes the logical product of the
signal flowing through the internal SCL and that flowing through the SCL pin. This function operates
over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the
rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit
to "1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this
bit to "0" frees the output fixed to "L".
Rev. 1.0
126
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit.
Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows.
(1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered
next as the first bit. The UART2 output value, however, doesn’t change until the first bit data is
output after the entrance of the clock, and remains unchanged from the value at the moment when
the microcomputer detected the start condition.
(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the
clock entered next as the first bit.
(3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit
of the clock.
Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the
transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.
Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting
this bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even
if UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2
clock is input/output.
Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output enable bit. Setting this
bit to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of
this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost
detection flag is turned on.
Rev. 1.0
127
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.11.7 S I/O3, 4
S I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os.
Figure 2.11.31 shows the S I/O3, 4 block diagram, and Figure 2.11.32 shows the S I/O3, 4 control
register.Table 2.11.13 shows the specifications of S I/O3, 4.
f1
Data bus
SMi1
SMi0
f8
f32
Synchronous
circuit
SMi3
SMi6
1/2
1/(ni+1)
Transfer rate register (8)
SMi6
P90/CLK3
(P95/CLK4)
S I/O counter i (3)
S I/Oi
interrupt request
SMi2
SMi3
P92/SOUT3
(P96/SOUT4)
SMi5 LSB
P91/SIN3
(P97/SIN4)
MSB
S I/Oi transmission/reception register (8)
8
Note: i = 3, 4.
ni = A value set in the S I/O transfer rate register i (036316, 036716).
Figure 2.11.31 S I/O3, 4 block diagram
Rev. 1.0
128
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SiC
Bit
symbol
SMi0
Address
036216, 036616
When reset
4016
Description
Bit name
R W
b1 b0
Internal synchronous
clock select bit
SMi1
SMi2
SOUTi output disable bit
SMi3
S I/Oi port select bit
(Note 2)
0 0 : Selecting f1
0 1 : Selecting f8
1 0 : Selecting f32
1 1 : Not to be used
0 : SOUTi output
1 : SOUTi output disable(high impedance)
0 : Input-output port
1 : SOUTi output, CLK function
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
SMi5
Transfer direction lect bit
0 : LSB first
1 : MSB first
SMi6
Synchronous clock
select bit (Note 2)
0 : External clock
1 : Internal clock
Effective when SMi3 = 0
0 : L output
1 : H output
Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the
S I/Oi control register (i = 3, 4).
Note 2: When using the port as an input/output port by setting the SI/Oi port
select bit (i = 3, 4) to "1", be sure to set the sync clock select bit to "1".
SMi7
SOUTi initial value
set bit
SI/Oi bit rate generator
b7
Symbol
S3BRG
S4BRG
b0
Address
036316
036716
When reset
Indeterminate
Indeterminate
Values that can be set
Indeterminate
Assuming that set value = n, BRGi divides the count
source by n + 1
R W
0016 to FF16
SI/Oi transmit/receive register
b7
b0
Symbol
S3TRR
S4TRR
Address
036016
036416
When reset
Indeterminate
Indeterminate
Indeterminate
R W
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
Figure 2.11.32 S I/O3, 4 related register
Rev. 1.0
129
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 2.11.13 Specifications of S I/O3, 4
Item
Transfer data format
Transfer clock
Conditions for
transmission/
reception start
Interrupt request
generation timing
Select function
Precaution
Specifications
• Transfer data length: 8 bits
• With the internal clock selected (bit 6 of 036216, 036616 = “1”): f1/2(ni+1),
f8/2(ni+1), f32/2(ni+1) (Note 1)
• With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2)
• To start transmit/reception, the following requirements must be met:
- Select the synchronous clock (use bit 6 of 036216, 036616).
Select a frequency dividing ratio if the internal clock has been selected (use bits
0 and 1 of 036216, 036616).
- SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1.
- S I/Oi port select bit (bit 3 of 036216, 036616) = 1.
- Select the transfer direction (use bit 5 of 036216, 036616)
-Write transfer data to SI/Oi transmit/receive register (036016, 036416)
• To use S I/Oi interrupts, the following requirements must be met:
- Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi
transmit/receive register (bit 3 of 004916, 004816) = 0.
• Rising edge of the last transfer clock. (Note 3)
• LSB first or MSB first selection
Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be
selected.
• Function for setting an SOUTi initial value selection
When using an external clock for the transfer clock, the user can choose the
SOUTi pin output level during a non-transfer time. For details on how to set, see
Figure 2.11.33.
• Unlike UART0–2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer.
Therefore, do not write the next transfer data to the SI/Oi transmit/receive register
(addresses 036016, 036416) during a transfer. When the internal clock is selected
for the transfer clock, SOUTi holds the last data for a 1/2 transfer clock period after
it finished transferring and then goes to a high-impedance state. However, if the
transfer data is written to the SI/Oi transmit/receive register (addresses 036016,
036416) during this time, SOUTi is placed in the high-impedance state immediately
upon writing and the data hold time is thereby reduced.
Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4).
Note 2: With the external clock selected:
•Before data can be written to the SI/Oi transmit/receive register (addresses 036016, 036416), the
CLKi pin input must be in the low state. Also, before rewriting the SI/Oi Control Register (addresses
036216, 036616)’s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held low.
• The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it,
so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,
automatically stops.
Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state.
Rev. 1.0
130
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(1) Functions for setting an SOUTi initial value
When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer
time can be set to the high or the low state. Figure 2.11.33 shows the timing chart for setting an SOUTi
initial value and how to set it.
(Example) With “H” selected for SOUTi:
S I/Oi port select bit SMi3 = 0
Signal written to the S I/Oi
transmission/reception
register
SOUTi initial value select bit
SMi7 = 1
(SOUTi: Internal
“H” level)
SOUTi's initial value
set bit (SMi7)
S I/Oi port select bit
SMi3 = 0
1
(Port select: Normal port
SOUTi)
S I/Oi port select bit
(SMi3)
D0
SOUTi (internal)
SOUTi terminal = “H” output
D0
Port output
Signal written to the S I/Oi register
=“L”
“H”
“L”
(Falling edge)
SOUTi terminal output
Initial value = “H” (Note)
(i = 3, 4)
Setting the SOUTi
initial value to H
Port selection
(normal port
SOUTi)
SOUTi terminal = Outputting
stored data in the S I/Oi transmission/
reception register
Note: The set value is output only when the external clock has been selected. When
initializing SOUTi, make sure the CLKi pin input is held “L” level.
If the internal clock has been selected or if SOUT output disable has been set,
this output goes to the high-impedance state.
Figure 2.11.33 Timing chart for setting SOUTi’s initial value and how to set it
(2) S I/Oi operation timing
Figure 2.11.34 shows the S I/Oi operation timing
1.5 cycle (max)
SI/Oi internal clock
"H"
"L"
Transfer clock
(Note 1)
"H"
"L"
Signal written to the
S I/Oi register
"H"
"L"
S I/Oi output SOUTi
"H"
"L"
Note2
(i= 3, 4)
S I/Oi input SINi
(i= 3, 4)
SI/Oi interrupt request
(i= 3, 4)
bit
Hiz
D0
D1
D2
D3
D4
D5
D6
D7
Hiz
"H"
"L"
"1"
"0"
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register.
(i=3,4) (No frequency division, 8-division frequency, 32-division frequency.)
Note 2: With the internal clock selected for the transfer clock, the SOUTi pin becomes to the high-impedance state after the transfer finishes.
Note 3: Shown above is the case where the SOUTi (i = 3, 4) port select bit ="1".
Figure 22.11.34 S I/Oi operation timing chart
Rev. 1.0
131
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.12 A-D Converter
The A-D converter consists of one 8-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P9 5, and P96 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit
5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins.
Table 2.12.1 shows the performance of the A-D converter. Figure 2.12.1 shows the block diagram of the
A-D converter, and Figures 2.12.2 and 2.12.3 show the A-D converter-related registers.
Table 2.12.1 Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC )
Operating clock φ AD (Note 2) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD =f(XIN)
Resolution
8-bit
Absolute precision
• Without sample and hold function
±3LSB
• With sample and hold function
±2LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D
conversion starts when the A-D conversion start flag is “1” and the
__________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
49 φAD cycles
• With sample and hold function
28 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the φAD frequency to 250kHZ min.
With the sample and hold function, set the φAD frequency to 1MHZ min.
Rev. 1.0
132
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
CKS1=1
φAD
CKS0=1
fAD
1/2
1/2
CKS0=0
CKS1=0
A-D conversion rate
selection
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C016)
(03C216)
(03C416)
(03C616)
A-D register 0(8)
A-D register 1(8)
A-D register 2(8)
A-D register 3(8)
(03C816)
A-D register 4(8)
(03CA16)
(03CC16)
A-D register 5(8)
A-D register 6(8)
(03CE16)
A-D register 7(8)
Vref
Decoder
VIN
Comparator
Data bus
AN0
CH2,CH1,CH0=000
AN1
CH2,CH1,CH0=001
AN2
CH2,CH1,CH0=010
AN3
CH2,CH1,CH0=011
AN4
CH2,CH1,CH0=100
AN5
CH2,CH1,CH0=101
AN6
CH2,CH1,CH0=110
AN7
CH2,CH1,CH0=111
OPA1,OPA0=0,0
OPA1, OPA0
OPA1,OPA0=1,1
OPA0=1
ANEX0
0
0
1
1
0 : Normal operation
1 : ANEX0
0 : ANEX1
1 : External op-amp mode
OPA1,OPA0=0,1
ANEX1
OPA1=1
Figure 2.12.1 Block diagram of A-D converter
Rev. 1.0
133
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
RW
Function
b2 b1 b0
CH0
Analog input pin select bit
CH1
CH2
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
MD0
MD1
(Note 2)
b4 b3
(Note 2)
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
CKS0
Frequency select bit 0
A
A
A
AA
AA
A
AA
A
A
A
AA
A
AA
A
AA
A-D control register 1 (Note)
b7
b6
b5
b4
b3
0
b2
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
SCAN0
Function
When single sweep and repeat sweep
mode 0 are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
When repeat sweep mode 1 is selected
b1 b0
SCAN1
MD2
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
A-D operation mode
select bit 1
Reserved bit
CKS1
VCUT
OPA0
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
Must always be set to "0"
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
0 : Vref not connected
1 : Vref connected
External op-amp
connection mode bit
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
A
AA
RW
AA
A
AA
A
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 2.12.2 A-D converter-related registers (1)
Rev. 1.0
134
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
A-D control register 2 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
Address
When reset
ADCON2
03D416
0000XXX02
Bit symbol
SMP
Bit name
A-D conversion method
select bit
Function
0 : Without sample and hold
1 : With sample and hold
Always set to “0”
Reserved bit
A
A
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
A-D register i
b7
Address
03C016,03C216,03C416,03C616,
03C816,03CA16,03CC16,03CE16
ADi(i=0 to 7)
When reset
Indeterminate
b0
Function
Eight bits of A-D conversion result
Figure 2.12.3 A-D converter-related registers (2)
AA
AA
R W
Rev. 1.0
135
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D
conversion. Table 2.12.2 shows the specifications of one-shot mode. Figure 2.12.4 shows the A-D
control register in one-shot mode.
Table 2.12.2 One-shot mode specifications
Item
Specification
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
End of A-D conversion
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Analog input pin select
bit
CH0
CH1
CH2
MD0
A-D operation mode
select bit 0
Trigger select bit
MD1
Function
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
(Note 2)
b4 b3
0 0 : One-shot mode
(Note 2)
0 : Software trigger
1 : ADTRG trigger
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0: fAD/4 is selected
Frequency select bit 0
1: fAD/2 is selected
TRG
ADST
CKS0
AAAA
AAAA
AAAA
AA
RW
b2 b1 b0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin
select bit
Invalid in one-shot mode
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
SCAN0
SCAN1
MD2
Reserved bit
CKS1
Must always be set to "0".
Frequency select bit1
VCUT
Vref connect bit
OPA0
External op-amp
connection mode bit
OPA1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
AAAA
AAAA
AAAA
AAAA
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 2.12.4 A-D conversion register in one-shot mode
Rev. 1.0
136
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 2.12.3 shows the specifications of repeat mode. Figure 2.12.5 shows the A-D control
register in repeat mode.
Table 2.12.3 Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Star condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
Bit name
Analog input pin
select bit
CH1
CH2
MD0
When reset
00000XXX2
MD1
A-D operation mode
select bit 0
TRG
Trigger select bit
ADST
A-D conversion start flag
CKS0
Frequency select bit 0
Function
(Note 2)
b4 b3
0 1 : Repeat mode
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
b2 b1 b0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
(Note 2)
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin select bit Invalid in repeat mode
SCAN1
MD2
A-D operation mode
select bit 1
Reserved bit
0 : Any mode other than repeat sweep mode 1
Must always be set to "0".
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
Vref connect bit
1 : Vref connected
OPA0
External op-amp
connection mode bit
OPA1
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 2.12.5 A-D conversion register in repeat mode
Rev. 1.0
137
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one
A-D conversion. Table 2.12.4 shows the specifications of single sweep mode. Figure 2.12.6 shows the
A-D control register in single sweep mode.
Table 2.12.4 Single sweep mode specifications
Item
Function
Start condition
Stop condition
Specification
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Writing “1” to A-D converter start flag
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
End of A-D conversion
AN0 and AN1 (2 pins), AN0 to AN 3 (4 pins), AN0 to AN 5 (6 pins), or AN0 to AN7 (8 pins)
Read A-D register corresponding to selected pin
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin select bit Invalid in single sweep mode
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 0 : Single sweep mode
MD1
TRG
Trigger select bit
ADST
A-D conversion start flag
CKS0
Fbequency select bit 0
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
Bit name
A-D sweep pin select bit
0 : Any mode other than repeat sweep mode 1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Must always be set to "0".
VCUT
Vref connect bit
OPA0
External op-amp
connection mode
bit (Note 2)
OPA1
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A-D operation mode
select bit 1
Reserved bit
CKS1
Function
R W
When single sweep and repeat sweep mode 0
are
selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
When reset
0016
1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
isindeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 2.12.6 A-D conversion register in single sweep mode
Rev. 1.0
138
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat
sweep A-D conversion. Table 2.12.5 shows the specifications of repeat sweep mode 0. Figure 2.12.7
shows the A-D control register in repeat sweep mode 0.
Table 2.12.5 Repeat sweep mode 0 specifications
Item
Specification
Function
Start condition
Stop condition
Interrupt request generation timing
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
None generated
Input pin
Reading of result of A-D converter
AN0 and AN 1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin select bit Invalid in repeat sweep mode 0
CH1
CH2
MD0
MD1
A-D operation mode
select bit 0
TRG
Trigger select bit
ADST
A-D conversion start flag
CKS0
Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
A
A
A
A
A
A
A
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
Bit name
A-D sweep pin select bit
A-D operation mode
select bit 1
Reserved bit
CKS1
0 : Any mode other than repeat sweep mode 1
Must always be set to "0".
Frequency select bit 1
VCUT
Vref connect bit
OPA0
External op-amp
connection mode
bit (Note 2)
OPA1
Function
When single sweep and repeat sweep mode 0
are
selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
When reset
0016
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
A
A
AA
A
A
A
A
A
R W
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit.
Figure 2.12.7 A-D conversion register in repeat sweep mode 0
Rev. 1.0
139
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 2.12.6 shows the specifications of repeat sweep
mode 1. Figure 2.12.8 shows the A-D control register in repeat sweep mode 1.
Table 2.12.6 Repeat sweep mode 1 specifications
Item
Specification
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
None generated
AN0 (1 pin), AN0 and AN 1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Read A-D register corresponding to selected pin (at any time)
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin select bit Invalid in repeat sweep mode 1
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 1 : Repeat sweep mode 1
MD1
TRG
Trigger select bit
ADST
A-D conversion start flag
CKS0
Frequency select bit 0
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0
1
b1
b0
Symbol
ADCON1
Address
03D716
Bit symbol
Bit name
SCAN0
A-D sweep pin select bit
When reset
0016
Function
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
A-D operation mode
select bit 1
1 : Repeat sweep mode 1
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
Vref connect bit
1 : Vref connected
OPA0
External op-amp
connection mode
bit (Note 2)
MD2
Reserved bit
OPA1
Must always be set to "0".
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
R W
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 2.12.8 A-D conversion register in repeat sweep mode 1
Rev. 1.0
140
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”.
When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD
cycle is achieved. Sample and hold can be selected in all modes. However, in all modes, be sure to
specify before starting A-D conversion whether sample and hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1
can also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D7 16) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D7 16) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1,
can be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7
is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored
in the corresponding A-D register. The speed of A-D conversion depends on the response of the
external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 2.12.9 is an
example of how to connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
Analog
input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ANEX0
ANEX1
Comparator
External op-amp
Figure 2.12.9 Example of external op-amp connection mode
Rev. 1.0
141
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.13 D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters
of this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set
the target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
V REF : reference voltage
Table 2.13.1 lists the performance of the D-A converter. Figure 2.13.1 shows the block diagram of the
D-A converter. Figure 2.13.2 shows the D-A control register. Figure 2.13.3 shows the D-A converter
equivalent circuit.
Table 2.13.1 Performance of D-A converter
Item
Conversion method
Resolution
Analog output pin
Performance
R-2R method
8 bits
2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816)
AAA
AAA
D-A0 output enable bit
R-2R resistor ladder
D-A register1 (8)
P93/DA0
(Address 03DA16)
AAA
D-A1 output enable bit
R-2R resistor ladder
P94/DA1
Figure 2.13.1 Block diagram of D-A converter
Rev. 1.0
142
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
D-A control register
b7
b6
b5
b4
b3
b2
b1
Symbol
DACON
b0
Address
03DC16
Bit symbol
When reset
0016
Bit name
AA
A
AA
A
Function
DA0E
D-A0 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”
D-A register
b7
Symbol
DAi (i = 0,1)
b0
Address
03D816, 03DA16
When reset
Indeterminate
AA
A
Function
RW
R
W
Output value of D-A conversion
Figure 2.13.2 D-A control register
D-A0 output enable bit
"0"
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
DA0
"1"
2R
MSB
LSB
D-A0 register0
AVSS
VREF
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016
so that no current flows in the resistors Rs and 2Rs.
Figure 2.13.3 D-A converter equivalent circuit
Rev. 1.0
143
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.14 CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The
CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register
after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is
completed in two machine cycles.
Figure 2.14.1 shows the block diagram of the CRC circuit. Figure 2.14.2 shows the CRC-related registers. Figure 2.14.3 shows the calculation example using the CRC calculation circuit
Data bus high-order bits
Data bus low-order bits
AAAAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAA
AAAAAA
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 03BD16, 03BC16)
CRC code generating circuit
x16 + x12 + x5 + 1
CRC input register (8)
(Address 03BE16)
Figure 2.14.1 Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
Values that
can be set
Function
CRC calculation result output register
000016 to FFFF16
A
RW
CRC input register
b7
Symbo
CRCIN
b0
Function
Data input register
Address
03BE16
When reset
Indeterminate
Values that
can be set
0016 to FF16
A
RW
Figure 2.14.2 CRC-related registers
Rev. 1.0
144
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
b15
b0
CRC data register CRCD
[03BD16, 03BC16]
(1) Setting 000016
b7
b0
CRC input register
(2) Setting 0116
CRCIN
[03BE16]
2 cycles
After CRC calculation is complete
b15
b0
CRC data register
118916
CRCD
[03BD16, 03BC16]
Stores CRC code
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
9
1000 0000 0000
1000 1000 0001
1000 0001
1000 1000
1001
LSB
8
1
0000
0000
0000
0001
0001
0000
1
1000
0000
1000
0000
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
0
1
1000
MSB
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
(3) Setting 2316
CRCIN
[03BE16]
After CRC calculation is complete
b15
b0
0A4116
CRC data register
CRCD
[03BD16, 03BC16]
Stores CRC code
Figure 2.14.3 Calculation example using the CRC calculation circuit
Rev. 1.0
145
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15 Expansion Function
2.15.1 Expansion function description
Expansion function cousists of OSD display function, data slicer fanction, data encoder function and
humming decoder function. Each function is controld by expansion memories.
(1) OSD function
Character is consisted of 12 ✕ 10 dots, can display 40 (horizontal) ✕ 25 (vertical) on the fixed line. And
also, can be written over with built-in composite RAM.
M306H0SFP can be reduced external circuit by built-in SYNC-SEP (synchronous separate) and synchronous correction circuit. And it also can reduce error of character display at superimpose.
Table 2.15.1 OSD function outline
Screen composition
Number of characters displayed
Character composition
Characters available
Character sizes available
Display locations available
Blinking
40 characters ✕ 25 lines Fixed line display
(at scrolling 40 characters ✕ 24 lines)
1000 (Max.)
12 ✕ 10 dot matrix
(horizontal direction : 12 dots, vertical direction : 10 dots)
Font RAM : 256 characters
Composite RAM(SYRAM) : 15 characters
Horizontal : one time, two times
Vertical : one time, two times
setting by every line
Horizontal direction : 486 locations
Vertical direction : 235 locations
Character units
Cycle : approximately 1 second, or approximately 0.5 seconds (per screen)
Coloring
Blanking
Superimpose
Synchronous signal
Scrolling
General-purpose output ports
Synchronous correction circuit
Synchronous separation circuit
Duty 25%, 50% or 75% (per screen)
Character coloring : 8 colors choices per character
Character Background coloring : 8 colors choices per character
Background coloring : 8 colors choices per screen
Character blanking
Matrix-outline
Halftone blanking
Can be set by every line
Can be displayed
(PAL/SECAM)(monotone display)
Composite synchronous signal generate (only PAL)
Composite video signal generate (only PAL)
The top and bottom smooth scroll of the soft control
Combined port output : 9
(switching to R,G,B,GRAY,BLNK,CSYN,SLICEON, EDO1, EDO2 output)
Built-in
Built-in
(2) Data slicer function
Corresponds to TELETEXT, VPS, and VBI data
(3) Data encoder function
Encode VBI data
(4) Humming decoder function
8/4 humming and 24/18 humming
Rev. 1.0
146
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
OSD Block
Sync
generator
P117/GRAY
CSYN
Display location detection
P116/R
P115/G
Port
control
P114/B
P113/BLNK
SYRAM
P112/CSYN
Display
RAM
FSCIN
Clock
generator
SYNCIN
Syncseparate
circuit
Font
RAM
R,G,B,BLANK,GRAY
Display
control
P111/EDO1
P110/EDO2
EDO1
EDO2
VBI
encorder
VBI RAM
Clock
generator
Selecter
CVIDEO1
CVIDEO2
SVREF
Selecter
SECAMIN
Video generator
VPS
CVIN1
Clock
generator
CVIN2
Selecter
Selector
PDC
Clock
generator
Data
slicer
Slice
RAM
24/18
humming
8/4
humming
Data bus (16 bits)
CPU block
Figure 2.15.1 Block diagram of expansion function
VBI H level
VBI L level
Selecter
CVIDEO2
Selecter
CVIDEO1
CVIN2
CVIN1
SYNC/PED/GRAY
OSD white level
OSD black level
Color/color burst upper level
Color/color burst lower level
SECAMIN
Figure 2.15.2 Block diagram of video generator
Rev. 1.0
147
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.2 Expansion memory
Expansion function memory is divided by 6 patterns ; display RAM, Font RAM, SYRAM, Slice RAM,
VBIRAM and expansion register. (Humming decoder operates by the register placed on SFR). Data
writing and read out to these RAM and the expansion register are carried out 16 bit unit by the data
setting register (addresses 020216 to 021816) placed on SFR.
Contents of each memory and data setting register are shown in Table 2.15.2.
Table 2.15.2 Expansion memory composition
Expansion memory
Contents
Data setting register
Display RAM
1 screen (40 characters ✕ 25 lines) display character
setting. RAM font (character code), character color, character
backgroud color, blinking, SYRAM font (character code)
and SYRAM character color are specified by 1 character unit.
Display RAM address control register (020216)
Display RAM data control register (020416)
Font RAM
255 character fonts setting.
SYRAM
15 composite character fonts setting.
Slice RAM
Store slice data.
VBIRAM
VBI encode data setting.
Expansion register
This register controls OSD display, data slicer and
VBI encoder.
Font RAM address control register (020616 )
Font RAM data control register (020816 )
SYRAM address control register (020A16)
SYRAM data control register (020C16)
Slice RAM address control register (020E16)
Slice RAM data control register (021016 )
VBIRAM address control register (0212 16)
VBIRAM data control register (021416)
OSD register address control register (0216 16)
OSD register data control register (021816)
Rev. 1.0
148
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.3 Display RAM
Set 1 screen (40 characters ✕ 25 lines) display character.
1 character display character setting is consists is 2 addresses (even address 16 bits + odd address
8 bits), set characters available, character color, blinking, character background color, SYRAM available and SYRAM color. Display RAM composition is shown in Table 2.15.3.
Table 2.15.3 Display RAM composition
Address
(CA10 to CA0)
CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1
BB
BG
00016
0
00116
0
00216
0
BB
BG
00316
0
0
0
00416
0
BB
BG
00516
0
0
0
BR BLINK CB
Character background
0
0
0
Blinking
0
CG
CR
C7
C6
Character color
0
0
0
C5
C4
SB
SG
SR
0
CR
C7
C6
C5
C4
0
0
0
SB
SG
SR
0
BR BLINK CB
CG
CR
C7
C6
C5
C4
0
0
SB
SG
SR
0
0
0
0
0
C1
C0
Character setting of the 0th
SYC3 SYC2 SYC1 SYC0
character of the 0th line.
SYRAM character code(Note)
CG
0
C2
Remarks
Font RAM character code
SYRAM character code(Note)
BR BLINK CB
C3
CD0
C3
C2
C1
C0 Character setting of the first
SYC3 SYC2 SYC1 SYC0 character of the 0th line.
C3
C2
C1
C0
Character setting of the second
SYC3 SYC2 SYC1 SYC0 character of the 0th line.
Character setting of the third
character of the 0th line.
...
...
...
00616
Character setting of the 37th
character of the 24th line.
7CB16
7CC16
0
BB
BG
7CD16
0
0
0
7CE16
0
BB
BG
7CF16
0
0
0
BR BLINK CB
CG
CR
C7
C6
C5
C4
0
0
0
SB
SG
SR
0
BR BLINK CB
CG
CR
C7
C6
C5
C4
0
0
SB
SG
SR
0
0
0
0
0
0
C3
C2
C1
C0 Character setting of the 38th
SYC3 SYC2 SYC1 SYC0 character of the 24th line.
C3
C2
C1
C0 Character setting of the 39th
SYC3 SYC2 SYC1 SYC0 Character of the 24th line.
Note: SYRAM setting bit is G1character setting bit when set 00 16 to font RAM character code.
(Refer to Teletext G1 character display for detal)
Set accessing address (CA10 to CA0) (shown in Table 2.15.3) to display RAM address control register (address 020216), and write data (CD15 to CD0) from display RAM data control register (address
020416). After data accessing fixed, display RAM address control register iuncrements address automatically. Then, writing next address data is possible.
Display RAM bit composition is shown in Figure 2.15.3, Display RAM access registers are shown in
Figure 2.15.4, Display RAM data access block diagram is shown in Figure 2.15.5, and Address map is
shown in Figure 2.15.6 and Figure 2.15.7.
Rev. 1.0
149
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Display RAM bit composition
Even
address
CD15
Odd
address
CD14
CD13
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BB
BG
BR
BLINK
CB
CG
CR
C7
C6
C5
C4
C3
C2
C1
C0
CD15
CD14
CD13
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
0
0
0
0
0
0
0
0
SB
SG
SR
__
B it
C0
Bit name
__
SYC3 SYC2 SYC1 SYC0
Function
Font RAM bit
Set font RAM character code.
C1
C2
Character code 0016 is corresponded to teletext G1 character.
(Refer to "Teletext G1 character display".)
C3
C4
C5
C6
C7
CR
Character color bit
Set color code of font RAM character color (Note 2)
CG
CB
BLINK
Blinking bit
0 : Do not blink
1 : Blink
BR
Character background color bit
Set color code of font RAM character background color (Note 2)
BG
BB
__
SYC0
__
SYRAM bit
Set SYRAM character code which composes to font RAM
setting by C0 to C7. When it is not composed, set character
code F16.
These bit are teletext G1 character setting bit when C7 to C0 is
0016 setting.
SYC1
SYC2
SYC3
__
SR
Must always be set to "0".
__
SYRAM color bit
SG
SB
Must always be set to "0".
Set color code of SYRAM color (Note 2).
These bit are teletext G1 character setting bit when C7 to C0 is
0016 setting.
Notes 1. The contents of display RAM is indefinite at reset.
2. Color code setting
B
0
0
0
0
1
1
1
1
Color code
G
0
0
1
1
0
0
1
1
R
0
1
0
1
0
1
0
1
Color setting
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
Color code (R, G, B) is corresponded to character color bit (CR, CG,
CB), Character backgroud color bit (BR,BG, BB) and SYRAM color bit
(SR, SG, SB).
Refer to expansion register composition (Address 0A16) for color setting
at expansion register GRYON = "1".
Figure 2.15.3 Display RAM bit composotion
Rev. 1.0
150
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Display RAM address control register
b15
b10
b8
b7
b0
Symbol
CA
Address
020216
Function
When reset
00002
Setting possible value
Specify accessing display RAM address
RW
00016 to 7CF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : When access to display RAM, must be set display RAM address at first, then use
display RAM data control register (0204 16).
Display RAM address control register increments by accessing display RAM data
control register. So, it is not neccesary to setting the next display RAM address.
Display RAM data control register
b15
b8 b7
b0
Symbol
CD
Address
020416
Function
When reset
00002
Setting possible value
Write and read out the data of display RAM which is specified
by display RAM address control register (address 0202 16)
RW
000016 to 7FFF16
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.4 Display RAM access registers
Data bus (16-bit)
(address 020216)
Display RAM address control
register (11) (CA10 to CA0)
Display RAM data control
register (16) (CD15 to CD0)
(address 020416)
Increment automatically
after data access
Display RAM
40 characters 25 lines
Figure 2.15.5 Display RAM access block diagram
Rev. 1.0
151
152
368 36A 36C 36E
369 36B 36D 36F
408 40A 40C 40E
409 40B 40D 40F
458 45A 45C 45E
459 45B 45D 45F
4F8 4FA 4FC 4FE
4F9 4FB 4FD 4FF
548 54A 54C 54E
549 54B 53D 54F
286 288 28A 28C 28E 290
287 289 28B 28D 28F 291
376 378 37A 37C 37E 380
377 379 37B 37D 37F 381
466 468 46A 46C 46E 470
467 469 46B 46D 46F 471
280 282 284
281 283 285
320 322 324
321 323 325
370 372 374
371 373 375
3C0 3C2 3C4 3C6 3C8 3CA 3CC 3CE 3D0 3D2 3D4 3D6 3D8 3DA 3DC 3DE 3E0 3E2 3E4 3E6 3E8 3EA 3EC 3EE 3F0 3F2 3F4 3F6 3F8 3FA 3FC 3FE 400 402 404 406
3C1 3C3 3C5 3C7 3C9 3CB 3CD 3CF 3D1 3D3 3D5 3D7 3D9 3DB 3DD 3DF 3E1 3E3 3E5 3E7 3E9 3EB 3ED 3EF 3F1 3F3 3F5 3F7 3F9 3FB 3FD 3FF 401 403 405 407
416 418 41A 41C 41E 420
417 419 41B 41D 41F 421
230 232 234
231 233 235
2D0 2D2 2D4 2D6 2D8 2DA 2DC 2DE 2E0 2E2 2E4 2E6 2E8 2EA 2EC 2EE 2F0 2F2 2F4 2F6 2F8 2FA 2FC 2FE 300 302 304 306 308 30A 30C 30E 310 312 314 316
2D1 2D3 2D5 2D7 2D9 2DB 2DD 2DF 2E1 2E3 2E5 2E7 2E9 2EB 2ED 2EF 2F1 2F3 2F5 2F7 2F9 2FB 2FD 2FF 301 303 305 307 309 30B 30D 30F 311 313 315 317
326 328 32A 32C 32E 330
327 329 32B 32D 32F 331
190 192 194
191 193 195
1E0 1E2 1E4 1E6 1E8 1EA 1EC 1EE 1F0 1F2 1F4 1F6 1F8 1FA 1FC 1FE 200
1E1 1E3 1E5 1E7 1E9 1EB 1ED 1EF 1F1 1F3 1F5 1F7 1F9 1FB 1FD 1FF 201
236 238 23A 23C 23E 240
237 239 23B 23D 23F 241
140 142 144
141 143 145
410 412 414
411 413 415
460 462 464
461 463 465
4B0 4B2 4B4 4B6 4B8 4BA 4BC 4BE 4C0 4C2 4C4 4C6 4C8 4CA 4CC 4CE 4D0 4D2 4D4 4D6 4D8 4DA 4DC 4DE 4E0 4E2 4E4 4E6 4E8 4EA 4EC 4EE 4F0 4F2 4F4 4F6
4B1 4B3 4B5 4B7 4B9 4BB 4BD 4BF 4C1 4C3 4C5 4C7 4C9 4CB 4CD 4CF 4D1 4D3 4D5 4D7 4D9 4DB 4DD 4DF 4E1 4E3 4E5 4E7 4E9 4EB 4ED 4EF 4F1 4F3 4F5 4F7
500 502 504
501 503 505
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 11
Line 12
Line 13
Line 14
Line 15
Line 16
278 27A 27C 27E
279 27B 27D 27F
228 22A 22C 22E
229 22B 22D 22F
188 18A 18C 18E
189 18B 18D 18F
138 13A 13C 13E
139 13B 13D 13F
512 514 516 518 51A 51C 51E 520
513 515 517 519 51B 51D 51F 521
472 474 476 478 47A 47C 47E 480
473 475 477 479 47B 47D 47F 481
422 424 426 428 42A 42C 42E 430
423 425 427 429 42B 42D 42F 431
382 384 386 388 38A 38C 38E 390
383 385 387 389 38B 38D 38F 391
332 334 336 338 33A 33C 33E 340
333 335 337 339 33B 33D 33F 341
522 524 526 528 52A 52C 52E 530 532 534 536 538 53A 53C 53E 540 542 544 546
523 525 527 529 52B 52D 52F 531 533 535 537 539 53B 53D 53F 541 543 545 547
482 484 486 488 48A 48C 48E 490 492 494 496 498 49A 49C 49E 4A0 4A2 4A4 4A6 4A8 4AA 4AC 4AE
483 485 487 489 48B 48D 48F 491 493 495 497 499 49B 49D 49F 4A1 4A3 4A5 4A7 4A9 4AB 4AD 4AF
432 434 436 438 43A 43C 43E 440 442 444 446 448 44A 44C 44E 450 452 454 456
433 435 437 439 43B 43D 43F 441 443 445 447 449 44B 43D 44F 451 453 455 457
392 394 396 398 39A 39C 39E 3A0 3A2 3A4 3A6 3A8 3AA 3AC 3AE 3B0 3B2 3B4 3B6 3B8 3BA 3BC 3BE
393 395 397 399 39B 39D 39F 3A1 3A3 3A5 3A7 3A9 3AB 3AD 3AF 3B1 3B3 3B5 3B7 3B9 3BB 3BD 3BF
342 344 346 348 34A 34C 34E 350 352 354 356 358 35A 35C 35E 360 362 364 366
343 345 347 349 34B 23D 34F 351 353 355 357 359 35B 35D 35F 361 363 365 367
292 294 296 298 29A 29C 29E 2A0 2A2 2A4 2A6 2A8 2AA 2AC 2AE 2B0 2B2 2B4 2B6 2B8 2BA 2BC 2BE 2C0 2C2 2C4 2C6 2C8 2CA 2CC 2CE
293 295 297 299 29B 29D 29F 2A1 2A3 2A5 2A7 2A9 2AB 2AD 2AF 2B1 2B3 2B5 2B7 2B9 2BB 2BD 2BF 2C1 2C3 2C5 2C7 2C9 2CB 2CD 2CF
242 244 246 248 24A 24C 24E 250
243 245 247 249 24B 24D 24F 251
162 164 166 168 16A 16C 16E 170 172 174 176 178 17A 17C 17E 180 182 184 186
163 165 167 169 16B 16D 16F 171 173 175 177 179 17B 17D 17F 181 183 185 187
112 114 116 118 11A 11C 11E 120 122 124 126 128 12A 12C 12E 130 132 134 136
113 115 117 119 11B 11D 11F 121 123 125 127 129 12B 12D 12F 131 133 135 137
Notes 1. The hexadecimal numbers in the boxes show the display RAM address.
2. A character is set in 2 addresses (even address (upper stage in the figure 1) 16 bit + odd number address (lower step in the figure 1) 8 bits).
506 508 50A 50C 50E 510
507 509 50B 50D 50F 511
318 31A 31C 31E
319 31B 31D 31F
252 254 256 258 25A 25C 25E 260 262 264 266 268 26A 26C 26E 270 272 274 276
253 255 257 259 25B 25D 25F 261 263 265 267 269 26B 26D 26F 271 273 275 277
152 154 156 158 15A 15C 15E 160
153 155 157 159 15B 15D 15F 161
146 148 14A 14C 14E 150
147 149 14B 14D 14F 151
196 198 19A 19C 19E 1A0 1A2 1A4 1A6 1A8 1AA 1AC 1AE 1B0 1B2 1B4 1B6 1B8 1BA 1BC 1BE 1C0 1C2 1C4 1C6 1C8 1CA 1CC 1CE 1D0 1D2 1D4 1D6 1D8 1DA 1DC 1DE
197 199 19B 19D 19F 1A1 1A3 1A5 1A7 1A9 1AB 1AD 1AF 1B1 1B3 1B5 1B7 1B9 1BB 1BD 1BF 1C1 1C3 1C5 1C7 1C9 1CB 1CD 1CF 1D1 1D3 1D5 1D7 1D9 1DB 1DD 1DF
202 204 206 208 20A 20C 20E 210 212 214 216 218 21A 21C 21E 220 222 224 226
203 205 207 209 20B 20D 20F 211 213 215 217 219 21B 21D 21F 221 223 225 227
102 104 106 108 10A 10C 10E 110
103 105 107 109 10B 10D 10F 111
0F0 0F2 0F4 0F6 0F8 0FA 0FC 0FE 100
0F1 0F3 0F5 0F7 0F9 0FB 0FD 0FF 101
Line 3
098 09A 09C 09E
099 09B 98D 09F
0A0 0A2 0A4 0A6 0A8 0AA 0AC 0AE 0B0 0B2 0B4 0B6 0B8 0BA 0BC 0BE 0C0 0C2 0C4 0C6 0C8 0CA 0CC 0CE 0D0 0D2 0D4 0D6 0D8 0DA 0DC 0DE 0E0 0E2 0E4 0E6 0E8 0EA 0EC 0EE
0A1 0A3 0A5 0A7 0A9 0AB 0AD 0AF 0B1 0B3 0B5 0B7 0B9 0BB 0BD 0BF 0C1 0C3 0C5 0C7 0C9 0CB 0CD 0CF 0D1 0D3 0D5 0D7 0D9 0DB 0DD 0DF 0E1 0E3 0E5 0E7 0E9 0EB 0ED 0EF
072 074 076 078 07A 07C 07E 080 082 084 086 088 08A 08C 08E 090 092 094 096
073 075 077 079 07B 07D 07F 081 083 085 087 089 08B 08D 08F 091 093 095 097
Line 2
062 064 066 068 06A 06C 06E 070
063 065 067 069 06B 06D 06F 071
056 058 05A 05C 05E 060
057 059 05B 05D 05F 061
050 052 054
051 053 055
Character 39
048 04A 04C 04E
049 04B 04D 04F
Line 1
022 024 026 028 02A 02C 02E 030 032 034 036 038 03A 03C 03E 040 042 044 046
023 025 027 029 02B 02D 02F 031 033 035 037 039 03B 03D 03F 041 043 045 047
Line 0
012 014 016 018 01A 01C 01E 020
013 015 017 019 01B 01D 01F 021
006 008 00A 00C 00E 010
007 009 00B 00D 00F 011
000 002 004
001 003 005
Character 0
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Figure 2.15.6 Address map 1 (continued)
Rev. 1.0
752 754 756 758 75A 75C 75E 760 762 764 766 768 76A 76C 76E 770 772 774 776
753 755 757 759 75B 75D 75F 761 763 765 767 769 76B 76D 76F 771 773 775 777
6E0 6E2 6E4 6E6 6E8 6EA 6EC 6EE 6F0 6F2 6F6 6F6 6F8 6FA 6FC 6FE 700
6E1 6E3 6E5 6E7 6E9 6EB 6ED 6EF 6F1 6F3 6F5 6F7 6F9 6FB 6FD 6FF 701
736 738 73A 73C 73E 740
737 739 73B 73D 73F 741
786 788 78A 78C 78E 790
787 789 78B 78D 78F 791
690 692 694
691 693 695
730 723 734
731 733 735
780 782 784
781 783 785
Line 21
Line 22
Line 23
Line 24
662 664 666 668 66A 66C 66E 670 672 674 676 678 67A 67C 67E 680 682 684 686
663 665 667 669 66B 66D 66F 671 673 675 677 679 67B 67D 67F 681 683 685 687
778 77A 77C 77E
779 77B 77D 77F
728 72A 72C 72E
729 72B 72D 72F
688 68A 68C 68E
689 68B 68D 68F
Notes 1. The hexadecimal numbers in the boxes show the display RAM address.
2. A character is set in 2 addresses (even address (upper stage in the figure 1) 16 bit + odd number address (lower step in the figure 1) 8 bits).
792 794 796 798 79A 79C 79E 7A0 7A2 7A4 7A6 7A8 7AA 7AC 7AE 7B0 7B2 7B4 7B6 7B8 7BA 7BC 7BE 7C0 7C2 7C4 7C6 7C8 7CA 7CC 7CE
793 795 797 799 79B 79D 79F 7A1 7A3 7A5 7A7 7A9 7AB 7AD 7AF 7B1 7B3 7B5 7B7 7B9 7BB 7BD 7BF 7C1 7C3 7C5 7C7 7C9 7CB 7CD 7CF
743 744 746 748 74A 74C 74E 750
744 745 747 749 74B 74D 74F 751
696 698 69A 69C 69E 6A0 6A2 6A4 6A6 6A8 6AA 6AC 6AE 6B0 6B2 6B4 6B6 6B8 6BA 6BC 6BE 6C0 6C2 6C4 6C6 6C8 6CA 6CC 6CE 6D0 6D2 6D4 6D6 6D8 6DA 6DC 6DE
697 699 69B 69D 69F 6A1 6A3 6A5 6A7 6A9 6AB 6AD 6AF 6B1 6B3 6B5 6B7 6B9 6BB 6BD 6BF 6C1 6C3 6C5 6C7 6C9 6CB 6CD 6CF 6D1 6D3 6D5 6D7 6D9 6DB 6DD 6DF
702 704 706 708 70A 70C 70E 710 712 714 716 718 71A 71C 71E 720 722 724 726
703 705 707 709 70B 70D 70F 711 713 715 717 719 71B 71D 71F 721 723 725 727
652 654 656 658 65A 65C 65E 660
653 655 657 659 65B 65D 65F 661
646 648 64A 64C 64E 650
647 649 64B 64D 64F 651
640 642 644
641 643 645
638 63A 63C 63E
639 63B 63D 63F
Line 20
612 614 616 618 61A 61C 61E 620 622 624 626 628 62A 62C 62E 630 632 634 636
613 615 617 619 61B 61D 61F 621 623 625 627 629 62B 62D 62F 631 633 635 637
602 604 606 608 60A 60C 60E 610
603 605 607 609 60B 60D 60F 611
5F0 5F2 5F4 5F6 5F8 5FA 5FC 5FE 600
5F1 5F3 5F5 5F7 5F9 5FB 5FD 5FF 601
Line 19
Character 39
598 59A 59C 59E
599 59B 59D 59F
5A0 5A2 5A4 5A6 5A8 5AA 5AC 5AE 5B0 5B2 5B4 5B6 5B8 5BA 5BC 5BE 5C0 5C2 5C4 5C6 5C8 5CA 5CC 5CE 5D0 5D2 5D4 5D6 5D8 5DA 5DC 5DE 5E0 5E2 5E4 5E6 5E8 5EA 5EC 5EE
5A1 5A3 5A5 5A7 5A9 5AB 5AD 5AF 5B1 5B3 5B5 5B7 5B9 5BB 5BD 5BF 5C1 5C3 5C5 5C7 5C9 5CB 5CD 5CF 5D1 5D3 5D5 5D7 5D9 5DB 5DD 5DF 5E1 5E3 5E5 5E7 5E9 5EB 5ED 5EF
572 574 576 578 57A 57C 57E 580 582 584 586 588 58A 58C 58E 590 592 594 596
573 575 577 579 57B 57D 57F 581 583 585 587 589 58B 58D 58F 591 593 595 597
Line 18
562 564 566 568 56A 56C 56E 570
563 565 567 569 56B 56D 56F 571
Line 17
556 558 55A 55C 55E 560
557 559 55B 55D 55F 561
550 552 554
551 553 555
Character 0
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Figure 2.15.7 Address map 2
Rev. 1.0
153
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Teletext G1 character display
Can display teletext G1 character by setting character code 0016 to font RAM bit (C7 to C0) of display
RAM. SYRAM setting is invalid when set 00 16 to font RAM bit (C7 to C0), set G1 character by G1
character bit (G0 to G5) and G1character form bit(G6). At the time, set 0 to all addresses of font RAM
code 0016 (font RAM addresses 00016 to 00916).
Display RAM composition at G1 character display is shown in Figure 2.15.8.
Even
address
CD15
Odd
address
CD14
CD13
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
BB
BG
BR
BLINK
CB
CG
CR
0
(C7)
0
(C6)
0
(C5)
0
(C4)
0
(C3)
0
(C2)
0
(C1)
0
(C0)
CD15
CD14
CD13
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
0
0
0
0
0
0
0
0
G6
(SB)
G5
(SG)
G4
(SR)
__
Bit
0(C0)
Bit name
__
CD2
CD1
CD0
G2
(SYC2)
G1
(SYC1)
G0
(SYC0)
Function
Font RAM bit
Set 0016 when display teletext G1 character.
At the time , set space in font RAM(0016).
G1 character color bit
Set color code of G1 character color.
0(C1)
CD3
G3
(SYC3)
0(C2)
0(C3)
0(C4)
0(C5)
0(C6)
0(C7)
CR
CG
CB
BLINK
Blinking bit
0 : Do not blink
1 : Blink
BR
BG
BB
__
G0(SYC0)
G1 character background
color bit
__
G1 character bit(1)
Set color code of G1 character background color.
Must always be set to "0".
Set G1 character by G0 to G5.
(Refer to the next page.)
G1(SYC1)
G2(SYC2)
G3(SYC3)
__
G4(SR)
__
Set G1 character by G0 to G5.
(Refer to the next page.)
G1 character form bit
0 : Contiguous form (Refer to the next page)
1 : Separated form
G5(SG)
G6(SB)
Must always be set to "0".
G1 character bit(1)
Figure 2.15.8 Display RAM bit composotion(at G1 character displaying )
Rev. 1.0
154
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
G1 character composition
Set G1 character by display RAM G1 character bit (G0 to G5) and G1 character form bit(G6). G1
character composition is shown in Figure 2.15.9. G1 character is divided to 6 blocks (refer to Figure
2.15.9), and set character by G0 to G5 in each block. Also, G1 character form is set by G6.
Can display 64 patterns G1 character by using G0 to G5. G1 character composition is shown in Figure
2.15.10.
10dots
12dots
G0
G1
3dots
G2
G3
4dots
G4
G5
3dots
6dots
6dots
Figure 2.15.9 G1 character composition
Example1:G0,G1,G5=1,G2,G3,G4=0
Example2:G3,G4=1,G0,G1,G2,G5=0
10 dots
G6=0
(Contiguous
form)
12 dots
10 dots
12 dots
12 dots
10 dots
G6=1
(Separated
form)
10 dots
12 dots
Figure 2.15.10 G1 character setting
Set 0 to G0 to G5 when use font RAM code 0016 as normal character.
However, SYRAM can not be displayed.
Rev. 1.0
155
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.4 Font RAM
Character font composited horizontal direction 12 dots ✕ vertical direction 10 dots is set to font RAM
code 0016 to FF16 (255 available, 7F16:blank code).
1 character setting is 10 address composite (12-bit ✕ 10 addresses).
Setting character is displayed by specifying font RAM code to font RAM bit of display RAM. Font RAM
code 0016 is corresponds to Teletext G1 character. Then, font RAM code 7F16 is fixed by blank,
character font setting to this code is disable. Font RAM composition is shown in Table 2.15.4.
Table 2.15.4 Font RAM composition
Font RAM addresses
FD11 FD10
(FA11 to FA0)
00016
00116
00216
00316
00416
00516
00616
00716
00816
00916
F0B
F1B
F2B
F3B
F4B
F5B
F6B
F7B
F8B
F9B
F0A
F1A
F2A
F3A
F4A
F5A
F6A
F7A
F8A
F9A
FD9
FD8
F09
F19
F29
F39
F49
F59
F69
F79
F89
F99
F08
F18
F28
F38
F48
F58
F68
F78
F88
F98
FD7
F07
F17
F27
F37
F47
F57
F67
F77
F87
F97
FD6
FD5
FD4
FD3
FD2
FD1
FD0
F06
F16
F26
F36
F46
F56
F66
F76
F86
F96
F05
F15
F25
F35
F45
F55
F65
F75
F85
F95
F04
F14
F24
F34
F44
F54
F64
F74
F84
F94
F03
F13
F23
F33
F43
F53
F63
F73
F83
F93
F02
F12
F22
F32
F42
F52
F62
F72
F82
F92
F01
F11
F21
F31
F41
F51
F61
F71
F81
F91
F00
F10
F20
F30
F40
F50
F60
F70
F80
F90
Font RAM code (0016)
F04
F03
F02
F01
F00
Font RAM code (0116)
Remarks
...
00A16
Unused area
...
...
...
...
...
...
F05
...
F06
...
F07
...
F08
...
F09
...
F0A
...
F0B
...
00F16
01016
01916
F9B
F9A
F99
F98
F97
F96
F95
F94
F93
F92
F91
F90
02016
...
...
F93
F03
F92
F02
F91
F01
F90
F00
F9B
F9A
F99F F98F F97
...
...
F94
F04
...
F95
F05
...
F96
F06
...
F97
F07
...
F98
F08
...
F99
F09
...
F9A
F0A
...
F9B
F9B
...
...
F00
...
F01
...
F02
...
F03
...
F04
...
F05
...
F06
...
F07
...
F08
...
F09
...
FF916
F0A
...
...
FE916
FF016
F0B
...
...
FD916
FE016
...
...
Font RAM code (0216)
Font RAM code (FD16)
F96
F95
F94
F93
F92
F91
F90
Font RAM code (FE16)
Font RAM code (FF16)
For accessing to font RAM data, set accessing address (FA11 to FA0) (shown in Table 2.15.4) to font
RAM address control register (020616 ). Then write data (FD11 to FD0) by font RAM data control
register (020816. After data accessing fixed, font RAM address control register increments address
automatically. Then, next address data writing is possible. Do not access to unused area (addresses
xA16 to xF16) of each Font RAM codes. But, when write data in succession, jump unused area and
increments address automatically. (ex. increment automatically from address 00916 to 01016).
Font composition is shown in Figure 2.15.11, Setting example is shown in Figure 2.15.12, Font RAM
access registers are shown in Figure 2.15.13 and Font RAM access block diagram is shown in Figure
2.15.14.
10 dots
12 dots
Figure 2.15.11 Font composition
Rev. 1.0
156
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Example of font RAM code 0216 ....... Set character by addresses 02016 to 02916 data setting.
Address
10 dots
FA
02016
02116
02216
02316
02416
02516
02616
02716
02816
02916
12 dots
FD
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 1 1 1 1 1 0 0 0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
1
1
0
0
0
10 dots
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
12 dots
1 bit: 1 dot of character
Figure 2.15.12 Setting example of font RAM
Font RAM address control register
b15
b11
b8
b7
b0
Symbol
FA
Function
Address
020616
When reset
00002
Setting possible value
RW
00016 to FF916
Specify accessing font RAM address
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : When access to font RAM, must be set font RAM at first, then use font RAM data
control register (020816).
Font RAM address control register increments by accessing font RAM data
control register. So, it is not neccesary to setting the next font RAM address.
Font RAM data control register
b15
b11
b8
b7
b0
Symbol
FD
Function
Write and read out the data of font RAM which is specified
by font RAM address control register (address 0206 16)
Address
020816
When reset
00002
Setting possible value
RW
00016 to FFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.13 Font RAM access registers
Rev. 1.0
157
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Data bus (16-bit)
(address 020616)
Font RAM address control
register (11) (FA11 to FA0)
Font RAM data control
register (12) (FD11 to FD0)
(address 020816)
Increment automatically
after data access
Font RAM
Character code 0016 to FF16
Figure 2.15.14 Font RAM access block diagram
Rev. 1.0
158
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.5 SYRAM
Character font composite horizontal direction 12 dots ✕ vertical direction 10 dots is set to SYRAM
code 016 to E16 (15 available).
Setting composite character is composed to font RAM by specifying SYRAM code to SYRAM bit of
display RAM. Then, SYRAM code F16 is fixed by blank, character font setting to this code is disable.
Use F16 when SYRAM is not composed to character.
SYRAM composite is shown in Table 2.15.5.
Table 2.15.5 SYRAM composition
Font RAM addresses
YD12 YD11
(FA10 to FA0)
0016
0116
0216
0316
0416
0516
0616
0716
0816
0916
SYEX0
SYEX1
SYEX2
SYEX3
SYEX4
SYEX5
SYEX6
SYEX7
SYEX8
SYEX9
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
Remarks
SY0B
SY1B
SY0A
SY1A
SY09
SY19
SY08
SY18
SY07
SY17
SY06
SY16
SY05
SY15
SY04
SY14
SY03
SY13
SY02
SY12
SY01
SY11
SY00
SY10
SYRAM code (016)
SY2B
SY3B
SY4B
SY5B
SY2A
SY3A
SY4A
SY5A
SY29
SY39
SY49
SY59
SY28
SY38
SY48
SY58
SY27
SY37
SY47
SY57
SY26
SY36
SY46
SY56
SY25
SY35
SY45
SY55
SY24
SY34
SY44
SY54
SY23
SY33
SY43
SY53
SY22
SY32
SY42
SY52
SY21
SY31
SY41
SY51
SY20
SY30
SY40
SY6B
SY7B
SY8B
SY6A
SY7A
SY8A
SY69
SY79
SY89
SY68
SY78
SY88
SY67
SY77
SY87
SY66
SY76
SY86
SY65
SY75
SY85
SY64
SY74
SY84
SY63
SY73
SY83
SY62
SY72
SY82
SY61
SY71
SY81
SY50
SY60
SY70
SY80
SY9B
SY9A
SY99
SY98
SY97
SY96
SY95
SY94
SY93
SY92
SY91
SY90
SY05
SY04
SY03
SY02
SY01
SY00
YD10
YD9
YD8
...
0A16
...
...
...
SY97
SY06
...
SY98
SY07
...
...
...
SY99
SY08
...
SY9A
SY09
...
SYEX9 SY9B
SY0A
...
...
SYEX0 SY0B
...
1916
Unused area
...
...
0F16
1016
SY96
SY95
SY94
SY93
SY92
SY91
SY90
2016
...
SY90
SY01
SY00
SY97
SY96
SY95
SY94
SY93
SY92
SY91
...
...
SY91
SY02
...
SY92
SY03
...
SY93
SY04
...
SY94
SY05
...
SY95
SY06
...
SY96
SY07
...
SY97
SY08
...
SY98
...
...
...
SY00
...
SY01
...
SY02
...
SY03
...
SY04
SY09
SY98
...
SY05
SY99
SY99
...
SY06
SY0A
SY9A
...
SY07
SY9A
SYEX9 SY9B
...
SY08
SYEX0 SY9B
...
...
SY09
SYEX9 SY9B
...
...
SY0A
...
E916
SYEX0 SY0B
...
...
D916
E016
...
SYRAM code (216)
...
...
C916
D016
SYRAM code (116)
SYRAM code (C16)
SYRAM code (D16)
SYRAM code (E16)
SY90
For accessing to SYRAM data, set accessing address (YA7 to YA0) (shown in Table 2.15.5) to
SYRAM address control register (020A16). Then write data (YD12 to YD0) by SYRAM data control
register (020C16 ). When end the accessing, SYRAM address control register increments address
automatically. Then, next address data writing is possible. Do not access to unused area (addresses
xA16 to xF 16) of each SYRAM codes. But, when write data in succession, jump unused area and
increments address automatically. (ex. increment automatically from address 0916 to 1016).
Setting example is shown in Figure 2.15.15, SYRAM access registers are shown in Figure 2.15.16
and SYRAM access block diagram is shown in Figure 2.15.17.
Rev. 1.0
159
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
10 dots
Example of SYRAM code 016 ....... Set character by addresses 0016 to 0916 data setting.
12 dots
Address
YA 12 1110 9
0016 * 0 0 0
0116 * 0 0 0
0216 * 0 0 0
0316 * 0 0 0
0416 * 0 0 0
0516 * 0 0 0
0616 * 0 0 0
0716 * 0 0 0
0816 * 0 0 0
0916 * 0 0 1
8
0
0
0
0
0
0
0
0
1
1
7
0
0
0
0
0
0
0
1
1
1
FD
6
0
0
0
0
0
0
1
1
1
1
5
0
0
0
0
0
1
1
1
1
1
4
0
0
0
0
1
1
1
1
1
1
3
0
0
0
1
1
1
1
1
1
1
2
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1 10 dots
1
1
1
1
1
12 dots
Color expansion bit SYEXx (set for each dot line)
The HIDE register (address 0D16 ) becomes valid for
only the dot line where * = 1.
For details, refer to the next section, “Compositing
font RAM and SYRAM.”
1 bit: 1 dot of character
Figure 2.15.15 Setting example of SYRAM
SYRAM address control register
b15
b8
b7
b0
Symbol
YA
Function
Address
020A16
When reset
000016
Setting possible value
Specify accessing SYRAM address
RW
0016 to E916
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : When access to SYRAM, must be set SYRAM at first, then use SYRAM data
control register (020C16).
SYRAM address control register increments by accessing SYRAM data control
register. So, it is not neccesary to setting the next SYRAM address.
SYRAM data control register
b15
b8
b7
b0
Symbol
YD
Function
Write and read out the data of SYRAM which is specified
by SYRAM address control register (address 020A16)
Address
020C16
When reset
000016
Setting possible value
RW
000016 to 1FFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.16 SYRAM access registers
Rev. 1.0
160
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Data bus (16-bit)
(address 020A16)
SYRAM address control
register (8) (YA7 to YA0)
SYRAM data control
register (13) (YD12 to YD0)
(address 020C16)
Increment automatically
after data access
SYRAM
Character code 016 to E16
Figure 2.15.17 SYRAM access block diagram
Rev. 1.0
161
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Compositing font RAM and SYRAM
Can composite characters in font RAM with SYRAM.
The compositing method is determined by the SYEXx color expansion bit and the HIDE register (address 0D16).
For dot lines where SYEXx = 0, the SYRAM color is set by the display RAM’s SR, SG, and SB irrespective of the HIDE register’s content.
If the HIDE register’s content is 0, the SYRAM color for dot lines where SYEXx = 1 is set by the
registers LINER, LINEG, and LINEB (address 0816).
If the HIDE register’s content is 1, the font RAM part of the dot lines where SYEXx = 1 is overwritten in
HIDE mode with colors set by the registers LINER, LINEG, and LINEB irrespective of the font RAM’s
content and color. The color of the SYRAM part is set by the display RAM’s SR, SG, and SB as in the
case of dot lines where SYEXx = 0.
Figure 2.15.18 shows an example for each instance of compositing.
Font RAM
SYRAM
Compositing
Contents of
register
HIDE
0 (normal mode)
1 (HIDE mode)
SYEXx
Ex. 1
Ex. 2
0
0
0
0
0
0
0
0
0
0
SYEXx
1
1
1
1
1
0
0
0
0
0
SR,
SG,
SB
LINER,
LINEG,
LINEB
SR,
SG,
SB
SYEXx
0
0
0
0
0
0
0
0
0
0
SYEXx
1
1
1
1
1
0
0
0
0
0
SR,
SG,
SB
LINER,
LINEG,
LINEB
SR,
SG,
SB
When HIDE = 1, the font RAM’s contents for dot lines where SYEXx = 1 become invisible.
Figure 2.15.18 Compositing example
Rev. 1.0
162
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.6 Slice RAM
Store 18-line slice data. There are 3 types of Slice data : PDC, VPS and VBI. All data are stored to
addresses which corresponds to slicing line (ex. 22 line' data is stored to addresses 20016 to 21716 ).
24 addresses (SR00x to SR17x) are prepared for 1 line, slice data is stored in order from LSB side.
Then, slice datas and field information are stored to the top address of each line.
Slice RAM composite is shown in Table 2.15.6.
Table 2.15.6 Slice RAM composition
Slice RAM addresses
SD15 SD14 SD13 SD12 SD11 SD10 SD9
(SA9 to SA0)
01616
01716
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1 SD0
Remarks
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 6th line or 318th line
SR01F SR01E SR01D SR01C SR01B SR01A SR019 SR018 SR017 SR016 SR015 SR014 SR013 SR012 SR011 SR010 slice data
...
...
00016
00116
SR16F SR16E SR16D SR16C SR16B SR16A SR169 SR168 SR167 SR166 SR165 SR164 SR163 SR162 SR161 SR160
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
01816
03716
Unused area
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 7th line or 319 th line
slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
...
01F16
02016
8th line to 21th line
or 320th line to 333 line
slice data
23716
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 23th line or 335th line
slice data
...
...
21716
22016
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 22th line or 334th line
slice data
...
...
1F716
20016
...
...
04016
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
For accessing to slice RAM data, set accessing address (SA9 to SA0) (shown in Table 2.15.6) to slice
RAM address control register (address 020E16 ). Then read out data from slice RAM data control
register (address 021016 ). When end the data reading, slice RAM address control register increments address automatically. Then, next address data reading is possible. Do not access to unused
area of each character codes. Must set address to each line because unused area has no address'
automatically increment.
Slice RAM bit composition is shown in Figure 2.15.19, Slice RAM access registers are shown in
Figure 2.15.20 and Slice RAM access block diagram is shown in Figure 2.15.21.
Rev. 1.0
163
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
The each head address of the address is corresponded to slicing line has stored next slice information.
PDC
VPS
VBI
Other
SR002
0
0
1
0
SR003
field * (Note)
field * (Note)
field * (Note)
0
SR00F to SR004
0
0
0
0
SR001
0
1
0
0
SR000
1
0
0
0
Note : * the first field : 1
the second field : 0
(1) PDC
In case of the PDC data, 16 bits (2 data) are stored for the 1 address from the LSB side.
Clock run-in
+ flaming code
Data 1
Data 3
Data 2
L
S
B
Data 5
Data 4
Data 39
Data 42
Data 41
M
S
B
ML
S S
B B
SR010
Data 40
Data 6
SR01F
SR020
SR030
S02F
S03F
SR140
S14F
SR150
S15F
SR16x to SR17x are unused area.
(2) VPS
In case of the VPS data, 8 bits (a data) are stored for an address from the LSB side.
Low-order 8 bits stores the slice data. And, high-order 8 bits become warning bit, when the send data is not recognized as bi-phase
type.
The case of bi-phase data ="1,0" or "0,1" (the bi-phase type) becomes "0" for this warning bit, and it becomes "1" in bi-phase data
="0,0" or "1,1" (it is not the bi-phase type). (For example, bi-phase data of SR011 is "0,0" or "1,1", "1" is set to SR019.)
Clock run-in
+ flaming code
Data 1
Data 3
Data 12
Data 2
L
S
B
SR010
Data 4
M L
S S
B B
M
S
B
SR017
SR020
SR030
SR027
Data 11
SR037
SR040
SR0B0
SR047
Data 13
SR0B7 SR0D0
SR0C0
SR0D7
SR0C7
SR0Ex to SR17x are unused area.
(3) VBI
Clock run-in
+ flaming code
Data 1
Data 2
L
S
B
M L
S S
B B
SR010
SR017
SR020
Data 3
Data 4
Data 5
M
S
B
SR030
SR027
SR037
SR040
SR050
SR047
SR057
SR06x to SR17x are unused area.
Figure 2.15.19 Slice RAM bit composition
Rev. 1.0
164
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Slice RAM address control register
b15
b9
b8
b7
b0
Symbol
SA
Function
Address
020E16
When reset
000016
Setting possible value R W
Specify accessing slice RAM address
00016 to 23716
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : When access to slice RAM, must be set slice RAM at first, then use slice RAM data
control register (021016).
Slice RAM address control register increments by accessing slice RAM data control
register. So, it is not neccesary to setting the next slice RAM address.
Slice RAM data control register
b15
b9
b8
b7
b0
Symbol
SD
Address
021016
When reset
000016
Function
RW
Read out the data of slice RAM.
Read out data of slice RAM which is specified by slice RAM address control register (
address 020E16) by reading this register.
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.20 Slice RAM access registers
Data bus (16-bit)
(address 020E16)
Slice RAM data control
register (16) (SD15 to SD0)
Slice RAM address control
register (10) (SA9 to SA0)
(address 021016)
Increment automatically
after data access
Slice RAM
Figure 2.15.21 Slice RAM access block diagram
Rev. 1.0
165
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.7 VBIRAM
Set 18-line VBI encode data. 5 addresses (8-bit ✕ 5) are prepared for 1 line, out put data in order from
LSB side in bi-phase type. Specifiy output pattern (the NRZ type) of header (clock-run in and framing
code) (each line command) at addresses 0016 to 0416.
VBIRAM composite is shown in Table 2.15.7, VBI encode data composite is shown in Figure 2.15.20.
Table 2.15.7 VBIRAM composition
VBIRAM addresses
(EA6 to EA0)
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
0016
0116
VF07
VF17
VF06
VF16
VF05
VF15
VF04
VF14
VF03
VF13
VF02
VF12
VF01
VF11
VF00
VF10
...
VF30
VF40
0516
0616
VR07
VR17
VR06
VR16
VR05
VR15
VR04
VR14
VR03
VR13
VR02
VR12
VR01
VR11
VF00
VF10
VF30
VF40
0A16
VR07
VR06
VR05
VR04
VR03
VR02
VR01
VF00
0E16
VR47
VR46
VR45
VR44
VR43
VR42
VR41
VF40
VR07
VR06
VR05
VR04
VR03
VR02
VR01
VF00
Specify output data of 7th line and 319th line.
1-bit corresponds to bi-phase 1-bit (4T).
...
VF40
VR01
VF00
...
...
VR41
VR02
...
...
VR42
VR03
...
...
VR43
VR04
...
...
VR44
VR05
...
...
VR45
VR06
...
...
VR46
VR07
...
VR47
...
...
...
...
5916
5A16
...
...
5516
Specify output data of 6th line and 318th line.
1-bit corresponds to bi-phase 1-bit (4T).
...
...
VR31
VR41
...
VR32
VR42
...
VR33
VR43
...
VR34
VR44
...
VR35
VR45
...
VR36
VR46
...
VR37
VR47
...
0816
0916
...
...
...
VF31
VF41
...
...
VF32
VF42
...
...
VF33
VF43
...
...
VF34
VF44
...
...
VF35
VF45
...
...
VF36
VF46
...
...
VF37
VF47
...
0316
0416
...
...
Remarks
Specify Clock-run in and Framing code pattern.
1-bit corresponds to 1T (Max.40 bits).
Outputs before data in each line (each line common).
5E16
VR47
VR46
VR45
VR44
VR43
VR42
VR41
VF40
Specify output data of 22th line and 334th line.
1-bit corresponds to bi-phase 1-bit (4T).
Specify output data of 23th line and 335th line.
1-bit corresponds to bi-phase 1-bit (4T).
Header part
40 bits
(NRZ)
Data part
5 bits
(bi-phase)
1 line
1
0
T
T
1
0
1
1
4T
0
4T
T : VBI encode base clock (frequency is 5 MHz, cycle is 200ns)
Figure 2.15.22 VBIRAM encode data composition
For accessing to VBIRAM data, set accessing address (EA) (shown in Table 2.15.7) to VBIRAM address
control register (address 021216). Then write data (ED) from VBIRAM data control register (address
021416). When end the data accessing, VBIRAM address control register increments address automatically. Then, next address data writing is possible.
VBIRAM access registers are shown in Figure 2.15.23 and VBIRAM access block diagram is shown in
Figure 2.15.24.
Rev. 1.0
166
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
VBIRAM address control register
b15
b8
b7
b0
Symbol
EA
Address
021216
When reset
000016
A
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Function
Setting possible value R W
00016 to 5E16
Specify accessing VBIRAM address
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : When access to VBIRAM, must be set VBIRAM at first, then use VBIRAM data
control register (021416).
VBIRAM address control register increments by accessing VBIRAM data control
register. So, it is not neccesary to setting the next VBIRAM address.
VBIRAM data control register
b15
b8
b7
b0
Symbol
ED
Address
021416
Function
When reset
000016
A
AA
AAA
Setting possible value R W
Write and read out the data of VBIRAM which is specified
by SYRAM address control register (address 021216)
0016 to FF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.23 VBIRAM access registers
Data bus (16-bit)
(address 021216)
VBIRAM data control
register (8) (ED7 to ED0)
VBIRAM address control
register (7) (EA6 to EA0)
(address 021416)
Increment automatically
after data access
VBIRAM
Figure 2.15.24 VBIRAM access block
Rev. 1.0
167
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(1) Setting of Clock-run in and Flaming code
Specify clock-run in and flamig code output pattern at VBIRAM addresses 0016 to 0416 (40 bits). Data
1-bit corresponds to 1T, every byte is output at LSB first.
When clock-run in and flaming code are less than 40 bits (40T), put "0" to the top (from the end, set "0"
to unused bit). This pattern of every line is common, outputting before data of every line. Example of
setting is shown in Figure 2.15.25.
Clock-run in
11001100110011
Flaming code
000111001100110000011100
....(a)
0011001100110011
000111001100110000011100
....(b)
00110011
00110011
00011100
11001100
00011100
....(c)
CCH
CCH
38H
33H
38H
....(d)
VBIRAM address
0016
0116
0216
0316
0416
Data
00CC16
00CC16
003816
003316
003816
....(e)
(a) Clock-run in flaming code output pattern
(1-bit corresponds to T)
(b) Add 0 ✕ 2 to the top for becoming 40 bits.
(c) Cut every 8 bits.
(d) Change upper and lower for LSB first mode.
(e) Write from VBIRAM address 0016 at 16-bit mode
Figure 2.15.25 Example of setting
(2) Data setting
Set 5 bytes data for 1 line. Setting data is output in bi-phase method. VBI data 1 bit is corresponds to
output bi-phase 1 bit (4T). Data specifying is set to RAM which is corresponds to RAM corresponding
to the line specifying composition at expansion register VBIL0 to VBIL17. When set to RAM of unspecific line, output is disable.
Rev. 1.0
168
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) EDO2 (VBI-BLNK) signal output specification
EDO2 signal (BLNK signal for VBI signal) output including former 1.8µs and outer 6.4µs of VBI encode
data. Example of output timing is shown in Figure 2.15.26.
Horizontal synchronous signal
Clock-run in +
Flaming code
Data 5 bytes
EDO1
(VBI encode data)
1.8µ s
EDO2
(VBI blank)
6.4µ s
Expansion register
(CO0 to CO5)
Figure 2.15.26 Example of output timing
Rev. 1.0
169
170
_
_
SEL_VPSH
_
_
_
RGBWH
HGSL
VBIL15
_
1216
1316
1416
1516
1616
1716
1816
1916
_
_
_
_
1D16
1E16
_
2116
_
_
2016
_
_
_
_
_
1F16
_
_
1C16
_
_
2216
VBIL16
VBIL13
_
_
_
_
_
VPS_LINE4
VBIL12
CCD
_
_
_
_
_
_
_
_
YON0
NXP
TIMBAS
SEND4
GRYB
_
DSP112
C03
DSP012
_
VSZ12
TEST2
HSZ12
PTD3
PTC3
DD12
VPS_LINE3
VBIL11
_
_
_
_
_
_
_
_
_
ALL24
EQP
_
SEND3
GRYG
_
DSP111
C02
DSP011
BLINK2
VSZ11
TEST1
HSZ11
PTD2
PTC2
DD11
VBIL9
_
PD1
VPS_VCO_ON
_
_
_
_
_
_
_
LEVEL0
YON1
SEND1
GRYON
_
DSP19
C00
DSP09
BLINK0
VSZ9
BCOL
HSZ9
PTD0
PTC0
DD9
VPS_LINE2 VPS_LINE1
VBIL10
_
PD2
_
_
_
_
_
SYNCSEP_ON0
_
_
HIDE
_
SEND2
GRYR
_
DSP110
C01
DSP010
BLINK1
VSZ10
TEST0
HSZ10
PTD1
PTC1
DD10
VPS_LINE0
VBIL8
_
_
_
_
_
_
_
_
ADON
_
INTNON
_
SEND0
SLIN4
DSP124
DSP18
DSP024
DSP08
VSZ24
VSZ8
HSZ24
HSZ8
HP8
STBY0
DD8
ENCF2
VBIL7
VPS_HP10
PDC_HP10
_
_
_
_
_
SLSLVL
_
_
PALH
PC7
_
SLIN3
DSP123
DSP17
DSP023
DSP07
VSZ23
VSZ7
HSZ23
HSZ7
HP7
VP7
DD7
_
_
MIN5
_
_
_
_
CHK_VPS5
_
_
MIN4
_
_
_
SELPEEK
_
_
_
MIN3
_
_
DIV_VPS8
DIV_PDC8
_
_
_
MIN2
_
_
DIV_VPS7
DIV_PDC7
_
_
_
MIN1
_
_
DIV_VPS6
DIV_PDC6
_
_
_
MIN0
_
_
DIV_VPS5
DIV_PDC5
_
_
_
_
MACRON
_
DIV_VPS4
DIV_PDC4
_
VPS_FLC7 VPS_FLC6 VPS_FLC5 VPS_FLC4 VPS_FLC3 VPS_FLC2 VPS_FLC1 VPS_FLC0 PDC_FLC7
VBIL17
VBIL14
HGSLS
_
_
_
_
1B16
1A16
STBY1
_
_
_
_
1116
_
_
_
_
MPAL
SELSLI
_
_
IN0
PTD7
_
_
DSP113
C04
1016
_
0E16
_
_
DSP114
C05
DSP013
_
VSZ13
_
HSZ13
PTD4
PTC4
DD13
0F16
SELFLD
0D16
PTD8
_
_
0A16
SECAM
_
0B16
DSP115
0816
0916
0C16
_
_
0716
DSP014
_
VSZ14
_
VSZ15
0416
_
HSZ14
DSP015
_
0216
0316
PTC5
PTD5
0516
HSZ15
0116
DD14
0616
PTC6
PTD6
0016
DD15
DA5 to DA0
_
DBL_HEIGHT
_
_
_
DIV_VPS3
DIV_PDC3
_
PDC_FLC6
ENCF1
VBIL6
VPS_HP9
PDC_HP9
PDC_VCO_ON
IN1
_
_
_
SLI_VP2
_
LBLACK
_
PC6
PTC8
SLIN2
DSP122
DSP16
DSP022
DSP06
VSZ22
VSZ6
HSZ22
HSZ6
HP6
VP6
DD6
_
_
MAX5
_
_
DIV_VPS2
DIV_PDC2
CHK_PDC5
PDC_FLC5
VBIF2
VBIL5
VPS_HP8
PDC_HP8
_
_
_
SEKI5
_
SLI_VP1
SEL_PDCH
LINEB
_
PC5
PTC7
SLIN1
DSP121
DSP15
DSP021
DSP05
VSZ21
VSZ5
HSZ21
HSZ5
HP5
VP5
DD5
_
_
MAX4
FLD
_
DIV_VPS1
DIV_PDC1
_
PDC_FLC4
VBIF1
VBIL4
VPS_HP7
PDC_HP7
_
_
_
SEKI4
_
SLI_VP0
_
LINEG
_
PC4
SST4
SLIN0
DSP120
DSP14
DSP020
DSP04
VSZ20
VSZ4
HSZ20
HSZ4
HP4
VP4
DD4
_
_
MAX3
_
_
DIV_VPS0
DIV_PDC0
_
PDC_FLC3
VPSF2
VBIL3
VPS_HP6
PDC_HP6
XTAL_VCO
_
_
SEKI3
_
_
_
LINER
DSPONV
PC3
SST3
SBIT3
DSP119
DSP13
DSP019
DSP03
VSZ19
VSZ3
HSZ19
HSZ3
HP3
VP3
DD3
_
PDC_FLC1
PDCF2
VBIL1
VPS_HP4
PDC_HP4
_
_
_
SEKI1
_
VPS_SUB
_
PHASE1
_
PC1
SST1
SBIT1
DSP117
DSP11
DSP017
DSP01
VSZ17
VSZ1
HSZ17
HSZ1
HP1
VP1
DD1
Vertical display position, Port setting
Horizontal size setting
Display control setting
Display frequency setting
Scroll, port setting
Gray, scroll setting
Display mode setting
Display mode setting
Display mode setting
Display mode setting
Vertical size and blinking setting
Vertical size setting
Horizontal size setting
Slicer control setting
—
Slice setting
VBI encode setting
VPS slice position setting
PDC slice position setting
Oscillation ON/OFF setting
Display setting
Slice setting
—
Sync separation, slice setting
_
—
PDC_FLC0 PDC, VPS flaming setting
PDCF1
VBIL0
VPS_HP3
PDC_HP3
CK_VCO
_
_
SEKI0
_
_
_
Remarks
Horizontal display position, Port setting
PHASE0 Color setting
EX
PC0
SST0
SBIT0
DSP116
DSP10
DSP016
DSP00
VSZ16
VSZ0
HSZ16
HSZ0
HP0
VP0
DD0
_
_
MAX2
_
_
_
_
MAX1
_
_
_
_
MAX0
_
_
Macro, field flag
Slice setting
—
—
—
DIV_VPSS2 DIV_VPSS1 DIV_VPSS0 VPS frequency setting
DIV_PDCS2 DIV_PDCS1 DIV_PDCS0 PDC frequency setting
_
PDC_FLC2
VPSF1
VBIL2
VPS_HP5
PDC_HP5
_
_
_
SEKI2
_
_
_
PHASE2
DSPON
PC2
SST2
SBIT2
DSP118
DSP12
DSP018
DSP02
VSZ18
VSZ2
HSZ18
HSZ2
HP2
VP2
DD2
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.8 Expansion Register
Control function of OSD function, Data slicer function and VBI encoder function. Expansion register
composition is shown in Table 2.15.8.
Table 2.15.8 Expansion register composition
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
For accessing to expantion register data, set accessing address (DA5 to DA0) (shown in Table 2.15.8)
to expantion register address control register (address 021616). Then write data (DD15 to DD0) by
expantion register data control register (address 021816). When end the data accessing, expantion
register address control register increments address automatically. Then, next address data writing is
possible.
Expantion register access registers are shown in Figure 2.15.27, expansion register access block
diagram is shown in Figure 2.15.28, and expansion register bit compositions are shown in p172 to p197.
Expansion register address control register
b15
b8
b7
b5
b0
Symbol
DA
Address
021616
Function
When reset
000016
Setting possible value
Specify accessing expansion register address
RW
0016 to 2216
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Expansion register address auto increments set
0:vaid / 1:invaid (Note2)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note1 : When access to expansion register, must be set expansion register address
at first, then use expansion register data control register (021816).
Note2 : When bit 8 =“0” setting,expansion register data control register increments by
accessing expansion register data control register,so it is not neccesary to
setting the next expansion register address.When bit 8 =“1” setting,the address
is fixed.
Expansion register data control register
b15
b8
b7
b0
Symbol
DD
Address
021816
Function
When reset
000016
Setting possible value
Write and read out the data of expansion register which is
specified by expansion register address control register
(address 021616)
RW
000016 to FFFF16
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.15.27 Expansion register access registers composition
Data bus (16-bit)
(address 021616) (DA8)
Expansion register address
control register (5) (DA5 to DA0)
Expansion register data control
register (16) (DD15 to DD0)
(address 021816)
Increment automatically
after data access
Expansion register
Figure 2.15.28 Expansion register access block diagram
Rev. 1.0
171
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Expansion register construction
(1) Address 00 16 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
VP0
Vertical display start position
selection bit
Function
R W
If VS is the vertical display start position,
7
VS= H✕∑2nVPn
n=0
VP1
H: Cycle with the horizontal synchronizing
pulse
VP2
HOR
VP3
VS
VERT
VP4
VP5
VP6
HS
character
displaying
area
VP7 to VP0 ≤ (000011102)
are disable
VP7
STBY0
Stand-by mode selection bit
PTC0
Port P110 output selection bit
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
Port P111 output selection bit
Port P112 output selection bit
Port P113 output selection bit
Port P114 output selection bit
Port P115 output selection bit
Port P116 output selection bit
0
Normal mode
1
Stand-by mode
0
P0 output
1
EDO2 output
0
P1 output
1
EDO1 output
0
P2 output
1
CSYN output
0
P3 output
1
BLNK output
0
P4 output
1
B output
0
P5 output
1
G output
0
P6 output
1
R output
Rev. 1.0
172
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(2) Address 0116 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
Function
HP0
Horizontal display start position
selection bit
If HS is the vertical display start position,
R W
8
HS= T1✕∑2nHPn+9
n=0
HP1
T1 : Cycle with the display clock
HP2
HOR
HP3
VS
VERT
HP4
HP5
HS
character
displaying
area
HP6
HP8 to HP0 ≤ (0000100112)
are disable
HP7
HP8
0
PTD0
Port P110 data selection bit
1
0
PTD1
Port P111 data selection bit
1
0
PTD2
Port P112 data selection bit
1
0
PTD3
Port P113 data selection bit
1
0
PTD4
Port P114 data selection bit
1
0
PTD5
Port P115 data selection bit
1
0
PTD6
Port P116 data selection bit
1
When port output : fixed to L , when EDO2
output : specified negative polarity.
When port output : fixed to H , when EDO2
output : specified positive polarity.
When port output : fixed to L , when EDO1
output : specified negative polarity.
When port output : fixed to H , when EDO1
output : specified positive polarity.
When port output : fixed to L , when CSYN
output : specified negative polarity.
When port output : fixed to H , when CSYN
output : specified positive polarity.
When port output : fixed to L , when BLNK
output : specified negative polarity.
When port output : fixed to H , when BLNK
output : specified positive polarity.
When port output : fixed to L , when B output :
specified negative polarity.
When port output : fixed to H , when B output :
specified positive polarity.
When port output : fixed to L , when G output :
specified negative polarity.
When port output : fixed to H , when G output :
specified positive polarity.
When port output : fixed to L , when R output :
specified negative polarity.
When port output : fixed to H , when R output :
specified positive polarity.
Rev. 1.0
173
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(3) Address 02 16 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
HSZ0
The 0th line horizontal
character selection bit
HSZ1
The first line horizontal
character selection bit
HSZ2
The second line horizontal
character selection bit
HSZ3
The third line horizontal
character selection bit
Horizontal direction character size
of the line n is set by HSZn
(n = 0 to 24).
Set at one time or two times in the
each every line.
HSZn
HSZ4
The 4th line horizontal
character selection bit
HSZ5
The 5th line horizontal
character selection bit
HSZ6
The 6th line horizontal
character selection bit
HSZ7
The 7th line horizontal
character selection bit
HSZ8
The 8th line horizontal
character selection bit
HSZ9
The 9th line horizontal
character selection bit
HSZ10
The 10th line horizontal
character selection bit
HSZ11
The 11th line horizontal
character selection bit
HSZ12
The 12th line horizontal
character selection bit
HSZ13
The 13th line horizontal
character selection bit
HSZ14
The 14th line horizontal
character selection bit
HSZ15
The 15th line horizontal
character selection bit
R W
Horizontal direction
character size
0
1T/dot (one time)
1
2T/dot (two times)
T : Display clock
Rev. 1.0
174
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(4) Address 0316 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0
Bit symbol
Function
Bit name
HSZ16
The 16th line horizontal
character selection bit
HSZ17
The 17th line horizontal
character selection bit
HSZ18
The 18th line horizontal
character selection bit
HSZ19
The 19th line horizontal
character selection bit
HSZ20
The 20th line horizontal
character selection bit
HSZ21
The 21th line horizontal
character selection bit
HSZ22
The 22th line horizontal
character selection bit
HSZ23
The 23th line horizontal
character selection bit
HSZ24
The 24th line horizontal
character selection bit
BCOL
All blanking selection bit
R W
Horizontal direction character size
of the line n is set by HSZn
(n = 0 to 24).
Set at one time or two times in the
each every line.
HSZn
Horizontal direction
character size
0
1T/dot (one time)
1
2T/dot (two times)
T : Display clock
0
Blanking of DSP1n and DSP0n
1
All raster blanking
TEST0
TEST1
Test bit
Must always be set to "0".
TEST2
Reserved bit
Must always be set to "0".
✕
Rev. 1.0
175
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(5) Address 04 16 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
Function
VSZ0
The 0th line vertical character
size selection bit
VSZ1
The first line vertical character
size selection bit
Vertical direction character size of
the line n is set by VSZn (n = 0 to 24)
Set at one time or two times each
every line.
VSZ2
The second line vertical
character size selection bit
VSZ3
The third line vertical
character size selection bit
VSZ4
The 4th line vertical character
size selection bit
VSZ5
The 5th line vertical character
size selection bit
VSZ6
The 6th line vertical character
size selection bit
VSZ7
The 7th line vertical character
size selection bit
VSZ8
The 8th line vertical character
size selection bit
VSZ9
The 9th line vertical character
size selection bit
VSZ10
The 10th line vertical
character size selection bit
VSZ11
The 11th line vertical
character size selection bit
VSZ12
The 12th line vertical
character size selection bit
VSZ13
The 13th line vertical
character size selection bit
VSZ14
The 14th line vertical
character size selection bit
VSZ15
The 15th line vertical
character size selection bit
VSZn
Vertical direction
character size
0
1H/dot (one time)
1
2H/dot (two times)
R W
H : Horizontal synchronous pulse
Rev. 1.0
176
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(6) Address 0516 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0
Bit symbol
Function
Bit name
VSZ16
The 16th line vertical
character size selection bit
VSZ17
The 17th line vertical
character size selection bit
VSZ18
The 18th line vertical
character size selection bit
VSZ19
The 19th line vertical
character size selection bit
VSZ20
The 20th line vertical
character size selection bit
VSZ21
The 21th line vertical
character size selection bit
VSZ22
The 22th line vertical
character size selection bit
VSZ23
The 23th line vertical
character size selection bit
VSZ24
The 24th line vertical
character size selection bit
BLINK0
Blinking duty selection bit
BLINK1
R W
Vertical direction character size of
the line n is set by VSZn (n = 0 to 24)
Set at one time or two times in the
each every line.
VSZn
Vertical direction
character size
0
1H/dot (one time)
1
2H/dot (two times)
H : Horizontal synchronous pulse
BLINK1 BLINK0
0
0
1
0
1
1
0
1
DUTY
Blinking off
25%
50%
75%
0 Cycle approximatery 1 second.
BLINK2
Reserved bit
Blinking cycle selection bit
1 Cycle approximatery 0.5 second.
Must always be set to "0".
✕
Rev. 1.0
177
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(7) Address 06 16 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
DSP00
The 0th line display mode
selection bit
DSP01
DSP02
DSP03
DSP04
DSP05
Function
R W
Set the display mode of the line n
(blanking mode) by combination of
DSP0n (addresses 0616 and 0716)
The first line display mode
and DSP1n
selection bit
(addresses 0816 and 0916)
The second line display mode (n = 0 to 24)
3 kinds of following setting are
selection bit
possible for the each every line.
The third line display mode
Display mode
DSP1n DSP0n
selection bit
Character
0
0
The 4th line display mode
1
Disable
0
selection bit
0
1
Matrix-outline
1
1
Halftone
The 5th line display mode
selection bit
DSP06
The 6th line display mode
selection bit
DSP07
The 7th line display mode
selection bit
DSP08
The 8th line display mode
selection bit
DSP09
The 9th line display mode
selection bit
DSP010
The 10th line display mode
selection bit
DSP011
The 11th line display mode
selection bit
DSP012
The 12th line display mode
selection bit
DSP013
The 13th line display mode
selection bit
DSP014
The 14th line display mode
selection bit
DSP015
The 15th line display mode
selection bit
Rev. 1.0
178
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(8) Address 07 16 ( = DA5 to 0)
DD15
DD8DD7
DD0
0
Bit symbol
Function
Bit name
DSP016
The 16th line display mode
selection bit
DSP017
The 17th line display mode
selection bit
DSP018
The 18th line display mode
selection bit
DSP019
The 19th line display mode
selection bit
DSP020
The 20th line display mode
selection bit
DSP021
The 21th line display mode
selection bit
DSP022
The 22th line display mode
selection bit
DSP023
The 23th line display mode
selection bit
DSP024
The24th line display mode
selection bit
CO0
VBI encode horizontal start
position selection bit
R W
Set the display mode of the line n
(blanking mode) by combination of
DSP0n (addresses 0616 and 0716)
and DSP1n
(addresses 0816 and 0916)
( n = 0 to 24)
3 kinds of following setting are
possible for the each every line.
DSP1n DSP0n
0
0
1
0
0
1
1
1
Display mode
Character
Disable
Matrix-outline
Halftone
VBI encode horizontal
start position
CO1
CO2
CO3
CO0 to CO5
CO4
(Each line are set to common)
CO5
Reserved bit
Must always be set to "0".
✕
Rev. 1.0
179
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(9) Address 08 16 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
DSP10
The 10th line display mode
selection bit
DSP11
The 11th line display mode
selection bit
DSP12
The 12th line display mode
selection bit
DSP13
The 13th line display mode
selection bit
DSP14
The 14th line display mode
selection bit
DSP15
The 15th line display mode
selection bit
DSP16
The 16th line display mode
selection bit
DSP17
The 17th line display mode
selection bit
DSP18
The 18th line display mode
selection bit
DSP19
The 19th line display mode
selection bit
DSP110
The 20th line display mode
selection bit
DSP111
The 21th line display mode
selection bit
DSP112
The 22th line display mode
selection bit
DSP113
The 23th line display mode
selection bit
DSP114
The 24th line display mode
selection bit
DSP115
The 25th line display mode
selection bit
Function
R W
Set the display mode of the line n
(blanking mode) by combination of
DSP0n (addresses 0616 and 0716)
and DSP1n
(addresses 0816 and 0916)
( n = 0 to 24)
3 kinds of following setting are
possible for the each every line.
DSP1n DSP0n
0
0
1
0
0
1
1
1
Display mode
Character
Disable
Matrix-outline
Halftone
Rev. 1.0
180
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(10) Address 0916 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0
Bit symbol
Bit name
DSP116
The 16th line display mode
selection bit
DSP117
The 17th line display mode
selection bit
DSP118
The 18th line display mode
selection bit
DSP119
The 19th line display mode
selection bit
DSP120
The 20th line display mode
selection bit
DSP121
The 21th line display mode
selection bit
DSP122
The 22th line display mode
selection bit
DSP123
The 23th line display mode
selection bit
DSP124
The24th line display mode
selection bit
Reserved bit
Function
R W
Set the display mode of the line n
(blanking mode) by combination of
DSP0n (addresses 0616 and 0716)
and DSP1n
(addresses 0816 and 0916)
( n = 0 to 24)
3 kinds of following setting are
possible for the each every line.
DSP1n DSP0n
0
0
1
0
0
1
1
1
Display mode
Character
Disable
Matrix-outline
Halftone
Must always be set to "0".
✕
Rev. 1.0
181
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(11) Address 0A16 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0
Bit symbol
SBIT0
Function
Bit name
Scroll display start dot
selection bit
SBIT1
R W
If SA is display start dot of scroll
block,
3
SA= ∑2nSBITn
n=0
SBIT2
SBIT3 to SBIT0 ≥ (10102)
is disable
SBIT3
SLIN0
Scroll display start dot
selection bit
SLIN1
If SB is display start dot of scroll
block,
4
SB= ∑2nSBITn
n=0
SLIN2
SLIN4 to SLIN0 ≥ (110012)
is disable.
Set the value which is satisfies
with shown below :
SST4 to SST0 ≤ SLIN4 to SLIN0
< SEND4 to SEND0
SLIN3
SLIN4
Gray display selection bit
GRYON
GRYR
0 Normal display.
1 Gray display setting one color of
eight colors. (Note 1)
Gray display color
selection bit
GRYG
GRYB
0
0
0
0
1
1
1
1
GRYG GRYR
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Color
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
GRYB
Gray color is set by this register
Valid only ot GRYON = "1"
Reserved bit
Must always be set to "0".
✕
Note 1. Refer to register RGBWH (Address 1616) about RGB output.
Rev. 1.0
182
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(12) Address 0B16 ( = DA5 to 0)
DD15
0
DD8DD7
DD0
0
Bit symbol
Function
Bit name
Scroll block start line
selection bit
SST0
R W
If SC is start line of scroll block,
SST1
4
SC= ∑2nSSTn
n=0
SST2
SST3
SST4 to SST0 ≥ (110002)
is disable
SST4
PTC7
PTC8
Port P7 output selection bit
Port P8 output selection bit
0
P7 output
1
GRAY output
0
P8 output
1
SLICEON output
Must always be set to "0".
Reserved bit
SEND0
Scroll block last line
selection bit
✕
If SD is the fixation start line of the
below the scroll block
(last line of the scroll block + 1)
SEND1
4
SD= ∑2nSENDn
n=0
SEND2
Set the value which will be
(SEND4 to SEND0) ≥ (SST4 to SST0) + 2
SEND3
When scroll on,
SEND4 to SEND0 ≤ (000012) and
SEND4 to SEND0 ≥ (110102) are disable.
SEND4
When scroll off,
SEND4 to SEND0 = (000002) is available.
0
PTD7
Port P7 data selection bit
1
0
PTD8
Port P8 data selection bit
1
Reserved bit
When port output : fixed to "H" when GRAY
output : specified negative polarity
When port output : fixed to "L" when GRAY
output : specified positive polarity
When port output : fixed to "H" when
SLICEON output : specified negative polarity
When port output : fixed to "L" when
SLICEON output : specified positive polarity
Must always be set to "0".
✕
Rev. 1.0
183
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(13) Address 0C16 ( = DA5 to 0)
DD8DD7
DD15
0
0 0
DD0
0
Bit symbol
PC0
Function
Bit name
Display frequency
selection bit
R W
Control display frequency fT,
7
PC1
fT = fH ✕ {∑2nPCn+512}
PC2
fH : Horizontal synchronous signal
frequency
n=0
PC3
PC7 to PC0 ≤ (011111112)
is disable.
PC4
PC5
Set PC7 to PC0 = (111101012),
normally.
PC6
PC7
Must always be set to "0".
Reserved bit
YON1
0
Color burst at internal
synchronous selection bit (Note) 1
TIMBAS
Time base selection bit
IN0
Internal synchronous
selection bit
Color burst OFF
0
Time base ON
1
Time base OFF
0
External synchronous setting
1
Internal synchronous setting
Must always be set to "0".
Reserved bit
Combination selection bit
from SECAMIN pin
SECAM
Color burst ON
Must always be set to "0".
Reserved bit
✕
0
Do not superimpose the carrier
1
Superimpose the carrier from
✕
✕
from SECAMIN pin.
SECAMIN pin.
Note1. When moto-tone display (YON0(address 0E16)= "1") setting, must be set to "1".
Rev. 1.0
184
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(14) Address 0D16 ( = DA5 to 0)
DD15
0
DD8DD7
0 0 0
DD0
0
Bit symbol
EX
Function
Bit name
Must always be set to "0".
Reserved bit
DSPON
DSPONV
R W
External/internal synchronous 0 External synchronization
selection bit
1 Internal synchronization
Digital display selection bit
✕
0 Digital output display OFF.
1 Digital outoput display ON.
Analog display selection bit
0 Composite video signal output display OFF.
1 Composite video signal output display ON.
Must always be set to "0".
Reserved bit
PALH
PALH
Number of scanning line
selection bit
0
0
1
1
INTNON
LEVEL0
HIDE
EQP
✕
INT/NON Number of scanning line
625H
0
626H
1
624H
0
628H
1
Video signal generation
selection bit
0 Composite video signal generation circuit OFF.
SYRAM expantion display
selection bit
0 SYRAM writing over
Equivalent pulse selection bit
0 Do not include equivalent pulse.
1 Composite video signal generation circuit ON.
1 SYRAM writing over or character erasing
1 Includes equivalent pulse.
NXP
Broadcast method
selection bit
MPAL
Field at non interlace
selection bit
MPAL
0
0
1
1
0
1
0
1
Broadcasting method
NTSC
M-PAL
PAL
Disable
Must always be set to "0".
Reserved bit
SELFLD
N/P
0
The secound field.
1
The first field.
✕
Rev. 1.0
185
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(15) Address 0E16 ( = DA5 to 0)
DD15
0 0 0
DD8DD7
DD0
0 0 0 0
Bit symbol
Function
Bit name
PHASE2 PHASE1 PHASE0
PHASE0
0
0
0
0
1
1
1
1
Raster color selection bit
PHASE1
LINEB LINEG LINER
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SYRAM color selection bit
LINEG
LINEB
LBLACK
0
1
0
1
0
1
0
1
Raster color setting when Register
GRYON = 0
Refer to address 0A16 when color
setting at GRYON = 1
PHASE2
LINER
0
0
1
1
0
0
1
1
R W
Color
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
Video signal black level
selection bit
Color
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
SYRAM color setting when Register
GRYON = 0.
Refer to address 0A16 when color
setting at GRYON = 1.
0 1.6V
1 1.8V
Must always be set to "0".
Reserved bit
✕
0 OSD horizontal display range (40 characters)
ALL24
Horizontal direction matrix
outline range selection bit
YON0
0 Color display
Internal synchronous
moto-tone display selection bit 1 Mono-ton display (Note1 )
1 All range of horizontal display period.
Must always be set to "0".
Reserved bit
✕
Note1. When moto-tone display(YON0="1") setting, must be set YON1(address OC16)="1".
(16) Address 0F16 ( = DA5 to 0)
DD15
DD8DD7
0 0 0 0 0 0 0
0 0
DD0
0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
SEL_PDCH
Must always be set to "0".
PDC clock selection bit
Reserved bit
ADON
Reserved bit
0
Generats PDC clock in based on external fH.
1
Generats PDC clock in based on FSCIN pin
input signal.
Must always be set to "0".
Data slicer control bit
R W
✕
✕
0 Data slicer OFF
1 Data slicer ON
Must always be set to "0".
✕
Note1. When ADLAT0="1" setting, must be set ADLAT1(address 1416)="1".
Rev. 1.0
186
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(17) Address1016 ( = DA5 to 0)
DD15
0 0 0 0
DD8DD7
0 0
DD0
0 1
0
Bit symbol
Function
Bit name
Must always be set to "0".
Reserved bit
VPS_SUB
Flaming code check selection bit
for VPS data.
R W
✕
0 Later 8bits of flaming code 16bits
Former 4bits and later 4bits of flaming
1 code 16bits (Select 8bits which is set in
VPS_FLC0 to 7)
Reserved bit
Must always be set to "1".
✕
Reserved bit
Must always be set to "0".
✕
SLI_VP0
SLI_VP1
Slice start line selection bit
(Field 1 and 2 are common)
Stores data for 18 lines from
the 6th line,normally.
(SLI_VP2 to SLI_VPO = "316"
fixed)
If the slice start line is SLI_VS,
2
<Field 1> SLI_VS= ∑2nSLI_VPn+3
n=0
2
<Field 2> SLI_VS= ∑2nSLI_VPn+315
n=0
Stores data for 18 lines from line which
SLI_VP2
is set by this register to slice RAM.
SLSLVL
Slice level control bit
0
Auto level for data slice
1
Fix level for data slice
Must always be set to "0".
Reserved bit
SYNCSEP_ON0
Synchronous separation
control bit
0
Sync-sep circuit OFF
1
Sync-sep circuit ON
Must always be set to "0".
Reserved bit
SELSLI
Slice signal input pin
selection bit
0
CVIN1 pin
1
CVIN2 pin
✕
✕
(18) Address 1116( = DA5 to 0)
DD15
DD8DD7
DD0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Bit name
Function
R W
Reserved bit
Must always be set to "0".
✕
Reserved bit
Must always be set to "1".
✕
Reserved bit
Must always be set to "0".
✕
Rev. 1.0
187
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(19) Address 1216 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0
Bit symbol
Function
Bit name
Data slicer control bit 1
SEKI0
SEKI0
N
0
0
1
1
0
1
0
1
5
4
3
2
N times of the digital value after AD is done.
SEKI1
Data slicer control bit 2
SEKI2
SEKI3
SEKI2
N
0
0
1
1
0
1
0
1
4
3
1
SEKI5
SEKI4
N
0
0
1
1
0
1
0
1
4
3
1
Not differentiate
It is differentiated for digital value after the
SEKI0, 1 operation at digital value in the
before N/8 period(clock run-in period).
SEKI3
Data slicer control bit 3
SEKI4
Not differentiate
It is differentiated for digital value after the
SEKI3, 2 operation at digital value in the
after N/8 period(clock run-in period).
SEKI5
Must always be set to "0"
Reserved bit
0
SEL_VPSH
R W
SEKI1
VPS clock selection bit
✕
Generats VPS clock in based on external fH.
Generats VPS clock in based on FSCIN pin
1 input signal.
(20) Address 1316 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Reserved bit
Bit name
Function
Must always be set to "0".
R W
✕
Rev. 1.0
188
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(21) Address 1416 ( = DA5 to 0)
DD8DD7
DD15
0 0 0 0 0 0 0 0 0
DD0
0 0 0 0 0 0
Bit symbol
Reserved bit
IN1
Function
Bit name
Must always be set to "0".
Internal synchronous
selection bit
Reserved bit
R W
✕
0 External synchronous setting
1 Internal synchronous setting
Must always be set to "0".
✕
(22) Address 1516 ( = DA5 to 0)
DD8DD7
DD15
0 0
0 0 0
0 0
DD0
0 0
0 0
Bit symbol
CK_VCO
Function
Bit name
Display clock oscillation
selection bit
0
Display clock OFF
1
Display clock oscillation
Must always be set to "0".
Reserved bit
XTAL_VCO
Synchronous clock oscillation 0
selection bit
1
PDC_VCO_ON
PDC clock oscillation
selection bit
VPS_VCO_ON
PDC clock OFF
1
PDC clock oscillation
Must always be set to "0".
VPS and VBI clock oscillation 0
selection bit
1
Reserved bit
Stand-by mode selection bit
✕
✕
VPS and VBI clock OFF
VPS and VBI clock oscillation
Must always be set to "0".
Reserved bit
STBY1
Synchronizing clock oscillation
0
Reserved bit
✕
Synchronizing clock OFF
Must always be set to "0".
Reserved bit
R W
0
Normal mode
1
Stand-by mode.
Must always be set to "0".
✕
✕
Rev. 1.0
189
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(23) Address 1616 ( = DA5 to 0)
DD15
0 0 0
DD8DD7
DD0
0
Bit symbol
PDC_HP3
Bit name
PDC slice check start
position selection bit
Function
R W
If the PDC slice check start position
is PDC_HS,
10
PDC_HS= T3 ✕ ∑2(n-3)PDC_HPn
PDC_HP4
n=3
T3 : PDC clock run-in cycle ÷2
PDC_HP5
PDC_HP6
PDC_HP7
PDC_HP8
Set to flaming code check start
position
PDC_HP9
Set by the 144ns (1bit)
PDC_HP10
Reserved bit
PD1
Must always be set to "0".
PDC, VPS, VBI clock phase
control bit
✕
Adjust clock phase for Data slicer.
Normaly, PD2 to PD1=(10)2 fixed.
PD2
✕ ✕
Nothing is assigned.
Reserved bit
RGBWH
Must always be set to "0".
RGB out put (gray display)
selection bit
✕
0 Normal
1 RGB output of gray display color is white.
Rev. 1.0
190
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(24) Address 1716 ( = DA5 to 0)
DD8DD7
DD15
1
0
0 0
DD0
0
Bit symbol
Bit name
VPS_HP3
VPS and VBI slice check
start position selection bit
Function
R W
If VPS and VBI slice check start
position is VPS_HS,
10
VPS_HS= T2 ✕ ∑2(n-3)VPS_HPn
VPS_HP4
n=3
T2 : VPS or VBI clock run-in cycle ÷2
VPS_HP5
VPS_HP6
VPS_HP7
VPS_HP8
Set to flaming code check start
position
VPS_HP9
Set by the 200ns (1bit)....VPS
Set by the 800ns (1bit)....VBI
VPS_HP10
Reserved bit
Must always be set to "0".
✕ ✕
Nothing is assigned.
Reserved bit
CCD
Must always be set to "0".
CCD slicer selection bit
0
PDC, VPS, VBI
1
CCD
Reserved bit
Must always be set to "0".
HGSLS
Data slicer control bit
HGSL
Data slicer control bit
✕
0
PDC, VPS
1
VBI
✕
✕
Must always be set to "1".
Rev. 1.0
191
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(25) Address 1816 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
VBIL0
6th line or 318th line VBI
encode selection bit
VBIL1
7th line or 319th line VBI
encode selection bit
VBIL2
8th line or 320th line VBI
encode selection bit
Set the line which encodes by VBIn
( n = 0 to 17).
It can be setin the each every line
VBILn
Encode of N line
0
Do not set
1
VBIL3
9th line or 321th line VBI
encode selection bit
VBIL4
10th line or 322th line VBI
encode selection bit
VBIL5
11th line or 323th line VBI
encode selection bit
VBIL6
12th line or 324th line VBI
encode selection bit
VBIL7
13th line or 325th line VBI
encode selection bit
VBIL8
14th line or 326th line VBI
encode selection bit
VBIL9
15th line or 327th line VBI
encode selection bit
VBIL10
16th line or 328th line VBI
encode selection bit
VBIL11
17th line or 329th line VBI
encode selection bit
VBIL12
18th line or 330th line VBI
encode selection bit
VBIL13
19th line or 331th line VBI
encode selection bit
VBIL14
20th line or 332th line VBI
encode selection bit
VBIL15
21th line or 333th line VBI
encode selection bit
R W
Set
N : (n+6) or (n+318)
Rev. 1.0
192
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(26) Address 1916 ( = DA5 to 0)
DD15
DD8DD7
DD0
0
Function
Bit symbol
Bit name
PDCF1
PDC data slice selection bit
(field1)
0 Do not slice field 1 PDC data
PDCF2
PDC data sline selection bit
(field2)
0 Do not slice field 2 PDC data
VPSF1
VPS data slice selection bit
(field1)
0 Do not slice field 1 VPS data
VPSF2
VPS data slice selection bit
(field2)
0 Do not slice field 2 VPS data
VBIF1
VBI data slice selection bit
(field1)
0 Do not slice field 1 VBI data
VBIF2
VBI data slice selection bit
(field2)
0 Do not slice field 2 VBI data
ENCF1
VBI data encode selection bit
(field1)
0 Do not slice field 1 VBI data
ENCF2
VBI data encode selection bit
(field2)
0 Do not slice field 2 VBI data
VPSF_LINE0
VPS data slice line
selection bit
R W
1 Slice field 1 PDC data
1 Slice field 2 PDC data
1 Slice field 1 VPS data
1 Slice field 2 VPS data
1 Slice field 1 VBI data
1 Slice field 2 VBI data
1 Slice field 1 VBI data
1 Slice field 2 VBI data
When VPS data slice line is
VPS_LINES,
4
VPS_LINES = ∑ 2n VPS_LINEn + 7
VPSF_LINE1
n=0
Fix to 16th line normally.
VPSF_LINE2
(VPS_LINE4 to VPS LINE0 = "010012"
fixed)
Setting value from 000002 to 100002
(7th line to 23 line)
VPSF_LINE3
VPSF_LINE4
VBIL16
22th line or 334th line VBI
encode selection bit
VBIL17
23th line or 335th line VBI
encode selection bit
Reserved bit
Set encode line by VBILn (n = 0 to 17)
Refer to address 1816
Must always be set to "0".
✕
Rev. 1.0
193
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(27) Addrres 1A 16 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
PDC_FLC0
Flaming code selection bit
at PDC slice
Function
[PDC]
R W
Flaming code (8 bits)
Clock run - in
PDC_FLC1
Data
Setting
PDC_FLC2
PDC_FLC0 to PDC_FLC7
PDC_FLC3
PDC_FLC4
PDC_FLC0 to 7 = 11100100
Flaming code selection bit
at VBI slice
[VBI]
Clock run - in
Flaming code (24 bits)
PDC_FLC5
Data
PDC_FLC6
PDC_FLC4 to 7
PDC_FLC7
VPS_FLC0
Flaming code selection bit
at VPS and VBI slice
VPS_FLC0 to 7
Set last 8bits
[VPS]
When VPS_SUB (address1216) = 0
Flaming code (16 bits)
VPS_FLC1
Crock run - in
Data
VPS_FLC2
VPS_FLC3
VPS_FLC0 to VPS_FLC7
Set last 8bits
VPS_FLC0 to 7 = 10011001
VPS_FLC4
VPS_SUB = 1
Flaming code (16 bits)
VPS_FLC5
Data
VPS_FLC6
VPS_FLC7
VPS_FLC0 to 3 VPS_FLC4 to 7
(Set first 4bits) (Set last 4 bits) = 8bits
VPS_FLC0 to 7 = 10001001
Rev. 1.0
194
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(28) Address 1B16 ( = DA5 to 0)
DD15
0 0
DD8DD7
0 0 0 0 0 0 0
DD0
0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
CHK_PDC5
Must always be set to "0".
Flaming code check
0 PDC_FLC5 valid
selection bit
1 PDC_FLC5 invalid (Note1)
Reserved bit
CHK_VPS5
Must always be set to "0".
Flaming code check
0 VPS_FLC5 valid
selection bit
1 VPS_FLC5 invalid (Note1)
Must always be set to "0".
Reserved bit
R W
✕
✕
✕
Note1. At VBI slice, must be set to "1".
(29) Address 1C16 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0
Bit symbol
DIV_PDCS0
Function
Bit name
PLL control bit for PDC
R W
Contorl the slice clock frequency
fPDC for PDC.
8
fPDC =fH ✕ ( ∑ 2nDIV_VPSn
n=0
+ ∑ 2m-3DIV_PDCSm)
DIV_PDCS1
m=0
DIV_PDCS2
DIV_PDC0
PLL divided value selection
bit for PDC
fH : Horizontal synchronized signal
frequency
When SEL_PDCH (address 0F16) = “0”,
DIV_PDC8 to DIV_PDC0
= (110111011)2
DIV_PDC2 to DIV_PDC0
= (110)2
DIV_PDC1
DIV_PDC2
DIV_PDC3
When SEL_PDCH = “1”
DIV_PDC8 to DIV_PDC0
= (000010010)2
DIV_PDC2 to DIV_PDCS0
= (101)2
DIV_PDC4
DIV_PDC5
DIV_PDC6
DIV_PDC7
DIV_PDC8
SELPEEK
Peek point detect selection bit
0 Detect from A/D data
1 Detect from data of digital calculation
after normally "1"setting.
Reserved bit
Must always be set to "0".
✕
Rev. 1.1
195
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(30) Address 1D16 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0
Bit symbol
Function
Bit name
PLL control bit for VPS
DIV_VPSS0
and VBI
Control the slice clock frequency
fVPS for VPS and VBI.
DIV_VPSS1
fPDC =fH ✕ ( ∑ 2nDIV_VPSn
R W
8
n=0
2
+ ∑ 2m-3DIV_VPSSm)
m=0
DIV_VPSS2
DIV_VPS0
PLL divided value selection
bit for VPS and VBI
fH : Horizontal synchronized signal
frequency
When SEL_VPSH (address 1216) = “0”,
DIV_VPS8 to DIV_VPS0
= (100111111)2
DIV_VPSS2 to DIV_VPSS0
= (110)2
DIV_VPS1
DIV_VPS2
DIV_VPS3
When SEL_VPSH = “1”,
DIV_VPS8 to DIV_VPS0
= (000001111)2
DIV_VPSS2 to DIV_VPSS0
= (110)2
DIV_VPS4
DIV_VPS5
DIV_VPS6
DIV_VPS7
DIV_VPS8
Reserved bit
Must always be set to "0".
✕
(31) Address 1E16 ( = DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
R W
Writing is disable.
Reading exclusive bit.
✕ ✕
Bit name
Reserved bit
(32) Address 1F16 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0
Bit symbol
Reserved bit
FLD
Fild flag
Reserved bit
MACRON
Function
R W
Writing is disable.
Reading exclusive bit.
✕ ✕
Bit name
Macro vision flag
Reserved bit
0 The secound field.
✕
1 The first field.
Writing is disable.
Reading exclusive bit.
0 No macro vision.
1 Macro vision
Writing is disable.
Reading exclusive bit.
✕ ✕
✕
✕ ✕
Rev. 1.1
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(33) Address 2016 ( = DA5 to 0)
DD15
0 0
DD8DD7
DD0
0 0
Bit symbol
MAX0
Function
Bit name
Slice data sampling maximum
value selection bit
R W
Set slice data sampling maximum
value after A/D conversion.
5
SAMAX = ∑2n ✕ MAXn (Note1)
MAX1
n=0
MAX2
MAX3
MAX4
MAX5
Reserved bit
Must always be set to "0".
MIN0
Set slice data sampling minimun
value after A/D conversion.
Slice data sampling minimum
value selection bit
5
SAMIN = ∑2n ✕ MINn (Note1)
MIN1
n=0
MIN2
MIN3
MIN4
MIN5
Must always be set to "0".
Reserved bit
Note1.
Video signal
Sampling image after A/D conversion
A/D conversion
SAMAX
maximun value
SAMIN
(34) Address 2116 ( = DA5 to 0)
DD15
DD8DD7
0 0 0 0 0 0 0 0 0
Clock run in
A/D conversion
minimum value
DD0
0 0 0 0 0 0
Bit symbol
Bit name
Function
Must always be set to "0".
Reserved bit
DBL_HEIGHT Double height display selection bit
✕
next line, when vertical direction
0 Display
character size is two times.
Do
not
display
next line, when vertical
1 direction character
size is two times.
Must always be set to "0".
Reserved bit
R W
✕
(35) Address 2216 ( = DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Reserved bit
Bit name
Function
Must always be set to "0".
R W
✕
Rev. 1.1
197
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.9 Expansion Register Construction Composition
R (G, B, BLNK, CSYN,
GRAY, SLICEON, EDO1
and EDO2)
PTD
PTC
1
1
0
0
Polarity
Select
PTD
Figure 2.15.29 Switching of port output, R, G and B output
Table 2.15.9 Video signal level
Color
name
Phase (rad)
—
Sync-chip
—
Pedestal
±4π/16
Color burst
—
Black
Red
± 7π/16 ± 2π/16
Green
±
Yellow
± π/16 ± 2π/16
Blue
15π/16 ± 2π/16
11π/16 ± 2π/16
±
Cyan
±
±
Magenta
5π/16 ± 2π/16
9π/16 ± 2π/16
Gray
—
White
—
Luminance level (V) (Note1)
Typ.
1.00
1.60
1.60
1.60
1.80
2.05
2.35
1.70
1.90
2.20
2.20
2.50
Min.
0.90
1.50
1.50
1.50
1.70
1.95
2.25
1.60
1.80
2.10
2.10
2.40
Max.
1.10
1.70
1.70
1.70
1.90
2.15
2.45
1.80
2.00
2.30
2.30
2.60
Chroma level (mV) (Note1)
Min.
Typ.
Max.
—
—
—
—
—
—
480
600
720
—
—
—
1020
1200
1380
930
1100
1270
670
800
920
670
800
920
930
1100
1270
1020
1200
1380
—
—
—
—
—
—
Chroma amplitude (Notes 1 and 2)
Max.
Min.
Typ.
—
—
—
—
—
—
—
—
1.00
—
—
—
2.30
1.70
2.00
2.11
1.55
1.83
1.53
1.13
1.33
1.53
1.13
1.33
2.11
1.55
1.83
2.30
1.70
2.00
—
—
—
—
—
—
Notes. 1 The luminance level and the chroma amplitude of this video signal are ruled only for PAL method.
2 The chroma amplitude is ruled as shown below,
[Each color’s chroma ÷ Color burst’s chroma]
The SLICEON signal is output in the slice possible period.
Vertical blanking erase period pulse
The first field
Slice possible period
622 623 624 625 1
2
3
4
5
6
7
8
9
19
20
21
22
23
24
SLICEON output period
The second field
310 311 312 313 314 315 316 317 318 319 320 321
331 332 333 334 335 336
The scanning lines number in figure is corresponds to slice RAM .
Figure 2.15.30 Slice timing
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.10 Display Forms
(1) Blanking mode
Display forms are shown in Table 2.15.10, display forms at each display mode are shown in Figure
2.15.31.
Table 2.15.26 Display forms
Display mode
Character
Disable
Matrix-outline
Halftone
DSP1 XX
DSP0 XX
(Addresses 0816 (Addresses 0616
and 0916 )
and 0716 )
0
0
0
1
1
0
1
1
BLNK output
Character size
—
All blanking
Blanking OFF
12 dots
14 dots
14 dots
Scanning
10dots
BLNK
R,G,B
c
b c
b
b c b
d
d d
d
d d
b
c b
b
a
a
GRAY
d
CVIDEO1
(Internal sync)
c b
b c b
(External sync)
(1) Character size
a
(2) Matrix-outline size
a
a: External display
signal
b: Background color
c: Character color
d: Output only at
gray display (RGB
output is not be
change at gray
display)
(3) Halftone size
Figure 2.15.31 Blanking mode display
For matrix and halftone, a character’s number of dots in the horizontal direction increases to 14.
Figure 2.15.32 shows a display example for a case where adjacent characters have different background colors and for character code 7F16.
13 dots
12 dots
13 dots
11 dots
11 dots
14 dots
11 dots
40 characters
Character code 7F16
Figure 2.15.32 Number of dots in the horizontal direction at matrix-outline or halftone
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(2) Setting matrix outline
Matrix outline is set by using register ALL24 (address 0E16).Matrix outline can be set for each line
by using the register DSP1XX (addresses 08 16 and 0916) .
However, this setting is disabled if the register EX (address 0D16) is 0 (external sync). An example
of setting example of all matrix-outline area is shown in Figure 2.15.33.
Setting example of register
DSP1xx
DSP1 00
“ 0”
ALL24
“ ”
40 characters all matrix-outline
“1”
ALL24
Horizontal display area all
matrix-outline
40 characters
DSP1 11
DSP1 12
DSP1 13
DSP1 24
“ 0”
“ 1”
“ 0”
“ 0”
OSD display area
BR,BG,BB
The 12th
line
TV Screen
PHASE0,PHASE1,PHASE2
Note : Disable to set when external synchronous. (register EX = “0”)
Figure 2.15.33 Setting example of all matrix-outline area
(3) Blinking mode
Blinking by BLINK bit of display RAM.
And, use registers BLINK0, 1, and 2 (address 0516) to set the duty ratio and period that determines the
blinking time.
Blinking mode is shown in Table 2.15.11(SYRAM do not blink).
The register settings and the duty ratio and period are shown in tables 2.15.12 and 2.15.13.
Table 2.15.11 Blinking mode
Blinking mode
Blinking
Table 2.15.12 Setting of duty ratio
at blinking OFF
BLINK0
BLINK1
0
1
0
1
Blink OFF
Duty 50%
Duty 25%
Duty 75%
Table 2.15.13 Setting of cycle
BLINK2
0
1
Cycle
Approximately 1 second (Vertical sync
divided into 1/64)
Approximately 0.5 second (Vertical sync
divided into 1/32)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(4) Scroll display mode
The scroll display mode is entered by setting registers SBIT0 to 3 (SA), SLIN0 to 4 (SB) (address
0A16), SST0 to 4 (SC), and SEND0 to 4 (SD) (address 0B16). (Scroll is turned off when SD = 0.)
The screen is scrolled in the range from the (SC)’th line to the (SD-1)’th line, and sections above and
below this range are fixed. The beginning line and beginning dot of scroll are the (SA)’th dot on the
(SB)’th line.
The screen can be scrolled up or down by successively incrementing or decrementing SA and SB.
Figure 2.15.34 shows examples of how the display is scrolled. The scroll range in these examples
contains 20 lines (second to the 21th lines). However, the screen can display only 19 lines at a time,
and the remaining one line is handled as a dummy line and not displayed.
Line number when
on screen display
0
1
Zero line
1st line
2
3
4
5
6
2nd line (0 dot to 9 dots)
3rd line
4th line
5th line
<Scrolling block>
6th line
17
18
19
20
17th line
18th line
19th line
20th line (0 dot to 9 dots)
21
22
23
22th line
23th line
24th line
Dummy line
21th line (0 dot to 9 dots)
<fixed block>
Line number when
on screen display
0
1
Zero line
1st line
<fixed block>
5th line (3 dots to 9 dots)
2
3
4
5
6th line
7th line
8th line
....
Setting example 2
SA = 3
SB = 5
SC = 2
SD = 22
<fixed block>
.....
....
Setting example 1
SA = 0
SB = 2
SC = 2
SD = 22
.....
16
17
18
19
20
19th line
20th line
21th line
2nd line
3rd line
21
22
23
22th line
23th line
24th line
<Scrolling block>
Dummy line
5th line (0 dot to 2 dots)
and
4th line (3 dots to 9 dots)
4th line (0 dot to 2 dots)
<fixed block>
When displayed in order of SA = 0, 1, 2, and so on, the screen scrolls up. When displayed in order of SA = 9, 8, 7 and so
on, the screen scrolls down.
(1) To scroll the screen up, write the dummy line after setting the 0th dot in SA but before setting the 1st dot.
(2) To scroll the screen down, write the dummy line after setting the 0th dot in SA but before setting the 9th dot of the preceding line.
Figure 2.15.34 Scrolling example
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.11 8/4 Humming Decoder
8/4 humming decoder opetates only by written the data which 8/4 humming- decoded to 8/4 humming
register (address 021A16). 8/4 humming register consists of 16 bits, can decode two data at a time.
Can obtain the decoded result by reading 8/4 humming register, and the decoded value and error
information are output. Corrects and outputs the decoded value for single error, and outputs only error
information for double error. Decoded result is shown in Figure 2.15.35 and humming 8/4 register
composition is shown in Figure 2.15.36.
Humming data ➁
Humming data ➀
LSB MSB
MSB
LSB
Writing
Address
8/4 humming register
021A 16
Reading
Error information
➁
0
0
Error information
➀
0
0
“1” output when
single error
Decode value
➁
MSB
Decode value
➀
LSB
MSB
LSB
“1” output when single error
“1” output when double error
“1” output when double error
Figure 2.15.35 Decoded result
Humming 8/4 register
b15
b8 b7
b0
Symbol
HM 8
Address
021A16
When reset
000016
Function
RW
8/4 humming decoder opetates only by written the data which 8/4 humming-decoded to 8/4
humming register.Can obtain the decoded result by reading this register, and can decode 2
couples of data at the same time.
Figure 2.15.36 Humming 8/4 register composition
Rev. 1.0
202
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.12 24/18Humming Decoder
24/18 humming decoder operates only by written the data which 24/18 humming-encoded to 24/18
humming register 0 (address 021C16) and 1 (address 021E16). Can obtain the decoded result by
reading the same 24/18 humming register. Decoded result is shown in Figure 2.15.37 and humming
24/18 register composition is shown in Figure 2.15.38.
Humming data L
Humming data M
Humming data H
MSB
LSB
Writing
Writing
Address
24/18 humming register 1
021E16
Reading
Reading
Error information
0
0
0
0
0
0
0
0
0
Address
021C 16
24/18 humming register 0
0
0
0
Decode
value
MSB
Decode value
LSB
“1” output when single error
Output after correcting single error
“1” output when double error
Figure 2.15.37 Decoded result
Humming 24/18 register 0
b15
b8 b7
b0
Symbol
HM0
Address
021C16
When reset
000016
R W
Function
24/18 humming decoder opetates by two ways : writing data low-order and middle-order 16
bits to this register and writing data high-order 8 bits to humming 24/18 register 1 (021E16).
Can obtain the decoded result by reading this register and humming 24/18 register 1.
Humming 24/18 register 1
b15
b8 b7
b0
Symbol
HM1
Address
021E16
When reset
000016
Function
RW
24/18 humming decoder opetates by two ways : writing data low-order and middle-order 16
bits to humming 24/18 register 0 (021C16) to this register and writing data high-order 8 bits
to this register.
Can obtain the decoded result by reading this register and humming 24/18 register 0.
Figure 2.15.38 Humming 24/18 register composition
Rev. 1.0
203
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Continuous error correction
When uses humming 8/4 (address 021A16) at tha same time as humming 24/18, can do the continuous error correction.
Continuous error correction sequence is shown in Figure 2.15.39.
A
Humming data➀
M
Humming data➀
L
B
Humming data➁
L
Humming data➀
H
C
Humming data➁
H
Humming data➁
M
D
Humming data ➂
M
Humming data ➂
L
E
Humming data➃
L
Humming data ➂
H
F
Humming data➃
H
Humming data➃
M
1. Writes data A to address 021C 16 and writes data B to address
021E16 . (Setting the humming data ➀ and L of humming data
➁.)
2. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➀).
3. Writes data C to address 021A 16 (Setting H and M of the humming data ➁).
4. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➁).
5. Writes data D to address 021C 16 and writes data E to 021E16
(Setting the humming data ➂ and L of humming data ➃.)
6. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➂).
7. Writes data F to address 021A 16 (Setting H and M of the humming data ➃).
8. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➃).
Figure 2.15.39 Continuous error correction sequence
Then, because using a part of circuit of humming 8/4 about this operation, cannot use this operation
at the same time.
When using the humming circuit, do the decoded result reading operation at once after the setting
data of humming. And do not access other memories (Including the humming circuit) before reading
of the decoded result.
Rev. 1.0
204
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.15.13 I/O Composition of pins for Expansion Memory
Figure 2.15.40 and figure 2.15.41 show pins for expansion memory.
SECAMIN,CVIN1,
CVIN2,
CVIDEO1,CVIDEO2
from internal circuit
VCC
(Note1)
SECAMIN
VCC
VSS
CVIDEO1
(Note1)
VSS
from internal circuit
VCC
CVIN1
(Note1)
VSS
from internal circuit
from internal circuit
to slicer
VCC
CVIN2
(Note1)
VSS
from internal circuit
VCC
CVIDEO2
from internal circuit
SYNCIN
from internal circuit
(Note1)
VSS
to internal circuit
VDD2
VCC
from internal circuit
INPUT
(Note1)
VSS
to internal
circuit
VSS2
Note1 :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 2.15.40 Pins for expansion memory(1)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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P110 ~ P118
VCC
OSD OUTPUT
VCC
OUTPUT
(Note2)
VSS
Port P11 data selection bit (Note1)
VSS
Port P11 output selection bit (Note1)
VCC
VERT
to internal circuit
INPUT
(Note2)
VSS
VDD2
LP1, LP2, LP3, LP4
VCC
from internal circuit
OUTPUT
(Note2)
VSS
VSS2
to internal circuit
VCC
FSCIN
INPUT
to internal circuit
(Note2)
VSS
from internal circuit
VSS2
VDD2
SVREF
VCC
from internal circuit
INPUT
(Note2)
VSS
to internal
circuit
VSS2
Note1 : Refer expansion register construction
Note2 :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 2.15.41 Pins for expansion memory(2)
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
2.16 Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85
is an input-only port and has no built-in pull-up resistance.
Figures 2.16.1 to 2.16.4 show the programmable I/O ports. Figure 2.16.5 shows the I/O pins.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to
input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A
converter), they function as outputs regardless of the contents of the direction registers. When pins are to
be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 2.16.6 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 2.16.7 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 2.16.8 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, the pull-up control register of P0 to P5 is invalid.
(4) Port control register
Figure 2.16.9 shows the port control register.
The bit 0 of port control resister is used to read port P1 as follows:
0 : When port P1 is input port, port input level is read.
When port P1 is output port , the contents of port P1 register is read.
1 : The contents of port P1 register is read always.
This register is valid in the following:
• External bus width is 8 bits.
• Port P1 can be used as a port in multiplexed bus for the entire space.
Rev. 1.0
207
MITSUBISHI MICROCOMPUTERS
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
VCC
Pull-up selection
VSS
Direction register
P00 to P07, P20 to P27,
P30 to P37, P40 to P47,
P50 to P54, P56
Data bus
Port latch
(Note1)
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Data bus
Port latch
(Note1)
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Pull-up selection
Direction register
P57, P60, P61, P64, P65,
P72 to P76, P80, P81,
P90, P92
"1"
Output
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Note1 :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 2.16.1 Programmable I/O ports (1)
Rev. 1.0
208
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
VCC
Pull-up selection
VSS
P82 to P84
Direction register
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Pull-up selection
Direction register
P55, P62, P66, P77,
P91, P97
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67
"1"
Data bus
Port latch
Output
(Note1)
P85
Data bus
NMI interrupt input
P70, P71
(Note1)
Direction register
"1"
Data bus
Port latch
Output
(Note1)
Input to respective peripheral functions
Note1 :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 2.16.2 Programmable I/O ports (2)
Rev. 1.0
209
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
VCC
Pull-up selection
P100 to P103
(inside dotted-line not included)
P104 to P107
(inside dotted-line included)
VSS
Direction register
Data bus
Port latch
(Note1)
Analog input
Input to respective peripheral functions
Pull-up selection
D-A output enabled
Direction register
P93, P94
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Analog output
D-A output enabled
Pull-up selection
Direction register
P96
"1"
Data bus
Port latch
Output
(Note1)
Analog input
Pull-up selection
Direction register
P95
"1"
Data bus
Port latch
Output
(Note1)
Input to respective peripheral functions
Analog input
Note1 :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 2.16.3 Programmable I/O ports (3)
Rev. 1.0
210
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
VCC
Pull-up selection
VSS
Direction register
P87
Data bus
Port latch
(Note1)
fc
Rf
Pull-up selection
Rd
Direction register
P86
"1"
Data bus
Port latch
Output
(Note1)
Note1 :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 2.16.4 Programmable I/O ports (4)
VCC
BYTE
VSS
BYTE signal input
(Note1)
CNVSS
CNVSS signal input
(Note1)
RESET
RESET signal input
(Note1)
Note 1:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each pin.
Figure 2.16.5 I/O pins
Rev. 1.0
211
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Port Pi direction register (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PDi (i = 0 to 10, except 8)
Bit symbol
Address
03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F316, 03F616
Bit name
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
PDi_4
Port Pi3 direction register
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
Function
A
A
A
A
A
A
When reset
0016
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 10 except 8)
Note: Set bit 2 of protect register (address 000A16) to “1” before rewriting to
the port P9 direction register.
Port P8 direction register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PD8
Bit symbol
Address
03F216
Bit name
PD8_0
Port P80 direction register
PD8_1
Port P81 direction register
PD8_2
Port P82 direction register
PD8_3
Port P83 direction register
When reset
00X000002
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
PD8_4
Port P84 direction register
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
PD8_6
Port P86 direction register
PD8_7
Port P87 direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
A
A
A
A
A
A
RW
Figure 2.16.6 Direction register
Rev. 1.0
212
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Pi (i = 0 to 10, except 8)
Bit symbol
Address
03E016, 03E116, 03E416, 03E516, 03E816
03E916, 03EC16, 03ED16, 03F116, 03F416
Bit name
Pi_0
Port Pi0 register
Pi_1
Pi_2
Port Pi1 register
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data (Note)
(i = 0 to 10 except 8)
When reset
Indeterminate
Indeterminate
A
A
A
A
A
RW
Note : Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
Port P8 register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P8
Bit symbol
Address
03F016
Bit name
P8_0
Port P80 register
P8_1
Port P81 register
P8_2
Port P82 register
P8_3
Port P83 register
P8_4
Port P84 register
P8_5
Port P85 register
P8_6
Port P86 register
P8_7
Port P87 register
When reset
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : “L” level data
1 : “H” level data
A
A
A
A
A
A
R W
Figure 2.16.7 Port register
Rev. 1.0
213
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Pull-up control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Bit symbol
Address
03FC16
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
PU04
P20 to P23 pull-up
PU05
P24 to P27 pull-up
PU06
P30 to P33 pull-up
PU07
P34 to P37 pull-up
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Inhibited
A
A
A
A
A
RW
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit symbol
Address
03FD16
Bit name
PU10
P40 to P43 pull-up
PU11
P44 to P47 pull-up
PU12
P50 to P53 pull-up
PU13
P54 to P57 pull-up
PU14
P60 to P63 pull-up
PU15
P64 to P67 pull-up
When reset
0016 (Note 2)
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Inhibited
A
A
A
A
A
A
R W
The corresponding port is pulled
high with a pull-up resistor
PU16
P70 to P73 pull-up (Note 1) 0 : Not pulled high
1 : Pulled high
PU17
P74 to P77 pull-up
Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them.
Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes
to 0216 when reset (PU11 becomes to “1”).
Pull-up control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR2
Bit symbol
Address
03FE16
Bit name
PU20
P80 to P83 pull-up
PU21
P84 to P87 pull-up
(Except P85)
PU22
P90 to P93 pull-up
PU23
PU24
P94 to P97 pull-up
P100 to P103 pull-up
PU25
P104 to P107 pull-up
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
A
A
A
A
A
RW
Figure 2.16.8 Pull-up control register
Rev. 1.0
214
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Port control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
PCR
Address
03FF16
Bit symbol
PCR0
Bit name
Port P1 control register
When reset
0016
Function
0 : When input port, read port
input level. When output port,
read the contents of port P1
register.
1 : Read the contents of port P1
register though input/output
port.
R W
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be “0”.
Figure 2.16.9 Port control register
Rev. 1.0
215
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 2.16.1 Example connection of unused pins.
Pin name
Connection
Ports P6 to P10
(excluding P85)
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
P45 ,P46/CS2, P47/CS3
Sets ports to input mode, sets bits CS2, CS3 to 0, and connects to Vcc
via resistors (pull-up).
BHE, ALE, HLDA,
XOUT(Note), BCLK
Open
HOLD, RDY, NMI
Connect via resistor to VCC (pull-up)
AVCC
Connect to VCC
AVSS, VREF
Connect to VSS
CNVSS
Connect via resistor to VCC (pull-up)
Note: With external clock input to XIN pin.
Microcomputer
Port P6 to P10 (except for P85)
...
...
(Input mode)
(Input mode)
(Output mode)
Port P45
P46 / CS2
P47 / CS3
NMI
BHE
HLDA
ALE
XOUT
BCLK
Open
Open
VCC
HOLD
RDY
0.47µF
CNVSS
AVCC
AVSS
VREF
VSS
Figure 2.16.10 Example connection of unused pins
Rev. 1.0
216
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
3. Usage Precaution
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the
timer Ai register after setting a value in the timer Ai register with a count halted but before the counter
starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
(3) In the case of using “Event counter mode” as “Free-Run type” for timer A, the timer register contents
may be unkown when counting begins. If the timer register is set before counting has started, then the
starting value will be unkown.
This issue will occuer only for the “Event counter mode” operating as “Free-Run type”. The value of
the timer register will not be unkown during counting.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after
the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after
the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
Rev. 1.0
217
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by AD conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the
WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction
queue are prefetched and then the program stops. So put at least four NOPs in succession either to
the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”.
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
stack pointer before
accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack point at the beginning of a program.
Concerning the
_______
first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohib
ited.
Rev. 1.0
218
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor
(pull-up) if unused. Be sure to work on it.
_______
• Do not get either into stop mode with the NMI pin set to “L”.
(4) External interrupt
________
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to “1”.
After changing the polarity, set the interrupt request bit to “0”.
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
Rev. 1.1
219
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Other Notes
(1) Timing of power supplying
The power need to supply to VCC, VDD1, VDD2, VDD3 and AVCC at a time. While operating, must set same
voltage.
(2) Power supply noise and latch-up
In order to avoid power supply noise and latch-up, connect a bypass capacitor (more than 0.1µF) directly
between the VCC pin and VSS pin, VDD1 pin and VSS1 pin, VDD2 pin and VSS2 pin, VDD3 pin and VSS3 pin,
AVCC pin and AVSS pin using a heavy wire.
(3) After the reset
After the reset, until the oscillator circuit stabilizes, data is sometimes not set correctly in the display RAM,
font RAM, SYRAM and VBIRAM. Therefore, use the following start-up procedure.
(a) Reset release.
(b) Set expansion register CK_VCO, XTAL_VCO, PDC_VCO_ON,VPS_VCO_ON = “H”. (oscillation start)
(c) Set expansion register SYNCSEP_ON0 = “H”.
(d) Set expansion register NXP = “H”.
(e) Set expansion register PCn, DIV_PDCn, DIV_PDCSn, DIV_VPSn, DIV_VPSSn.
(f) Disable data input for a 20 m sec (time enough to allow theinternal oscillator circuit to stabilize).
(g) Set other expansion registers.
(h) Set the SYRAM.
(i) Set the display RAM.
(j) Set expansionregister DSPON and DSPONV to display ON.
(k) Possible to access slice RAM.
(4) When resuming internal oscillation from the off state
The each internal oscillator circuit of expansion function stops oscillating when expansion register
CK_VCO,XTAL_VCO,PDC_VCO_ON,VPS_VCO_ON = “L”.
When resuming internal oscillation from the off state, up until the oscillator circuit stabilizes, data is sometimes not set correctly in the display RAM , font RAM, SYRAM and VBIRAM. Therefore, start oscillation
as follows.
(a) Set expansion register CK_VCO = “H”.
(b) Set expansion register XTAL_VCO = “H”.
(c) Set expansion register PDC_VCO_ON= “H”, VPS_VCO_ON = “H”.
(Necessity none when data sliceris not used)
(d) Wait for a 20 m sec. (time enough to allow the internal oscilla-tor circuit to stabilize)
(e) Access the other memories.
Especially, set expansion register XTAL_VCO = “H” when access to display RAM, font RAM, SYRAM,
VBIRAM and slice RAM. And input 4.43 MHz sub carrier frequency clock from the FSCIN pin.
Access the memory after waiting for 20ms certaninly when resuming synchronous oscillation from the
off state, and begin to input clock into the FSCIN pin.
Rev. 1.1
220
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
(5) Other notes on oscillation
Make note of the fact that the internal oscillator circuit cannot stabilize in the below situations.
(a) When the external composite video signal is discontinuous. (when changing channels, etc.)
(b) When expansion register PCn setting is changed.
(c) When expansion register SYNCSEP_ON0 setting is changed.
Before changing settings, turn expansion registers DSPON and DSPONV off. Also, disable data input for
20 m sec after making settings.
(6) When no external composite video signal is input
Without a signal, characters cannot be displayed by external synchronization. Therefore, switch to internal synchronization.
(7) When signal level of the external composite video signal is extremely poor
With a weak electric field, character display is uncontrollable by external synchronization. Therefore,
switch to internal synchronization.
(8) When oscillation circuit stop for data slicer
Expansion register PDC_VCO_ON,VPS_VCO_ON is set at “L”, when the data slicer is not used, and the
oscillation is stopped. When starting oscillation again, set data at the folowing order.
(a) Set expansion register PDC_VCO_ON,VPS_VCO_ON = “L”.
(b) Set expansion register PDC_VCO_ON,VPS_VCO_ON = “H”.
(c) 60 ms or more is a waiting state (stability period of internal oscillation circuit + data slice preparation).
To operate slice RAM , set expansion register XTAL_VCO = “H”. And input 4.43 MHz sub carrier frequency clock from the FSCIN pin.
Access the memories after wating for 20 ms certainly when resuming synchronous oscillation from the off
state , and begin to input clock into the FSCIN pin.
(9) When the data slicer is used without displaying OSD
If expansion register DSPON is set in “L”, the OSD display is turned off.
Expansion register CK_VCO must be set “H” in that case
(10) At stop mode (clock is stopped)
Set each input pins to as follows.
(a) Set VERT pin = VSS.
(b) Stop the FSCIN pin input.
(c) Set expansion register STBY0 and STBY1 = “H”.
Set all expansion registers to “L” except for the superscription register.
(11) When operation start from stop mode (clock is stopped)
Input FSCIN pin clock after set “L” to register STBY0 and STBY1.
At next, set expansion register as notes (4).
Rev. 1.0
221
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
4. Electrical characteristic
Table 4.1 Absolute maximum ratings
Symbol
Vcc
AVcc
VI
VO
Pd
Topr
Tstg
Parameter
Supply voltage
Analog supply voltage
Input
RESET, CNVss, BYTE,
voltage
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P87,
P90 to P97, P100 to P107,
VREF, XIN, HOR,VERT
P70, P71
Output
P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37,P40 to P47, P50 to P57,
P60 to P67,P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
XOUT, P110 to P118
P70, P71
Power dissipation
Operating ambient temperature
Storage temperature
Condition
Rated value
Unit
VCC=AVCC
VCC=AVCC
-0.3 to 5.75
V
-0.3 to 5.75
V
-0.3 to Vcc+0.3
V
-0.3 to 5.75
V
-0.3 to Vcc+0.3
V
-0.3 to 5.75
1000
-20 to 70
-40 to 125
V
mW
C
C
Ta=25 C
Rev. 1.0
222
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Tabl 4.2 Recommended operating conditions (referenced to VCC = 4.75V to 5.25V at Ta = – 20 to
70 oC unless otherwise specified)
Symbol
Parameter
Vcc
AVcc
Vss
AVss
Supply voltage
Analog supply voltage
Supply voltage
Analog supply voltage
VIH
HIGH input P31 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, P100 to P107,
voltage
XIN, RESET, CNVSS, BYTE, HOR, VERT
P00 to P07, P10 to P17, P20 to P27, P30
VIL
VCVIN
VFSCIN
I OH (peak)
I OH (avg)
I OL (peak)
Min
P00 to P07, P10 to P17, P20 to P27, P30
CVIN1, CVIN2
V
V
V
V
0.8Vcc
Vcc
V
0.5Vcc
Vcc
V
0
0.2Vcc
V
0
0.16Vcc
V
V
4.0V P-P
V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
10
MHz
Composite video input voltage
Input voltage
FSCIN(Note 1)
5.0
Vcc
0
0
2V P-P
0.3V P-P
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
P40 to P47, P50 to P57, P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P118
HIGH average output P00 to P07, P10 to P17, P20 to P27,P30 to P37,
current
P40 to P47, P50 to P57, P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P118
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
LOW peak output
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
current
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P118
HIGH peak output
current
(Note 2.3)
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P110 to P118
I OL (avg)
LOW average
output current
f (XIN)
Main clock input
oscillation frequency
f (XcIN)
Subclock oscillation frequency
No wait
with wait
Vcc=4.75V to 5.25V
f (FSCIN) Oscillation frequency for synchronous signal(Duty 40% to 60%)
Unit
5.25
4.75
LOW input P31 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, P100 to P107,
voltage
XIN, RESET, CNVSS, BYTE, HOR, VERT
Standard
Typ.
Max.
0
32.768
4.434
50
kHz
MHz
Note 1: Noise component is within 30mV.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH
(peak) for ports P0, P1,
P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and
P80 to P8 4 must be
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P7 7, and P80 to P84 must be 80mA
max.
Rev. 1.0
223
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 4.3 Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 oC, f(XIN) =10MHZ
unless otherwise specified)
Parameter
Symbol
VOH
Measuring condition
HIGH output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
IOH=-5mA
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P110 to P118
Standard
Min Typ. Max.
Unit
3.0
V
VOH
HIGH output P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
voltage
IOH=-200µA
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P110 to P118
4.7
V
VOH
HIGH output
LP1 to LP4
voltage
V
VOH
VOL
VOL
HIGH output
voltage
XOUT
HIGH output
voltage
XCOUT
VCC=4.75V, IOH=-0.5mA
3.75
HIGHPOWER
IOH=-1mA
3.0
LOWPOWER
IOH=-0.5mA
3.0
HIGHPOWER
With no load applied
With no load applied
LOWPOWER
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P110 to P118
LOW output
LP1 to LP4
voltage
VOL
LOW output
voltage
XOUT
LOW output
voltage
XCOUT
Hysteresis
VT+-VT-
3 .0
1.6
V
2 .0
V
0.45
V
VCC=4.75V, IOH=-0.5mA
0.4
V
HIGHPOWER
IOL=1mA
2.0
LOWPOWER
IOL=0.5mA
2.0
HIGHPOWER
With no load applied
With no load applied
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P110 to P118
VOL
V
LOWPOWER
IOL=5mA
IOL=200µA
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB2IN, INT0 to INT5,
ADTRG, CTS1, CLK1, NMI
TA2OUT to TA4OUT,KI0 to KI3
0
V
0
0.2
V
0.8
V
VT+-VT-
Hysteresis
CTS0, CLK0
0 .2
1.4
V
VT+-VT-
Hysteresis
RESET
0 .2
1.8
V
VI=5V
5.0
µA
VI=0V
-5.0
µA
167.0
kΩ
IIH
I IL
RPULLUP
HIGH input P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
current
P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
XIN, RESET, CNVss, BYTE,
HOR, VERT
LOW input P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
current
P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
XIN, RESET, CNVss, BYTE,
HOR, VERT
Pull-up
P00 to P07, P10 to P17, P20 to P27,
resistance P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107
VI=0V
30.0
50.0
V SYNCIN
Sync voltage amplitude
0 .3
0 .6
1 .2
V
V dat(text)
Teletext data voltage amplitude
0 .6
0 .9
1 .4
V
䉭 f/ f
Range for display oscillator circuit
±7
fH
Horizontal synchronous signal frequency
14.6
%
15.625
17.0
kHZ
Rev. 1.0
224
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 4.4 Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) = 10MHZ
unless otherwise specified)
Symbol
Parameter
Measuring condition
RfXIN
Feedback resistance XIN
R fXCIN
Feedback resistance XCIN
V
RAM retention voltage
When clock is stopped
Power supply current
When OSD operate,
RAM
I cc
Standard
Min Typ. Max.
1.0
MΩ
6.0
MΩ
2.0
f(XIN)=10MHz
Unit
V
150
When clock is stopped
180
mA
3
mA
Tabl 4.5 Video signal input conditions (VCC = 5.0V, Ta = –20 to 70oC)
Symbol
V IN-cu
Parameter
Composite video signal input clamp voltage
Measuring condition
Sync-chip voltage
Standard
Min Typ. Max.
1.0
Unit
V
Rev. 1.0
225
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Table 4.6 A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V
at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Standard
Symbol
Parameter
Measuring condition
Unit
Min. Typ. Max.
Resolution
8 Bits
VREF = VCC
Absolute
accuracy
RLADDER
tCONV
tSAMP
VREF
VI A
Sample & hold function not available
Sample & hold function available(8bit)
Ladder resistance
Conversion time(8bit)
Sampling time
Reference voltage
Analog input voltage
VREF = VCC = 5V
VREF = VCC = 5V
VREF = VCC
10
±3
±2
40
LSB
LSB
kΩ
2
VCC
µs
µs
V
0
VREF
V
2.8
0.3
Table 4.7 D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V at
Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Symbol
tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Measuring condition
(Note)
Standard
Typ. Max.
8
1.0
3
4
10
20
1.5
Min.
Unit
Bits
%
µs
kΩ
mA
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
Rev. 1.0
226
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 4.8 External clock input
Symbol
Parameter
tc
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
tw(H)
tw(L)
tr
tf
_______
__________
Standard
Min.
Max.
Unit
ns
100
40
40
18
18
ns
ns
ns
ns
__________
Table 4.9 RDY, HOLD, HLDA imput
Symbol
Parameter
tac1(RD-DB)
Data input access time (no wait)
tac2(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK )
tsu(HOLD-BCLK )
th(RD-DB)
th(BCLK -RDY)
th(BCLK-HOLD )
td(BCLK-HLDA )
Standard
Max.
Min.
(Note)
(Note)
(Note)
40
Unit
ns
ns
ns
40
ns
ns
ns
0
ns
0
ns
30
ns
0
40
ns
Note: Calculated according to the BCLK frequency as follows:
tac1(RD – DB) =
10 9
– 45
f(BCLK) X 2
tac2(RD – DB) =
3 X 10
– 45
f(BCLK) X 2
tac3(RD – DB) =
3 X 10
– 45
f(BCLK) X 2
[ns]
9
[ns]
9
[ns]
Rev. 1.0
227
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 4.10 Timer A input (counter input in event counter mode)
Symbol
Parameter
Standard
Min.
Max.
100
Unit
ns
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input HIGH pulse width
40
ns
tw(TAL)
TAiIN input LOW pulse width
40
ns
Table 4.11 Timer A input (gating input in timer mode)
Symbol
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Standard
Max.
Min.
400
200
200
Unit
ns
ns
ns
Table 4.12 Timer A input (external trigger input in one-shot timer mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
100
100
ns
ns
Table 4.13 Timer A input (external trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
Parameter
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Standard
Max.
Min.
100
100
Unit
ns
ns
Table 4.14 Timer A input (up/down input in event counter mode)
tc(UP)
TAiOUT input cycle time
tw(UPH)
TAiOUT input HIGH pulse width
Standard
Min.
Max.
2000
1000
tw(UPL)
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
1000
400
400
Symbol
tsu(UP-TIN)
th(TIN-UP)
Parameter
Unit
ns
ns
ns
ns
ns
Rev. 1.0
228
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Timing requirements (referenced to V CC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 4.15 Timer B input (counter input in event counter mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
40
200
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
80
ns
ns
Table 4.16 Timer B input (pulse period measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
200
200
ns
ns
Table 4.17 Timer B input (pulse width measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input HIGH pulse width
200
ns
tw(TBL)
TBiIN input LOW pulse width
200
ns
Table 4.18 A-D trigger input
Symbol
tc(AD)
tw(ADL)
Parameter
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
Standard
Min.
1000
125
Max.
Unit
ns
ns
Table 4.19 Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input HIGH pulse width
100
ns
tw(CKL)
CLKi input LOW pulse width
100
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
RxDi input setup time
RxDi input hold time
th(C-D)
ns
80
ns
0
30
ns
90
ns
ns
_______
Table 4.20 External interrupt INTi inputs
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
Standard
Min.
250
250
Max.
Unit
ns
ns
Rev. 1.0
229
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Switching characteristics (referenced to V CC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
Table 4.21 No wait
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Measuring condition
Parameter
Symbol
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
Standard
Min.
Max.
25
4
0
0
25
4
25
Figure 4.1
–4
25
0
25
0
40
4
(Note1)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 9
– 40
f(BCLK) X 2
[ns]
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
R
DBi
C
Rev. 1.0
230
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Switching characteristics (refer to VCC = 5V, VSS = 0V at Ta = 25 oC, CM15 = “1” unless otherwise
specified)
Table 4.22 With wait, accessing external memory
Measuring condition
Parameter
Symbol
Standard
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
4
0
0
td(BCLK-CS)
th(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
4
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
th(BCLK-RD)
td(BCLK-WR)
RD signal output hold time
WR signal output delay time
th(BCLK-WR)
td(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
25
ns
ns
ns
ns
25
25
ns
ns
ns
ns
ns
25
ns
ns
40
ns
ns
25
–4
Figure 4.1
Unit
0
0
4
(Note1)
ns
ns
ns
0
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 9
f(BCLK)
– 40
[ns]
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
R
DBi
C
Rev. 1.0
231
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Switching characteristics (referenced to V CC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
Table 4.23 With wait, accessing external memory, multiplex bus area selected
Symbol
Measuring condition
Parameter
Standard
Min.
Max.
25
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
th(RD-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
(Note)
ns
ns
th(WR-AD)
Address output hold time (WR standard)
(Note)
ns
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
Chip select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
th(BCLK-DB)
td(DB-WR)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
th(WR-DB)
td(BCLK-ALE)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
td(AD-ALE)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
(Note)
ns
ns
th(ALE-AD)
td(AD-RD)
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
50
0
ns
ns
td(AD-WR)
tdZ(RD-AD)
Post-address WR signal output delay time
Address output floating start time
4
25
4
(Note)
(Note)
25
0
25
0
40
Figure 4.1
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note)
(Note)
25
–4
0
8
ns
ns
ns
ns
Note: Calculated according to the BCLK frequency as follows:
th(RD – AD) =
10 9
f(BCLK) X 2
th(WR – AD) =
10
f(BCLK) X 2
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
[ns]
th(WR – CS) =
10
f(BCLK) X 2
td(DB – WR) =
10 X 3
– 40
f(BCLK) X 2
th(WR – DB) =
10
f(BCLK) X 2
[ns]
td(AD – ALE) =
10 9
– 25
f(BCLK) X 2
[ns]
[ns]
9
9
[ns]
9
[ns]
9
Rev. 1.0
232
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
P0
P1
P2
30pF
P3
P4
P5
P6
P7
P8
P9
P10
P11
Figure 4.1 Port P0 to P11 measurement circuit
Rev. 1.0
233
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 4.2 Timing diagram (1)
Rev. 1.0
234
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Valid Only With Wait
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
Valid With Or Without Wait
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 4.3 Timing diagram (2)
Rev. 1.0
235
MITSUBISHI MICROCOMPUTERS
M306H1SFP
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with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
With No Wait
Read timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
4ns.min
25ns.max
CSi
th(RD–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
ALE
4ns.min
th(RD–AD)
td(BCLK–ALE) th(BCLK–ALE)
0ns.min
–4ns.min
25ns.max
th(BCLK–RD)
td(BCLK–RD)
25ns.max
0ns.min
RD
tac1(RD–DB)
Hi–Z
DB
tSU(DB–RD)
th(RD–DB)
40ns.min
0ns.min
td(BCLK–CS)
th(BCLK–CS)
Write timing
BCLK
4ns.min
25ns.max
CSi
th(WR–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK-AD)
25ns.max
ADi
BHE
4ns.min
td(BCLK–ALE) th(BCLK–ALE)
th(WR–AD) 0ns.min
–4ns.min
ALE
25ns.max
th(BCLK–WR)
td(BCLK–WR)
WR,WRL,
WRH
DB
0ns.min
25ns.max
td(BCLK–DB)
40ns.max
Hi-Z
th(BCLK–DB)
4ns.min
td(DB–WR)
th(WR–DB)
0ns.min
(tcyc/2–40)ns.min
Figure 4.4 Timing diagram (3)
Rev. 1.0
236
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
When Accessing External Memory Area With Wait
Read timing
BCLK
th(BCLK–CS)
td(BCLK–CS)
4ns.min
25ns.max
CSi
th(RD–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
4ns.min
td(BCLK–ALE) 25ns.max
th(BCLK–ALE)
th(RD–AD)
0ns.min
–4ns.min
ALE
th(BCLK–RD)
td(BCLK–RD)
0ns.min
25ns.max
RD
tac2(RD–DB)
Hi–Z
DB
tSU(DB–RD)
th(RD–DB)
40ns.min
0ns.min
Write timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
4ns.min
25ns.max
CSi
th(WR–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
4ns.min
td(BCLK–ALE)
th(WR–AD)
25ns.max
th(BCLK–ALE)
0ns.min
–4ns.min
ALE
td(BCLK–WR)
25ns.max
WR,WRL,
WRH
td(BCLK–DB)
40ns.max
th(BCLK–WR)
0ns.min
th(BCLK–DB)
4ns.min
DBi
td(DB–WR)
(tcyc–40)ns.min
th(WR–DB)
0ns.min
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V
Figure 4.5 Timing diagram (4)
Rev. 1.0
237
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
When Accessing External Memory Area With Wait, And Select Multiplexed bus
Read timing
BCLK
td(BCLK–CS)
tcyc
CSi
td(AD–ALE)
th(BCLK–CS)
th(RD–CS)
(tcyc/2)ns.min
25ns.max
4ns.min
th(ALE–AD)
(tcyc/2-25)ns.min
30ns.min
ADi
/DBi
Address
Data input
tdz(RD–AD)
tac3(RD–DB)
8ns.max
Address
th(RD–DB)
tSU(DB–RD)
0ns.min
40ns.min
td(AD–RD)
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
ALE
4ns.min
td(BCLK–ALE)
th(BCLK–ALE)
th(RD–AD)
(tcyc/2)ns.min
–4ns.min
25ns.max
th(BCLK–RD)
td(BCLK–RD)
0ns.min
25ns.max
RD
Write timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
tcyc
th(WR–CS)
25ns.max
4ns.min
(tcyc/2)ns.min
CSi
th(BCLK–DB)
td(BCLK–DB)
4ns.min
40ns.max
ADi
/DBi
Data output
Address
td(DB–WR)
(tcyc*3/2–40)ns.min
td(AD–ALE)
(tcyc/2–25)ns.min
ADi
BHE
ALE
Address
th(WR–DB)
(tcyc/2)ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
4ns.min
td(BCLK–ALE)
th(BCLK–ALE)
–4ns.min
td(AD–WR)
0ns.min
25ns.max
td(BCLK–WR)
25ns.max
WR,WRL,
WRH
th(WR–AD)
(tcyc/2)ns.min
th(BCLK–WR)
0ns.min
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with VOL=0.8V, VOH=2.0V
Figure 4.6 Timing diagram (5)
Rev. 1.0
238
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
5. Marking Figure
M306H1SFP
XXXXXX
XXXXXX: Mitsubishi lot number
Rev. 1.0
239
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
6. Package Outline
144P6Q-A
Plastic 144pin 20✕20mm body LQFP
Weight(g)
1.23
JEDEC Code
–
Lead Material
Cu Alloy
MD
e
EIAJ Package Code
LQFP144-P-2020-0.50
b2
D
144
ME
HD
109
1
l2
Recommended Mount Pad
108
36
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
73
37
72
A
L1
F
e
x
L
M
Detail F
Lp
c
b
A1
y
A3
A2
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
1.7
–
–
0.125
0.2
0.05
1.4
–
–
0.17
0.22
0.27
0.105
0.125
0.175
19.9
20.0
20.1
19.9
20.0
20.1
0.5
–
–
21.8
22.0
22.2
21.8
22.0
22.2
0.35
0.5
0.65
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
0.1
–
–
0°
8°
–
0.225
–
–
0.95
–
–
20.4
–
–
–
–
20.4
Rev. 1.0
240
MITSUBISHI MICROCOMPUTERS
M306H1SFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
•
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective Oct. 2000.
Specifications subject to change without notice.
REVISION HISTORY
Rev.
No.
1.0
1.1
M306H1SFP (Rev.1.1) DATA SHEET
Revision Description
PDF First Edition
Rev.
date
0006
Expansion register construction corrected
(28) Address 1B16 ( = DA5 to 0) (page 195)
(29) Address 1C16 ( = DA5 to 0) (page 195)
(34) Address 2116 ( = DA5 to 0) (page 197)
(35) Address 2216 ( = DA5 to 0) (page 197)
0010
The change of the page layout
Usage precaution (page 219 and 220)
(1/1)