MX25L3208E MX25L3208E DATASHEET P/N: PM1614 1 REV. 1.2, NOV. 28, 2013 MX25L3208E Contents FEATURES................................................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 6 PIN CONFIGURATIONS .............................................................................................................................................. 7 PIN DESCRIPTION....................................................................................................................................................... 7 BLOCK DIAGRAM........................................................................................................................................................ 8 MEMORY ORGANIZATION.......................................................................................................................................... 9 Table 1. Memory Organization............................................................................................................................. 9 DEVICE OPERATION................................................................................................................................................. 10 Figure 1. Serial Modes Supported........................................................................................................ 10 DATA PROTECTION................................................................................................................................................... 11 Table 2. Protected Area Sizes............................................................................................................................. 12 HOLD FEATURES...................................................................................................................................................... 13 Figure 2. Hold Condition Operation ......................................................................................................... 13 COMMAND DESCRIPTION........................................................................................................................................ 14 Table 4. COMMAND DEFINITION...................................................................................................................... 14 (1) Write Enable (WREN).................................................................................................................................... 15 (2) Write Disable (WRDI)..................................................................................................................................... 15 (3) Read Status Register (RDSR)....................................................................................................................... 15 (4) Write Status Register (WRSR)....................................................................................................................... 16 Table 5. Protection Modes................................................................................................................................... 17 (5) Read Data Bytes (READ).............................................................................................................................. 18 (6) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 18 (7) Dual Output Mode (DREAD).......................................................................................................................... 18 (8) Sector Erase (SE).......................................................................................................................................... 18 (9) Block Erase (BE)............................................................................................................................................ 19 (10) Chip Erase (CE)........................................................................................................................................... 19 (11) Page Program (PP)...................................................................................................................................... 19 (12) Deep Power-down (DP)............................................................................................................................... 20 (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .............................................. 20 (14) Read Identification (RDID)........................................................................................................................... 21 (15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................... 21 Table 6. ID DEFINITIONS .................................................................................................................................. 21 (16) Enter Secured Area (ENSA)......................................................................................................... 21 (17) Exit Secured Area (EXSA)............................................................................................................ 21 (18) Read Security Register (RDSCUR)............................................................................................................. 22 Table 7. SECURITY REGISTER DEFINITION.................................................................................................... 22 (19) Write Security Register (WRSCUR)............................................................................................................. 22 POWER-ON STATE.................................................................................................................................................... 23 P/N: PM1614 2 REV. 1.2, NOV. 28, 2013 MX25L3208E ELECTRICAL SPECIFICATIONS............................................................................................................................... 24 ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 24 Figure 3.Maximum Negative Overshoot Waveform............................................................................................ 24 CAPACITANCE TA = 25°C, f = 1.0 MHz.............................................................................................................. 24 Figure 4. Maximum Positive Overshoot Waveform............................................................................................. 24 Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................... 25 Figure 6. OUTPUT LOADING............................................................................................................................ 25 Table 8. DC CHARACTERISTICS....................................................................................................................... 26 Table 9. AC CHARACTERISTICS....................................................................................................................... 27 Timing Analysis......................................................................................................................................................... 28 Figure 7. Serial Input Timing............................................................................................................................... 28 Figure 8. Output Timing....................................................................................................................................... 28 Figure 9. Hold Timing.......................................................................................................................................... 29 Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1................................................ 29 Figure 11. Write Enable (WREN) Sequence (Command 06).............................................................................. 30 Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................... 30 Figure 13. Read Status Register (RDSR) Sequence (Command 05)................................................................. 31 Figure 14. Write Status Register (WRSR) Sequence (Command 01)................................................................ 31 Figure 15. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 31 Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B).................................................... 32 Figure 17. Dual Output Read Mode Sequence (Command 3B).......................................................................... 33 Figure 18. Sector Erase (SE) Sequence (Command 20)................................................................................... 33 Figure 19. Block Erase (BE) Sequence (Command 52 or D8)........................................................................... 33 Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 34 Figure 21. Page Program (PP) Sequence (Command 02)................................................................................. 34 Figure 22. Deep Power-down (DP) Sequence (Command B9).......................................................................... 35 Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)................................................ 35 Figure 24. Read Electronic Signature (RES) Sequence (Command AB)........................................................... 35 Figure 25. Read Identification (RDID) Sequence (Command 9F)....................................................................... 36 Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)............................... 36 Figure 27. Program/Erase flow with read array data........................................................................................... 37 Figure 28. Power-up Timing................................................................................................................................ 38 Table 10. Power-Up Timing ................................................................................................................................ 38 OPERATING CONDITIONS........................................................................................................................................ 39 Figure 29. AC Timing at Device Power-Up.......................................................................................................... 39 Figure 30. Power-Down Sequence..................................................................................................................... 40 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 41 DATA RETENTION..................................................................................................................................................... 41 LATCH-UP CHARACTERISTICS............................................................................................................................... 41 P/N: PM1614 3 REV. 1.2, NOV. 28, 2013 MX25L3208E ORDERING INFORMATION....................................................................................................................................... 42 PART NAME DESCRIPTION...................................................................................................................................... 43 PACKAGE INFORMATION......................................................................................................................................... 44 REVISION HISTORY .................................................................................................................................................. 46 P/N: PM1614 4 REV. 1.2, NOV. 28, 2013 MX25L3208E 32M-BIT [x 1 / x 2] CMOS SERIAL FLASH FEATURES GENERAL • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 33,554,432 x 1 bit structure or 16,777,216 x 2 bits (Dual Output mode) structure • 1024 Equal Sectors with 4K byte each - Any Sector can be erased individually •64 Equal Blocks with 64K byte each - Any Block can be erased individually • Program Capability - Byte base - Page base (256 bytes) • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast access time: 86MHz serial clock - Serial clock of Dual Output mode : 80MHz - Fast program time: 0.6ms(typ.) and 3ms(max.)/page - Byte program time: 9us (typical) - Fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block • Low Power Consumption - Low active read current: 25mA(max.) at 86MHz - Low active programming current: 15mA (typ.) - Low active sector erase current: 9mA (typ.) - Standby current: 15uA (typ.) - Deep power-down mode 2uA (typical) • Typical 100,000 erase/program cycles • 20 years of data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP3~BP0 status bit defines the size of the area to be software protection against program and erase instructions - Additional 512 bits secured area for unique ID • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM1614 5 REV. 1.2, NOV. 28, 2013 MX25L3208E • Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES • PACKAGE - 8-pin SOP (200mil) - 8-land WSON (6x5mm) - All devices are RoHS Compliant and Halogen-free GENERAL DESCRIPTION The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output. The device provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. P/N: PM1614 6 REV. 1.2, NOV. 28, 2013 MX25L3208E PIN DESCRIPTION PIN CONFIGURATIONS 8-PIN SOP (200mil) SYMBOL DESCRIPTION CS# CS# SO/SIO1 WP# GND 1 2 3 4 8 7 6 5 Chip Select Serial Data Input (for 1 x I/O)/ Serial Data SI/SIO0 Input & Output (for Dual Output mode) Serial Data Output (for 1 x I/O)/ Serial Data SO/SIO1 Output (for Dual Output mode) SCLK Clock Input WP# Write protection Hold, to pause the device without HOLD# deselecting the device VCC + 3.3V Power Supply GND Ground VCC HOLD# SCLK SI/SIO0 8-LAND WSON (6x5mm) CS# SO/SIO1 WP# GND P/N: PM1614 1 2 3 4 8 7 6 5 VCC HOLD# SCLK SI/SIO0 7 REV. 1.2, NOV. 28, 2013 MX25L3208E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SO/SIO1 CS#, WP#, HOLD# SCLK SRAM Buffer Mode Logic State Machine Sense Amplifier HV Generator Clock Generator Output Buffer P/N: PM1614 8 REV. 1.2, NOV. 28, 2013 MX25L3208E MEMORY ORGANIZATION Table 1. Memory Organization Block 63 62 Sector 1023 : 1008 1007 : 992 Address Range 3FF000h 3FFFFFh : : 3F0000h 3F0FFFh 3EF000h 3EFFFFh : : 3E0000h 3E0FFFh : : : : : : : : 0 15 : 3 2 1 0 00F000h : 003000h 002000h 001000h 000000h 00FFFFh : 003FFFh 002FFFh 001FFFh 000FFFh P/N: PM1614 9 REV. 1.2, NOV. 28, 2013 MX25L3208E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown in "Figure 1. Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, DREAD, RES, and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP, ENSA, EXSA,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1614 10 REV. 1.2, NOV. 28, 2013 MX25L3208E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM): MX25L3208E: use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "protected area sizes". - The Hardware Proteced Mode (HPM) uses WP# to protect the MX25L3208E: BP3-BP0 bits and SRWD bit. P/N: PM1614 11 REV. 1.2, NOV. 28, 2013 MX25L3208E Table 2. Protected Area Sizes BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Status bit BP2 BP1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 32Mb 0 (none) 1 (1block, block 63rd) 2 (2blocks, block 62nd-63rd) 3 (4blocks, block 60th-63rd) 4 (8blocks, block 56nd-63rd) 5 (16blocks, block 48nd-63rd) 6 (32blocks, block 32nd-63rd) 7 (64blocks, all) 8 (64blocks, all) 9 (32blocks, block 0th-31st) 10 (48blocks, block 0th-47th) 11 (56blocks, block 0th-55th) 12 (60blocks, block 0th-59th) 13 (62blocks, block 0th-61st) 14 (63blocks, block 0th-62nd) 15 (64blocks, all) II. Additional 512-bit Secured Area for unique ID: to provide 512-bit read-only unique ID data. Please refer to table 3. 512-bit secured area definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To read the 512-bit secured area by entering 512-bit secured area mode (with ENSA command), and going through normal read procedure, and then exiting 512-bit secured area mode by writing EXSA command. Table 3. 512-bit Secured Area Definition P/N: PM1614 Address range Size xxxx00~xxxx3F 512-bit 12 Standard Factory Lock unique ID REV. 1.2, NOV. 28, 2013 MX25L3208E HOLD FEATURES HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2. Figure 2. Hold Condition Operation CS# SCLK HOLD# Hold Condition (standard) Hold Condition (non-standard) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1614 13 REV. 1.2, NOV. 28, 2013 MX25L3208E COMMAND DESCRIPTION Table 4. COMMAND DEFINITION FAST READ (fast read data) 06 (hex) 04 (hex) 03 (hex) 0B (hex) AD1 AD1 AD2 AD2 AD3 AD3 Dummy to write new outputs to read out n bytes read n bytes read sets the (WEL) resets the write enable (WEL) write values to the JEDEC the values out until CS# out until CS# goes high latch bit enable latch status register ID: 1-byte of the status goes high bit Manufact-urer register ID & 2-byte Device ID Command WREN (write WRDI (write (byte) enable) disable) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action REMS (read Command RES (read electronic (byte) electronic ID) manufacturer & device ID) 1st byte AB (hex) 90 (hex) 2nd byte x x 3rd byte x x 4th byte x ADD (Note 1) 5th byte to read out output the 1-byte Device Manufacturer Action ID ID & Device ID RDSCUR WRSCUR Command (read security (write security (byte) register) register) 1st byte 2B (hex) 2F (hex) 2nd byte 3rd byte 4th byte 5th byte to read value to set the of security lock-down bit register as "1" (once Action lock-down, cannot be updated) WRSR RDID RDSR (write status (read identific- (read status register) ation) register) 01 (hex) 9F (hex) 05 (hex) DREAD (Dual Output Mode command) 3B (hex) AD1 AD2 AD3 Dummy n bytes read out by Dual Output until CS# goes high SE (sector erase) 20 (hex) AD1 AD2 AD3 to erase the selected sector BE (block erase) C1 (hex) CE (chip erase) PP (page program) 52 or D8 (hex) 60 or C7 (hex) AD1 AD2 AD3 to erase the selected block ENSA (enter EXSA (exit DP (Deep secured area) secured area) power down) B1 (hex) READ (read data) B9 (hex) to enter the to exit the 512 enters deep bits secured power down 512 bits mode secured area area mode mode to erase whole chip 02 (hex) AD1 AD2 AD3 to program the selected page RDP (Release from deep power down) AB (hex) release from deep power down mode Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. P/N: PM1614 14 REV. 1.2, NOV. 28, 2013 MX25L3208E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence is shown as Figure 11. (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence is shown as Figure 12. The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence is shown as Figure 13. The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3-BP0) bits, non-volatile bits, indicate the protected area (as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3-BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). P/N: PM1614 15 REV. 1.2, NOV. 28, 2013 MX25L3208E SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3-BP0) are read only. Status Register bit7 bit6 SRWD (status register write protect) 0 bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) 1=status register write disable 0 (note 1) (note 1) (note 1) (note 1) Non-volatile bit 0 Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit note 1: see the table "Protected Area Size". (4) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3-BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence is shown as Figure 14. The WRSR instruction has no effect on b6, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. P/N: PM1614 16 REV. 1.2, NOV. 28, 2013 MX25L3208E Table 5. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP3-BP0 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP3-BP0 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3-BP0) bits of the Status Register, as shown in Table 2. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3-BP0. The protected area, which is defined by BP3-BP0 is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3-BP0. The protected area, which is defined by BP3-BP0 is at software protected mode (SPM) Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3-BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3-BP0. P/N: PM1614 17 REV. 1.2, NOV. 28, 2013 MX25L3208E (5) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence is shown as Figure 15. (6) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence is shown as Figure 16. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (7) Dual Output Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence is shown as Figure 17. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. The DREAD only perform read operation. Program/Erase /Read ID/Read status....operation do not support DREAD throughputs. (8) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 1) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence is shown as Figure 18. P/N: PM1614 18 REV. 1.2, NOV. 28, 2013 MX25L3208E The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3-BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (9) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 1) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 19. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3-BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (10) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 20. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3-BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3-BP0 all set to "0". (11) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence is shown as Figure 21. P/N: PM1614 19 REV. 1.2, NOV. 28, 2013 MX25L3208E The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3-BP0 bits, the Page Program (PP) instruction will not be executed. (12) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence is shown as Figure 22. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 9. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown in Figure 23 and Figure 24. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. P/N: PM1614 20 REV. 1.2, NOV. 28, 2013 MX25L3208E (14) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as table of "ID Definitions". The sequence is shown as Figure 25. While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. (15) Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 26. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table 6. ID DEFINITIONS Command Type RDID Command manufacturer ID C2 RES Command REMS Command manufacturer ID C2 MX25L3208E memory type 20 electronic ID 15 device ID 15 memory density 16 (16) Enter Secured Area (ENSA) The ENSA instruction is for entering the additional 512-bit secured area mode. The additional 512-bit secured area is independent from main array, which is used to store unique ID for system identifier. After entering the Secured Area mode, follow standard read procedure to read out the data. The sequence of issuing ENSA instruction is: CS# goes low→ sending ENSA instruction to enter Secured Area mode→ CS# goes high. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure area region. (17) Exit Secured Area (EXSA) The EXSA instruction is for exiting the additional 512-bit secured area mode. The sequence of issuing EXSA instruction is: CS# goes low→ sending EXSA instruction to exit Secured Area mode→ CS# goes high. P/N: PM1614 21 REV. 1.2, NOV. 28, 2013 MX25L3208E (18) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction → Security Register data out on SO→ CS# goes high. The definition of the Security Register bits is as below: Secured Area Indicator bit. The Secured Area indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. Table 7. SECURITY REGISTER DEFINITION bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x x Secured Area indicator bit reserved reserved reserved reserved reserved reserved reserved volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit 1 = factory lock (default) Non-volatile bit Non-volatile bit (19) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN instruction is not required before sending WRSCUR instruction. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1614 22 REV. 1.2, NOV. 28, 2013 MX25L3208E POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). P/N: PM1614 23 REV. 1.2, NOV. 28, 2013 MX25L3208E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2.Specifications contained within the following tables are subject to change. 3.During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 3 and 4. Figure 3.Maximum Negative Overshoot Waveform 20ns Figure 4. Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol CIN COUT P/N: PM1614 Parameter Input Capacitance Output Capacitance Min. Typ. 24 Max. 6 8 Unit pF pF Conditions VIN = 0V VOUT = 0V REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.2VCC Output timing reference level 0.7VCC AC Measurement Level 0.3VCC 0.5VCC Note: Input pulse rise and fall time are <5ns Figure 6. OUTPUT LOADING DEVICE UNDER TEST 2.7K ohm CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=30pF/15pF Including jig capacitance P/N: PM1614 25 REV. 1.2, NOV. 28, 2013 MX25L3208E Table 8. DC CHARACTERISTICS Symbol Parameter Notes Min. Typ. Max. Units Test Conditions ILI Input Load Current 1 ±2 uA VCC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 ±2 uA VCC = VCC Max, VOUT = VCC or GND ISB1 VCC Standby Current 1 15 40 uA VIN = VCC or GND, CS# = VCC ISB2 Deep Power-down Current 2 20 uA VIN = VCC or GND, CS# = VCC 25 mA f=86MHz fT=80MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 20 mA f=66MHz, SCLK=0.1VCC/0.9VCC, SO=Open 10 mA f=33MHz, SCLK=0.1VCC/0.9VCC, SO=Open 15 20 mA 3 20 mA 1 9 20 mA Erase in Progress, CS#=VCC 1 15 20 mA Erase in Progress, CS#=VCC -0.5 0.3VCC V 0.7VCC VCC+0.4 V 0.4 V IOL = 1.6mA V IOH = -100uA ICC1 VCC Read VIL VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 ICC3 ICC4 ICC5 1 1 VCC-0.2 Program in Progress, CS# = VCC Program status register in progress, CS#=VCC Notes : 1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds). 2. Not 100% tested. P/N: PM1614 26 REV. 1.2, NOV. 28, 2013 MX25L3208E Table 9. AC CHARACTERISTICS Symbol fSCLK fRSCLK fTSCLK Alt. Parameter Clock Frequency for the following instructions: fC FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR fR Clock Frequency for READ instructions fT Clock Frequency for DREAD instructions tCH(1) tCLH Clock High Time tCL(1) tCLL Clock Low Time tCLCH(2) Clock Rise Time (3) (peak to peak) tCHCL(2) Clock Fall Time (3) (peak to peak) tSLCH tCSS CS# Active Setup Time (relative to SCLK) tCHSL CS# Not Active Hold Time (relative to SCLK) tDVCH tDSU Data In Setup Time tCHDX tDH Data In Hold Time tCHSH CS# Active Hold Time (relative to SCLK) tSHCH CS# Not Active Setup Time (relative to SCLK) tSHSL tCSH CS# Deselect Time Min. fC=86MHz fR=33MHz fC=86MHz fR=33MHz Read Write tSHQZ(2) tDIS Output Disable Time tCLQV tV Clock Low to Output Valid tCLQX tHO Output Hold Time tHLCH HOLD# Setup Time (relative to SCLK) tCHHH HOLD# Hold Time (relative to SCLK) tHHCH HOLD Setup Time (relative to SCLK) tCHHL HOLD Hold Time (relative to SCLK) tHHQX(2) tLZ HOLD to Output Low-Z tHLQZ(2) tHZ HOLD# to Output High-Z tWHSL(4) Write Protect Setup Time tSHWL (4) Write Protect Hold Time tDP(2) CS# High to Deep Power-down Mode tRES1(2) CS# High to Standby Mode without Electronic Signature Read tRES2(2) CS# High to Standby Mode with Electronic Signature Read tW Write Status Register Cycle Time tBP Byte-Program tPP Page Program Cycle Time tSE Sector Erase Cycle Time tBE Block Erase Cycle Time tCE Chip Erase Cycle Time tRPD1 CS# High to Power-Down Typ. Max. Unit DC 86 MHz DC DC 5.5 13 5.5 13 0.1 0.1 7 7 2 5 7 7 15 40 33 80 MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us us us ms us ms ms s s ns 8 8 0 5 5 5 5 8 8 20 100 100 10 8.8 8.8 40 50 3 200 2 40 5 9 0.6 40 0.4 12.5 Notes: 1. tCH + tCL must be greater than or equal to 1/ f (fC or fR). For Fast Read, tCL/tCH=5.5/5.5. 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as "Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL". P/N: PM1614 27 REV. 1.2, NOV. 28, 2013 MX25L3208E Timing Analysis Figure 7. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 8. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI P/N: PM1614 tSHQZ ADDR.LSB IN 28 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 9. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# * SI is "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI SO P/N: PM1614 High-Z 29 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 11. Write Enable (WREN) Sequence (Command 06) CS# 1 0 2 3 4 5 6 7 SCLK Command SI 06 High-Z SO Figure 12. Write Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO P/N: PM1614 04 High-Z 30 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 13. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI Status Register Out High-Z SO 7 6 5 4 3 2 Status Register Out 1 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 14. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI Status Register In 01 7 5 4 3 2 0 1 MSB High-Z SO 6 Figure 15. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command SI 03 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1614 31 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1614 4 32 6 5 4 3 2 1 0 7 MSB REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 17. Dual Output Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 9 10 11 39 40 41 42 43 30 31 32 SCLK 8 Bit Instruction SO/SO1 address bit23, bit22, bit21...bit0 3B(hex) SI/SO0 8 dummy cycle 24 BIT Address dummy High Impedance Data Output data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... Figure 18. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20 2 1 0 MSB Note: SE command is 20(hex). Figure 19. Block Erase (BE) Sequence (Command 52 or D8) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 52 or D8 2 1 0 MSB Note: BE command is 52 or D8(hex). P/N: PM1614 33 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 20. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Note: CE command is 60(hex) or C7(hex). Figure 21. Page Program (PP) Sequence (Command 02) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02 SI Data Byte 1 2076 24-Bit Address 2075 Command 4 1 0 MSB MSB 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CS# SCLK Data Byte 2 SI 7 6 MSB P/N: PM1614 5 4 3 2 Data Byte 3 1 0 7 6 5 4 MSB 3 2 Data Byte 256 1 0 7 6 5 4 3 2 MSB 34 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 22. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Deep Power-down Mode Stand-by Mode Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI AB High-Z SO Deep Power-down Mode Stand-by Mode Figure 24. Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI AB tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM1614 35 Stand-by Mode REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 25. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification High-Z SO 7 6 5 3 2 1 MSB Device Identification 0 15 14 13 3 2 1 0 MSB Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI 2 Dummy Bytes 15 14 13 90 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. P/N: PM1614 36 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 27. Program/Erase flow with read array data start WREN command RDSR command WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0 Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase fail Program/erase successfully Program/erase another block? Yes No Program/erase completed P/N: PM1614 37 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 28. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) Device is fully accessible tVSL time Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Table 10. Power-Up Timing Symbol Parameter Min. tVSL(1) VCC(min) to CS# low 200 Max. Unit us Note: 1. The parameter is characterized only. P/N: PM1614 38 REV. 1.2, NOV. 28, 2013 MX25L3208E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in "Figure 29. AC Timing at Device Power-Up" and "Figure 30. Power-Down Sequence" are the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power down, CS# need to follow the voltage applied on VCC to keep the device not be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 29. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX tCLCH LSB IN MSB IN SI High Impedance SO Symbol Parameter tVR VCC Rise Time Notes Min. Max. Unit 1 20 500000 us/V Notes : 1.Sampled, not 100% tested. 2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 9. AC CHARACTERISTICS". P/N: PM1614 39 REV. 1.2, NOV. 28, 2013 MX25L3208E Figure 30. Power-Down Sequence During power down, CS# need to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1614 40 REV. 1.2, NOV. 28, 2013 MX25L3208E ERASE AND PROGRAMMING PERFORMANCE PARAMETER Min. TYP. (1) Max. (2) UNIT Write Status Register Time 5 40 ms Sector Erase Time 40 200 ms Block Erase Time 0.4 2 s Chip Erase Time 12.5 40 s 9 50 us 0.6 3 ms Byte Program Time (via page program command) Page Program Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. Erase/Program cycles comply with JEDEC: JESD-47 & JESD22-A117 standard. DATA RETENTION PARAMETER Condition Min. Data retention 55˚C 20 Max. UNIT years LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1614 41 REV. 1.2, NOV. 28, 2013 MX25L3208E ORDERING INFORMATION CLOCK (MHz) Temperature MX25L3208EM2I-12G 86 -40°C~85°C MX25L3208EZNI-12G 86 -40°C~85°C PART NO. P/N: PM1614 42 PACKAGE Remark 8-SOP (200mil) 8-WSON (6x5mm) RoHS Compliant RoHS Compliant REV. 1.2, NOV. 28, 2013 MX25L3208E PART NAME DESCRIPTION MX 25 L 3208E M2 I 12 G OPTION: G: RoHS Compliant and Halogen-free SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M2: 200mil 8-SOP ZN: 6x5mm 8-WSON DENSITY & MODE: 3208E: 32Mb TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1614 43 REV. 1.2, NOV. 28, 2013 MX25L3208E PACKAGE INFORMATION P/N: PM1614 44 REV. 1.2, NOV. 28, 2013 MX25L3208E P/N: PM1614 45 REV. 1.2, NOV. 28, 2013 MX25L3208E REVISION HISTORY Revision No. Description 1.1 1. Added 6x5mm 8-WSON package solution 1.2 1. Updated parameters for DC Characteristics. 2. Updated Erase and Programming Performance. P/N: PM1614 46 Page Date P6,7,42,43, JUN/14/2012 P45 P5,26 NOV/28/2013 P5,27,41 REV. 1.2, NOV. 28, 2013 MX25L3208E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2010~2013. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 47