MX29LV040C 4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY EQUAL SECTOR FLASH MEMORY FEATURES • • • • • • • • • • • • • • • Extended single - supply voltage range 2.7V to 3.6V 524,288 x 8 only Single power supply operation - 3.0V only operation for read, erase and program operation Fully compatible with MX29LV040 device Fast access time: 55Q/70/90ns Low power consumption - 30mA maximum active current - 0.2uA typical standby current Command register architecture - 8 equal sector of 64K-Byte each - Byte Programming (9us typical) - Sector Erase (Sector structure 64K-Byte x8) Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability - Automatically program and verify data at specified address Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase Status Reply - Data# Polling & Toggle bit for detection of program and erase operation completion Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Any combination of sectors can be erased with erase suspend/resume function CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access 100,000 minimum erase/program cycles Latch-up protected to 100mA from -1V to VCC+1V Package type: - 32-pin PLCC - 32-pin TSOP (8mmx20mm, 8mmx14mm) - All devices are RoHS Compliant P/N:PM1149 REV. 2.6, APR. 11, 2012 1 MX29LV040C PIN CONFIGURATIONS 32 TSOP (Standard Type) (8mm x 20mm) A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MX29LV040C 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 MX29LV040C 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 1 32 PIN DESCRIPTION A17 A16 4 VCC 5 A18 A7 A15 A12 32 PLCC WE# 32 TSOP (8mm x 14mm) 30 29 A6 A13 A5 A8 A4 A3 A9 9 MX29LV040C 25 A11 A2 OE# A1 A10 A0 CE# 21 20 Q5 Q4 Q3 GND Q2 17 PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Output Enable Input Ground Pin +3.0V single power supply Q7 Q6 13 14 Q1 Q0 SYMBOL A0~A18 Q0~Q7 CE# WE# OE# GND VCC A14 P/N:PM1149 REV. 2.6, APR. 11, 2012 2 MX29LV040C BLOCK DIAGRAM CE# OE# WE# CONTROL INPUT LOGIC A0-A18 LATCH BUFFER Y-DECODER AND HIGH VOLTAGE X-DECODER ADDRESS PROGRAM/ERASE WRITE STATE MACHINE (WSM) STATE FLASH ARRAY Y-PASS GATE SENSE AMPLIFIER PGM DATA HV REGISTER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER P/N:PM1149 REV. 2.6, APR. 11, 2012 3 MX29LV040C Table 1. SECTOR (GROUP) STRUCTURE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 A18 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh Note:All sectors are 64 Kbytes in size. P/N:PM1149 REV. 2.6, APR. 11, 2012 4 MX29LV040C Table 2-1. BUS OPERATION Operation Read Mode Write Standby Mode Output Disable CE# L L Vcc±0.3V L OE# L H X H WE# H L X H Address AIN AIN X X Q7~Q0 DOUT DIN High-Z High-Z Table 2-2. BUS OPERATION Operation Read Silicon ID Manufactures Code Read Silicon ID Device Code Sector Protect Chip Unprotected Sector Protect Verify CE# OE# WE# A0 A1 A6 A9 Q7~Q0 L L H L L X Vhv C2H L L H H L X Vhv 4FH L L L Vhv Vhv L L L H X X X X X H L H X Vhv Vhv Vhv X X Code(1) Notes: 1. Sector unprotected code:00h. Sector protected code:01h. 2. AM: MSB of address. 3. Sector addresses: A18~A16. 4. Vhv is 11.5V to 12.5V. 5. X means don't care. P/N:PM1149 REV. 2.6, APR. 11, 2012 5 MX29LV040C WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a period of time no more than Tready1 and the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode or CFI mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. P/N:PM1149 REV. 2.6, APR. 11, 2012 6 MX29LV040C SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on that protected sector. MX29LV040C provides a methods for sector protection. The method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. CHIP UNPROTECT OPERATION MX29LV040C provides one methods for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sector groups are unprotected when shipped from the factory. The method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. AUTOMATIC SELECT OPERATION When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. VERIFY SECTOR PROTECT STATUS OPERATION MX29LV040C provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A16 to A18 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is not protected. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. P/N:PM1149 REV. 2.6, APR. 11, 2012 7 MX29LV040C LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than 1.4V. This prevents data from spuriously altered. The device automatically resets itself when Vcc is lower than 1.4V and write cycles are ignored until Vcc is greater than 1.4V. System must provide proper signals on control pins after Vcc is larger than 1.4V to avoid unintentional program or erase operation WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29LV040C is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1149 REV. 2.6, APR. 11, 2012 8 MX29LV040C TABLE 3. MX29LV040C COMMAND DEFINITIONS Command 1st Bus Cyc 2nd Bus Cyc 3rd Bus Cyc Addr Data Addr Data Addr Data 4th Bus Addr Cyc Data 5th Bus Addr Cyc Data 6th Bus Addr Cyc Data Read Mode Reset Mode Addr Data XXX F0 Automatic Select Sector Program Silicon Device Protect ID ID Verify 555 555 555 555 AA AA AA AA 2AA 2AA 2AA 2AA 55 55 55 55 555 555 555 555 90 90 90 A0 (Sector) X00 X01 Addr X02 C2 4F 00/01 Data Chip Erase Sector Erase Erase CFI Read Erase Suspend Resume 555 AA 2AA 55 555 80 555 AA 2AA 55 555 80 555 555 AA 2AA 55 555 10 AA 2AA 55 Sector 30 AA 98 XXX B0 XXX 30 Notes: 1. It is not allowed to adopt any other code which is not in the above command definition table. P/N:PM1149 REV. 2.6, APR. 11, 2012 9 MX29LV040C RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify • CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. P/N:PM1149 REV. 2.6, APR. 11, 2012 10 MX29LV040C AUTOMATIC PROGRAMMING The MX29LV040C can provide the user program function by the form of Byte-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device requires the user to write the program command and data only. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready1. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. The typical chip program time at room temperature of the MX29LV040C is less than 4.5 seconds. When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress*1 Finished Exceed time limit Q7 Q7# Q7 Q7# Q6 Toggling Stop toggling Toggling Q5 0 0 1 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector. P/N:PM1149 REV. 2.6, APR. 11, 2012 11 MX29LV040C CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress Finished Exceed time limit Q7 0 1 0 Q6 Toggling Stop toggling Toggling Q5 0 0 1 Q2 Toggling 1 Toggling SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Time-out period In progress Finished Exceed time limit Q7 0 0 1 0 Q6 Toggling Toggling Stop toggling Toggling Q5 0 0 0 1 Q3 0 1 1 1 Q2 Toggling Toggling 1 Toggling *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. P/N:PM1149 REV. 2.6, APR. 11, 2012 12 MX29LV040C SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1 (<=20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2 to judge the sector is erasing or the erase is suspended. Status Erase suspend read in erase suspended sector Erase suspend read in non-erase suspended sector Erase suspend program in non-erase suspended sector Q7 1 Data Q7# Q6 No toggle Data Toggle Q5 0 Data 0 Q3 N/A Data N/A Q2 Toggle Data N/A When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume. SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 400uS interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. P/N:PM1149 REV. 2.6, APR. 11, 2012 13 MX29LV040C QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LV040C features CFI mode. Host system can retrieve the operating characteristics, structure and vendorspecified information such as identifying information, memory size, byte configuration, operating voltages and timing information of this device by CFI mode. If the system writes the CFI Query command "98h", to address "55h"/"AAh", the device will enter the CFI Query Mode, any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 4. Once user enters CFI query mode, user can not issue any other commands except reset command. The reset command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for alternate algorithm extended query table (none) Address (h) (Byte Mode) 10 11 12 13 14 15 16 17 18 19 1A Data (h) 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Table 4-2. CFI Mode: System Interface Data Values Description Vcc supply minimum program/erase voltage Vcc supply maximum program/erase voltage VPP supply minimum program/erase voltage VPP supply maximum program/erase voltage Typical timeout per single word/byte write, 2n us Typical timeout for maximum-size buffer write, 2n us Typical timeout per individual block erase, 2n ms Typical timeout for full chip erase, 2n ms Maximum timeout for word/byte write, 2n times typical Maximum timeout for buffer write, 2n times typical Maximum timeout per individual block erase, 2n times typical Maximum timeout for chip erase, 2n times typical P/N:PM1149 Address (h) (Byte Mode) 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Data (h) 0027 0036 0000 0000 0004 0000 000A 0000 0005 0000 0004 0000 REV. 2.6, APR. 11, 2012 14 MX29LV040C Table 4-3. CFI Mode: Device Geometry Data Values Description n Device size = 2 in number of bytes Flash device interface description (02=asynchronous x8/x16) Maximum number of bytes in buffer write = 2n (not support) Number of erase regions within device Index for Erase Bank Area 1 Index for Erase Bank Area 2 Index for Erase Bank Area 3 Index for Erase Bank Area 4 P/N:PM1149 Address (h) (Byte Mode) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C Data (h) 0013 0000 0000 0000 0000 0001 0007 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 REV. 2.6, APR. 11, 2012 15 MX29LV040C Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Query - Primary extended table, unique ASCII string, PRI Major version number, ASCII Minor version number, ASCII Unlock recognizes address (0= recognize, 1= don't recognize) Erase suspend (2= to both read and program) Sector protect (N= # of sectors/group) Temporary sector unprotect (1=supported) Sector protect/Chip unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode (0=not supported) Page mode (0=not supported) P/N:PM1149 Address (h) (Byte Mode) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C Data (h) 0050 0052 0049 0031 0030 0001 0002 0001 0001 0004 0000 0000 0000 REV. 2.6, APR. 11, 2012 16 MX29LV040C ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias Storage Temperature -65°C to +125°C -65°C to +150°C -0.5V to +4.0 V VCC Voltage Range A9 and OE# The other pins Output Short Circuit Current (less than one second) -0.5 V to +12.5 V -0.5V to Vcc +0.5V 200 mA OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ) 0°C to +70°C Industrial (I) Grade Surrounding Temperature (TA ) -40°C to +85°C VCC Supply Voltages VCC range +2.7 V to 3.6 V P/N:PM1149 REV. 2.6, APR. 11, 2012 17 MX29LV040C DC CHARACTERISTICS Symbol Iilk Iilk9 Iolk Icr1 Icr2 Description Input Leak A9 Leak Output Leak Read Current(5MHz) Read Current(1MHz) Min. Typ. 7mA 2mA Max. ± 1.0uA 35uA ± 1.0uA 12mA 4mA Icw Write Current 15mA 30mA Isb Standby Current 0.2uA 5uA Isbs Vil Vih Sleep Mode Current Input Low Voltage Input High Voltage Very High Voltage for hardware Protect/Unprotect/Auto Select Output Low Voltage Ouput High Voltage Ouput High Voltage 0.2uA -0.5V 0.7xVcc 5uA 0.8V Vcc+0.3V 11.5V 12.5V Vhv Vol Voh1 Voh2 0.45V 0.85xVcc Vcc-0.4V P/N:PM1149 Remark A9=12.5V CE#=Vil, OE#=Vih CE#=Vil, OE#=Vih CE#=Vil, OE#=Vih, WE#=Vil Vcc=Vcc max, other pin disable Iol=4.0mA Ioh1=-2mA Ioh2=-100uA REV. 2.6, APR. 11, 2012 18 MX29LV040C SWITCHING TEST CIRCUITS Vcc 0.1uF R2 TESTED DEVICE CL R1 +3.3V DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=2.7K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30pF(70ns)/100pF(90ns) Rise/Fall Times : 5ns In/Out reference levels :1.5V SWITCHING TEST WAVEFORMS 3.0V 1.5V 1.5V Test Points 0.0V INPUT OUTPUT P/N:PM1149 REV. 2.6, APR. 11, 2012 19 MX29LV040C AC CHARACTERISTICS Symbol Taa Tce Toe Tdf Toh Trc Twc Tcwc Tas Tah Tds Tdh Tvcs Tcs Tch Toes Toeh Tws Twh Tcep Tceph Twp Twph Tghwl Tghel Twhwh1 Twhwh2 Tbal Description Valid data output after address Valid data output after CE# low Valid data output after OE# low Data output floating after OE# high or CE# high Output hold time from the earliest rising edge of address, CE#, OE# Read period time Write period time Command write period time Address setup time Address hold time Data setup time Data hold time Vcc setup time Chip enable Setup time Chip enable hold time Output enable setup time Read Output enable hold time Toggle & Data# Polling WE# setup time WE# hold time CE# pulse width CE# pulse width high WE# pulse width WE# pulse width high Read recover time before write Read recover time before write Program operation Sector erase operation Sector add hold time P/N:PM1149 Min. Typ. Max. 55/70/90 55/70/90 30/30/35 25/25/30 Unit ns ns ns ns 0 ns 55/70/90 70/90 70/90 0 45 35/45 0 50 0 0 0 0 10 0 0 35 30 35 30 0 0 ns ns ns ns ns ns ns us ns ns ns ns ns ns ns ns ns ns ns ns ns us sec us 9 0.7 50 REV. 2.6, APR. 11, 2012 20 MX29LV040C Figure 1. COMMAND WRITE OPERATION Tcwc CE# Vih Vil Tch Tce WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Data Vih Vil DIN VA: Valid Address P/N:PM1149 REV. 2.6, APR. 11, 2012 21 MX29LV040C READ OPERATION Figure 2. READ TIMING WAVEFORMS CE# Tce Vih Vil Vih WE# OE# Vil Toeh Tdf Toe Vih Vil Toh Taa Trc Vih Addresses Outputs ADD Valid Vil Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1149 REV. 2.6, APR. 11, 2012 22 MX29LV040C ERASE/PROGRAM OPERATION Figure 3. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address 555h 2AAh Tds Data Read Status Tah Tas VA Tdh 55h VA In Progress Complete 10h P/N:PM1149 REV. 2.6, APR. 11, 2012 23 MX29LV040C Figure 4. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1149 REV. 2.6, APR. 11, 2012 24 MX29LV040C Figure 5. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Data Tdh 55h Sector Address 1 Sector Address n Tah 30h VA VA In Progress Complete 30h P/N:PM1149 30h REV. 2.6, APR. 11, 2012 25 MX29LV040C Figure 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data Address 555H Write Data Address 2AAH Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1149 REV. 2.6, APR. 11, 2012 26 MX29LV040C Figure 7. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H Toggle Bit checking Q6 NO ERASE SUSPEND not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1149 REV. 2.6, APR. 11, 2012 27 MX29LV040C Figure 8. AUTOMATIC PROGRAM TIMING WAVEFORMS CE# Tch Twhwh1 Twp WE# Tcs Twph Tghwl OE# Last 2 Program Command Cycle Address 555h VA PA Tds Data Last 2 Read Status Cycle Tah Tas VA Tdh A0h PD P/N:PM1149 Status DOUT REV. 2.6, APR. 11, 2012 28 MX29LV040C Figure 9. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Tws Tcep Twh CE# Twhwh1 or Twhwh2 Tceph Tghwl OE# Tah Tas Address 555h Tds Data VA PA VA Tdh A0h PD P/N:PM1149 Status DOUT REV. 2.6, APR. 11, 2012 29 MX29LV040C Figure 10. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Byte to be Programed YES Auto Program Completed P/N:PM1149 REV. 2.6, APR. 11, 2012 30 MX29LV040C SECTOR PROTECT/CHIP UNPROTECT Figure 11. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM 150us: Sector Protect 15ms: Chip Unprotect 1us CE# WE# OE# Verification Data SA, A6 A1, A0 60h 60h 40h VA VA Status VA VA: valid address P/N:PM1149 REV. 2.6, APR. 11, 2012 31 MX29LV040C Figure 12. SILICON ID READ TIMING WAVEFORM CE# Vih Vil Tce Vih WE# Vil Toe Vih OE# Tdf Vil Toh Toh Vhv Vih A9 A0 Vil Vih Vil Taa A1 Taa Vih Vil ADD DATA Q7~Q0 Vih Vil Vih Vil DATA OUT DATA OUT C2H 4FH P/N:PM1149 REV. 2.6, APR. 11, 2012 32 MX29LV040C WRITE OPERATION STATUS Figure 13. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Q6~Q0 Complement Complement True Valid Data Status Data Status Data True Valid Data P/N:PM1149 High Z High Z REV. 2.6, APR. 11, 2012 33 MX29LV040C Figure 14. DATA# POLLING ALGORITHM Start Read Q7~Q0 at valid address (Note 1) Q7 = Data# ? No Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address Q7 = Data# ? (Note 2) No Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1149 REV. 2.6, APR. 11, 2012 34 MX29LV040C Figure 15. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data VA : Valid Address P/N:PM1149 REV. 2.6, APR. 11, 2012 35 MX29LV040C Figure 16. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Twice (Note 1) NO Q6 Toggle ? YES NO Q5 = 1? YES Read Q7~Q0 Twice NO Q6 Toggle ? YES PGM/ERS fail Write Reset CMD PGM/ERS Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1149 REV. 2.6, APR. 11, 2012 36 MX29LV040C RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device powerup. If the timing in the figure is ignored, the device may not operate correctly. Vcc Vcc(min) GND Tvr Tvcs Tf CE# WE# Tce Vil Vih Vil Tf OE# Tr Vil Taa Vih Tr or Tf Valid Address Vil Voh DATA Toe Vih Tr or Tf ADDRESS Tr Vih High Z Valid Ouput Vol Figure A. AC Timing at Device Power-Up Symbol Tvr Tr Tf Parameter Vcc Rise Time Input Signal Rise Time Input Signal Fall Time Min. 20 Max. 500000 20 20 Unit us/V us/V us/V Note: Not tested 100%. P/N:PM1149 REV. 2.6, APR. 11, 2012 37 MX29LV040C ERASE AND PROGRAMMING PERFORMANCE Parameter Min. Chip Erase Time Sector Erase Time Erase/Program Cycles Chip Programming Time Byte Programming Time 100,000 Limits Typ. 4 0.7 Max. 32 8 4.5 9 13.5 300 Units sec sec Cycles sec us DATA RETENTION Parameter Condition Min. Data retention 55˚C 20 Max. Unit years LATCH-UP CHARACTERISTICS Input Voltage difference with GND on A9, OE# pins Input Voltage difference with GND on all I/O pins Input current pulse All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing Min. -1.0V -1.0V -100mA Max. 12.5V Vcc + 1.0V +100mA PIN CAPACITANCE Parameter Symbol CIN2 COUT CIN Parameter Description Control Pin Capacitance Output Capacitance Input Capacitance Test Set VIN=0 VOUT=0 VIN=0 P/N:PM1149 Max. 12 12 8 Unit pF pF pF REV. 2.6, APR. 11, 2012 38 MX29LV040C ORDERING INFORMATION ACCESS TIME (ns) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (uA) MX29LV040CTC-55Q 55 30 5 MX29LV040CTC-70G 70 30 5 MX29LV040CTC-90G 90 30 5 MX29LV040CQC-55Q MX29LV040CQC-70G MX29LV040CQC-90G 55 70 90 30 30 30 5 5 5 MX29LV040CTI-55Q 55 30 5 MX29LV040CTI-70G 70 30 5 MX29LV040CTI-90G 90 30 5 MX29LV040CQI-55Q MX29LV040CQI-70G MX29LV040CQI-90G 55 70 90 30 30 30 5 5 5 MX29LV040CT2I-70G 70 30 5 MX29LV040CT2I-90G 90 30 5 PART NO. P/N:PM1149 PACKAGE Remark 32 Pin TSOP (8x20 mm) 32 Pin TSOP (8x20 mm) 32 Pin TSOP (8x20 mm) 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin TSOP (8x20 mm) 32 Pin TSOP (8x20 mm) 32 Pin TSOP (8x20 mm) 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin TSOP (8x14 mm) 32 Pin TSOP (8x14 mm) REV. 2.6, APR. 11, 2012 39 MX29LV040C PART NAME DESCRIPTION MX 29 LV 040 C T C 70 G OPTION: G: RoHS compliant package Q: Restricted VCC (3.0V~3.6V) with RoHS compliant package SPEED: 55: 55ns 70: 70ns 90: 90ns TEMPERATURE RANGE: C: Commercial (0°C to 70°C) I: Industrial (-40°C to 85°C) PACKAGE: Q: PLCC T: TSOP (8mm x 20mm) T2: TSOP (8mm x 14mm) REVISION: C DENSITY & MODE: 040: 4M, x8 Equal Sector TYPE: L, LV: 3V DEVICE: 29:Flash P/N:PM1149 REV. 2.6, APR. 11, 2012 40 MX29LV040C PACKAGE INFORMATION P/N:PM1149 REV. 2.6, APR. 11, 2012 41 MX29LV040C P/N:PM1149 REV. 2.6, APR. 11, 2012 42 MX29LV040C P/N:PM1149 REV. 2.6, APR. 11, 2012 43 MX29LV040C REVISION HISTORY Revision No. Description Page 1.0 1. Removed "Preliminary" P1 2. Added "Recommended Operating Conditions" P43 1.1 1. Modified "Low power consumption--active current" from 20mA(Max.)P1 to 30mA(Max.) 2. Added description about Pb-free devices are RoHS Compliant P1 1.2 1. Modified Erase Resume from delay 10ms to delay 400us P12,32 1.3 1. Modified table 15. CFI mode P45,46 2. Added VLKO description P15,18 1.4 1. Modified CFI mode P45,46 1.5 1. Datasheet format changed All 1.6 1. Data modification All 1.7 1. Data modification All 1.8 1. Added statement P44 1.9 1. Revised statement P14 2.0 1. Added note 1 into table 3. Command Definitions P9 2.1 1. Modified Figure 9. CE# Controlled Write Timing Waveform P29 2.2 1. Revised Twc, Tcwc, Tds AC timing spec P20 2.3 1. Added 32-TSOP (8mm x 14mm) package information P1,2,39 P40,43 2.4 1. Added data retention table P38 2. Modified the sector erase time max from 15s to 8s P38 3. Deleted Lead EPN P39,40 2.5 1. Modified description for RoHS compliance P1,40 2. Added note P37 2.6 1. Modified Part Name Description P40 2. Modified Figure 9. CE# Controlled Write Timing Waveform P29 P/N:PM1149 Date JUN/30/2005 AUG/30/2005 JAN/17/2006 APR/24/2006 JUL/11/2006 AUG/15/2006 AUG/16/2006 AUG/17/2006 NOV/06/2006 DEC/28/2007 JAN/17/2008 FEB/21/2008 JUL/31/2008 MAR/25/2009 AUG/21/2009 DEC/15/2011 APR/11/2012 REV. 2.6, APR. 11, 2012 44 MX29LV040C Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2006~2012. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 45