IRDC3899-P3V3 SupIRBuck TM USER GUIDE FOR IR3899 EVALUATION BOARD 3.3Vout DESCRIPTION The IR3899 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 4mm X 5 mm Power QFN package. Key features offered by the IR3899 include internal Digital Soft Start/Soft Stop, precision 0.5Vreference voltage, Power Good, thermal protection, programmable switching frequency, Enable input, input under-voltage lockout for proper start-up, enhanced line/ load regulation with feed forward, external frequency synchronization with smooth clocking, internal LDO and pre-bias startup. Pulse by pulse current limit and output overcurrent protection function is implemented by sensing the voltage developed across the onresistance of the synchronous rectifier MOSFET for optimum cost and performance and the current limit is thermally compensated. This user guide contains the schematic and bill of materials for the IR3899 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3899 is available in the IR3899 data sheet. BOARD FEATURES • Vin = +12V (+ 13.2V Max) • Vout = +3.3V @ 0-9A • Fs = 1MHz • L = 0.68uH • Cin = 4x10uF (ceramic 1206) + 1X330uF (electrolytic) • Cout = 4x22uF (ceramic 0805) 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 1 IRDC3899-P3V3 CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum of 9A load should be connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I. IR3899 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vcc is required, then R15 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin and Vcc/LDOout pins should be shorted together for external Vcc operation. The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero ohm resistor for R21). The value of R14 and R28 can be selected to provide the desired tracking ratio between output voltage and the tracking input. Table I. Connections Connection Signal Name VIN+ Vin (+12V) VIN- Ground of Vin Vout+ Vout(+3.3V) Vout- Ground for Vout Vcc+ Vcc/ LDO_out Pin Vcc- Ground for Vcc input Enable Enable P_Good Power Good Signal AGnd Analog ground LAYOUT The PCB is a 4-layer board (2.23”x2”) using FR4 material. All layers use 2 Oz. copper. The PCB thickness is 0.062”. The IR3899 and other major power components are mounted on the top side of the board. Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located close to IR3899. The feedback resistors are connected to the output at the point of regulation and are located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 2 IRDC3899-P3V3 Connection Diagram Vin Gnd Gnd Vout Enable VDDQ Top View Vref Sync S-Ctrl AGnd PGood Vsns Vcc+ Vcc- Bottom View Fig. 1: Connection Diagram of IR3899/98/97 Evaluation Boards 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 3 IRDC3899-P3V3 Fig. 2: Board Layout-Top Layer Single point connection between AGnd and PGnd Fig. 3: Board Layout-Bottom Layer 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 4 IRDC3899-P3V3 Fig. 4: Board Layout-Mid Layer 1 Fig. 5: Board Layout-Mid Layer 2 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 5 Vcc- 49.9K R17 Vcc+ N/S C10 N/A VCC R14 0 ohm VDDQ R28 PGood 1 R1 SYNC 1.82K 23.2K R9 100pF 6.8nF C26 180pF C11 1 C12 S_Ctrl R13 0 ohm C23 2.2uF VCC S_Ctrl Vp Rt_Sy nc Gnd COMP C32 1.0uF IR3899 R4 R3 787 N38703 Vsns N/S C25 2200pF A R15 R6 787 R12 B 4.42K R11 0 ohm R50 0.68uH L1 0 ohm 20 ohm C7 0.1uF 0.1uF C24 N/S R29 VCC PGND C8 11 12 13 4.42K R2 75 ohm N/A R7 PGnd SW PVin 0 ohm R10 49.9K R18 N/S N/S + C35 N/S C29 C30 + C36 N/S N/S C28 Fig. 6: Schematic of the IR3899 evaluation board 6 16 5 4 3 1 FB N/S 9.09K U1 C37 R19 2 VREF 1 15 Enable R21 N/S 1 Boot 1 1 1 9 Vin PGood 7 Vcc/LDO_OUT 10 14 Vsns 8 GND 17 VREF 1 Agnd 1 1 1 1 8/8/2013 1 Enable N/S C27 C20 N/S N/S C19 C5 10uF C6 N/A C4 22uF C18 10uF C3 22uF C17 10uF 22uF C16 22uF C15 1 Vin- Vin+ 1 C14 0.1uF 1 Vout- Vout+ (3.3V) Vout C2 C1 + 10uF 330uF/25V 1 IRDC3899-P3V3 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 6 IRDC3899-P3V3 Bill of Materials BOM IRDC3899 Vin-12V Vout-3.3V/9.0A Freq-1MHz Item Qty Part Reference Value 1 1 C1 330uF 2 4 C2 C3 C4 C5 10uF 3 4 C7 C12 C14 C24 0.1uF 4 1 C8 2200pF 5 1 C11 180pF 6 4 C15 C16 C17 C18 22uF 7 1 C23 2.2uF 8 1 C26 6.8nF 9 1 C32 1.0uF 10 1 L1 0.68uH 11 1 R1 1.82K 12 2 R2 R11 4.42K 13 2 R3 R12 787 14 1 R4 75 15 1 R6 20 16 1 R9 23.2K 17 5 R10 R13 R14 R15 R50 0 18 2 R17 R18 49.9K 19 1 R19 9.09K 20 1 U1 IR3899 8/8/2013 Description Manufacturer SMD Electrolytic F size 25V 20% Panasonic 1206, 16V, X5R, 20% Part Number EEV-FK1E331P TDK C3216X5R1C106M 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B 0603,50V,X7R Murata GRM188R71H222KA01B 0603, 50V, NP0, 5% Murata GRM1885C1H181JA01D TDK C2012X5R0J226M TDK C1608X5R1C225M Murata GRM188R71E682KA01J Murata GRM188R61E105KA12D 0805, 6.3V, X5R, 20% 0603, 16V, X5R, 20% 0603, 25V, X7R, 10% 0603, 25V, X5R, 10% SMD 7.1x6.5x5mm,0.39mΩ Cyntec Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% PQFN 4x5mm PIMB065T-R68 Panasonic ERJ-3EKF1821V Panasonic ERJ-3EKF4421V Panasonic ERJ-3EKF7870V Panasonic ERJ-3EKF75R0V Panasonic ERJ-3EKF20R0V Panasonic ERJ-3EKF2322V Panasonic ERJ-3GEY0R00V Panasonic ERJ-3EKF4992V Panasonic ERJ-3EKF9091V IR IR3899MPBF Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 7 IRDC3899-P3V3 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-9A, Room Temperature, no airflow Fig. 7: Start up at 9A Load Ch1:Vo, Ch2:Vin, Ch3:PGood Ch4:Enable Fig. 8: Start up at 9A Load, Ch1:Vo, Ch2:Vin, Ch3:PGood, Ch4: Vcc Fig. 9: Start up with 1.0V Pre Bias , 0A Load, Ch1:Vo Fig. 10: Output Voltage Ripple, 9A load Ch1: Vo Fig. 12: Short circuit (Hiccup) Recovery Ch1:Vo , Ch4:Io Fig. 11: Inductor node at 9A load Ch1:LX 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 8 IRDC3899-P3V3 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-9A, Room Temperature, no air flow Fig. 13: Transient Response, 4.5A to 9A step Ch1:Vo Ch4-Io 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 9 IRDC3899-P3V3 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-6A, Room Temperature Fig. 14: Bode Plot at 9A load shows a bandwidth of 159.8KHz and phase margin of 48.52 degrees 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 10 IRDC3899-P3V3 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-9A, Room Temperature, no air flow Fig. 15: Soft start and soft stop using S_Ctrl pin Fig. 16: Feed Forward for Vin change from 7 to 16V and back to 7V Ch2-Vo Ch3-Vin 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 11 IRDC3899-P3V3 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-9A, Room Temperature, no air flow 95 93 91 Efficiency (%) 89 87 85 83 81 79 77 6.5 7.0 7.5 8.0 8.5 9.0 6.5 7.0 7.5 8.0 8.5 9.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 75 Load Current (A) Fig. 17: Efficiency versus load current 3.0 Power Dissipation (W) 2.5 2.0 1.5 1.0 0.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Load Current (A) Fig. 18: Power loss versus load current 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 12 IRDC3899-P3V3 THERMAL IMAGES Vin=12.0V, Vo=3.3V, Io=0-9A, Room Temperature, No Air flow Fig. 19: Thermal Image of the board at 9A load Test point 1 is IR3899: 92.240C Test point 2 is inductor: 69.000C 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 13 IRDC3899-P3V3 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 20: PCB Metal Pad Spacing (all dimensions in mm) 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 14 IRDC3899-P3V3 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 21: Solder resist 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 15 IRDC3899-P3V3 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses. Figure 22: Stencil Pad Spacing (all dimensions in mm) 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 16 IRDC3899-P3V3 PACKAGE INFORMATION Figure 23: Package Dimensions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice.04/11 8/8/2013 Confidential This evaluation board is a preliminary version meant for the engineering evaluation of the IR3899. Based on the results of the continuing evaluation, this board can evolve and change without notice 17