MACH Power-Up Reset February 2002 MACH® devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic from ground. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Description Parameter Symbol tPR Power-Up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW VPWR Power-up Voltage for 3.3V Devices Unit 10 µs See Switching Characteristics Power-Up Voltage for 5V Devices Power Max 2.7 V 4 V VCC VPWR tPR Registered output tS Clock tWL Figure 1. Power-Up Reset Waveform www.latticesemi.com 1 99DBPOW_02